Packaging structure and preparation method thereof
By designing light-transmitting dielectric material pillars in the photonic chip packaging structure, the problem of optical window contamination was solved, high-performance optical coupling was achieved, and the reliability and signal integrity of the optical interface were improved.
Patent Information
- Application Number
- CN202511731236.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-24
- Publication Date
- 2026-02-24
AI Technical Summary
In the current silicon photonics chip packaging process, the optical window is easily contaminated, which leads to a decrease in the performance of the optical interface and makes it impossible to achieve high-performance optical coupling.
A first encapsulation layer is formed around the photonic chip on the substrate, exposing the optical coupler. A pillar of light-transmitting medium material is formed on the side away from the substrate to prevent the optical window from being blocked. Subsequent encapsulation layers do not contaminate the optical window, and vertical optical coupling is achieved through the light-transmitting medium material.
It effectively protects the optical window, avoids contamination during the packaging process, ensures the optical performance of the optical coupler, and achieves a high-performance optical interface.
Smart Images
Figure CN121568474A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a packaging structure and its fabrication method. Background Technology
[0002] With the explosive growth in bandwidth demand from artificial intelligence, high-performance computing, and data centers, co-packaged optical technology has become a development trend due to its ability to significantly reduce power consumption and increase bandwidth density.
[0003] Currently, silicon photonics chip packaging mainly adopts on-board optics (BOB) or near-package optics (NPO) architectures, and the optical coupling of the optical engine (OE) mostly uses edge couplers. In order to protect the optical window of the optical coupler inside the photonic chip from contamination during the packaging process, traditional packaging must strictly avoid the optical window when filling the chip bottom with adhesive, and it is not possible to perform overall plastic encapsulation to protect the chip.
[0004] Therefore, how to avoid contamination of the optical window during the molding process and achieve a high-performance optical interface has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] Therefore, it is necessary to provide a packaging structure and its fabrication method to address the issue of how to avoid contamination of the optical window during the molding process and achieve a high-performance optical interface.
[0006] To achieve the above objectives, in one respect, the present invention provides a method for preparing an encapsulation structure, comprising:
[0007] A carrier board and a photonic chip are provided, the photonic chip including an optical coupler;
[0008] A photonic chip is mounted on one side of the carrier board, and a first encapsulation layer is formed around the photonic chip, the first encapsulation layer exposing the photonic chip;
[0009] A first redistribution layer is formed on the side of the first encapsulation layer and the photonic chip away from the carrier. The first redistribution layer includes a dielectric layer and a wiring layer. The orthographic projection of the wiring layer on the carrier does not overlap with the orthographic projection of the optical coupler on the carrier.
[0010] A light-transmitting dielectric material column is formed on the side of the first redistribution layer away from the carrier plate, and the orthographic projection of the light-transmitting dielectric material column on the carrier plate overlaps with the orthographic projection of the optical coupler on the carrier plate.
[0011] A first chip is mounted on the side of the first redistribution layer away from the carrier board, and a second encapsulation layer is formed around the first chip and the light-transmitting dielectric material pillar, the second encapsulation layer exposing the light-transmitting dielectric material pillar.
[0012] In one embodiment, the method for forming the photonic chip includes:
[0013] A chip substrate is provided, and an optical coupler and a first connection structure are formed on one side of the chip substrate at intervals.
[0014] A light-transmitting protective layer is formed on the side of the optical coupler and the first connection structure away from the chip substrate, covering the optical coupler and surrounding the first connection structure.
[0015] In one embodiment, before forming the light-transmitting dielectric material pillar on the side of the first redistribution layer away from the carrier plate, the following steps are included:
[0016] An optical adhesive layer is formed on the side of the first rewiring layer away from the optical coupler, and the orthographic projection of the optical adhesive layer on the carrier overlaps with the orthographic projection of the optical coupler on the carrier.
[0017] In one embodiment, before forming the optical adhesive layer on the side of the first redistribution layer away from the optical coupler, the following steps are included:
[0018] An anti-reflection layer is formed on the side of the first rewiring layer away from the optical coupler, and the orthographic projection of the anti-reflection layer on the carrier plate overlaps with the orthographic projection of the optical coupler on the carrier plate;
[0019] Alternatively, after forming an optical adhesive layer on the side of the first redistribution layer away from the optical coupler, the method includes:
[0020] The anti-reflective layer is formed on the side of the optical adhesive layer away from the optical coupler.
[0021] In one embodiment, the process further includes, before mounting the photonic chip on one side of the carrier plate:
[0022] Provides silicon interconnect chips;
[0023] The silicon interconnect chip is mounted on one side of the carrier board. The silicon interconnect chip includes passive devices and / or voltage regulation circuitry that can be integrated.
[0024] In one embodiment, after mounting the first chip on the side of the first redistribution layer away from the carrier board and forming a second encapsulation layer surrounding the first chip and the light-transmitting dielectric material pillars, the process includes:
[0025] Remove the carrier plate;
[0026] A second wiring layer is formed on the side of the photonic chip away from the first wiring layer;
[0027] A first pad is formed on the side of the second wiring layer away from the photonic chip;
[0028] Provide encapsulated components;
[0029] The first pad is bonded to the package assembly.
[0030] In one embodiment, a packaging structure is also provided, including:
[0031] A photonic chip and a first encapsulation layer surrounding the photonic chip, the photonic chip including an optical coupler, the first encapsulation layer exposing the photonic chip;
[0032] The first wiring layer is located on one side of the first packaging layer and the photonic chip. The first wiring layer includes a dielectric layer and a wiring layer. The orthographic projection of the wiring layer on the photonic chip does not overlap with the orthographic projection of the optical coupler.
[0033] A light-transmitting dielectric material pillar is located on the side of the first redistribution layer away from the first encapsulation layer, and the orthogonal projection of the light-transmitting dielectric material pillar on the photonic chip overlaps with the orthogonal projection of the optical coupler.
[0034] The first chip is located on the side of the first interconnect layer that is away from the first interconnect layer;
[0035] A second encapsulation layer surrounds the first chip and the light-transmitting dielectric material pillars, and the second encapsulation layer exposes the light-transmitting dielectric material pillars.
[0036] In one embodiment, the packaging structure further includes:
[0037] A silicon interconnect chip is located within the first packaging layer and on the same layer as the photonic chip. The silicon interconnect chip includes passive devices and / or voltage regulation circuitry that can be integrated.
[0038] An optical adhesive layer is located between the light-transmitting dielectric material pillar and the first redistribution layer, and the orthographic projection of the optical adhesive layer on the photonic chip overlaps with the orthographic projection of the optical coupler.
[0039] An anti-reflective layer, wherein the orthographic projection of the anti-reflective layer on the photonic chip overlaps with the orthographic projection of the optical coupler, and the anti-reflective layer is located between the optical adhesive layer and the first redistribution layer; or the anti-reflective layer is located between the optical adhesive layer and the light-transmitting medium material pillar.
[0040] In one embodiment, the packaging structure further includes:
[0041] A photonic crystal is located on the side of the light-transmitting dielectric material pillar that is away from the first redistribution layer.
[0042] In one embodiment, the packaging structure further includes:
[0043] The second wiring layer is located on the side of the photonic chip away from the first wiring layer;
[0044] The first pad is located on the side of the second redistribution layer away from the photonic chip;
[0045] The packaged component is located on the side of the first pad away from the second overlay layer.
[0046] Compared with existing technologies, the above technical solution has the following advantages:
[0047] In this packaging structure and its fabrication method, a photonic chip with an optical coupler is mounted on a carrier plate. The optical coupler is located on the side of the photonic chip away from the carrier plate, forming a first packaging layer surrounding the photonic chip, which exposes the photonic chip. A first rewiring layer is formed on the side of the first encapsulation layer and the photonic chip away from the substrate. The first rewiring layer includes a wiring layer and a dielectric layer. The orthographic projection of the wiring layer on the substrate does not overlap with the orthographic projection of the optical coupler on the substrate. That is, the wiring layer does not block the optical window of the optical coupler. A light-transmitting dielectric material pillar is formed on the side of the first rewiring layer away from the substrate. The orthographic projection of the light-transmitting dielectric material pillar on the substrate overlaps with the orthographic projection of the optical coupler on the substrate. At this time, when the first chip is mounted on the side of the first rewiring layer away from the substrate and a second encapsulation layer is formed around the first chip and the light-transmitting dielectric material pillar, the optical window of the optical coupler is blocked by the light-transmitting dielectric material pillar. During the subsequent fabrication of the second encapsulation layer, the optical window will not be contaminated. In addition, the second encapsulation layer exposes the light-transmitting dielectric material pillar, and the optical coupler achieves vertical optical coupling through the light-transmitting dielectric material pillar. Attached Figure Description
[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0049] Figure 1 This is a schematic flowchart illustrating a method for fabricating a packaging structure according to an embodiment of this application;
[0050] Figure 2 This is a schematic diagram of the structure of a chip substrate provided in an embodiment of this application;
[0051] Figure 3 This is a schematic diagram of a photonic chip forming an optical coupler and a first connection structure provided in an embodiment of this application;
[0052] Figure 4 This is a schematic diagram of a photonic chip forming a light-transmitting protective layer, provided in an embodiment of this application.
[0053] Figure 5 This is a schematic diagram of a photonic chip thinned to form a dicing film, provided in an embodiment of this application.
[0054] Figure 6 This is a schematic diagram of a packaging structure forming conductive pillars on a carrier plate, provided in an embodiment of this application.
[0055] Figure 7 This application provides a schematic diagram of a packaging structure for mounting a photonic chip and a silicon interconnect chip on a carrier board.
[0056] Figure 8 This is a schematic diagram of the structure for forming a first encapsulation material layer in an embodiment of this application.
[0057] Figure 9 This is a schematic diagram of the structure for forming the first encapsulation layer of an encapsulation structure provided in an embodiment of this application;
[0058] Figure 10 This is a schematic diagram of the structure for forming the first redistribution layer of a packaging structure provided in an embodiment of this application;
[0059] Figure 11 This is a schematic diagram of the structure of a light-transmitting dielectric material pillar for an encapsulation structure provided in an embodiment of this application;
[0060] Figure 12 This is a schematic diagram of a packaging structure for mounting a first chip, provided in an embodiment of this application.
[0061] Figure 13 This is a schematic diagram of the structure for forming a second encapsulation material layer in an embodiment of this application.
[0062] Figure 14 This is a schematic diagram of a packaging structure with the carrier plate removed, provided in an embodiment of this application.
[0063] Figure 15 This is a schematic diagram of the packaging structure after removing the cutting film, provided in an embodiment of this application.
[0064] Figure 16 This application provides a schematic diagram of the formation of a second wiring layer and a first pad in a packaging structure according to an embodiment of the present application.
[0065] Figure 17 This is a schematic diagram of a packaging structure forming a second packaging layer, provided in an embodiment of this application.
[0066] Figure 18 This is a schematic diagram of the structure of a bonding packaging assembly provided in an embodiment of this application;
[0067] Figure 19 This is a top view of a packaging structure provided in an embodiment of this application.
[0068] Explanation of reference numerals in the attached figures: 01-Carrier board; 02-Photonic chip; 021-Optical coupler; 022-First connection structure; 023-Chip substrate; 024-Light-transmitting protective layer; 025-Cut film; 03-Conductive pillar; 04-First encapsulation layer; 041-First encapsulation material layer; 05-First redistribution layer; 052-Wire layer; 051-Dielectric layer; 06-Light-transmitting dielectric material pillar; 07-First chip; 071-Electrical chip; 072-Computing chip; 073-High bandwidth memory; 08-Underfill layer; 09-Second encapsulation layer; 091-Second encapsulation material layer; 10-Optical adhesive layer; 11-Anti-reflective layer; 12-Silicon interconnect chip; 13-Second redistribution layer; 14-First pad; 15-Encapsulation component; 16-Photonic crystal; 17-Fiber optic array unit. Detailed Implementation
[0069] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0071] It should be understood that when a layer is referred to as "on," "adjacent to," or "connected to" other layers, it can be directly on, adjacent to, or connected to other layers, or there can be intervening layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," or "directly connected to" other layers, there are no intervening layers.
[0072] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.
[0073] To make the objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0074] refer to Figure 1 , Figure 1 This application provides a schematic flowchart of a method for fabricating a packaging structure, including:
[0075] S10: Provides a carrier board 01 and a photonic chip 02, the photonic chip 02 including an optical coupler 021 (e.g. Figure 7 (As shown).
[0076] In this step, the carrier plate 01 provided can be a glass carrier plate 01.
[0077] It should be noted that conductive posts 03 (through insulator via, TIV) can be pre-formed on the carrier board 01 to facilitate subsequent interconnection of circuits (e.g., Figure 6 (As shown). The conductive pillar 03 can be made of a metallic material, such as a copper pillar. The copper pillar can be fabricated using processes such as photolithography, electroplating, vertical wire bonding, and laser welding, without any specific limitations.
[0078] The photonic chip 02 includes an optical coupler 021. It should be noted that the optical coupler 021 can be located on one side of the surface of the photonic chip 02 to facilitate the reception of optical signals.
[0079] S20: A photonic chip 02 is mounted on one side of the carrier board 01, and a first encapsulation layer 04 is formed around the photonic chip 02. The first encapsulation layer 04 exposes the photonic chip 02 (e.g., ...). Figure 9 (As shown).
[0080] In this step, the photonic chip 02 is mounted on the side of the carrier plate 01 where the conductive post 03 is located. At this time, the optical coupler 021 is located on the side away from the carrier plate 01.
[0081] After the photonic chip 02 is mounted, the first encapsulation is performed to form the first encapsulation layer 04. It should be noted that the first encapsulation material layer 041 can be formed first on the side of the carrier board 01 where the photonic chip 02 is located (e.g., Figure 8As shown, the first encapsulation material layer 041 encapsulates the photonic chip 02 and the conductive pillar 03. Then, the first encapsulation material layer 041 is polished until the conductive pillar 03 and the photonic chip 02 are exposed, forming the first encapsulation layer 04. Afterward, polishing can be performed to remove surface scratches and obtain a flat surface. Polishing can be performed by chemical mechanical polishing (CMP) or mechanical grinding.
[0082] S30: A first redistribution layer 05 is formed on the side of the first encapsulation layer 04 and the photonic chip 02 away from the carrier plate 01. The first redistribution layer 05 includes a dielectric layer 051 and a wiring layer 052. The orthographic projection of the wiring layer 052 on the carrier plate 01 does not overlap with the orthographic projection of the optical coupler 021 on the carrier plate 01 (e.g., Figure 10 (As shown).
[0083] In this step, a first redistribution layer 05 is formed on the side of the first encapsulation layer 04 and the photonic chip 02 away from the carrier 01. The first redistribution layer 05 includes a wiring layer 052 and a dielectric layer 051. The wiring layer 052 is used to better connect the photonic chip 02 to subsequent chips. It should be noted that the orthographic projection of the wiring layer 052 on the carrier 01 does not overlap with the orthographic projection of the optical coupler 021 on the carrier 01. That is, at this time, only the dielectric layer 051 is provided on the side of the optical coupler 021 away from the carrier 01, leaving the optical window of the optical coupler 021. That is, no wiring layer 052 is provided at the optical window of the optical coupler 021 to avoid obstructing the optical window.
[0084] The line width or spacing of the first routing layer 05 can range from 0.5μm to 10μm, including endpoint values. For example, the line width or spacing of the first routing layer 05 can be 0.5μm, or the line width or spacing of the first routing layer 05 can be 2μm, or the line width or spacing of the first routing layer 05 can be 5μm, or the line width or spacing of the first routing layer 05 can be 6.2μm, etc., without any specific limitation.
[0085] S40: A light-transmitting dielectric material pillar 06 is formed on the side of the first wiring layer 05 away from the carrier plate 01. The orthographic projection of the light-transmitting dielectric material pillar 06 on the carrier plate 01 overlaps with the orthographic projection of the optical coupler 021 on the carrier plate 01 (e.g., ...). Figure 11 (As shown).
[0086] In this step, a light-transmitting dielectric material pillar 06 is formed on the side of the first redistribution layer 05 away from the carrier plate 01. It should be noted that the light-transmitting dielectric material pillar 06 is formed of or includes a light-transmitting material. The light-transmitting material may include one or more of glass, quartz, sapphire, silicon oxide, silicon nitride, silicon dioxide, aluminum oxide, and optical-grade polymers, without specific limitations, and can be selected as needed. For example, a glass pillar may be used.
[0087] In some embodiments, the height of the light-transmitting medium material column 06 can be in the range of 650μm-750μm, including the endpoint value. For example, the height of the light-transmitting medium material column 06 can be 675μm, or 693μm, or 700μm, or 750μm, etc., without specific limitation.
[0088] The orthographic projection of the light-transmitting medium material column 06 on the carrier plate 01 overlaps with the orthographic projection of the optical coupler 021 on the carrier plate 01. At this time, the optical window of the optical coupler 021 is protected by the light-transmitting medium material column 06.
[0089] S50: A first chip 07 is mounted on the side of the first rewiring layer 05 away from the carrier board 01, and a second encapsulation layer 09 is formed around the first chip 07 and the light-transmitting dielectric material pillar 06, the second encapsulation layer 09 exposing the light-transmitting dielectric material pillar 06.
[0090] In this step, the first chip 07 is mounted on the side of the first wiring layer 05 away from the carrier board 01. It should be noted that the first chip 07 may include an electrical chip 071 (EIC), a computing chip 072 (XPU), and a high-bandwidth memory 073 (HBM), etc., without specific limitations (e.g., Figure 12 (As shown).
[0091] In some embodiments, a second pad 053 may be formed first on the side of the first wiring layer 05 away from the carrier board 01, and then the electrical chip 071, computing chip 072, and high-bandwidth memory 073, etc., may be mounted by flip-chip bonding. Figure 12 (As shown).
[0092] After mounting the first chip 07, a bottom filler layer 08 can be formed on the first chip 07 (e.g., ...). Figure 13 As shown), a second encapsulation is then performed to form the second encapsulation layer 09. It should be noted that the second encapsulation material layer 091 (as shown) can be formed first. Figure 13 As shown, the second encapsulation material layer 091 encapsulates the first chip 07 and the light-transmitting dielectric material pillar 06. Then, the second encapsulation material layer 091 is ground until the light-transmitting dielectric material pillar 06 is exposed, forming the second encapsulation layer 09.
[0093] In this embodiment, the optical window of the optical coupler 021 is not obstructed by the wiring layer 052 in the first redistribution layer 05. A light-transmitting dielectric material pillar 06 is formed on the side of the first redistribution layer 05 away from the carrier plate 01. The orthographic projection of the light-transmitting dielectric material pillar 06 on the carrier plate 01 overlaps with the orthographic projection of the optical coupler 021 on the carrier plate 01. The optical window of the optical coupler 021 is obstructed by the light-transmitting dielectric material pillar 06. When the second encapsulation layer 09 is subsequently fabricated, the optical window will not be contaminated. In addition, the second encapsulation layer 09 exposes the light-transmitting dielectric material pillar 06, and the optical coupler 021 achieves vertical optical coupling through the light-transmitting dielectric material pillar 06.
[0094] In another embodiment of this application, the method for forming the photonic chip 02 includes:
[0095] S101: Provides chip substrate 023 (e.g.) Figure 2 As shown, an optical coupler 021 and a first connection structure 022 are formed at intervals on one side of the chip substrate 023.
[0096] In this step, an optical coupler 021 and a first connection structure 022 are first formed on one side of the provided chip substrate 023 with spacing. It should be noted that the first connection structure 022 can be a copper bump for subsequent circuit interconnection (e.g., Figure 3 (As shown).
[0097] The cross-section of the first connecting structure 022 can be circular, elliptical, square, etc., without any specific limitation.
[0098] S102: A light-transmitting protective layer 024 (e.g., covering the optical coupler 021 and surrounding the first connection structure 022 on the side away from the chip substrate 023) is formed. Figure 4 (As shown).
[0099] In this step, a light-transmitting protective layer 024 can be formed on the side of the optical coupler 021 and the first connection structure 022 away from the chip substrate 023. The light-transmitting protective layer 024 covers the optical coupler 021 and surrounds the first connection structure 022.
[0100] In some embodiments, the thickness of the light-transmitting protective layer 024 can range from 0.5 μm to 50 μm, including endpoint values. For example, the thickness of the light-transmitting protective layer 024 can be 0.5 μm, 12 μm, 20 μm, or 46 μm, etc. The transmittance of the light-transmitting protective layer 024 at a communication wavelength of 1550 nm can be greater than 95%.
[0101] In some embodiments, the material of the light-transmitting protective layer 024 may include polymer materials, inorganic dielectric materials, or composite stacks thereof.
[0102] In some embodiments, the polymer material may include one of polyimide, benzocyclobutene, parylene, UV-curable optical adhesive, photoresist, etc., without specific limitation.
[0103] In some embodiments, the inorganic dielectric material may include one of silicon oxide, silicon nitride, silicon oxynitride, and spin-coated glass, without specific limitation.
[0104] In some embodiments, the thickness of the light-transmitting protective layer 024 is 0.5 μm to 50 μm, which is used in 1550 nm communication waves.
[0105] It should be noted that after the photonic chip 02 is fabricated, the chip substrate 023 can be thinned, and a dicing film 025 can be formed on the side of the chip substrate 023 away from the first connection structure 022. The photonic chip 02 is then diced to obtain individual photonic chips 02, facilitating the subsequent fabrication of packaging structures (such as...). Figure 5 (As shown).
[0106] In this embodiment, the light-transmitting protective layer 024 can protect the optical coupler 021, prevent contamination of the optical window of the optical coupler 021, and increase optical performance.
[0107] In another embodiment of this application, before forming the light-transmitting dielectric material pillar 06 on the side of the first redistribution layer 05 away from the carrier plate 01, the following steps are included:
[0108] An optical adhesive layer 10 is formed on the side of the first redistribution layer 05 away from the optical coupler 021. The orthographic projection of the optical adhesive layer 10 on the carrier plate 01 overlaps with the orthographic projection of the optical coupler 021 on the carrier plate 01 (e.g., Figure 11 (As shown).
[0109] Specifically, the material of the optical adhesive layer 10 can be a UV-curable optical adhesive or a thermosetting optical epoxy resin, etc.
[0110] It should be noted that the orthographic projection of the optical adhesive layer 10 on the carrier plate 01 overlaps with the orthographic projection of the optical coupler 021 on the carrier plate 01. In other words, the optical adhesive layer 10 is used to bond the light-transmitting medium material pillar 06 to the first rewiring layer 05, thereby improving the reliability of the light-transmitting medium material pillar 06.
[0111] In another embodiment of this application, before forming the optical adhesive layer 10 on the side of the first redistribution layer 05 away from the optical coupler 021, the following steps are included:
[0112] An anti-reflection layer 11 is formed on the side of the first rewiring layer 05 away from the optical coupler 021. The orthographic projection of the anti-reflection layer 11 on the carrier plate 01 overlaps with the orthographic projection of the optical coupler 021 on the carrier plate 01 (e.g., Figure 11 (as shown)
[0113] Alternatively, after forming the optical adhesive layer 10 on the side of the first redistribution layer 05 away from the optical coupler 021, it includes:
[0114] An anti-reflection layer 11 (not shown) is formed on the side of the optical adhesive layer 10 away from the optical coupler 021.
[0115] Specifically, an anti-reflective layer 11 is formed on the side of the first rewiring layer 05 away from the optical coupler 021. The orthographic projection of the anti-reflective layer 11 on the carrier plate 01 overlaps with the orthographic projection of the optical coupler 021 on the carrier plate 01. That is, the anti-reflective layer 11 can be set in the area of the optical window of the optical coupler 021. The anti-reflective layer 11 can also be set on the side of the optical adhesive layer 10 away from the light-transmitting protective layer 024. The position of the anti-reflective layer 11 is not specifically limited.
[0116] In this embodiment, an anti-reflection layer 11 is provided between the optical coupler 021 and the light-transmitting medium material column 06. When light passes through the optical window, the anti-reflection layer 11 can reduce reflected light interference and increase the signal integrity of communication.
[0117] In another embodiment of this application, before mounting the photonic chip 02 on one side of the carrier 01, the following steps are included:
[0118] Provides silicon interconnect chip 12;
[0119] A silicon interconnect chip 12 is mounted on one side of the carrier board 01. The silicon interconnect chip 12 includes passive devices and / or voltage regulation circuitry that can be integrated.
[0120] Specifically, before mounting the photonic chip 02, a silicon interconnect chip 12 can be provided. This silicon interconnect chip 12 may include logic switching chips or silicon interposers, etc., which have pre-integrated through-silicon vias (TSVs) and can integrate passive devices (IPDs) and / or voltage regulation circuits (IVRs) (such as...). Figure 7 (As shown).
[0121] Subsequently, the silicon interconnect chip 12 is mounted on the carrier board 01. During the first encapsulation, the first encapsulation material layer 041 encapsulates the silicon interconnect chip 12 simultaneously with the photonic chip 02 and the conductive pillar 03. In this embodiment, the silicon interconnect chip 12 achieves higher interconnect density and system performance (e.g., Figure 9 (As shown).
[0122] In another embodiment of this application, after mounting the first chip 07 on the side of the first redistribution layer 05 away from the carrier board 01 and forming a second encapsulation layer 09 surrounding the first chip 07 and the light-transmitting dielectric material pillars 06, the process includes:
[0123] Remove carrier plate 01 (e.g.) Figure 14 (as shown)
[0124] A second wiring layer 13 is formed on the side of the photonic chip 02 away from the first wiring layer 05 (e.g. Figure 16 (as shown)
[0125] A first pad 14 is formed on the side of the second wiring layer 13 away from the photonic chip 02 (e.g. Figure 16 (as shown)
[0126] Provide 15 encapsulated components;
[0127] Connect the first pad 14 to the package assembly 15 (e.g.) Figure 18 (As shown).
[0128] Specifically, after forming the second encapsulation layer 09, the carrier board 01 is removed based on the second encapsulation layer 09. The carrier board 01 can be removed by debonding (e.g., Figure 14 (As shown). The surface after removing the carrier plate 01 is then ground to expose the surface of the connecting structure (TVS) (as shown). Figure 15 (As shown).
[0129] Alternatively, after removing the carrier board 01, a second wiring layer 13 is formed on the exposed side of the photonic chip 02 and / or silicon interconnect chip 12 away from the first wiring layer 05. It should be noted that the second wiring layer 13 also includes a second routing layer and a second dielectric layer. The first routing layer in the second wiring layer 13 is not specifically limited (e.g., ...). Figure 16 (As shown).
[0130] Then, a first pad 14 is formed on the side of the second wiring layer 13 away from the photonic chip 02. It should be noted that the first pad 14 is used to bond the package assembly 15. Bonding can be achieved through hybrid bonding, solder bonding, etc. (e.g.,...) Figure 16 (As shown).
[0131] It should be noted that before bonding the packaging component 15, the formed packaging structure can be diced to obtain a single packaged chip.
[0132] In some embodiments, the packaging component 15 includes a packaging substrate, a printed circuit board, a package, etc.
[0133] It should be noted that the second encapsulation layer 09 can then be ground to expose the light-transmitting dielectric material pillar 06, and then the light-transmitting dielectric material pillar 06 can be polished to make its roughness less than 1μm, forming a light-transmitting plane (e.g., Figure 17 (As shown).
[0134] In some embodiments, a photonic crystal 16 may also be formed on the side of the light-transmitting dielectric material pillar 06 away from the photonic chip 02 to precisely control the performance of the packaging structure (e.g., Figure 17 (As shown).
[0135] In this embodiment, bonding the first pad 14 to the package assembly 15 can improve the stability, reliability and functional integrity of the device.
[0136] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0137] In another embodiment of this application, based on the above-described method for preparing the packaging structure, this application also provides a packaging structure, comprising:
[0138] The photonic chip 02 and the first encapsulation layer 04 surrounding the photonic chip 02, the photonic chip 02 including an optical coupler 021, the first encapsulation layer 04 exposing the photonic chip 02;
[0139] The first wiring layer 05 is located on one side of the first packaging layer 04 and the photonic chip 02. The first wiring layer 05 includes a dielectric layer 051 and a wiring layer 052. The orthographic projection of the wiring layer 052 on the photonic chip 02 does not overlap with the orthographic projection of the optical coupler 021.
[0140] The light-transmitting dielectric material pillar 06 is located on the side of the first redistribution layer 05 away from the first encapsulation layer 04. The orthographic projection of the light-transmitting dielectric material pillar 06 on the photonic chip 02 overlaps with the orthographic projection of the optical coupler 021.
[0141] The first chip 07 is located on the side of the first redistribution layer 05 that is away from the first redistribution layer 05;
[0142] The second encapsulation layer 09 surrounds the first chip 07 and the light-transmitting dielectric material pillar 06, and the second encapsulation layer 09 exposes the light-transmitting dielectric material pillar 06.
[0143] Specifically, the photonic chip 02 includes an optical coupler 021. It should be noted that the optical coupler 021 can be located on one side of the surface of the photonic chip 02 to facilitate the reception of optical signals. A first encapsulation layer 04 surrounds the photonic chip 02 and exposes the connection structure of the photonic chip 02 (e.g., ...). Figure 9 (As shown).
[0144] The first wiring layer 05 includes a wiring layer 052 and a dielectric layer 051. The wiring layer 052 is used to better connect the photonic chip 02 to subsequent chips. It should be noted that the orthographic projection of the wiring layer 052 onto the photonic chip 02 does not overlap with the orthographic projection of the optical coupler 021. That is, at this point, only the dielectric layer 051 is placed on one side of the optical coupler 021, reserving space for the optical window of the optical coupler 021. Specifically, no wiring layer 052 is placed at the optical window of the optical coupler 021 to avoid obstructing the optical window (e.g., ...). Figure 10 (As shown).
[0145] The line width or spacing of the first routing layer 05 can range from 0.5μm to 10μm, including endpoint values. For example, the line width or spacing of the first routing layer 05 can be 0.5μm, or the line width or spacing of the first routing layer 05 can be 2μm, or the line width or spacing of the first routing layer 05 can be 5μm, or the line width or spacing of the first routing layer 05 can be 6.2μm, etc., without any specific limitation.
[0146] The light-transmitting medium material column 06 is formed of, or includes, a light-transmitting material. The light-transmitting material may include one or more of glass, quartz, sapphire, silicon oxide, silicon nitride, silicon dioxide, aluminum oxide, and optical-grade polymers, without specific limitations, and can be selected as needed; for example, a glass column may be used.
[0147] The height of the light-transmitting medium material column 06 can range from 650μm to 750μm, including the endpoint values. For example, the height of the light-transmitting medium material column 06 can be 675μm, or 693μm, or 700μm, or 750μm, etc., without any specific limitation.
[0148] The orthographic projection of the light-transmitting dielectric material pillar 06 onto the photonic chip 02 overlaps with the orthographic projection of the optical coupler 021. At this time, the optical window of the optical coupler 021 is protected by the light-transmitting dielectric material pillar 06 (e.g., Figure 11 (As shown).
[0149] The first chip 07 may include an electronically controlled chip (EIC), a computing chip (XPU), and a high-bandwidth memory (HBM), etc., without specific limitations. The second encapsulation layer 09 encapsulates the first chip 07 and the light-transmitting dielectric material pillar 06 (such as... Figure 12 (As shown).
[0150] In this embodiment, the optical window of the optical coupler 021 is not obstructed by the wiring layer 052 in the first wiring layer 05. A light-transmitting dielectric material pillar 06 is formed on one side of the first wiring layer 05. The orthographic projection of the light-transmitting dielectric material pillar 06 on the photonic chip 02 overlaps with the orthographic projection of the optical coupler 021. The optical window of the optical coupler 021 is obstructed by the light-transmitting dielectric material pillar 06. When the second encapsulation layer 09 is subsequently fabricated, the optical window will not be contaminated. In addition, the second encapsulation layer 09 exposes the light-transmitting dielectric material pillar 06, and the optical coupler 021 achieves vertical optical coupling through the light-transmitting dielectric material pillar 06.
[0151] In another embodiment of this application, the packaging structure further includes:
[0152] The silicon interconnect chip 12 is located within the first packaging layer 04 and is located on the same layer as the photonic chip 02. The silicon interconnect chip 12 includes passive devices and / or voltage regulation circuits that can be integrated.
[0153] The optical adhesive layer 10 is located between the light-transmitting dielectric material pillar 06 and the first redistribution layer 05. The orthographic projection of the optical adhesive layer 10 on the photonic chip 02 overlaps with the orthographic projection of the optical coupler 021.
[0154] The anti-reflection layer 11 has its orthographic projection on the photonic chip 02 overlapping with the orthographic projection of the optical coupler 021, and the anti-reflection layer 11 is located between the optical adhesive layer 10 and the first redistribution layer 05; or the anti-reflection layer 11 is located between the optical adhesive layer 10 and the light-transmitting medium material pillar 06.
[0155] Specifically, the silicon interconnect chip 12 may include logic switching chips or silicon interposers, etc., in which through-silicon vias (TSVs) are pre-integrated, and passive devices (IPDs) and / or voltage regulation circuits (IVRs) can be integrated.
[0156] The silicon interconnect chip 12 and the photonic chip 02 are located on the same layer. A first encapsulation layer 04 surrounds the silicon interconnect chip 12 and the photonic chip 02 to achieve the first encapsulation. A first redistribution layer 05 connects the silicon interconnect chip 12 and the photonic chip 02 (e.g., ...). Figure 9 (As shown).
[0157] The optical adhesive layer 10 can be made of UV-curable optical adhesive or thermosetting optical epoxy resin, etc. The optical adhesive layer 10 is used to bond the light-transmitting dielectric material pillar 06 to the first redistribution layer 05, improving the reliability of the light-transmitting dielectric material pillar 06 (e.g., ...). Figure 11 (As shown).
[0158] An anti-reflection layer 11 is disposed between the optical coupler 021 and the light-transmitting medium material pillar 06. When light passes through the optical window, this anti-reflection layer 11 can reduce reflected light interference and increase the signal integrity of communication (e.g., ...). Figure 11 (As shown).
[0159] In another embodiment of this application, the packaging structure further includes:
[0160] Photonic crystal 16 is located on the side of the light-transmitting dielectric material pillar 06 away from the first redistribution layer 05 (e.g., Figure 17 (As shown).
[0161] Specifically, the photonic crystal 16 is located on the side of the light-transmitting dielectric material pillar 06 away from the first redistribution layer 05, which is used to realize the super prism effect, improve bandwidth density, simplify the packaging structure, reduce loss and alignment difficulty, and improve device reliability.
[0162] In some embodiments, a fiber array unit (FAU) can be disposed on the side of the photonic crystal 16 away from the light-transmitting medium material pillar 06 to serve as an optical interface (e.g., Figure 18 (As shown).
[0163] In another embodiment of this application, such as Figure 16 As shown, the packaging structure also includes:
[0164] The second wiring layer 13 is located on the side of the photonic chip 02 that is away from the first wiring layer 05;
[0165] The first pad 14 is located on the side of the second redistribution layer 13 away from the photonic chip 02;
[0166] The package component 15 is located on the side of the first pad 14 away from the second rewiring layer 13.
[0167] Specifically, the second wiring layer 13 is located on the side of the photonic chip 02 and / or silicon interconnect chip 12 away from the first wiring layer 05. The second wiring layer 13 also includes a wiring layer 052 and a dielectric layer 051. The wiring layer 052 in the second wiring layer 13 is not specifically defined.
[0168] The first pad 14 is located on the side of the second wiring layer 13 away from the photonic chip 02, and is used to bond the packaging assembly 15, which includes a packaging substrate, a printed circuit board, a package, etc.
[0169] In this embodiment, bonding the first pad 14 to the package assembly 15 can improve the overall stability, reliability and functional integrity of the device.
[0170] This application also provides a top view structural illustration of an embodiment of the encapsulation structure, such as... Figure 19 As shown, the optical engine (OE) is the connection structure between photonic chip 02 and electrical chip 071. It should be noted that... Figure 19 The encapsulation structure includes multiple electrical chips 071, computing chips 072, and high-bandwidth memory 073. The photonic crystal at position 16 is the optical window corresponding to the optical coupler 021 in this embodiment. Its arrangement is only for illustrative purposes and is not a specific limitation.
[0171] In the description of this specification, references to terms such as "some embodiments," "another embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0172] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0173] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for preparing a packaging structure, characterized in that, include: A carrier board and a photonic chip are provided, the photonic chip including an optical coupler; A photonic chip is mounted on one side of the carrier board, and a first encapsulation layer is formed around the photonic chip, the first encapsulation layer exposing the photonic chip; A first redistribution layer is formed on the side of the first encapsulation layer and the photonic chip away from the carrier. The first redistribution layer includes a dielectric layer and a wiring layer. The orthographic projection of the wiring layer on the carrier does not overlap with the orthographic projection of the optical coupler on the carrier. A light-transmitting dielectric material column is formed on the side of the first redistribution layer away from the carrier plate, and the orthographic projection of the light-transmitting dielectric material column on the carrier plate overlaps with the orthographic projection of the optical coupler on the carrier plate. A first chip is mounted on the side of the first redistribution layer away from the carrier board, and a second encapsulation layer is formed around the first chip and the light-transmitting dielectric material pillar, the second encapsulation layer exposing the light-transmitting dielectric material pillar.
2. The method for preparing the packaging structure according to claim 1, characterized in that, The method for forming the photonic chip includes: A chip substrate is provided, and an optical coupler and a first connection structure are formed on one side of the chip substrate at intervals. A light-transmitting protective layer is formed on the side of the optical coupler and the first connection structure away from the chip substrate, covering the optical coupler and surrounding the first connection structure.
3. The method for preparing the packaging structure according to claim 1, characterized in that, Before forming a light-transmitting dielectric material pillar on the side of the first redistribution layer away from the carrier plate, the process includes: An optical adhesive layer is formed on the side of the first rewiring layer away from the optical coupler, and the orthographic projection of the optical adhesive layer on the carrier overlaps with the orthographic projection of the optical coupler on the carrier.
4. The method for preparing the packaging structure according to claim 3, characterized in that, Before forming the optical adhesive layer on the side of the first redistribution layer away from the optical coupler, the process includes: An anti-reflection layer is formed on the side of the first redistribution layer away from the optical coupler, and the orthographic projection of the anti-reflection layer on the carrier plate overlaps with the orthographic projection of the optical coupler on the carrier plate; Alternatively, after forming an optical adhesive layer on the side of the first redistribution layer away from the optical coupler, the method includes: The anti-reflective layer is formed on the side of the optical adhesive layer away from the optical coupler.
5. The method for preparing the packaging structure according to claim 1, characterized in that, Before mounting the photonic chip on one side of the carrier board, the process further includes: Provides silicon interconnect chips; The silicon interconnect chip is mounted on one side of the carrier board. The silicon interconnect chip includes passive devices and / or voltage regulation circuitry that can be integrated.
6. The method for preparing the packaging structure according to claim 1, characterized in that, After mounting the first chip on the side of the first redistribution layer away from the carrier board and forming a second encapsulation layer surrounding the first chip and the light-transmitting dielectric material pillars, the process includes: Remove the carrier plate; A second wiring layer is formed on the side of the photonic chip away from the first wiring layer; A first pad is formed on the side of the second wiring layer away from the photonic chip; Provide encapsulated components; The first pad is bonded to the package assembly.
7. A packaging structure, characterized in that, include: A photonic chip and a first encapsulation layer surrounding the photonic chip, the photonic chip including an optical coupler, the first encapsulation layer exposing the photonic chip; The first wiring layer is located on one side of the first packaging layer and the photonic chip. The first wiring layer includes a dielectric layer and a wiring layer. The orthographic projection of the wiring layer on the photonic chip does not overlap with the orthographic projection of the optical coupler. A light-transmitting dielectric material pillar is located on the side of the first redistribution layer away from the first encapsulation layer, and the orthogonal projection of the light-transmitting dielectric material pillar on the photonic chip overlaps with the orthogonal projection of the optical coupler. The first chip is located on the side of the first interconnect layer that is away from the first interconnect layer; A second encapsulation layer surrounds the first chip and the light-transmitting dielectric material pillars, and the second encapsulation layer exposes the light-transmitting dielectric material pillars.
8. The packaging structure according to claim 7, characterized in that, The packaging structure further includes: A silicon interconnect chip is located within the first packaging layer and on the same layer as the photonic chip. The silicon interconnect chip includes passive devices and / or voltage regulation circuitry that can be integrated. An optical adhesive layer is located between the light-transmitting dielectric material pillar and the first redistribution layer, and the orthographic projection of the optical adhesive layer on the photonic chip overlaps with the orthographic projection of the optical coupler. An anti-reflective layer, wherein the orthographic projection of the anti-reflective layer on the photonic chip overlaps with the orthographic projection of the optical coupler, and the anti-reflective layer is located between the optical adhesive layer and the first redistribution layer; or the anti-reflective layer is located between the optical adhesive layer and the light-transmitting medium material pillar.
9. The packaging structure according to claim 7, characterized in that, The packaging structure further includes: A photonic crystal is located on the side of the light-transmitting dielectric material pillar that is away from the first redistribution layer.
10. The packaging structure according to claim 7, characterized in that, The packaging structure further includes: The second wiring layer is located on the side of the photonic chip away from the first wiring layer; The first pad is located on the side of the second redistribution layer away from the photonic chip; The packaged component is located on the side of the first pad away from the second overlay layer.
Citation Information
Cited By
Photoelectric packaging structure and packaging method thereof
CN122194401A