Right-handed semiconductor device and system including same

Abstract

Disclosed is a right-handed semiconductor device comprising: a control connector, a first load connector, and a second load connector; wherein the connectors are arranged in the same plane and protrude from the package of the semiconductor device, forming fingers of the right hand arrangement structure; wherein a first load connector is arranged behind the control connector, and a second load connector is arranged behind the first load connector; and wherein the second load connector is a thumb of the right hand arrangement; wherein the package body includes a top side and a bottom side opposite the top side, and the right hand arrangement is viewed from a top view.

Description

Technical Field

[0001] The present disclosure relates to a right-hand semiconductor device comprising a control connector, a first load connector, and a second load connector. Furthermore, the present disclosure relates to a system comprising a right-hand semiconductor device, a corresponding left-hand semiconductor device, and a connector device for connecting the left-hand semiconductor device and the right-hand semiconductor device to a gate driver IC. Background Art

[0002] For example, the active area of ​​a single silicon carbide (SiC) chip is limited by yield and high-quality manufacturability requirements. Therefore, multiple chips or multiple discrete packages must be connected in parallel on a common substrate to increase the possible target output of high-power electrical converters. Discrete device packages based on silicon (Si) chips face the same problem, but for different reasons: for discrete device packages (such as TO-247PLUS), the upper limit of co-packaged diodes and IGBT chips is about ~150A.

[0003] Once designers start parallelizing available discrete components, such as surface mount devices (SMDs) or through-hole devices (THDs), several challenges arise.

[0004] Therefore, an object of the present disclosure is to improve the trade-off between perfect symmetry of the gate loop and parasitic amplitude without compromising DC+ / DC- field cancellation and proper shielding of the gate driver. Summary of the Invention

[0005] According to a first aspect of the present disclosure, there is provided a right-handed semiconductor device comprising: a control connector, a first load connector, and a second load connector; wherein the connectors are arranged in the same plane and protrude from a package of the semiconductor device to form fingers of a right-handed arrangement structure; wherein the control connector is followed by the first load connector, which is followed by the second load connector; and wherein the second load connector is the thumb of the right-handed arrangement structure; or wherein the first load connector is followed by the second load connector, which is followed by the control connector, and wherein the control connector is the thumb of the right-handed arrangement structure; wherein the package comprises a top side and a bottom side opposite to the top side, and the right-handed arrangement structure is observed from a top view.

[0006] According to this first aspect, a discrete package comprising a single Si / SiC chip can be provided. The package can further comprise a power transistor or a plurality of chips, for example a transistor and a diode. The transistor can have source, drain and gate connectors, forming a four-terminal device or a three-terminal device. Typically, the four terminals are referred to as a first load connector as a source connector, a second load connector as a drain connector and a control connector as a gate and Kelvin connector. In the following, the terms control-gate, first load-source and second load-drain are used as equivalent replacements and do not limit the disclosure in terms of the type of transistor that is present inside the package.

[0007] The connectors protrude from the overmoulded package such that the distal end of each connector points away from the package. Typical semiconductor packages of the above-mentioned type have connectors that are arranged parallel to each other and in a common plane. Thus, for reasons of electrical clearance, the drain connector is spaced apart from the source connector. According to the present disclosure, in the case of a four-terminal device, the connectors are arranged such that the gate connector is followed by the source connector, and the drain connector is arranged next to or adjacent to, but spaced apart from, the source connector. In the case of a three-terminal device, the source connector (first load) is followed by the drain electrode (second load), and the drain connector is followed by the gate connector. If the connectors of the semiconductor device are to be identified with the fingers of a human hand as seen from a top view, the drain connector of the four-terminal device or the gate connector of the three-terminal device can be identified with the thumb of the right hand. This identification is referred to as a "right-hand arrangement". In a usual arrangement, for example the arrangement of a standard TO-247-4 semiconductor device, the arrangement of the connectors is reversed, i.e. the drain connector forms the thumb of a left-hand arrangement, i.e. can be identified with the left-hand thumb from a top view.

[0008] By virtue of the first aspect of the present disclosure, the above-mentioned problems are at least mitigated by providing a mirror package (of each SMD and / or THD). The gate control loop has its own parasitic inductance / capacitance / resistance. In the following, this will be referred to as gate loop parasitic effect.

[0009] If the mirror package is used together with the corresponding non-mirror package, symmetry can be ensured with a minimum gate loop parasitic amplitude, making it easier to parallelize power transistors, paving the way for high-power discrete power converters with a single gate driver controlling multiple discrete chips.

[0010] According to one embodiment of the first aspect of the present invention, the bottom side is configured to be attachable to or comprises a cooling structure. The bottom side of the package can be the side adjacent to the drain side of the transistor within the package. The bottom side is opposite to the top side, which can be adjacent to the control side of the transistor within the package. The control side of the transistor comprises the control pad (gate) to which the respective connector is attached and the first load pad (source). However, in order to direct heat away from the transistor, the cooling structure can be attached or can at least be attachable to the bottom side of the package.

[0011] According to one embodiment of the first aspect of the present disclosure, the semiconductor device comprises a single chip / die in a single package or comprises a plurality of chips in a single package. It is noted that the present disclosure relates to mirror image discrete devices, which are placed together on a common substrate, e.g. a printed circuit board (PCB). Such devices can be referred to as discrete semiconductor devices.

[0012] Examples of discrete semiconductor devices include diodes, transistors, and thyristors. Diodes are two-terminal devices that allow current to flow in only one direction, and are commonly used in rectifier circuits to convert alternating current to direct current. Transistors are three-terminal devices that can amplify or switch electrical signals and are used in a variety of circuits, including amplifiers, oscillators, and digital logic circuits. Thyristors are four-layer, three-terminal semiconductor devices that are used as switches and are commonly used in power control circuits for alternating current loads.

[0013] According to one embodiment of the first aspect of the present disclosure, each connector is a pin, wherein the pins are arranged in parallel. Pins can be small cylindrical metal parts that can be used to provide electrical connections between devices or components, but can also provide mechanical support for the devices.

[0014] Pins are typically located at the end of an electrical cable or wire and can be inserted into a corresponding socket or connector on a circuit board or other electronic device.

[0015] Pins can be composed of a metal shaft or body, which can be coated with a layer of gold or other conductive material to improve conductivity and prevent corrosion. The end of the pin can be shaped to fit a particular type of socket or connector, or substrate or device integrated into a multi-layer substrate.

[0016] Pins allow the discrete semiconductor device to be secured to a substrate.

[0017] In particular, the right-hand semiconductor device comprises a Kelvin connector between the control connector and the first load connector. The Kelvin connector can be used to decouple the gate control loop from the power loop. It can provide a shorter connection without having to carry high load currents, thus significantly reducing parasitic effects when switching the transistor.

[0018] Faster switching, i.e. higher switching frequency, can thus be achieved. Faster switching can imply higher di / dt values. However, at higher di / dt values, the induced voltage at the parasitic stray inductance can increase, which can have a detrimental effect on the circuit.

[0019] According to one embodiment of the first aspect of the present disclosure, the semiconductor device is a through-hole device (THD) or a surface mount device (SMD).

[0020] A through-hole device refers to an electronic component that has leads (or pins) that are inserted into a through-hole on a printed circuit board (PCB) or other circuit substrate and then soldered. The leads on a through-hole component are typically thicker and more robust than those on a surface mount device, which are often preferred for components that require high mechanical stability or need to handle high currents or voltages.

[0021] A surface mount device (SMD) is an electronic component designed to be mounted directly on the surface of a printed circuit board (PCB) or other circuit substrate. Unlike through-hole components, SMDs are soldered to the surface of a PCB, which allows for smaller, more densely packed circuit boards. SMDs typically have smaller, flatter leads (or pads) than through-hole components, which allows for more efficient use of space on the circuit board.

[0022] According to one embodiment of the first aspect of the present disclosure, the right-hand semiconductor device comprises a non-monolithic leadframe, wherein the second load connector is attached to the non-monolithic leadframe via a connection wire.

[0023] A non-monolithic leadframe can also be referred to as a floating leadframe.

[0024] A non-monolithic leadframe is a type of leadframe used in semiconductor packaging. A leadframe is a thin metal structure that provides a means of connecting a semiconductor chip to the outside world. Unlike a monolithic leadframe, which is made from a single piece of metal, a non-monolithic leadframe is composed of multiple components that are assembled together to form the leadframe structure.

[0025] A non-monolithic leadframe can be composed of a base layer, die attach pads, and a plurality of lead fingers extending from the die attach pads. The base layer provides mechanical support for the leadframe, while the die attach pads are used to attach a semiconductor chip to the leadframe. The lead fingers provide electrical connections between the chip and the outside world.

[0026] Non-monolithic leadframes can be used in a variety of semiconductor packages, including flat, quad, no-lead (QFN) packages and small outline integrated circuit (SOIC) packages. They allow for more complex leadframe geometries and can accommodate more leads in smaller package sizes.

[0027] In the present embodiment, the non-monolithic leadframe can be arranged such that the drain connectors forming the thumb of the right-hand semiconductor device can be connected to the respective leadframe portions by connection wires. In other words, the non-monolithic leadframe can comprise drain portions forming the thumb of the respective right-hand arrangement of the leadframe. By providing the respective portions of the leadframe, the connection between the drain portions of the leadframe and the drain connectors is simplified, since the drain connectors can be identical to those in the usual left-hand arrangement, but connected to the right-hand drain portions of the floating leadframe via the connection wires. Thus, mirror semiconductor devices can be easily produced and costs kept at a minimum.

[0028] According to one embodiment of the first aspect of the present application, the connectors are bent to enable more connection schemes.

[0029] According to a second aspect of the present disclosure, a system is provided, the system comprising: a right-hand semiconductor device of the first aspect of the present disclosure; a left-hand semiconductor device comprising: a control connector, a first load connector and a second load connector; wherein the connectors are arranged in the same plane and protrude from a package of the semiconductor device forming a finger of a left-hand arrangement, wherein the control connector is followed by the first load connector, which is followed by the second load connector, wherein the second load connector is a thumb of the left-hand arrangement; or wherein the first load connector is followed by the second load connector, which is followed by the control connector, wherein the control connector is a thumb of the left-hand arrangement, wherein the package comprises a top side and a bottom side opposite the top side, wherein the left-hand arrangement is viewed from a top view; and a connector device for connecting the left-hand semiconductor device and the right-hand semiconductor device to a gate driver IC.

[0030] The system according to the second aspect of the present disclosure comprises a right-hand semiconductor device and a left-hand semiconductor device. The two devices can be mirror images of each other. Both semiconductor devices are connected to a connector device.

[0031] The connector device can be a PCB or any other layered substrate comprising at least one of a HV layer, an interconnect layer, a gate return layer, a gate layer and a ground layer.

[0032] Both semiconductor devices can be attached to the connector device in parallel. In such an arrangement, the thumb (two drain connectors) is arranged at opposite ends of the arrangement, with the remaining connectors in between.

[0033] However, the gate connectors can be arranged spaced apart, i.e. next to each other, and can be connected to the same gate layer in the connector device. Since the gate connectors are arranged next to each other, the size of the gate layer of the connector device can be reduced. Furthermore, since the drain connectors are spaced further apart than in the common arrangement with two parallel left-hand devices, the distance from the drain connectors to the gate connectors is increased. In the parallel arrangement according to the present disclosure, the drain connectors of one half of the semiconductor devices can not be adjacent to the gate connectors of the adjacent devices. Thus, the stray inductance that is generated from the drain connectors and influences the gate current is reduced. The gate control signal is thereby improved. The overall result is a reduced form factor.

[0034] Furthermore, in the above configuration, the bottom side of the left-hand devices and the bottom side of the right-hand devices are in the same plane and can be attached to a common heat sink or cooling structure.

[0035] In one embodiment of the second aspect of the present disclosure, the connector device is a layered substrate, the substrate comprising: a lead frame; a first load layer connected to the source connectors of the two semiconductor devices; a control layer connected to the gate connectors of the two semiconductor devices; wherein the footprint of the control layer can be smaller than the footprint of the first load layer; wherein the control layer is arranged in a plane parallel to the plane in which the first load layer is arranged; the control layer is symmetrically arranged on top of the first load layer.

[0036] As mentioned before, the control connectors are arranged next to each other. The control connectors can be connected to a common control layer, i.e. gate layer, wherein the footprint of the control layer can be smaller than the footprint of the first load layer. Thus, the gate layer forms only one small island on top of the first load layer, which can also be referred to as source layer. Thus, the size of the gate layer and the source layer can be reduced.

[0037] In particular, the second load connectors of each semiconductor device are connected to the lead frame, wherein the lead frame is a layer parallel to the plane of each of the control layer and the first load layer.

[0038] In one embodiment of the second aspect of the present disclosure, the left-hand semiconductor device is a mirror image of the right-hand semiconductor device, wherein the left-hand semiconductor device and the right-hand semiconductor device are arranged in the same plane such that the thumb of the right-hand device and the thumb of the left-hand device do not string together. The "fingers" of the devices, i.e. source, gate, gate loop connectors, string together, spacing the drain connectors apart from each other.

[0039] Those skilled in the art will realize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0040] The present disclosure is illustrated in the accompanying drawings, which are depicted by way of example and not limitation, in which like references indicate similar or like elements. Elements in the figures are not necessarily drawn to scale relative to one another. Features of various shown examples can be combined unless they are mutually exclusive.

[0041] Fig. 1 shows a schematic layer structure of an electronic system of the prior art.

[0042] Fig. 2 shows a connector scheme of a plurality of semiconductor devices of the prior art.

[0043] Figure 3 A connector scheme of a plurality of semiconductor devices according to the present disclosure is shown.

[0044] Figure 4a A semiconductor system of the prior art is shown.

[0045] Figure 4b A semiconductor system according to the present disclosure is shown.

[0046] Fig. 5 shows a connector scheme of a plurality of semiconductor devices connected to a connector device according to the prior art.

[0047] Figure 6 A connector scheme of a plurality of semiconductor devices connected to a connector device according to the present disclosure is shown.

[0048] Figure 7 A schematic mirror device according to the first aspect of the present disclosure is shown. DETAILED DESCRIPTION

[0049] Aspects of the present disclosure and further embodiments will be further described below by way of example.

[0050] Fig. 1 shows a schematic layer structure of an electronic system 1 of the prior art. The electronic system 1 comprises transistors 2, which are divided into a high side of a half bridge and a low side of a half bridge, each side comprising at least two transistors 2. Each side is connected to a gate driver IC 3 via a gate layer (layer 1). In order to reduce parasitic inductance, the transistors comprised by the sides of the half bridge are symmetrically sandwiched and arranged between a top layer, i.e. a voltage input layer V HV and a V GND layer. Thus, the free interconnections between the transistors (MOSFETs) and the gate driver IC 3 are parallel and arranged symmetrically, so that the inductance caused by the free path length is reduced by destructive interference. It can be seen that a carefully designed layout approach is required to solve the problem of stray inductance caused by the free conductor sections.

[0051] Fig. 2 shows a connector scheme of multiple semiconductor devices of the prior art. The semiconductor device is a left-hand semiconductor device 4. The drain connector 5 of the left-hand semiconductor device forms the thumb of the left-hand arrangement and is spaced from the remaining connectors to provide the correct clearance and creepage distance proportional to the voltage class of the electronic system. The semiconductor device can be an SMD or a THD. In case of two THDs (e.g. TO247-4) arranged in parallel, i.e. the connectors are arranged in the same plane and the devices have the same left-hand orientation. The drain connector 5 of one device is located next to the gate, gate kelvin and source connectors, which requires a certain clearance to do so, hindering the electronic system 1 to become smaller.

[0052] Figure 3 A connector scheme of parallel mirrored semiconductor devices according to the present disclosure is shown. A standard left-hand semiconductor device 4 (in the following called device) is connected to a control layer 6 by its gate connector G and its gate kelvin connector K. The source connector S is connected to a first load layer 7, which is located in the layered substrate below the control layer 6. A right-hand device 8, e.g. a mirrored version of a TO-247-4 package, is connected in a similar way to the control layer 6 and the first load layer 7. Thus, the drain connector 9 of the right-hand device 8 is spaced about twice the width of the device and is not arranged next to the neighboring non-mirrored device. This avoids that the inductance originating from the drain connectors 5, 9 influences the gate signal at the gate connector G. The gate G and the gate kelvin connector K are close to each other, thus they can be connected to the same control layer 6, in turn, the electronic system 1 can become smaller as in the corresponding case when using non-mirrored devices. This also applies to the first load layer 7, which can be designed to have the control layer 6 on top and only overlaps with the control layer 6 in the periphery, wherein the source connector S of the devices 4, 8 is connected to the first load layer 7.

[0053] Figure 4a A semiconductor system 1 of the prior art is shown. The semiconductor system 1 comprises two right-hand semiconductor devices 8 arranged in parallel. The high side and the low side are connected with the same orientation.

[0054] The semiconductor devices 8 are connected to a connector device 10 by their protruding connectors. The semiconductor devices 8 are plugged into the connector device 10 by pins, wherein the connectors are connected to different layers of the connector device 10. The connector device 10 comprises at least one drain layer 11, a source layer corresponding to the first load layer 7 and a gate / gate kelvin layer corresponding to the control layer 6. In this embodiment, the connectors are pins and are arranged in parallel.

[0055] Figure 4b A semiconductor system 1 is shown. As shown, the high side and the low side of the devices are flipped. In accordance with the present disclosure, the devices are connected to a control layer 6 by their gate connectors G and their gate kelvin connectors K. The source connectors S are connected to a first load layer 7, which is located in the layered substrate below the control layer 6. A right-hand device 8, e.g. a mirrored version of a TO-247-4 package, is connected in a similar way to the control layer 6 and the first load layer 7. Thus, the drain connector 9 of the right-hand device 8 is spaced about twice the width of the device and is not arranged next to the neighboring non-mirrored device. This avoids that the inductance originating from the drain connectors 5, 9 influences the gate signal at the gate connector G. The gate G and the gate kelvin connector K are close to each other, thus they can be connected to the same control layer 6, in turn, the electronic system 1 can become smaller as in the corresponding case when using non-mirrored devices. This also applies to the first load layer 7, which can be designed to have the control layer 6 on top and only overlaps with the control layer 6 in the periphery, wherein the source connector S of the devices 4, 8 is connected to the first load layer 7. Figure 4bIn the semiconductor system 1 of Fig. 4, two mirror devices 4, 8, i.e. the right-hand device 8 and the left-hand device 4, are used in the same parallel arrangement as shown in Figure 4a Fig. 1. The connectors of the devices 4, 8 are connected to the layer structure of the connector device 10 as described above in connection with Figure 3 Fig. 1. However, the shape of the layers and the structure of the layers can differ from the usual case described in connection with Figure 4a Fig. 1, which will be described in more detail below.

[0056] Fig. 5 shows a connector scheme for connecting a plurality of semiconductor devices Q1_1 and Q1_2 to a connector device 10 as Figure 4a shown in Fig. 1 and the corresponding layer structure of the connector device 10.

[0057] The substrate 12 comprises a drain layer connecting the two drain connectors D of the devices Q1_1 and Q1_2 (not shown) to each other. The drain layer 11 is shaped in a general U-shape and is recessed in order to avoid the source connectors S and the gate connectors G. Thus, the drain layer has a plurality of circular recesses with a diameter according to the respective gap distance, i.e. the required gap, according to the voltage class. The source layer 7 is covered by the gate layer 6 such that the source layer 7 overlaps with the gate layer 6 in order to enable the connection of the gate connectors G of the devices Q1_1. Furthermore, in order to connect the source connectors S of the devices Q1_2 to the source layer, a hole 13 is provided in the gate layer through which the source connectors of the devices Q1_2 are connected to the source layer but do not establish an electrical contact with the gate layer. Both the gate layer and the source layer comprise recesses in the vicinity of the drain connectors of the devices Q1_2 in order to establish the required gap. The gate layer is connected to the gate driver 3. The gate driver is connected to the gate areas of both Q1_1 and Q1_2 via a bus 14. The gate loop terminal 15 of the gate driver IC 3 is directly connected to the gate layer.

[0058] Figure 6 Fig. 6 shows a connector scheme for connecting a plurality of semiconductor devices Q2_1 and Q2_2 to a connector device 10 as Figure 4bThe connector scheme of the connector device 10 and the corresponding layer structure of the connector device 10 is shown in Fig. 1. The drain layer 11 is in a generally U-shape in the lateral plane and is recessed to avoid the source connectors S and the gate connectors G. In contrast to the prior art described above, the drain layer 11 encloses the source layer 7 and the gate layer 6. The drain layer 11 has a plurality of circular recesses with a diameter of the respective minimum gap distance allowed according to the respective voltage class, i.e. the required gap. The source layer 7 is covered by the gate layer 6, wherein the gate layer is arranged symmetrically on the source layer. The coverage area of the source layer 7 is larger than the source coverage area of the gate layer 6. The gate layer 6 does not completely overlap the source layer 7, so that a strip-shaped area remains free, wherein the source connectors of both semiconductor devices Q2_1 and Q2_2 are connected to the source layer without the need for a hole 13. Since the gate connectors G of each device are arranged next to each other, the bus 14 can be much smaller than the bus 14 of the prior art. Thus, the free conductive length is reduced, which in turn reduces the losses due to parasitic stray inductance. The control layer 6 and the first load layer 7 form parallel planes.

[0059] Figure 7 A schematic mirror device according to the first aspect of the disclosure is shown, wherein the mirror device is a right-hand device 8. The drain connectors 9 form the thumb of the right-hand device and are connected to the respective parts of a floating lead frame (not visible) within the device 8. The lead frame is a non-monolithic layer, which is parallel to each of the control layer 6 and the first load layer 7. The drain connectors 9 are attached to the lead frame via connection wires 23. The first load layer 7 arranged in an array is arranged on top of the device 8, and the respective source connectors 16 are connected to this array via source interconnects 17. Furthermore, the top side of the device 8 has the control layer 6, and the gate connectors 18 are linked to this control layer via gate interconnects 19. A gate loop layer 20 is also arranged at the device 8 and is connected to the gate loop connectors 21 by gate loop interconnects 22.

[0060] Technical advantages of the disclosure

[0061] Technical advantages of the embodiments described herein can be thought of from the following table. The table shows a comparison of the system shown in Figure 4a Fig. 1 (referred to as A in the table below) with the mirror embodiment claimed in Figure 4b Fig. 2 (referred to as B in the table below).

[0062]

[0063] The system of the disclosure using two mirror devices shows about 30% less gate loop parasitic inductance compared to the system described in Figure 4a Fig. 1.

[0064] Although specific examples have been shown and described herein, a person of ordinary skill in the art will understand that various alternative and / or equivalent implementations can be substituted for the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any modifications or variations of the specific examples discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

[0065] It should be noted that the systems and devices outlined herein, as well as their preferred embodiments, can be used individually or in combination with other systems and devices disclosed herein. Furthermore, features outlined with respect to a device also apply to the corresponding system and vice versa.

[0066] In particular, all embodiments of the right-handed semiconductor device apply to a corresponding left-handed semiconductor device which is a mirror image of the right-handed semiconductor device.

[0067] Furthermore, all aspects of the systems and devices outlined herein can be combined arbitrarily. In particular, features of claims can be combined with each other in any manner.

[0068] It should be noted that the description and drawings merely illustrate the principles of the proposed method and system. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiments outlined herein are primarily intended to merely to explain for the reader's understanding the principles of the proposed method and system. Furthermore, all statements herein as to the

[0069] List of reference signs

[0070] 1 system

[0071] 2 transistor

[0072] 3 gate driver IC

[0073] 4 left-handed semiconductor device

[0074] 5 drain of left-handed semiconductor device

[0075] 6 control layer

[0076] 7 first load layer

[0077] 8 right-handed semiconductor device

[0078] 9 drain connector of right-handed semiconductor device

[0079] 10 connector device

[0080] 11 drain layer

[0081] 12 substrate

[0082] 13 hole

[0083] 14 bus line

[0084] 15 gate loop terminal of gate driver IC

[0085] 16 source connector

[0086] 17 source interconnect

[0087] 18 gate connector

[0088] 19 gate interconnect

[0089] 20 gate loop layer

[0090] 21 gate loop connector

[0091] 22 gate loop interconnect

[0092] 23 connection wire

Claims

1. A right-handed semiconductor device comprising a control connector, a first load connector, and a second load connector; in, The connectors are arranged in the same plane and protrude from the package of the semiconductor device to form fingers of a right-hand arrangement; wherein the control connector is followed by a first load connector, and the first load connector is followed by a second load connector; and wherein the second load connector is a thumb of a right-hand arrangement; or The first load connector is followed by the second load connector, the second load connector is followed by the control connector, and Among them, the control connector is the thumb of the right-hand arrangement structure; The package body includes a top side and a bottom side opposite to the top side, and the right-hand arrangement structure is viewed from a top view.

2. The semiconductor device according to claim 1, wherein The bottom side is configured to be attachable to or include a cooling structure.

3. The semiconductor device according to claim 1 or 2, wherein The semiconductor device includes a single die in a single package.

4. A semiconductor device according to any one of the preceding claims, wherein Each connector is a pin, wherein the pins are arranged in parallel.

5. A semiconductor device according to any one of the preceding claims, wherein The semiconductor device includes a Kelvin connector between the control connector and the first load connector.

6. A semiconductor device according to any one of the preceding claims, wherein The semiconductor device is either a through-hole device (THD) or a surface mount device (SMD).

7. A semiconductor device according to any one of the preceding claims, wherein The semiconductor device includes a non-monolithic lead frame, wherein a second load connector is attached to the non-monolithic lead frame via a connecting wire.

8. A semiconductor device according to any one of the preceding claims, wherein The connector is curved.

9. A system comprising: A right-hand semiconductor device according to any one of the preceding claims; A left-hand semiconductor device comprising: a control connector, a first load connector, and a second load connector; wherein the connectors are arranged in the same plane and protrude from the package of the semiconductor device to form fingers of a left-hand arrangement, wherein the control connector is followed by a first load connector, which is followed by a second load connector, wherein the second load connector is the thumb of the left-hand arrangement; or The first load connector is followed by the second load connector, and the second load connector is followed by the control connector, wherein the control connector is the thumb of the left-hand arrangement structure. wherein the package comprises a top side and a bottom side opposite the top side, wherein the left-hand arrangement is viewed from a top view; and A connector device for connecting the left-hand semiconductor device and the right-hand semiconductor device to the gate driver IC.

10. The system according to claim 9, wherein: The connector device is a layered substrate, and the substrate comprises: lead frame; a first load layer connected to a first load connector of the two semiconductor devices; a control layer connected to control connectors of two semiconductor devices; The coverage area of ​​the control layer is smaller than the coverage area of ​​the first load layer; the control layer is arranged in a plane parallel to the plane where the first load layer is arranged; and the control layer is symmetrically arranged on top of the first load layer.

11. The system according to claim 9 or 10, wherein: The second load connector of each semiconductor device is connected to a lead frame, wherein the lead frame is a layer parallel to the plane of each of the control layer and the first load layer.

12. The system according to any one of claims 9 to 11, wherein: The left-hand semiconductor device is a mirror image of the right-hand semiconductor device, and the left-hand semiconductor device and the right-hand semiconductor device are arranged in the same plane so that the thumb of the right-hand semiconductor device and the thumb of the left-hand semiconductor device are not strung together.

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