Semiconductor device and electroplating method

Abstract

The invention discloses a semiconductor device and an electroplating method, and belongs to the technical field of semiconductors. The semiconductor device comprises an epitaxial wafer, a barrier layer, a seed layer and a main metal layer which are stacked in sequence, the barrier layer is a Ti layer, the seed layer is an Au layer or an Ag layer, and the main metal layer is an Au layer or a Cu layer; the thickness of the barrier layer is smaller than that of the seed layer, and the thickness of the seed layer is smaller than that of the main metal layer. The embodiment of the invention can improve the uniformity of the plating layer, thereby improving the performance of the semiconductor device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and an electroplating method. Background Art

[0002] GaN RF devices are semiconductor devices with significant advantages in high-frequency and high-power applications.

[0003] In related technologies, in the process of preparing GaN RF devices, an electroplating process is required to deposit metal layers, such as electrodes, interconnects, etc.

[0004] However, the electro-kinetic process in related technologies has problems such as uneven coating thickness and high surface roughness, which leads to large microwave signal transmission loss of GaN RF devices and affects signal transmission efficiency. Summary of the Invention

[0005] The present disclosure provides a semiconductor device and electroplating method that can improve the uniformity of the plating layer, thereby improving the performance of the semiconductor device. The technical solution is as follows:

[0006] In one aspect, an embodiment of the present disclosure provides a semiconductor device comprising an epitaxial wafer, a barrier layer, a seed layer, and a main metal layer stacked in sequence;

[0007] The barrier layer is a Ti layer, the seed layer is an Au layer or an Ag layer, and the main metal layer is an Au layer or a Cu layer;

[0008] The thickness of the barrier layer is smaller than that of the seed layer, and the thickness of the seed layer is smaller than that of the main metal layer.

[0009] In an implementation of the present disclosure, the thickness of the barrier layer is 5 to 15 nm, the thickness of the seed layer is 50 to 100 nm, and the thickness of the main metal layer is 1 to 3 μm.

[0010] On the other hand, an embodiment of the present disclosure provides an electroplating method applicable to the semiconductor device described in the previous aspect, the electroplating method comprising:

[0011] providing an epitaxial wafer;

[0012] Depositing a barrier layer on one side of the epitaxial wafer, wherein the barrier layer is a Ti layer;

[0013] Depositing a seed layer on a side of the barrier layer facing away from the epitaxial wafer, wherein the seed layer is an Au layer or an Ag layer, and the thickness of the barrier layer is smaller than the thickness of the seed layer;

[0014] depositing a main metal layer on the side of the seed layer away from the barrier layer, the main metal layer being an Au layer or a Cu layer, the thickness of the seed layer being less than the thickness of the main metal layer.

[0015] In one implementation of the present disclosure, a barrier layer is deposited on one side of the epitaxial wafer, comprising:

[0016] cleaning the epitaxial wafer;

[0017] depositing the barrier layer with a thickness of 5-15 nm on one side of the epitaxial wafer.

[0018] In one implementation of the present disclosure, a seed layer is deposited on the side of the barrier layer away from the epitaxial wafer, comprising:

[0019] configuring an electroplating solution;

[0020] setting the current density of the pulse current to a first density value, setting the pulse frequency of the pulse current to 100-200 Hz, and controlling the duty cycle to 30%-40%;

[0021] depositing the seed layer with a thickness of 50-100 nm.

[0022] In one implementation of the present disclosure, an electroplating solution is configured, comprising:

[0023] providing an Au electroplating solution;

[0024] adding nanoscale conductive particles into the Au electroplating solution.

[0025] In one implementation of the present disclosure, a main metal layer is deposited on the side of the seed layer away from the barrier layer, comprising:

[0026] configuring an electroplating solution;

[0027] setting the current density of the pulse current to a second density value, setting the pulse frequency of the pulse current to 50-100 Hz, and controlling the duty cycle to 50%-70%;

[0028] depositing the main metal layer with a thickness of 1-3 μm.

[0029] In one implementation of the present disclosure, an electroplating solution is configured, comprising:

[0030] providing a Cu electroplating solution;

[0031] adding a salt-based organic additive into the Cu electroplating solution.

[0032] In one implementation of the present disclosure, after the seed layer is deposited on the side of the barrier layer away from the epitaxial wafer, the electroplating method comprises:

[0033] The annealing time is set to 20-40 min, and the annealing temperature is set to 200-400 DEG C.

[0034] The annealing operation is performed.

[0035] In an implementation form of the present disclosure, the electroplating method further comprises:

[0036] An adjustable auxiliary anode structure is adopted to dynamically compensate the electric field intensity at the edge of the semiconductor device according to the structure and electroplating requirements of the semiconductor device.

[0037] The technical solution provided by the embodiments of the present disclosure has at least the following beneficial effects:

[0038] The semiconductor device provided by the embodiments of the present disclosure is provided with a barrier layer on one side of an epitaxial wafer, the barrier layer is a Ti layer, and the diffusion of metal atoms in the subsequent process of electroplating a seed layer and a main metal layer can be effectively prevented. One side of the barrier layer is deposited with a seed layer, the seed layer is an Au layer or an Ag layer, and a layer of uniform metal nucleation point can be formed, thereby laying a good foundation for the subsequent deposition of the main metal layer. With the assistance of the barrier layer and the seed layer, the main metal layer can be deposited with high quality, and the flatness and uniformity thereof are ensured, thereby avoiding large microwave signal transmission loss of the semiconductor device and affecting the signal transmission efficiency.

[0039] That is, the diffusion of metal atoms in the electroplating process is avoided by the barrier layer, and the flatness and uniformity of the electroplating of the main metal layer are ensured by the seed layer, thereby effectively improving the electroplating quality of the semiconductor device, effectively reducing the microwave signal transmission loss of the semiconductor device when used as a radio frequency device, and ensuring the signal transmission efficiency. Moreover, since the barrier layer and the seed layer are smaller than the main metal layer, even if the barrier layer and the seed layer are additionally provided, the overall size of the semiconductor device will not be greatly affected. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0041] Figure 1 is a structural schematic diagram of a semiconductor device provided by an embodiment of the present disclosure;

[0042] Figure 2 is a flowchart of an electroplating method provided by an embodiment of the present disclosure;

[0043] Figure 3is a flowchart of another electroplating method provided by the embodiments of the present disclosure.

[0044] Reference signs:

[0045] 10, epitaxial wafer;

[0046] 20, barrier layer;

[0047] 30, seed layer;

[0048] 40, main metal layer. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be further described in detail below with reference to the drawings.

[0050] GaN radio frequency device is a semiconductor device, which has obvious advantages in high frequency and high power applications.

[0051] In the related art, in the process of preparing GaN radio frequency devices, an electroplating process is needed to deposit metal layers such as electrodes, interconnection lines, etc.

[0052] However, the electroplating process in the related art has the problems of uneven plating layer thickness and high surface roughness, resulting in large microwave signal transmission loss of GaN radio frequency devices. Moreover, the nickel-palladium-gold plating layer has poor adhesion and high contact resistance, which affects the signal transmission efficiency. The electroplating uniformity of complex structure devices is poor, and the problems of considering specific nature and impedance matching cannot be taken into account, which affect the signal transmission efficiency.

[0053] In order to solve the above technical problems, the embodiments of the present disclosure provide a semiconductor device, which is a GaN radio frequency device, Figure 1 is a structural schematic diagram of the semiconductor device, see Figure 1 In the present embodiment, the semiconductor device includes an epitaxial wafer 10, a barrier layer 20, a seed layer 30 and a main metal layer 40 which are sequentially stacked. The barrier layer 20 is a Ti layer, the seed layer 30 is an Au layer or an Ag layer, and the main metal layer 40 is an Au layer or a Cu layer. The thickness of the barrier layer 20 is less than the thickness of the seed layer 30, and the thickness of the seed layer 30 is less than the thickness of the main metal layer 40.

[0054] The semiconductor device provided by the embodiment of the present disclosure is provided with a barrier layer 20 on one side of the epitaxial wafer 10, the barrier layer 20 is a Ti layer, and the diffusion of metal atoms in the subsequent electroplating seed layer 30 and main metal layer 40 process can be effectively prevented. The seed layer 30 is deposited on one side of the barrier layer 20, the seed layer 30 is an Au layer or an Ag layer, and a layer of uniform metal nucleation point can be formed, thereby laying a good foundation for the subsequent deposition of the main metal layer 40. With the assistance of the barrier layer 20 and the seed layer 30, the main metal layer 40 can be deposited with high quality, and the flatness and uniformity thereof are ensured, thereby avoiding the large microwave signal transmission loss of the semiconductor device and affecting the signal transmission efficiency.

[0055] That is, the diffusion of metal atoms in the electroplating process is avoided by the barrier layer 20, and the electroplating flatness and uniformity of the main metal layer 40 are ensured by the seed layer 30, thereby effectively improving the electroplating quality of the semiconductor device, effectively reducing the microwave signal transmission loss of the semiconductor device when used as a radio frequency device, and ensuring the signal transmission efficiency. Moreover, since the barrier layer 20 and the seed layer 30 are smaller than the main metal layer 40, even if the barrier layer 20 and the seed layer 30 are additionally provided, the overall size of the semiconductor device will not be greatly affected.

[0056] Exemplarily, the thickness of the barrier layer 20 is 5-15 nm, the thickness of the seed layer 30 is 50-100 nm, and the thickness of the main metal layer 40 is 1-3 μm.

[0057] In the embodiment, the thickness of the barrier layer 20 is 10 nm, the thickness of the seed layer 30 is 50 nm, and the thickness of the main metal layer 40 is 2 μm.

[0058] The barrier layer 20, the seed layer 30 and the main metal layer 40 are provided with the above thickness, which can ensure the functionality of the semiconductor device and avoid the decrease of the preparation efficiency caused by the excessive thickness.

[0059] Figure 2 A flowchart of an electroplating method provided by the embodiment of the present disclosure is combined with Figure 2 In the embodiment, the electroplating method comprises the following steps.

[0060] Step 201: providing an epitaxial wafer 10.

[0061] Step 202: depositing a barrier layer 20 on one side of the epitaxial wafer 10, the barrier layer 20 being a Ti layer.

[0062] Step 203: depositing a seed layer 30 on the side of the barrier layer 20 away from the epitaxial wafer 10, the seed layer 30 being an Au layer or an Ag layer, and the thickness of the barrier layer 20 being smaller than the thickness of the seed layer 30.

[0063] Step 204: depositing a main metal layer 40 on the side of the seed layer 30 opposite to the barrier layer 20, the main metal layer 40 being an Au layer or a Cu layer, the thickness of the seed layer 30 being less than the thickness of the main metal layer 40.

[0064] The semiconductor device prepared by the electroplating method provided by the embodiments of the present disclosure has the barrier layer 20 of the Ti layer on one side of the epitaxial wafer 10, which can effectively prevent the diffusion of metal atoms in the subsequent electroplating processes of the seed layer 30 and the main metal layer 40. The seed layer 30 of the Au layer or the Ag layer is deposited on one side of the barrier layer 20, which can form a layer of uniform metal nucleation points, thereby laying a good foundation for the subsequent deposition of the main metal layer 40. With the assistance of the barrier layer 20 and the seed layer 30, the main metal layer 40 can be deposited with high quality, ensuring its flatness and uniformity, thereby avoiding the large microwave signal transmission loss of the semiconductor device and affecting the signal transmission efficiency.

[0065] That is, the diffusion of metal atoms in the electroplating process is avoided by the barrier layer 20, and the flatness and uniformity of the electroplating of the main metal layer 40 are ensured by the seed layer 30, which effectively improves the electroplating quality of the semiconductor device, reduces the microwave signal transmission loss of the semiconductor device when used as a radio frequency device, and ensures the signal transmission efficiency. Moreover, since the barrier layer 20 and the seed layer 30 are both smaller than the main metal layer 40, the addition of the barrier layer 20 and the seed layer 30 will not greatly affect the overall size of the semiconductor device.

[0066] Figure 3 The flowchart of another electroplating method provided by the embodiments of the present disclosure is combined with the flowchart of the electroplating method provided by the embodiments of the present disclosure. Figure 3 In the present embodiment, the electroplating method comprises:

[0067] Step 301: providing an epitaxial wafer 10.

[0068] In the present embodiment, the epitaxial wafer 10 comprises a substrate and an epitaxial layer grown on one side of the substrate.

[0069] Step 302: cleaning the epitaxial wafer 10.

[0070] In step 302, the surface of the epitaxial wafer 10 is subjected to plasma cleaning to remove impurities and contaminants on the surface of the epitaxial wafer 10, so as to improve the bonding force between the subsequent plated layer and the surface of the epitaxial wafer 10.

[0071] It is worth noting that the cleaning of the epitaxial wafer 10 is mainly to clean the GaN surface of the epitaxial layer of the epitaxial wafer 10.

[0072] Step 303: depositing a barrier layer 20 on one side of the epitaxial wafer 10.

[0073] In step 303, the barrier layer 20 is a Ti layer, and the thickness of the barrier layer 20 is 5-15 nm.

[0074] In this embodiment, the thickness of the barrier layer 20 is 10 nm.

[0075] Step 304: depositing a seed layer 30 on the side of the barrier layer 20 opposite to the epitaxial wafer 10.

[0076] In this embodiment, the seed layer 30 is an Au layer or an Ag layer, and the thickness of the barrier layer 20 is less than the thickness of the seed layer 30.

[0077] In this embodiment, step 304 includes the following steps:

[0078] Step 3041: configuring an electroplating solution.

[0079] In this embodiment, the electroplating solution in step 3041 is configured in the following manner:

[0080] First, an Au electroplating solution is provided.

[0081] Then, nanoscale conductive particles are added to the Au electroplating solution.

[0082] Exemplarily, the nanoscale conductive particles are graphene or carbon nanotubes.

[0083] In the above implementation, the nanoscale conductive particles can reduce the resistivity of the electroplating solution, thereby improving the current efficiency in the electroplating process and making the plated layer more uniform and dense.

[0084] In this embodiment, the content of graphene in the electroplating solution is 0.8 g / L, i.e., 0.8 g of graphene is contained in 1 L of the electroplating solution.

[0085] Alternatively, the electroplating solution contains 0.5-2 wt% of nanoscale conductive particles.

[0086] Step 3042: setting the current density of the pulse current to a first density value, setting the pulse frequency of the pulse current to 100-200 Hz, and controlling the duty cycle to 30%-40%.

[0087] In this embodiment, the pulse frequency of the pulse current is set to 150 Hz, and the duty cycle is controlled to 35%.

[0088] Step 3043: depositing the seed layer 30 with a thickness of 50-100 nm.

[0089] In this embodiment, the thickness of the seed layer 30 is 50 nm.

[0090] In the above implementation, the seed layer 30 is Au uniformly arranged nanoparticles, as a uniform metal nucleation point, thereby laying a good foundation for subsequent deposition of the main metal layer 40.

[0091] In the process of depositing the main metal layer 40, an adjustable auxiliary anode structure is used to dynamically compensate the electric field intensity of the edge of the semiconductor device according to the structure of the semiconductor device and the plating requirements.

[0092] Step 305: depositing the main metal layer 40 on the side of the seed layer 30 opposite to the barrier layer 20.

[0093] In the embodiment, the main metal layer 40 is an Au layer or a Cu layer, and the thickness of the seed layer 30 is less than the thickness of the main metal layer 40.

[0094] In the embodiment, step 305 includes the following steps:

[0095] Step 3051: configuring a plating solution.

[0096] It is worth noting that the plating solution in step 3051 is configured separately, which is irrelevant to the plating solution in step 3041.

[0097] In the embodiment, the plating solution in step 3051 is configured by the following way:

[0098] First, a Cu plating solution is provided.

[0099] Then, a salt-based organic additive is added into the Cu plating solution.

[0100] Exemplarily, the salt-based organic additive is saccharin.

[0101] In the above implementation, the salt-based organic additive can inhibit the release of hydrogen bubbles in the plating process, avoid the micro-defects caused by the attachment of hydrogen bubbles, and thus can control the size of the micro-defects to be no more than 50 nm.

[0102] In the embodiment, the content of saccharin in the plating solution is 1.5 g / L, that is, 1.5 g of saccharin is contained in 1 L of the plating solution.

[0103] Alternatively, the plating solution contains 0.1-1 wt% of the salt-based organic additive.

[0104] Step 3052: setting the current density of the pulse current to a second density value, setting the pulse frequency of the pulse current to 50-100 Hz, and controlling the duty cycle to 50%-70%.

[0105] It is worth mentioning that the second density value is higher than the first density value, that is, in the process of electroplating the seed layer 30, a low current density pulse current is used, and in the process of electroplating the main metal layer 40, a high current density pulse current is used.

[0106] In the embodiment, the pulse frequency of the pulse current is set to 50 Hz, and the duty cycle is controlled to 60%.

[0107] Step 3053: depositing the main metal layer 40 with a thickness of 1-3 μm.

[0108] In the process of depositing the main metal layer 40, an adjustable auxiliary anode structure is used to dynamically compensate the electric field intensity at the edge of the semiconductor device according to the structure of the semiconductor device and the electroplating requirements.

[0109] In the embodiment, the thickness of the main metal layer 40 is 2 μm.

[0110] The adjustable auxiliary anode structure includes a main anode, an adjustable auxiliary anode, and a feedback control system, wherein the main anode is fixed at the bottom of the electroplating tank and is used to provide a basic current. The adjustable auxiliary anode is composed of an array of multiple independently controlled sub-anodes, which surrounds the semiconductor device or is embedded near the complex structure, and realizes local electric field compensation by dynamically adjusting the position, shape, and current input of each sub-anode. The feedback control system monitors the current density distribution on the surface of the semiconductor device in real time (such as through a sensor or a simulation model), and dynamically adjusts the parameters of the adjustable auxiliary anode.

[0111] In the embodiment, the surface electric field distribution of the device can be simulated by finite element analysis, such as COMSOL, to identify weak / strong field areas and thus to model the electric field. According to the electric field model, sub-anodes are deployed in key areas (such as the edge and the trench of the semiconductor device) to ensure coverage flexibility. In the process of actual adjustment, the sensor feeds back the current density data to the feedback control system, so as to dynamically adjust the current output of each sub-anode, such as reducing the current of the sub-anode at the edge by 10%-20% and increasing the current of the sub-anode at the center by 15%-30%.

[0112] The dynamic compensation of the electric field intensity at the edge of the semiconductor device is mainly carried out from three aspects.

[0113] The first is edge electric field suppression. In the edge area of the semiconductor device, the adjustable auxiliary anode inputs a reverse compensation current to weaken the edge electric field concentration phenomenon.

[0114] The second is complex structure enhancement. For high aspect ratio trenches, the position of the adjustable auxiliary anode is adjusted to the vicinity of the complex structure to enhance the local electric field intensity and ensure uniform deposition of metal ions.

[0115] Third, the multi-parameter coordinated regulation, combined with the pulse plating duty cycle / frequency variation, adjustable auxiliary anode current and main anode pulse synchronous modulation are adjusted to realize precise time and space control.

[0116] Step 306: annealing operation is performed.

[0117] Exemplarily, the annealing time is set to 20-40 min, and the annealing temperature is set to 200-400 DEG C.

[0118] In this embodiment, the annealing time is set to 30 min, and the annealing temperature is set to 300 DEG C.

[0119] In the above implementation mode, through the annealing treatment, the stress in the plating layer can be eliminated, the conductivity of the plating layer is improved, and the performance of the device is further optimized.

[0120] The semiconductor device prepared by the electroplating method provided by the embodiment of the present disclosure has a barrier layer 20 on one side of the epitaxial wafer 10, and the barrier layer 20 is a Ti layer, which can effectively prevent the diffusion of metal atoms in the subsequent electroplating seed layer 30 and main metal layer 40 process. One side of the barrier layer 20 is deposited with a seed layer 30, and the seed layer 30 is an Au layer or an Ag layer, which can form a layer of uniform metal nucleation point, thereby laying a good foundation for the subsequent deposition of the main metal layer 40. With the assistance of the barrier layer 20 and the seed layer 30, the main metal layer 40 can be deposited with high quality, ensuring its flatness and uniformity, thereby avoiding large microwave signal transmission loss of the semiconductor device, affecting the signal transmission efficiency.

[0121] That is, the diffusion of metal atoms in the electroplating process is avoided by the barrier layer 20, and the electroplating flatness and uniformity of the main metal layer 40 are ensured by the seed layer 30, effectively improving the electroplating quality of the semiconductor device, so that the microwave signal transmission loss of the semiconductor device is effectively reduced when it is used as a radio frequency device, and the signal transmission efficiency is ensured. Moreover, since the barrier layer 20 and the seed layer 30 are smaller than the main metal layer 40, even if the barrier layer 20 and the seed layer 30 are added, it will not greatly affect the overall size of the semiconductor device.

[0122] Through experiments, the semiconductor device prepared by the electroplating method provided by the embodiment of the present disclosure has at least the following beneficial effects:

[0123] 1. The uniformity of the plating layer is improved, and the deviation of the main metal layer 40 is reduced from ±25% to ±5%, covering high aspect ratio structures.

[0124] 2. The impedance is optimized, and the impedance is as low as 40.51Ω at 2-28GHz.

[0125] 3. High frequency performance enhancement, semiconductor device power added efficiency (PAE) > 70%, suitable for 5G base station power amplifier, satellite communication device, etc., which can greatly reduce manufacturing cost and improve reliability.

[0126] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The words "first", "second", "third", and the like used in the description and the claims of this disclosure do not necessarily have any order or sequence or importance, but are used to distinguish different components. Similarly, the words "one" or "a" or the like do not mean quantity limitation, but mean at least one. The words "include" or "contain" or the like mean that the elements or objects appearing before "include" or "contain" cover the elements or objects listed after "include" or "contain" and their equivalents, and do not exclude other elements or objects. The words "connect" or "connected" or the like are not limited to physical or mechanical connection, but can include electrical connection, whether direct or indirect. The words "up", "down", "left", "right", "top", "bottom", etc. are only used to indicate relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships may also change accordingly.

[0127] The above is not any form of limitation on the disclosure, although the disclosure has been disclosed as above through examples, but is not intended to limit the disclosure, any person skilled in the art, without departing from the technical solution of the disclosure, can make some changes or modifications to the equivalent embodiments of the disclosed technical content, but as long as it does not deviate from the technical solution of the disclosure, any simple modification, equivalent change and modification of the above examples according to the technical essence of the disclosure, all still belong to the scope of the technical solution of the disclosure.

Claims

1. A semiconductor device, characterized in that: It comprises an epitaxial wafer (10), a barrier layer (20), a seed layer (30) and a main metal layer (40) stacked in sequence; The barrier layer (20) is a Ti layer, the seed layer (30) is an Au layer or an Ag layer, and the main metal layer (40) is an Au layer or a Cu layer; The thickness of the barrier layer (20) is smaller than the thickness of the seed layer (30), and the thickness of the seed layer (30) is smaller than the thickness of the main metal layer (40).

2. The semiconductor device according to claim 1, wherein The thickness of the barrier layer (20) is 5 to 15 nm, the thickness of the seed layer (30) is 50 to 100 nm, and the thickness of the main metal layer (40) is 1 to 3 μm.

3. An electroplating method, characterized in that: The electroplating method is applicable to the semiconductor device according to claim 1 or 2, and the electroplating method comprises: Providing an epitaxial wafer (10); Depositing a barrier layer (20) on one side of the epitaxial wafer (10), wherein the barrier layer (20) is a Ti layer; Depositing a seed layer (30) on a side of the barrier layer (20) facing away from the epitaxial wafer (10), wherein the seed layer (30) is an Au layer or an Ag layer, and the thickness of the barrier layer (20) is less than the thickness of the seed layer (30); A main metal layer (40) is deposited on the side of the seed layer (30) facing away from the barrier layer (20), the main metal layer (40) being an Au layer or a Cu layer, and the thickness of the seed layer (30) being smaller than the thickness of the main metal layer (40).

4. The electroplating method according to claim 3, wherein: Depositing a barrier layer (20) on one side of the epitaxial wafer (10) comprises: Cleaning the epitaxial wafer (10); The barrier layer (20) having a thickness of 5 to 15 nm is deposited on one side of the epitaxial wafer (10).

5. The electroplating method according to claim 3, wherein: Depositing a seed layer (30) on a side of the barrier layer (20) facing away from the epitaxial wafer (10), comprising: Prepare electroplating solution; The current density of the pulse current is set to a first density value, the pulse frequency of the pulse current is set to 100 to 200 Hz, and the duty cycle is controlled to be 30% to 40%; The seed layer (30) is deposited to a thickness of 50-100 nm.

6. The electroplating method according to claim 5, characterized in that Prepare the plating solution, including: Provide Au electroplating solution; Nano-scale conductive particles are added into the Au electroplating solution.

7. The electroplating method according to claim 3, wherein: Depositing a main metal layer (40) on a side of the seed layer (30) facing away from the barrier layer (20), comprising: Prepare electroplating solution; The current density of the pulse current is set to a second density value, the pulse frequency of the pulse current is set to 50 to 100 Hz, and the duty cycle is controlled to be 50% to 70%; The main metal layer (40) is deposited to a thickness of 1 to 3 μm.

8. The electroplating method according to claim 7, wherein: Prepare the plating solution, including: Provide Cu electroplating solution; A salt-based organic additive is added to the Cu electroplating solution.

9. The electroplating method according to claim 3, wherein: After depositing a main metal layer (40) on a side of the seed layer (30) facing away from the barrier layer (20), the electroplating method comprises: Set the annealing time to 20-40 minutes and the annealing temperature to 200-400°C; Perform annealing operation.

10. The electroplating method according to claim 3, wherein: The electroplating method further comprises: An adjustable auxiliary anode structure is adopted to dynamically compensate the electric field intensity at the edge of the semiconductor device according to the structure and electroplating requirements of the semiconductor device.

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