Synchronous rectification control method and device
By adjusting the turn-off point of the synchronous rectifier at or near the current zero-crossing point, the problem of inaccurate judgment of the body diode conduction time in the prior art is solved, and the system efficiency and power conversion efficiency are improved.
Patent Information
- Application Number
- CN202511001008.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-18
- Publication Date
- 2025-10-17
AI Technical Summary
Existing technologies cannot accurately determine the body diode conduction time of SiC MOSFETs and synchronous rectifiers in resonant converters used in high-voltage applications, resulting in increased power losses and reduced system efficiency.
By adopting the method of blanking signal and step adjustment step size, the turn-off point of the synchronous rectifier is adjusted at or near the current zero-crossing point, thereby reducing the body diode conduction time.
The body diode conduction time is minimized to the greatest extent, improving system efficiency and power conversion efficiency.
Smart Images
Figure CN120811083A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a synchronous rectification control method and device, in particular to a synchronous rectification control method and device for reducing the body diode conduction time to the maximum extent. BACKGROUND
[0002] Synchronous rectification is a technology that uses a switching device to replace a rectifier diode. The on-state voltage of the switching device is lower than that of the diode, which can reduce power loss and improve system efficiency. Synchronous rectification technology is widely used in server power supplies, vehicle chargers, computer adapters and other high-efficiency high-power-density power supply devices.
[0003] The difficulty of synchronous rectification technology lies in how to generate a suitable driving signal for the controllable switching device, minimize the body diode conduction time, and avoid the generation of reverse current.
[0004] Referring to Figure 1 and Figure 2 , which are respectively a voltage and current processing circuit schematic diagram of a synchronous rectification tube of a prior art resonant converter and a first timing diagram of a synchronous rectification tube driving signal and a comparator output waveform. Figure 1 The synchronous rectification tube includes a CLLC resonant converter, a source-drain voltage sampling circuit and a source-drain voltage comparison circuit. Take the synchronous rectification tube Q2s as an example. Figure 2 From top to bottom, they are: the driving signal Vgs Q2s of the synchronous rectification tube Q2s, the current I Q2s flowing through the synchronous rectification tube Q2s, the sampling signal of the drain-source voltage Vds Q2s and the comparator output waveform CMP_out. The drain-source voltage Vds Q2s when the body diode of the synchronous rectification tube Q2s is turned on is less than the drain-source voltage Vds Q2s when the channel is turned on. The sampling signal of the drain-source voltage Vds Q2s is compared with the reference voltage Vref (determined by experiment), and the body diode conduction can be distinguished. The output waveform CMP_out is high, which represents the body diode conduction. Therefore, the synchronous rectification driving can be adjusted according to the body diode conduction state. Among them, Figure 2 Vds Q2s are all the sampling signals of the drain-source voltage Vds Q2s .
[0005] In addition, the prior art also uses a counter to count the output pulses of the comparator. The pulse width of the synchronous rectifier is controlled according to the count value. The turn-on time is fixed, the turn-off time is optimized, and the high level of the turn-on time always exists. Within a detection window, when two high levels are detected, it indicates that the body diode is still conducting after the synchronous rectifier is turned off, and the pulse width of the synchronous rectifier needs to be increased. When only one high level is detected, the body diode is not conducting after being turned off, and the pulse width of the synchronous rectifier needs to be reduced. Finally, the two critical states are alternately changed to minimize the body diode conduction time.
[0006] The aforementioned counter scheme cannot be applied to SiC MOSFET (Silicon Carbide MOSFET). Please refer to Figure 3 The second timing diagram of the driving signal of the synchronous rectifier and the output waveform of the comparator is shown in FIG. 4. When full load, the current is large, and the voltage drop generated by the current flowing through the channel is large. The comparator may generate 3 pulses in a period, and when light load, the comparator generates 2 pulses in a period. Therefore, the number of pulses cannot accurately determine the conduction of the body diode. Among them, Figure 3 Vds in FIG. 3 Q2s are the drain-source voltages Vds Q2s of the sampling signals.
[0007] In addition, the counter scheme cannot be applied to resonant converters in high-voltage applications. The drain-source voltage will oscillate due to parasitic parameters. When a large dv / dt acts on the junction capacitance of the diode in the sampling circuit, a corresponding charging and discharging current will be generated. When the voltage drop generated by the pull-up resistor in the sampling circuit is large, an additional high level will be triggered, and the conduction of the body diode cannot be accurately determined.
[0008] Therefore, how to design a synchronous rectification control method and device to make the turn-off point of the synchronous rectifier at or near the zero-crossing point of the current flowing through the synchronous rectifier to minimize the body diode conduction time is an important research topic for the present inventors. SUMMARY
[0009] An object of the present application is to provide a synchronous rectification control method to solve the problems of the prior art.
[0010] To achieve the above object, the application provides a synchronous rectification control method applied to synchronous rectification control of a switching power supply. off off off off off
[0011] In an embodiment, the switching power supply comprises a primary side switch and a secondary side switch, and the synchronous rectification tube is the secondary side switch.
[0012] In an embodiment, the end time of the effective interval of the blanking signal is the same as the end time of the driving signal of the synchronous rectification tube.
[0013] In an embodiment, the invalid interval of the blanking signal is not more than half of the oscillation period of the drain-source voltage.
[0014] In an embodiment, when the switching frequency of the switching power supply is greater than the resonance frequency, the start time of the driving signal of the synchronous rectification tube and the end time of the driving signal of the synchronous rectification tube change synchronously, so that the duty cycle of the driving signal of the synchronous rectification tube is set to a fixed value, and the duty cycle of the driving signal of the synchronous rectification tube is less than 50%.
[0015] In an embodiment, the switching power supply is a resonant converter.
[0016] Another object of the application is to provide a device comprising a switching power supply, a sampling circuit and a control unit, which solves the problems of the prior art.
[0017] To achieve the above object, the switching power supply comprises a primary side circuit, a secondary side circuit and an energy storage unit. The primary side circuit comprises at least one primary side switch bridge arm, and the primary side switch bridge arm comprises a primary side switch. The secondary side circuit comprises at least one secondary side switch bridge arm, and the secondary side switch bridge arm comprises a secondary side switch. The energy storage unit is arranged between the primary side circuit and the secondary side circuit. A sampling circuit is used to sample the drain-source voltage of the synchronous rectifier in the current switching period to obtain a first sampling signal. A control unit is used to receive the first sampling signal, a voltage reference signal and a blanking signal, and generate a state signal, wherein the blanking signal comprises an effective interval and an ineffective interval. The sampling circuit is further used to sample the state signal to obtain a second sampling signal. The control unit is used to perform the following steps: comparing the first sampling signal and the voltage reference signal to obtain a comparison signal; obtaining the state signal according to the blanking signal and the comparison signal, wherein the value of the state signal is a certain value in the effective interval, and the value of the state signal changes with the comparison signal in the ineffective interval; if the second sampling signal flips in the ineffective interval of the blanking signal, the control unit adjusts the ending time t off of the drive signal of the synchronous rectifier in the subsequent switching period to t off ’+△T, and if the second sampling signal does not flip in the ineffective interval of the blanking signal, the control unit adjusts the ending time t off of the drive signal of the synchronous rectifier in the subsequent switching period to t off ’-△T, wherein t off ’ is the ending time of the drive signal of the synchronous rectifier in the current switching period, and △T is a step adjustment step.
[0018] In an embodiment, the synchronous rectifier is the secondary side switch, and when the switching frequency of the switching power supply is less than or equal to the resonant frequency, the turn-on time of the drive signal of the synchronous rectifier lags behind the turn-on time of the drive signal of the primary side switch by a preset value.
[0019] In an embodiment, the ending time of the effective interval of the blanking signal is the same as the ending time of the drive signal of the synchronous rectifier.
[0020] In an embodiment, the ineffective interval of the blanking signal is not greater than half of the oscillation period of the drain-source voltage.
[0021] In an embodiment, when the switching frequency of the switching power supply is greater than the resonant frequency, the starting time of the drive signal of the synchronous rectifier and the ending time of the drive signal of the synchronous rectifier change synchronously, so that the duty cycle of the drive signal of the synchronous rectifier is set to a fixed value, and the duty cycle of the drive signal of the synchronous rectifier is less than 50%.
[0022] In one embodiment, the control unit comprises a first comparator and a digital signal processor. The first comparator is electrically connected to the sampling circuit for receiving the first sampling signal and the voltage reference signal, and generating a comparison signal. The digital signal processor comprises a second comparator, which is electrically connected to the first comparator for receiving the blanking signal and the comparison signal, and generating a status signal.
[0023] In one embodiment, the control unit comprises a first comparator, a digital isolator and a digital signal processor. The first comparator is connected to the sampling circuit for receiving the first sampling signal and the voltage reference signal, and generating a comparison signal. The digital isolator is electrically connected to the first comparator. The digital signal processor comprises a second comparator, which is electrically connected to the digital isolator. The second comparator is for receiving the blanking signal and the comparison signal through the digital isolator, and generating a status signal.
[0024] In one embodiment, the control unit comprises a comparator and a digital signal processor. The comparator is connected to the sampling circuit for receiving the first sampling signal, the voltage reference signal and the blanking signal, and generating a status signal. The digital signal processor comprises a sampling circuit for receiving the status signal, and generating a second sampling signal.
[0025] In one embodiment, the control unit comprises a comparator, a digital isolator and a digital signal processor. The comparator is connected to the sampling circuit for receiving the first sampling signal, the voltage reference signal and the blanking signal, and generating a status signal. The digital isolator is electrically connected to the comparator. The digital signal processor is electrically connected to the digital isolator, and receives the status signal through the digital isolator.
[0026] In one embodiment, the switching power supply is a resonant converter.
[0027] By the proposed synchronous rectification control method and device, the application has the following features and advantages: by introducing the blanking signal and providing step adjustment step length adjustment, the turn-off point of the synchronous rectification tube is on or adjacent to the zero crossing point of the current flowing through the synchronous rectification tube, so as to realize the maximum reduction of the body diode conduction time.
[0028] In order to further understand the technology, means and technical effects adopted by the application to achieve the predetermined purposes, please refer to the following detailed description and drawings of the application. It is believed that the purposes, features and characteristics of the application can be understood in depth and specifically from the above, however, the drawings are provided for reference and illustration only, and are not used to limit the application. BRIEF DESCRIPTION OF DRAWINGS
[0029] Figure 1 : Schematic diagram of voltage and current processing circuit of synchronous rectification tube of prior art resonant converter.
[0030] Figure 2 : This is the first timing diagram of the synchronous rectifier drive signal and the comparator output waveform in the prior art.
[0031] Figure 3 : This is the second timing diagram of the synchronous rectifier drive signal and the comparator output waveform in the prior art.
[0032] Figure 4A : is a schematic diagram of a first embodiment of a voltage and current processing circuit of a synchronous rectifier tube of a switching power supply of the present invention.
[0033] Figure 4B : is a schematic diagram of a second embodiment of the voltage and current processing circuit of the synchronous rectifier tube of the switching power supply of the present invention.
[0034] Figure 4C : is a schematic diagram of a third embodiment of a voltage and current processing circuit of a synchronous rectifier tube of a switching power supply of the present invention.
[0035] Figure 4D : is a schematic diagram of a fourth embodiment of a voltage and current processing circuit of a synchronous rectifier tube of a switching power supply of the present invention.
[0036] Figure 5 : A schematic waveform diagram of the voltage and current of the synchronous rectifier tube when the switching frequency of the switching power supply of the present invention is less than or equal to the resonant frequency.
[0037] Figure 6 : A schematic waveform diagram of an embodiment of the blanking signal function of the present invention.
[0038] Figure 7 : A schematic waveform diagram of another embodiment of the blanking signal function of the present invention.
[0039] Figures 8A-8D : A schematic waveform diagram of the dynamic adjustment of the synchronous positive flow tube drive signal of the present invention.
[0040] Figure 9 : A waveform diagram of the switching frequency of the switching power supply of the present invention when the switching frequency is less than or equal to the resonant frequency.
[0041] Figure 10 : A waveform diagram of the switching frequency of the switching power supply of the present invention when it is greater than the resonant frequency.
[0042] Figure 11 : is a flow chart of the synchronous rectification control method of the present invention.
[0043] Description of reference numerals:
[0044] DSP: Digital Signal Processor
[0045] CMPSS: Second comparator
[0046] CMPSS_out: state signal
[0047] Blanking: blanking signal
[0048] Vgs_Q2s: drive signal
[0049] CMP_out: comparison signal
[0050] CMP: comparator, first comparator
[0051] Q1p~Q4p: primary side switch tube
[0052] Q1s~Q4s: secondary side synchronous rectifier
[0053] Vref: voltage reference signal
[0054] IQ2s: current of synchronous rectifier
[0055] Vds Q2s : drain-source voltage
[0056] S10~S40, S51, S52: steps DETAILED DESCRIPTION
[0057] The technical content and detailed description of the present application are described as follows with the help of the accompanying drawings.
[0058] Please refer to Figure 4A The present application relates to the technical field of switching power supply, and the switching power supply in the present application can be a resonant converter. The control method of the present application can be applied to a non-isolated DCDC converter working in a discontinuous conduction mode (DCM) state, and is especially suitable for the synchronous rectification method of LLC, CLLC and SRC resonant converters. Taking Figure 4AAs shown, the switching power supply of the present invention includes a primary circuit, a secondary circuit and an energy storage unit. In this embodiment, the switching power supply is, for example, a resonant converter, and the energy storage unit is, for example, a resonant cavity. The primary circuit includes at least one primary switch bridge arm, wherein the primary switch bridge arm includes a primary switch. In this embodiment, the primary circuit includes two primary switch bridge arms, namely, a first primary switch bridge arm composed of a switch tube Q1p and a switch tube Q2p, and a second primary switch bridge arm composed of a switch tube Q3p and a switch tube Q4p. The secondary circuit includes at least one secondary switch bridge arm, wherein the secondary switch bridge arm includes a secondary switch. In this embodiment, the secondary circuit includes two secondary switch bridge arms, namely, a first secondary switch bridge arm composed of a switch tube Q1s and a switch tube Q2s, and a second secondary switch bridge arm composed of a switch tube Q3s and a switch tube Q4s. The energy storage unit is arranged between the primary circuit and the secondary circuit. Among them, the switch tubes Q1s~Q4s are also synchronous rectifier tubes. Compared with the circuit architecture of the prior art (such as Figure 1 As shown), the present invention further includes a digital signal processor (DSP).
[0059] like Figure 4A In the first embodiment shown, the present invention discloses a device comprising a switching power supply, a sampling circuit, and a control unit, wherein the control unit includes a first comparator CMP and a digital signal processor (DSP). The sampling circuit is connected to the switching transistor Q2s to sample the drain-source voltage of the switching transistor Q2s to obtain a first sampling signal (this embodiment uses the switching transistor Q2s as an example, but this is not intended to limit the present invention). The first comparator CMP is connected to the sampling circuit to receive the first sampling signal and a voltage reference signal Vref to generate a comparison signal CMP_out. The digital signal processor (DSP) includes a second comparator CMPSS, which is electrically connected to the first comparator and receives a blanking signal and the comparison signal CMP_out, and processes them to obtain a status signal CMPSS_out. In this embodiment, the second comparator CMPSS is internal to the digital signal processor (DSP), while the first comparator CMP is external to the digital signal processor (DSP). The digital signal processor (DSP) is configured on the secondary side of the switching power supply, i.e., the digital signal processor (DSP) and the secondary side circuit share a common ground.
[0060] Specifically, the internal of the digital signal processor DSP provides a second comparator CMPSS, which has a blanking function and can filter out redundant pulses. The blanking signal Blanking is triggered by pulse width modulation (PWM), wherein the blanking signal Blanking comprises an effective interval and an invalid interval. A state signal CMPSS_out is obtained according to the blanking signal Blanking and the comparison signal CMP_out. In the effective interval, the value of the state signal CMPSS_out is a certain value, which is independent of the comparison signal; in the invalid interval, the value of the state signal CMPSS_out varies with the comparison signal. It should be noted that in the invalid interval, it is not limited whether the state signal CMPSS_out is equal to the comparison signal CMP_out or the negation of the comparison signal CMP_out. The end time of the effective interval of the blanking signal Blanking is the same as the end time of the driving signal of the synchronous rectifier, and the invalid interval of the blanking signal is not greater than half of the oscillation period of the drain-source voltage. However, the present application does not limit the blanking signal Blanking to the signal provided by the internal of the DSP. Any signal that can provide a blanking function, including a blanking signal generated by the external, can be used as the blanking signal of the present application, and the differences will be described later.
[0061] Please refer to Figure 4B , which is a schematic diagram of a second embodiment of the voltage and current processing circuit of the synchronous rectifier of the switching power supply of the present application. The same parts as Figure 4A will not be described again, and the description of Figure 4A can be referred to. Compared with the first embodiment shown in Figure 4A , the second embodiment shown in Figure 4B discloses that the control unit further comprises a digital isolator DI, which is used for safe isolation and transmission of signals. The first comparator CMP is connected with the sampling circuit, which is used to receive the first sampling signal obtained by sampling the drain-source voltage and the voltage reference signal Vref to generate the comparison signal CMP_out. The digital isolator DI is electrically connected with the first comparator CMP. The digital signal processor DSP comprises a second comparator CMPSS, which is electrically connected with the digital isolator DI, is used to receive the blanking signal Blanking, and receives the comparison signal CMP_out through the digital isolator DI, and obtains the state signal CMPSS_out after processing. In this embodiment, the digital signal processor DSP is configured in the primary side of the switching power supply, that is, the digital signal processor DSP and the primary side circuit are grounded.
[0062] Please refer to Figure 4C , which is a schematic diagram of a third embodiment of the voltage and current processing circuit of the synchronous rectifier of the switching power supply of the present application. The same parts as Figure 4A and Figure 4BThe same parts are not described again, and can refer to the description of Figure 4A and Figure 4B . The third embodiment shown in Figure 4C discloses an apparatus comprising a switching power supply, a sampling circuit and a control unit, wherein the control unit comprises a comparator CMP and a digital signal processor DSP. The comparator CMP is connected with the sampling circuit, and is used to receive a first sampling signal obtained by sampling the drain-source voltage, a voltage reference signal Vref and a blanking signal Blanking, to generate a state signal CMPSS_out. In other words, the embodiment does not have two comparators as shown in Figure 4A , but integrates the first comparator CMP and the second comparator CMPSS in a single comparator CMP. Therefore Figure 4A the comparison signal CMP_out is not drawn in Figure 4C , but its function and generation can be realized by the comparator CMP shown in Figure 4C . And cooperating with the blanking signal Blanking, the state signal CMPSS_out is generated. Further, the digital signal processor DSP comprises a sampling circuit, and the sampling circuit receives the state signal CMPSS_out. In other words, the digital signal processor DSP performs corresponding control after receiving the state signal CMPSS_out generated by the external comparator CMP. In the embodiment, the digital signal processor DSP is configured on the secondary side of the switching power supply, that is, the digital signal processor DSP and the secondary side circuit are grounded. It should be noted that the sampling circuit can be one for sampling two signals, or two, one configured in front of the comparator CMP and one configured inside the digital signal processor DSP, and the present application is not limited thereto.
[0063] Please refer to Figure 4D , which is a schematic diagram of the fourth embodiment of the voltage and current processing circuit of the synchronous rectifier tube of the switching power supply of the present application. The same parts as Figure 4A , Figure 4B and Figure 4C are not described again, and can refer to the description of Figure 4A , Figure 4B and Figure 4C . Compared with the third embodiment shown in Figure 4C , Figure 4DThe fourth embodiment shown in the control unit also includes a digital isolator DI, wherein the digital isolator DI is used for safe isolation and transmission of signals. The comparator CMP is connected to the sampling circuit for receiving the first sampling signal obtained by sampling the drain-source voltage, the voltage reference signal Vref and the blanking signal Blanking to generate the state signal CMPSS_out. The digital isolator DI is electrically connected to the comparator CMP. The digital signal processor DSP is electrically connected to the digital isolator DI and receives the state signal CMPSS_out through the digital isolator DI. In this embodiment, the digital signal processor DSP is configured in the primary side of the switching power supply, i.e. the digital signal processor DSP and the primary side circuit are grounded. It should be noted that the sampling circuit can be one for sampling two signals, or two, one configured in front of the comparator CMP and one configured inside the digital signal processor DSP.
[0064] Referring to Figure 5 As shown in the figure, it is a schematic waveform diagram of the voltage and current of the synchronous rectifier when the switching frequency of the switching power supply is less than or equal to the resonance frequency. The end time of the effective interval of the blanking signal Blanking is the same as the end time of the driving signal Vgs_Q2s of the synchronous rectifier Q2s, and the invalid interval of the blanking signal is not greater than half of the oscillation period of the drain-source voltage Vds_Q2s. Furthermore, when the negative dv / dt acts on the junction capacitance of the sampling circuit diode, there is a risk of triggering a pulse, so the non-blanking time (window) of the blanking signal Blanking, i.e. the invalid interval, should be avoided during the negative dv / dt period.
[0065] Referring to Figure 11 As shown in the figure, it is a flow chart of the synchronous rectification control method of the present application, and is combined with the figure 4. The synchronous rectification control method is applied to the synchronous rectification control of a switching power supply. The switching power supply includes a primary side switch and a secondary side switch, and the synchronous rectifiers Q1s-Q4s are the secondary side switch. When the switching frequency of the switching power supply is less than or equal to the resonance frequency, the turn-on time of the driving signal of the synchronous rectifiers Q1s-Q4s lags behind the driving signal of the primary side switch by a predetermined value, and in actual working conditions, the turn-on time of the synchronous rectifiers Q1s-Q4s is a small delay compared to the turn-on time of the driving signal of the primary side switch. For the sake of convenience, the synchronous rectifier Q2s of the switching power supply shown in figure 4 is taken as an example for illustration. However, this does not limit the present application, i.e. the synchronous rectification control method of the present application can also be applied to any one of the synchronous rectifier Q1s, the synchronous rectifier Q3s and the synchronous rectifier Q4s, and the synchronous rectification control method of the present application can also be applied to other switching power supplies, such as ordinary step-down circuits working in light load DCM state, and the present application is not limited thereto.
[0066] The control method includes: first, sampling the drain-source voltage Vds_Q2s of the synchronous rectifier Q2s during the current switching cycle to obtain a first sampling signal and providing a voltage reference signal Vref (step S10). Then, comparing the first sampling signal with the voltage reference signal Vref to obtain a comparison signal CMP_out (step S20). In one embodiment, an operational amplifier (Op Amp) can be used as the comparator.
[0067] The control method also includes providing a blanking signal Blanking, which includes a valid interval and an invalid interval. And a state signal CMPSS_out is obtained based on the blanking signal Blanking and the comparison signal CMP_out (step S30). In the valid interval, the value of the state signal is a certain value, and in the invalid interval, the value of the state signal changes with the comparison signal. Therefore, the end time of the valid interval of the blanking signal Blanking is the same as the end time of the drive signal Vgs_Q2s of the synchronous rectifier Q2s. Specifically, the start time of the drive signal Vgs_Q2s of the synchronous rectifier Q2s corresponds to the closing of the synchronous rectifier Q2s, and the end time of the drive signal Vgs_Q2s corresponds to the turning off of the synchronous rectifier Q2s. In one embodiment, please refer to Figure 6 As shown, the blanking signal has the following characteristics: for example, but not limited to, within the same cycle, the blanking signal's valid interval is from the start time of the blanking signal to the end time of the blanking signal; and the blanking signal's invalid interval is from the end time of the blanking signal to the start time of the blanking signal in the subsequent cycle. It is worth noting that the blanking signal's invalid interval is no longer than half the oscillation period of the drain-source voltage Vds_Q2s.
[0068] Furthermore, the level of the blanking signal Blanking in the valid interval is different from that in the invalid interval. Figure 6 and Figure 7 As shown in FIG. , they are schematic waveform diagrams of one embodiment and another embodiment of the blanking signal function of the present invention. Figure 6In the comparison signal CMP_out, there are interference signals, which need to be blanked out by the blanking signal Blanking. Specifically, the pulses marked ①④ of the comparison signal CMP_out represent the conduction signals of the two body diodes. The blanking signal Blanking will shield the narrow pulse in front (that is, the pulse of ①) and only retain the wide pulse in the back (that is, the pulse of ④). For example, the pulses marked ②③⑤ of the comparison signal CMP_out are all interference types. For example, the pulse of ③ is the channel conduction, and the pulses of ②⑤ are the drain-source voltage oscillation trigger. These interference signals that may cause false triggering must be shielded. Therefore, the blanking signal Blanking is used to determine whether the status signal CMPSS_out exists after the drive signal Vgs_Q2s of the synchronous rectifier Q2s is turned off. Therefore, the blanking signal Blanking is enabled to provide a blanking effect before the drive signal Vgs_Q2s of the synchronous rectifier Q2s is turned off, and the blanking signal Blanking is disabled after the drive signal Vgs_Q2s of the synchronous rectifier Q2s is turned off. The level of the status signal CMPSS_out is then determined to determine whether the body diode is conductive.
[0069] The control method then samples the state signal to obtain a second sampling signal (step S40), and if the second sampling signal flips during the invalid interval of the blanking signal, the end time of the drive signal Vgs_Q2s of the synchronous rectifier Q2s in the subsequent switching cycle is adjusted to the end time of the drive signal Vgs_Q2s of the synchronous rectifier Q2s in the current switching cycle plus the step adjustment step, that is, t off =t off '+△T (step S51), see Figure 6 Where t off ' is the end time of the drive signal Vgs_Q2s for the synchronous rectifier Q2s in the current switching cycle, and ΔT is the step adjustment step size. In other words, if the second sampling signal flips during the invalid interval of the blanking signal Blanking (for example, if the level of the state signal CMPSS_out is different before and after the end time of the blanking signal Blanking), the end time of the drive signal Vgs_Q2s for the synchronous rectifier Q2s in the subsequent switching cycle is adjusted to t off =t off '+ΔT (for example, the end time of the subsequent switching cycle driving signal Vgs_Q2s is extended by one step adjustment step). However, it should be noted that the determination operation of the present invention is performed within an interrupt, and the step adjustment frequency is the interrupt frequency, which generally cannot achieve cycle-by-cycle control.
[0070] Conversely, if the second sampling signal does not flip in the invalid interval of the blanking signal Blanking, the end time of the drive signal Vgs_Q2s of the synchronous rectifier Q2s in the subsequent switching period is adjusted to t off = t off ' - ΔT (step S52), see Figure 7 Conversely, if the second sampling signal does not flip in the invalid interval of the blanking signal Blanking, the end time of the drive signal Vgs_Q2s of the synchronous rectifier Q2s in the subsequent switching period is adjusted to t off = t off ' - ΔT (for example, the end time of the drive signal Vgs_Q2s in the subsequent switching period is shortened by one step adjustment step).
[0071] It should be noted that the sampling circuit for sampling the first sampling signal and the second sampling signal can be two, for sampling the two signals respectively, as shown in FIG. Figure 4A The first sampling circuit is configured between the comparator CMP and the synchronous rectifier Q2s, and the second sampling circuit can be configured inside the digital signal processor DSP (not shown in the figure). The sampling circuit can also be one, and the present application is not limited thereto.
[0072] Therefore, please see Figures 8A-8D , which is a schematic waveform diagram of the dynamic adjustment of the drive signal of the synchronous rectifier according to the present application. The sequence of Figures 8A-8C is shown in the schematic diagram. When the second sampling signal flips in the invalid interval of the blanking signal Blanking (for example, when the level of the state signal CMPSS_out before and after the end time of the blanking signal Blanking is different, for example, low before the end and high after the end), the end time t off = t off ' + ΔT of the drive signal Vgs_Q2s in the subsequent switching period is adjusted to increase by one step adjustment step. Therefore, as shown in Figure 8D , when the step adjustment step is increased by one, the level of the state signal CMPSS_out before and after the end time of the blanking signal Blanking is the same (for example, both low before and after the end), the step adjustment step will not be increased any more. And the end time of the drive signal Vgs_Q2s of the synchronous rectifier Q2s in the subsequent switching period is shortened by one step adjustment step. In this way, the turn-off point of the synchronous rectifier Q2s is on or adjacent to the zero-crossing point of the current flowing through the synchronous rectifier Q2s, so as to achieve the maximum reduction of the body diode conduction time.
[0073] Please refer to Figure 9 Fig. 2 shows a waveform diagram of the switch power supply of the present application when the switching frequency is less than or equal to the resonant frequency. When the switching frequency is less than or equal to the resonant frequency, the turn-on time of the drive signal of the synchronous rectifier tube lags behind the turn-on time of the drive signal of the primary side switch by a preset value, that is, the turn-on of the secondary side synchronous rectifier tube has a very small delay time Td compared to the primary side switch, and the turn-off time of the synchronous rectifier tube is adjusted through the adaptive synchronous rectification control method proposed by the present application.
[0074] Please refer to Figure 10 Fig. 3 shows a waveform diagram of the switch power supply of the present application when the switching frequency is greater than the resonant frequency. When the switching frequency of the switch power supply is greater than the resonant frequency, take the synchronous rectifier tube Q2s as an example, the start time of the drive signal of the synchronous rectifier tube Q2s and the end time of the drive signal of the synchronous rectifier tube Q2s change synchronously, so that the duty cycle of the drive signal of the synchronous rectifier tube Q2s is set to a fixed value, and the duty cycle of the drive signal of the synchronous rectifier tube Q2s is less than 50%. Among them, the duty cycle of the drive signal of Q2s approaches 50% as the preferred embodiment.
[0075] When the switching frequency of the switch power supply is greater than the resonant frequency, the secondary side current is continuous, and its phase change is rightward shifted compared to when the switching frequency is less than or equal to the resonant frequency, and the delay of the turn-on time increases, and the current pulse width is about half of the switching period, at this time the duty cycle of the drive signal of the secondary side synchronous rectifier tube is set to a fixed value less than 50% (for example, a duty cycle of 45%, 49%), and the turn-off time of the synchronous rectifier is still controlled through the adaptive synchronous rectification control method proposed. When the turn-off time acts, in order to ensure that the duty cycle of the synchronous rectifier does not change, the start time of the drive signal Vgs Q2s changes synchronously with the end time of the drive signal Vgs Q2s , that is, the turn-on time and the turn-off time change synchronously. In other words, the end time of the drive signal Vgs Q2s is changed first, and then the start time changes synchronously, and the start time follows the end time.
[0076] In summary, the present application has the following characteristics and advantages: by introducing the blanking signal and providing step adjustment step length adjustment, the turn-off point of the synchronous rectifier tube is on or adjacent to the zero crossing point of the current flowing through the synchronous rectifier tube, so as to realize the maximum reduction of the body diode conduction time.
[0077] The above merely describes preferred specific embodiments of the present application with reference to the accompanying drawings, and the features of the present application are not limited thereto, and are not intended to limit the present application, and all ranges of the present application shall be subject to the following claims, and any embodiments of the present application that are similar to the concept of the claims of the present application and have similar changes shall be included in the scope of the present application, and any changes or modifications that can be easily thought of by any person skilled in the art in the field of the present application can be covered by the claims of the present disclosure.
Claims
1. A synchronous rectification control method, applied to synchronous rectification control of a switching power supply, characterized in that: The control method includes: Sampling a drain-source voltage of a synchronous rectifier in a current switching cycle to obtain a first sampling signal, providing a voltage reference signal, and comparing the first sampling signal with the voltage reference signal to obtain a comparison signal; Providing a blanking signal, the blanking signal including a valid interval and an invalid interval, obtaining a state signal according to the blanking signal and the comparison signal, wherein within the valid interval, the value of the state signal is a certain value, and within the invalid interval, the value of the state signal varies with the comparison signal; Sampling the state signal to obtain a second sampling signal; If the second sampling signal flips in the invalid interval of the blanking signal, the end time t of the driving signal of the synchronous rectifier tube in the subsequent switching cycle is adjusted. off =t off '+△T, if the second sampling signal does not flip in the invalid interval of the blanking signal, then adjust the end time t of the driving signal of the synchronous rectifier tube in the subsequent switching cycle off =t off '-△T, where t off ' is the end time of the driving signal of the synchronous rectifier tube in the current switching cycle, and ΔT is the step adjustment step.
2. The synchronous rectification control method according to claim 1, wherein: The switching power supply includes a primary switch and a secondary switch, and the synchronous rectifier tube is the secondary switch. When the switching frequency of the switching power supply is less than or equal to the resonant frequency, the turn-on time of the driving signal of the synchronous rectifier tube lags behind the turn-on time of the driving signal of the primary switch by a preset value.
3. The synchronous rectification control method according to claim 1, wherein: The end time of the effective interval of the blanking signal is the same as the end time of the driving signal of the synchronous rectifier.
4. The synchronous rectification control method according to claim 3, wherein: The inactive interval of the blanking signal is no longer than half of an oscillation period of the drain-source voltage.
5. The synchronous rectification control method according to claim 1, wherein: When the switching frequency of the switching power supply is greater than the resonant frequency, the start time of the drive signal of the synchronous rectifier tube and the end time of the drive signal of the synchronous rectifier tube change synchronously, so that the duty cycle of the drive signal of the synchronous rectifier tube is set to a fixed value, and the duty cycle of the drive signal of the synchronous rectifier tube is less than 50%.
6. The synchronous rectification control method according to claim 1, wherein: The switching power supply is a resonant converter.
7. A device comprising a switching power supply, a sampling circuit and a control unit, characterized in that: The switching power supply comprises: a primary circuit comprising at least one primary switch bridge arm, wherein the primary switch bridge arm comprises a primary switch; A secondary circuit includes at least one secondary switch bridge arm, wherein the secondary switch bridge arm includes a secondary switch; an energy storage unit, disposed between the primary circuit and the secondary circuit; The sampling circuit is used to sample a drain-source voltage of a synchronous rectifier tube in a current switching cycle to obtain a first sampling signal; and The control unit is configured to receive the first sampling signal, a voltage reference signal, and a blanking signal, and generate a status signal, wherein the blanking signal includes a valid interval and an invalid interval. The sampling circuit is further configured to sample the state signal to obtain a second sampling signal. The control unit is configured to perform the following steps: Comparing the first sampling signal with the voltage reference signal to obtain a comparison signal; obtaining the state signal according to the blanking signal and the comparison signal, wherein in the valid interval, the value of the state signal is a certain value, and in the invalid interval, the value of the state signal varies with the comparison signal; If the second sampling signal flips in the invalid interval of the blanking signal, the control unit adjusts the end time t of the driving signal of the synchronous rectifier tube in the subsequent switching cycle. off =t off '+△T, if the second sampling signal does not flip in the invalid interval of the blanking signal, the control unit adjusts the end time t of the driving signal of the synchronous rectifier tube in the subsequent switching cycle off =t off '-△T, where t off ' is the end time of the driving signal of the synchronous rectifier tube in the current switching cycle, and ΔT is the step adjustment step.
8. The device according to claim 7, wherein The synchronous rectifier is the secondary switch. When the switching frequency of the switching power supply is less than or equal to the resonant frequency, the turn-on time of the driving signal of the synchronous rectifier lags behind the turn-on time of the driving signal of the primary switch by a preset value.
9. The device according to claim 7, wherein The end time of the effective interval of the blanking signal is the same as the end time of the driving signal of the synchronous rectifier.
10. The device according to claim 9, wherein The inactive interval of the blanking signal is no longer than half of an oscillation period of the drain-source voltage.
11. The device according to claim 7, wherein When the switching frequency of the switching power supply is greater than the resonant frequency, the start time of the drive signal of the synchronous rectifier tube and the end time of the drive signal of the synchronous rectifier tube change synchronously, so that the duty cycle of the drive signal of the synchronous rectifier tube is set to a fixed value, and the duty cycle of the drive signal of the synchronous rectifier tube is less than 50%.
12. The device according to claim 7, wherein The control unit comprises: a first comparator connected to the sampling circuit, configured to receive the first sampling signal and the voltage reference signal, and generate the comparison signal; and A digital signal processor includes a second comparator, wherein the second comparator is electrically connected to the first comparator and is used to receive the blanking signal and the comparison signal to generate the status signal.
13. The device according to claim 7, wherein The control unit comprises: a first comparator, connected to the sampling circuit, configured to receive the first sampling signal and the voltage reference signal, and generate the comparison signal; a digital isolator electrically connected to the first comparator; and A digital signal processor includes a second comparator, wherein the second comparator is electrically connected to the digital isolator, and is used to receive the blanking signal and the comparison signal through the digital isolator to generate the status signal.
14. The device according to claim 7, wherein The control unit comprises: a comparator connected to the sampling circuit, configured to receive the first sampling signal, the voltage reference signal, and the blanking signal, and generate the status signal; and A digital signal processor includes the sampling circuit, wherein the sampling circuit is used to receive the state signal and obtain the second sampling signal.
15. The device according to claim 7, wherein The control unit comprises: a comparator connected to the sampling circuit, configured to receive the first sampling signal, the voltage reference signal, and the blanking signal, and generate the status signal; a digital isolator electrically connected to the comparator; and A digital signal processor is electrically connected to the digital isolator, and the digital signal processor receives the status signal through the digital isolator.
16. The synchronous rectification control method according to claim 7, wherein: The switching power supply is a resonant converter.