Amplitude-doubling filter circuit and reference voltage source

Abstract

The invention discloses an amplitude doubling filter circuit and a reference voltage source. The amplitude doubling filter circuit comprises an input control sub-circuit suitable for receiving an input voltage; n is greater than or equal to 1 and is an integer; wherein the n multiple amplitude filtering sub-circuits are suitable for amplifying the amplitude of the input voltage by (n + 1) times under the control of a clock signal, and filtering noise introduced by the clock signal. By adopting the scheme, the introduction of new noise can be avoided while the voltage is amplified.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to a double-amplitude filter circuit and a reference voltage source. BACKGROUND

[0002] The reference voltage source is used to provide a reference voltage in a circuit. Generally, the reference voltage provided by the reference voltage source is a zero-temperature coefficient voltage obtained by superimposing a positive temperature coefficient voltage and a negative temperature coefficient voltage.

[0003] In practical applications, the positive temperature coefficient voltage is generally small, and direct use requires a higher design requirement for the subsequent circuit.

[0004] In order to reduce the use requirement for the subsequent circuit, the positive temperature coefficient voltage needs to be amplified.

[0005] However, the existing circuit for amplifying the positive temperature coefficient voltage introduces new noise, affecting the stability of the reference voltage. SUMMARY

[0006] The problem to be solved by the present application is to amplify the voltage while avoiding the introduction of new noise.

[0007] To solve the above problems, the embodiment of the present application provides a double-amplitude filter circuit, which comprises:

[0008] An input control sub-circuit adapted to receive an input voltage;

[0009] And n double-amplitude filter sub-circuits, n≥1 and n is an integer;

[0010] Among them, the n double-amplitude filter sub-circuits are adapted to amplify the amplitude of the input voltage by (n+1) times under the control of a clock signal, and filter the noise introduced by the clock signal.

[0011] In a possible embodiment of the present application, the double-amplitude filter sub-circuit comprises a first double-amplitude module, and the first double-amplitude module comprises:

[0012] A first capacitor;

[0013] A first switch tube connected with the first capacitor;

[0014] A second switch tube connected with the first capacitor and the first switch tube;

[0015] The control end of the first switch tube is connected with a first clock signal, and the control end of the second switch tube is connected with a second clock signal, and the first clock signal and the second clock signal are opposite in phase and the same in frequency.

[0016] In a possible embodiment of the present application, the amplitude doubling filter sub-circuit further comprises (n-1) second amplitude doubling modules.

[0017] The second amplitude doubling module comprises a second capacitor, a third switch tube connected with the second capacitor, a fourth switch tube connected with the third switch tube and the second capacitor, and a fifth switch tube connected with the third switch tube.

[0018] The control end of the third switch tube is connected with the first clock signal, and the control ends of the fourth and fifth switch tubes are connected with the second clock signal.

[0019] In a possible embodiment of the present application, the input control sub-circuit comprises a sixth switch tube connected with the amplitude doubling filter sub-circuit, and the control end of the sixth switch tube is connected with the second clock signal.

[0020] In a possible embodiment of the present application, at least one notch filter is further included, which is connected with at least one of the input control sub-circuit and the amplitude doubling filter sub-circuit, and is adapted to filter the noise introduced by the input voltage.

[0021] In a possible embodiment of the present application, the number of the notch filters is n, and the n notch filters are connected with one end of the input voltage in the input control sub-circuit and the amplitude doubling filter sub-circuit one by one.

[0022] In a possible embodiment of the present application, the notch filter comprises a first switch control module and a second switch control module connected in parallel, and the first switch control module and the second switch control module are adapted to be turned on and turned off under the control of the first clock signal and the second clock signal, so as to filter the noise introduced by the input voltage.

[0023] In a possible embodiment of the present application, the first switch control module comprises a first CMOS switch control sub-module, a third capacitor and a second CMOS switch control sub-module connected in series, and the second switch control module comprises a third CMOS switch control sub-module, a fourth capacitor and a fourth CMOS switch control sub-module connected in series, and the first CMOS switch control sub-module to the fourth CMOS switch control sub-module are all composed of a PMOS tube and an NMOS tube connected in parallel.

[0024] The embodiment of the present application further provides a reference voltage source, which comprises any one of the amplitude doubling filter circuits, and the amplitude doubling filter circuit is adapted to amplify the positive temperature coefficient output voltage by n times under the control of the clock signal and filter the noise introduced by the clock signal.

[0025] In a possible embodiment of the present application, further comprising:

[0026] A positive temperature coefficient voltage generating circuit, connected with the amplitude doubling filter circuit, and adapted to generate a positive temperature coefficient voltage;

[0027] A negative temperature coefficient voltage generating circuit, connected with the amplitude doubling filter circuit, and adapted to generate a negative temperature coefficient voltage;

[0028] And a superposition circuit, adapted to superimpose the output voltage of the amplitude doubling filter circuit and the negative temperature coefficient voltage to obtain a reference voltage.

[0029] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0030] By applying the scheme of the present application, since the amplitude doubling filter circuit comprises n amplitude doubling filter sub-circuits, the n amplitude doubling filter sub-circuits can amplify the amplitude of the input voltage by n times under the control of the clock signal, and filter the noise introduced by the clock signal, thereby avoiding introducing new noise while amplifying the input voltage. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a structural schematic diagram of an amplitude doubling filter circuit in an embodiment of the present application;

[0032] Figure 2 is a structural schematic diagram of another amplitude doubling filter circuit in an embodiment of the present application;

[0033] Figure 3 is a structural schematic diagram of still another amplitude doubling filter circuit in an embodiment of the present application;

[0034] Figure 4 is a structural schematic diagram of yet another amplitude doubling filter circuit in an embodiment of the present application;

[0035] Figure 5 is a structural schematic diagram of still another amplitude doubling filter circuit in an embodiment of the present application;

[0036] Figure 6 is a structural schematic diagram of a notch filter in an embodiment of the present application;

[0037] Figure 7 is a simulation result diagram of the influence of the input voltage amplitude on the notch filter and Figure 5 is a simulation result diagram of the influence of the input voltage amplitude on the amplitude doubling filter circuit as a whole;

[0038] Figure 8 is a simulation result comparison diagram of the frequency spectrum characteristics of the notch filter and Figure 5 is a simulation result comparison diagram of the frequency spectrum characteristics of the amplitude doubling filter circuit as a whole;

[0039] Figure 9 is a structural schematic diagram of a reference voltage source in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The existing circuit for amplifying the positive temperature coefficient voltage can introduce new noise, affecting the stability of the reference voltage.

[0041] To solve the problem, the present application provides an amplitude doubling filter circuit, which comprises n amplitude doubling filter sub-circuits.

[0042] In order to make the above-mentioned purpose, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0043] The amplitude doubling filter circuit provided by the embodiments of the present application can comprise:

[0044] An input control sub-circuit adapted to receive an input voltage;

[0045] And n amplitude doubling filter sub-circuits, n≥1 and n is an integer;

[0046] Among them, the n amplitude doubling filter sub-circuits are adapted to amplify the amplitude of the input voltage by (n+1) times under the control of a clock signal, and filter the noise introduced by the clock signal.

[0047] In specific implementation, the input control sub-circuit can be implemented in various structures, which is not limited here.

[0048] In an embodiment of the present application, referring to Figures 1 to 3 The input control sub-circuit 11 can comprise a sixth switch tube Q6. The sixth switch tube Q6 is connected with the amplitude doubling filter sub-circuit; and the control end of the sixth switch tube Q6 is connected with the second clock signal CKB.

[0049] In specific implementation, the sixth switch tube Q6 can be implemented by using a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and the sixth switch tube Q6 can also be implemented by using other semiconductor devices such as an Insulated Gate Bipolar Transistor (IGBT). When the sixth switch tube Q6 is implemented by using a MOSFET, the sixth switch tube Q6 can be an NMOS tube or a PMOS tube.

[0050] In a specific implementation, the value of n can be set according to actual needs. It can be understood that the greater the value of n, the higher the amplification multiple of the amplitude doubling filter circuit to the input voltage, and the greater the value of the output voltage obtained after the input voltage is output by the amplitude doubling filter circuit.

[0051] For example, n can be set to 1, in which case the amplitude doubling filter circuit can amplify the input voltage by 2 times. n can also be set to 2, in which case the amplitude doubling filter circuit can amplify the input voltage by 3 times. n can also be set to 3, in which case the amplitude doubling filter circuit can amplify the input voltage by 4 times.

[0052] When n>1, the n amplitude doubling filter sub-circuits are connected in series in sequence, the input end of the first amplitude doubling filter sub-circuit is connected to the output end of the input control sub-circuit, and the output end of the last amplitude doubling filter sub-circuit is connected to the output end of the amplitude doubling filter circuit and connected to the output load.

[0053] In a specific implementation, the amplitude doubling filter sub-circuit can be composed of a capacitor and a switch tube, and the control end of the switch tube can be connected to a clock signal, thereby realizing amplification of the input voltage.

[0054] In an embodiment of the present application, n=1. Accordingly, with reference to Figure 1 , the amplitude doubling filter sub-circuit can include a first amplitude doubling module 12. Wherein:

[0055] The first amplitude doubling module 12 can include a first capacitor C1, a first switch tube Q1, and a second switch tube Q2. The first switch tube Q1 is connected to the first capacitor C1, and the second switch tube Q2 is connected to the first capacitor C1 and the first switch tube Q1.

[0056] The control end of the first switch tube Q1 is connected to a first clock signal CK, the control end of the second switch tube Q2 is connected to a second clock signal CKB, and the first clock signal CK and the second clock signal CKB are opposite in phase and the same in frequency.

[0057] In a specific implementation, the first switch tube Q1 and the second switch tube Q2 can be implemented using a variety of switching devices, for example, at least one of the first switch tube Q1 and the second switch tube Q2 can be implemented using a MOSFET, and at least one of the first switch tube Q1 and the second switch tube Q2 can also be implemented using an IGBT or other semiconductor device.

[0058] In an embodiment, the first switch tube Q1 and the second switch tube Q2 are both NMOS tubes. Since the first clock signal CK and the second clock signal CKB are opposite in phase, when the second clock signal CKB is logic "0", the first clock signal CK is logic "1", and when the second clock signal CKB is logic "1", the first clock signal CK is logic "0".

[0059] When the second clock signal CKB is logic "1" and the first clock signal CK is logic "0", the second switch tube Q2 and the sixth switch tube Q6 are turned on, and the first switch tube Q1 is turned off, so that the left plate of the first capacitor C1 is pulled to the ground by the sixth switch tube Q6, and the right plate of the first capacitor C1 is charged to the input voltage Vin by the second switch tube Q2.

[0060] Then, when the second clock signal CKB is logic "0" and the first clock signal CK is logic "1", the second switch tube Q2 and the sixth switch tube Q6 are turned off, and the first switch tube Q1 is turned on, so that the left plate of the first capacitor C1 is charged to the input voltage Vin. Since the voltage of the right plate of the first capacitor C1 is the input voltage Vin at the previous moment, and the voltage difference across the first capacitor C1 cannot change abruptly, the voltage of the right plate of the first capacitor C1 is 2*Vin at this moment, that is, the voltage of the output end Out of the doubling filter circuit is 2*Vin, realizing 2 times amplification of the input voltage Vin. The output voltage of the doubling filter circuit is used to power the equivalent load CL.

[0061] In addition, assuming that the period of the first clock signal CK and the second clock signal CKB is T, and the frequency is f, f = 1 / T, under the control of the first clock signal CK and the second clock signal CKB, the first capacitor C1 is charged every period T, so that in the frequency spectrum, the same frequency (i.e. f) signal is filtered, and the effect of filtering the noise introduced by the clock signal is achieved.

[0062] In another embodiment of the present application, n≥2. Accordingly, the doubling filter sub-circuit only includes one first doubling module, and in addition to the first doubling module, the doubling filter sub-circuit can further include (n-1) second doubling modules. Wherein:

[0063] The second doubling module includes a second capacitor, a third switch tube connected to the second capacitor, a fourth switch tube connected to the third switch tube and the second capacitor, and a fifth switch tube connected to the third switch tube.

[0064] The control end of the third switch tube is connected to the first clock signal, and the control ends of the fourth switch tube and the fifth switch tube are connected to the second clock signal.

[0065] For example, when n=2, the amplitude multiplication filter subcircuit may include only one second amplitude multiplication module. When n=3, the amplitude multiplication filter subcircuit may include only two second amplitude multiplication modules. When n=4, the amplitude multiplication filter subcircuit may include only three second amplitude multiplication modules. The (n-1) second amplitude multiplication modules are sequentially connected in series.

[0066] In a specific implementation, the third, fourth, and fifth switching transistors can be implemented using a variety of switching devices. For example, at least one of the third, fourth, and fifth switching transistors can be implemented using a MOSFET, or at least one of the third, fourth, and fifth switching transistors can be implemented using other semiconductor devices such as an IGBT.

[0067] Take n=2 as an example. Figure 2 The amplitude doubling filter subcircuit includes a first amplitude doubling module 12 and a second amplitude doubling module 13. Regarding the first amplitude doubling module 12, please refer to the above Figure 1 The implementation is based on the description of the first amplitude doubling module 12 in FIG.

[0068] and Figure 1 The amplitude multiplication filter subcircuit shown in FIG2 differs in that it also includes a second amplitude multiplication module 13. This second amplitude multiplication module 12 may include a second capacitor C2, a third switch Q3, a fourth switch Q4, and a fifth switch Q5. One end of the second capacitor C2 is connected to the input of the control subcircuit 11, and the other end is connected to the fourth switch Q4 and the third switch Q3. The other end of the third switch Q3 is connected to the fifth switch Q5.

[0069] Assuming that the third switch Q3, the fourth switch Q4, and the fifth switch Q5 are all NMOS transistors, when the second clock signal CKB is logic "1" and the first clock signal CK is logic "0", the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, and the second switch Q2 are turned on, while the third switch Q3 and the first switch Q1 are turned off. At this time, the left plate of the second capacitor C2 is pulled to ground by the sixth switch Q6, while the right plate of the second capacitor C2 is charged to the input voltage Vin through the fourth switch Q4. Correspondingly, the left plate of the first capacitor C1 is pulled to ground through the fifth switch Q5, while the right plate of the first capacitor C1 is charged to the input voltage Vin through the sixth switch Q6.

[0070] Then, when the second clock signal CKB is logic "0" and the first clock signal CK is logic "1", the fourth switch Q4, the fifth switch Q5, the sixth switch Q6 and the second switch Q2 are turned off, and the third switch Q3 and the first switch Q1 are turned on. At this time, the left plate of the second capacitor C2 is charged to the input voltage Vin, and the voltage of the right plate of the second capacitor C2 is the input voltage Vin at the previous time. Since the voltage difference across the second capacitor C2 cannot change abruptly, the voltage of the right plate of the second capacitor C2 (i.e. the voltage of terminal B) should be 2*VIN at this time. When the third switch Q3 is turned on, the voltage of the right plate of the second capacitor C2 is transmitted to the left plate of the first capacitor C1. Since the voltage of the left plate of the first capacitor C1 (i.e. the voltage of terminal A) is ground at the previous time, and the voltage of the right plate of the first capacitor C1 (i.e. the voltage of terminal D) is the input voltage Vin at the previous time, when the voltage of the left plate of the first capacitor C1 rises from ground to 2*VIN, the voltage of the right plate of the first capacitor C1 should be 3*VIN. In this way, the voltage of the right plate of the first capacitor C1 is transmitted to the output terminal Out through the first switch Q1, and at this time the output voltage VOut = 3*VIN. Thus, the output voltage has been changed to 3 times the input voltage.

[0071] Assuming that the period of the first clock signal CK and the second clock signal CKB is T, and the frequency is f, f = 1 / T, similar to the filtering effect of the first amplitude doubling module 12, in the second amplitude doubling module 13, under the control of the first clock signal CK and the second clock signal CKB, the second capacitor C2 is charged every period T. Thus, in the frequency spectrum, the filtering of signals of the same frequency (i.e. f) is achieved, and the effect of filtering the clock signal-induced noise is achieved.

[0072] When n = 3, referring to Figure 3 , the amplitude filtering sub-circuit includes one first amplitude doubling module 12 and two second amplitude doubling modules 13, which can achieve an amplification of 4 times the input voltage. Regarding Figure 3 the specific working process of the first amplitude doubling module 12 and the second amplitude doubling module 13, please refer to the above description of Figure 2 , which will not be described here.

[0073] In practical applications, the inventors have found that the input voltage itself can also introduce noise. For example, in a reference voltage source, in the process of generating a positive temperature coefficient output voltage, in order to improve the noise immunity of the positive temperature coefficient output voltage, a chopper circuit is generally provided in the positive temperature coefficient generating circuit to reduce the noise of the positive temperature coefficient voltage. However, the chopper circuit can introduce clock noise, and thus the positive temperature coefficient output voltage carries the clock noise.

[0074] In an embodiment of the present application, the amplitude doubling filter circuit can further comprise at least one notch filter. The notch filter can be connected to at least one of the input control sub-circuit and the amplitude doubling sub-circuit, and is adapted to filter the noise introduced by the input voltage.

[0075] In a specific implementation, the notch filter can be connected to one end of the input voltage accessed by the input control sub-circuit, so that the input voltage provided to the input control sub-circuit can be filtered. The notch filter can also be connected to one end of the input voltage accessed by the amplitude doubling sub-circuit, so that the input voltage provided to the input control sub-circuit can be filtered.

[0076] In a specific implementation, the number of notch filters can be set according to actual noise requirements. For example, referring to Figure 5 When n = 3, the amplitude doubling filter circuit can be provided with 2 notch filters. Specifically, a first notch filter 14 can be provided at one end of the input voltage Vin accessed by the input control sub-circuit 11, i.e., the C end, and a second notch filter 15 can be provided at one end of the input voltage Vin accessed by the fourth switch Q4 in the second amplitude doubling module 13.

[0077] In an embodiment of the present application, the number of notch filters is n + 1; one of the n + 1 notch filters is connected to the input control sub-circuit, and the remaining n notch filters are connected to the n amplitude doubling sub-circuits one by one. At this time, all ends of the amplitude doubling filter circuit accessing the input voltage are provided with notch filters, and the input voltage Vin is input to the input control sub-circuit and the amplitude doubling sub-circuit through the notch filters.

[0078] For example, referring to Figure 6 When n = 3, the amplitude doubling filter circuit can be provided with 3 notch filters. Specifically, a first notch filter 14 can be provided at one end of the input voltage Vin accessed by the input control sub-circuit 11, i.e., the C end, a second notch filter 15 can be provided at one end of the input voltage Vin accessed by the fourth switch Q4 in the second amplitude doubling module 13, and a third notch filter 16 can be provided at one end of the input voltage Vin accessed by the second switch Q2 in the first amplitude doubling module 11. In this way, for any input of the input voltage Vin to one end of the amplitude doubling filter circuit, the input voltage Vin is filtered through the notch filter, thereby minimizing the noise introduced by the input voltage Vin.

[0079] In a specific implementation, in order to facilitate design and reduce circuit area, the notch filter can be an SC notch filter. Specifically, referring to Figure 6The notch filter can include: a first switch control module 61 and a second switch control module 62 connected in parallel, and the first switch control module 61 and the second switch control module 62 are adapted to be turned on and off under the control of a first clock signal and a second clock signal, so as to filter the noise introduced by the input voltage Vin.

[0080] In a specific implementation, the first switch control module 61 includes: a first CMOS switch control submodule, a third capacitor and a second CMOS switch control submodule connected in series. The second switch control module 62 includes: a third CMOS switch control submodule, a fourth capacitor and a fourth CMOS switch control submodule connected in series. The first CMOS switch control submodule to the fourth CMOS switch control submodule are all composed of a PMOS tube and an NMOS tube connected in parallel.

[0081] Specifically, referring to Figure 6 , the first PMOS tube PM1 and the first NMOS tube NM1 constitute the first CMOS switch control submodule. The second PMOS tube PM2 and the second NMOS tube NM2 constitute the second CMOS switch control submodule. The third PMOS tube PM3 and the third NMOS tube NM3 constitute the third CMOS switch control submodule. The fourth PMOS tube PM4 and the fourth NMOS tube NM4 constitute the fourth CMOS switch control submodule. The MOS tubes in the first CMOS switch control submodule to the fourth CMOS switch control submodule are all controlled to be turned on and off by the first clock signal CK and the second clock signal CKB.

[0082] With the notch filter, when the first clock signal CK is logic "0" and the second clock signal CKB is logic "1", the input voltage Vin passes through the first CMOS switch control submodule composed of the first PMOS tube PM1 and the first NMOS tube NM1, charges the third capacitor connected to the E terminal, so that the E terminal voltage VE is equal to Vin. At this time, the second CMOS switch control submodule composed of the second PMOS tube PM2 and the second NMOS tube NM2 is disconnected, at the same time, the third CMOS switch control submodule composed of the third PMOS tube PM3 and the third NMOS tube NM3 is disconnected, and the fourth CMOS switch control submodule composed of the fourth PMOS tube PM4 and the fourth NMOS tube NM4 is turned on, thereby the F terminal voltage can be transmitted to the out terminal.

[0083] Conversely, when the first clock signal CK is at logic "1" and the second clock signal CKB is at logic "0," the third CMOS switch control submodule, consisting of the third PMOS transistor PM3 and the third NMOS transistor NM3, is turned on. The input voltage Vin charges the fourth capacitor C4 through the third CMOS switch control submodule, making the voltage VF at terminal F equal to Vin. Simultaneously, the first CMOS switch control submodule, consisting of the first PMOS transistor PM1 and the first NMOS transistor NM1, is turned off. The second CMOS switch control submodule, consisting of the second PMOS transistor PM2 and the second NMOS transistor NM2, is turned on. The fourth CMOS switch control submodule, consisting of the fourth PMOS transistor PM4 and the fourth NMOS transistor NM4, is turned off. This allows the voltage at terminal E to be transmitted to the output terminal.

[0084] Typically, the frequency of noise introduced by the input voltage is twice the frequency of the first clock signal CK and the second clock signal CKB. However, using the aforementioned notch filter, when the first clock signal CK or the second clock signal CKB is logic "1" for a period of T, the voltage at terminal E or terminal F is charged during each half-cycle. During the remaining half-cycle, the voltage at terminal E or terminal F is output at the output terminal, with the output Vout = Vin. This allows filtering of signals with a frequency of 2*f in the spectrum.

[0085] Figure 7 The influence of the notch filter on the input voltage amplitude is Figure 5 Schematic diagram of the simulation results of the influence of the amplitude doubling filter circuit as a whole on the input voltage amplitude. Among them, curve 71 represents the curve of the influence of the notch filter on the input voltage amplitude, and curve 72 represents the curve of the influence of the amplitude doubling filter circuit as a whole on the input voltage amplitude. It can be seen from curves 71 and 72 that the notch filter will not amplify the input voltage amplitude, but the amplitude doubling filter circuit as a whole, which includes n amplitude doubling filter sub-circuits, can amplify the input voltage amplitude by 3 times. In this way, by using the amplitude doubling filter circuit in the embodiment of the present invention, the input voltage with extremely low amplitude can be doubled, which is more friendly to the signal processing of the subsequent circuit. For example, the subsequent amplifier circuit can reduce the range requirements of the amplifier input signal, making the design simpler.

[0086] Figure 8 The spectrum characteristics of the notch filter and Figure 5 Schematic diagram of simulation results of spectrum characteristics of mid-amplitude filter circuit. Curve 81 represents spectrum characteristic curve of notch filter, and curve 82 represents Figure 5 Spectral characteristic curves of the amplitude doubling filter circuit. As can be seen from curves 81 and 82, when the frequencies of the first clock signal CK and the second clock signal CKB are both 2 MHz, the notch filter significantly suppresses the 4 MHz (i.e., 2*f) signal. The amplitude doubling filter circuit as a whole significantly suppresses both 2 MHz and 4 MHz signals.

[0087] The amplitude doubling filter circuit can not only amplify the amplitude of the input voltage, but also filter the noise introduced by the clock signal.

[0088] The reference voltage source comprises the amplitude doubling filter circuit in any of the above embodiments, and the amplitude doubling filter circuit is adapted to amplify the positive temperature coefficient output voltage by n times under the control of the clock signal and filter the noise introduced by the clock signal.

[0089] In an embodiment of the present application, the amplitude doubling filter circuit can further comprise at least one notch filter connected with at least one of the input control sub-circuit and the amplitude doubling filter sub-circuit, and adapted to filter the noise introduced by the input voltage. Thus, the amplitude doubling filter circuit can not only filter the noise introduced by the input voltage, but also filter the noise introduced by the clock signal.

[0090] In an embodiment of the present application, referring to Figure 9 , the reference voltage source can comprise:

[0091] The positive temperature coefficient voltage generating circuit 91 is connected with the amplitude doubling filter circuit 93 and adapted to generate the positive temperature coefficient voltage.

[0092] The negative temperature coefficient voltage generating circuit 92 is connected with the amplitude doubling filter circuit 93 and adapted to generate the negative temperature coefficient voltage.

[0093] The superposition circuit 94 is adapted to superimpose the output voltage of the amplitude doubling filter circuit 93 and the negative temperature coefficient voltage to obtain the reference voltage.

[0094] The amplitude doubling filter circuit 93 can perform amplitude doubling filtering on the positive temperature coefficient voltage output by the positive temperature coefficient voltage generating circuit 91, so that the positive temperature coefficient voltage can be amplified based on actual needs, and the noise can be avoided, and the reference voltage output by the superposition circuit 94 is more convenient for subsequent circuit use.

[0095] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. An amplitude doubling filter circuit, characterized in that: include: an input control subcircuit adapted to receive an input voltage; and n amplitude doubling filter subcircuits, where n≥1 and n is an integer; The n amplitude multiplication and filtering sub-circuits are adapted to amplify the amplitude of the input voltage by (n+1) times under the control of a clock signal, and filter the noise introduced by the clock signal.

2. The amplitude doubling filter circuit according to claim 1, wherein: The amplitude doubling filter subcircuit includes: a first amplitude doubling module; the first amplitude doubling module includes: a first capacitor; A first switching tube connected to the first capacitor; a second switching tube, connected to the first capacitor and the first switching tube; The control end of the first switch tube is connected to a first clock signal, and the control end of the second switch tube is connected to a second clock signal. The first clock signal and the second clock signal have opposite phases and the same frequency.

3. The amplitude doubling filter circuit according to claim 2, wherein: The amplitude doubling filter subcircuit further includes: (n-1) second amplitude doubling modules; The second amplitude doubling module includes: a second capacitor; a third switch connected to the second capacitor; a fourth switch connected to the third switch and the second capacitor; and a fifth switch connected to the third switch. The control end of the third switch tube is connected to the first clock signal, and the control ends of the fourth switch tube and the fifth switch tube are connected to the second clock signal.

4. The amplitude doubling filter circuit according to claim 2 or 3, characterized in that: The input control subcircuit includes: a sixth switch tube connected to the amplitude multiplication filter subcircuit; a control terminal of the sixth switch tube is connected to the second clock signal.

5. The amplitude doubling filter circuit according to claim 2 or 3, characterized in that: Also includes: At least one notch filter is connected to at least one of the input control subcircuit and the amplitude multiplication filter subcircuit, and is suitable for filtering noise introduced by the input voltage.

6. The amplitude doubling filter circuit according to claim 5, wherein: The number of the notch filters is n; the n notch filters are connected to the input control subcircuit and the amplitude multiplication filter subcircuit in a one-to-one correspondence with one end connected to the input voltage.

7. The amplitude doubling filter circuit according to claim 5, wherein: The notch filter includes: a first switch control module and a second switch control module connected in parallel, wherein the first switch control module and the second switch control module are adapted to switch on and off control lines of a first clock signal and a second clock signal to filter noise introduced by the input voltage.

8. The amplitude doubling filter circuit according to claim 7, wherein: The first switch control module includes: a first CMOS switch control submodule, a third capacitor, and a second CMOS switch control submodule connected in series; the second switch control module includes: a third CMOS switch control submodule, a fourth capacitor, and a fourth CMOS switch control submodule connected in series; the first CMOS switch control submodule to the fourth CMOS switch control submodule are all composed of PMOS transistors and NMOS transistors connected in parallel.

9. A reference voltage source, characterized in that: The invention comprises the amplitude doubling filter circuit according to any one of claims 1 to 8; the amplitude doubling filter circuit is suitable for amplifying the positive temperature coefficient output voltage by n times under the control of a clock signal and filtering the noise introduced by the clock signal.

10. The reference voltage source according to claim 9, wherein: Also includes: A positive temperature coefficient voltage generating circuit, connected to the amplitude multiplication filter circuit, and adapted to generate a positive temperature coefficient voltage; A negative temperature coefficient voltage generating circuit, connected to the amplitude multiplication filter circuit, and adapted to generate a negative temperature coefficient voltage; and a superposition circuit adapted to superimpose the output voltage of the amplitude multiplication filter circuit and the negative temperature coefficient voltage to obtain a reference voltage.

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