A method of signal adaptive control

Abstract

The application discloses a signal self-adaptive control method, comprising the following steps: S1, initializing a programmable logic device FPGA, and setting a running frequency preset value of an encoder; S2, counting pulse signals of a signal period through a counting function of the programmable logic device FPGA; S3, through a PLL function of the programmable logic device FPGA, the frequency of a clock is greater than 100MHz; S4, when the pulse signals appear twice same edges, a signal period detection is completed, and the programmable logic device FPGA stops counting; S5, starting a data calculation function; S6, making remainder accumulation to the algorithm, so that the signal error value is reduced to the lowest, and the running frequency preset value is infinitely close, the encoder signal of different frequency fluctuations of equipment is solved, and the image acquisition is more balanced and clear.

Description

Technical Field

[0001] This invention relates to the field of encoder signal control technology, and in particular to a signal adaptive control method. Background Technology

[0002] In existing technologies, after a product is manufactured, it needs to be inspected. Product surface inspection is an important inspection item. Currently, product surface inspection generally uses a material conveyor belt to transport the object to be tested to the area below a vision inspection device. The vision inspection device collects surface information of the object to be tested through a light source and a lens.

[0003] However, existing material conveyor belts often use encoders to control their operating speed. Due to the wide variety of objects being measured, the varying operating speeds of vision inspection equipment, and the difficulty in maintaining absolute stability in the operating speed of vision inspection equipment, factors such as different encoder specifications, varying image processing software algorithms and computing power, and unstable conveyor belt operation leading to encoder signal jitter can all cause irregularities in the signal frequency required by the encoder. Without any processing, the material conveyor belt cannot meet the actual operating requirements, resulting in uneven image acquisition by the line scan camera. This makes it impossible to ensure that the acquired image and the measured object are imaged at a 1:1 ratio, causing detection misjudgments or errors in dimensional positioning calculations.

[0004] In response to the problem that the signal frequency required by existing encoders is irregular, resulting in uneven image acquisition by line scan cameras and an inability to ensure that the image is captured at a 1:1 ratio with the object being measured, which leads to misjudgment in detection or errors in size positioning calculation, there is still a lack of better technical solutions. Summary of the Invention

[0005] In view of this, it is necessary to provide a signal adaptive control method to at least solve the problem that the signal frequency required by the existing encoder in the related technology is irregular, which leads to uneven image acquisition by the line scan camera, and cannot guarantee that the image is imaged at a 1:1 ratio with the object being measured, causing detection misjudgment or size positioning calculation error.

[0006] This application provides a signal adaptive control method, including the following steps:

[0007] S1. Initialize the programmable logic device FPGA and set the preset value n of the encoder's operating frequency;

[0008] S2. The pulse signal of one signal cycle is counted using the counting function of the FPGA (Programmable FPGA). The sum of the duration of one high-level pulse and the duration of one low-level pulse is denoted as one signal cycle, and one signal cycle is denoted as T. The high-level pulse signal of one signal cycle is denoted as T_0. HThe low level of a pulse signal in one signal cycle is denoted as T. L ;

[0009] S3. By using the PLL function of the FPGA (FPGA programmable logic device), the clock frequency is made to be greater than 100MHz.

[0010] S4. When the pulse signal has two identical edge timing signals, one signal cycle detection is completed, and the programmable logic device FPGA stops counting.

[0011] S5. Start the data calculation function;

[0012] From the formula: T and T can be obtained. a Where T is the running time of one signal cycle in step S2, T a T is the remainder of the running time of one signal cycle. H T is the high level of a pulse signal for one signal cycle. L The low level of a pulse signal that constitutes one signal cycle;

[0013] S6. Accumulate the remainders in the algorithm. When the remainders generate a carry, complete the time error correction, so that the signal period error value is minimized and infinitely close to the preset value n of the operating frequency.

[0014] From the formula: The cumulative remainder value K can be obtained, that is, the remainder of each signal cycle is accumulated. When the cumulative remainder of multiple signal cycles is greater than or equal to 1, the remainder is carried over to complete the error correction of time T. The corrected T is the running time of the signal cycle required to be evenly divided / multiplied after processing. Then, the periodic signal is output by the programmable logic device FPGA.

[0015] The beneficial effects of this invention are: This application solves the problem of encoder signals fluctuating at different frequencies in the device, and outputs them to the line scan camera in a relatively dynamic and uniform manner, so that the photos taken are smoother and clearer. Attached Figure Description

[0016] Figure 1 This is a schematic diagram showing the running time of the signal cycle required for the double output of the present invention;

[0017] Figure 2 This is a schematic diagram illustrating the running time of the signal cycle required by the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that when a component is said to be "mounted on" another component, it can be directly mounted on the other component or may be interspersed with a component. When a component is said to be "set on" another component, it can be directly set on the other component or may be interspersed with a component. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or may be interspersed with a component.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0021] Please refer to Figures 1 to 2 An adaptive signal control method according to an embodiment of this application includes the following steps:

[0022] S1. Initialize the programmable logic device FPGA and set the preset value n of the encoder's operating frequency;

[0023] S2. The pulse signal of one signal cycle is counted using the counting function of the FPGA (Programmable FPGA). The sum of the duration of one high-level pulse and the duration of one low-level pulse is denoted as one signal cycle, and one signal cycle is denoted as T. The high-level pulse signal of one signal cycle is denoted as T_0. H The low level of a pulse signal in one signal cycle is denoted as T. L ;

[0024] S3. By using the PLL function of the FPGA (FPGA programmable logic device), the clock frequency is made to be greater than 100MHz.

[0025] S4. When the pulse signal has two identical edge timing signals, one signal cycle detection is completed, and the programmable logic device FPGA stops counting.

[0026] S5. Start the data calculation function;

[0027] From the formula: T and T can be obtained.a Where T is the running time of one signal cycle in step S2, T a T is the remainder of the running time of one signal cycle. H T is the high level of a pulse signal for one signal cycle. L The low level of a pulse signal that constitutes one signal cycle;

[0028] S6. Accumulate the remainders in the algorithm. When the remainders generate a carry, complete the time error correction, so that the signal period error value is minimized and infinitely close to the preset value n of the operating frequency.

[0029] From the formula: K can be obtained, and the remainder of each signal cycle is accumulated. When the remainder of multiple signal cycles is accumulated to 1, the remainder is carried over to complete the time error correction. K is the running time of the signal cycle required to be evenly divided / multiplied after processing. Then, the periodic signal is output using a programmable logic device (FPGA).

[0030] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0031] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A signal adaptive control method, characterized in that, Includes the following steps: S1. Initialize the programmable logic device FPGA and set the preset value n of the encoder's operating frequency; S2. The pulse signal of one signal cycle is counted using the counting function of the FPGA (Programmable FPGA). The sum of the duration of one high-level pulse and the duration of one low-level pulse is denoted as one signal cycle, and one signal cycle is denoted as T. The high-level pulse signal of one signal cycle is denoted as T_0. H The low level of a pulse signal in one signal cycle is denoted as T. L ; S3. By using the PLL function of the FPGA (FPGA programmable logic device), the clock frequency is made greater than 100MHz. S4. When the pulse signal has two identical edge timing signals, one signal cycle detection is completed, and the programmable logic device FPGA stops counting. S5. Start the data calculation function; From the formula: ； T and T can be obtained a Where T is the running time of one signal cycle in step S2, T a T is the remainder of the running time of one signal cycle. H T is the high level of a pulse signal for one signal cycle. L The low level of a pulse signal that constitutes one signal cycle; S6. Accumulate the remainders in the algorithm. When the remainders generate a carry, complete the time error correction to minimize the signal period error value and make it infinitely close to the preset value n of the operating frequency. From the formula: ； The cumulative remainder value K can be obtained, which is the sum of the remainders for each signal cycle. When the cumulative remainders of multiple signal cycles are greater than or equal to 1, the remainder is carried over to complete the error correction of time T. The corrected T is the running time of the signal cycle required to be evenly divided / multiplied after processing. Then, the periodic signal is output using a programmable logic device (FPGA).

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