Preparation method of semiconductor device
By depositing a dense dielectric layer in the trench, the problem of metal silicide diffusion caused by edge depression of the shallow trench isolation structure is solved, thereby improving the electrical performance of the device.
Patent Information
- Application Number
- CN202510811657.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-17
- Publication Date
- 2025-10-17
AI Technical Summary
The depression at the edge of the shallow trench isolation structure causes serious downward diffusion of metal silicide in the edge area of the active area, resulting in PN junction leakage and affecting device performance.
A dense and uniform auxiliary dielectric layer is deposited in the trench, covering the trench sidewalls and bottom walls to prevent subsequent wet cleaning from damaging the isolation material layer, forming a uniform isolation structure and preventing the metal silicide layer from diffusing at the edge of the active area.
The diffusion of the metal silicide layer in the edge area of the active area is avoided, the leakage of the PN junction is reduced, and the electrical performance of the device is improved.
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Figure CN120812934A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a preparation method of a semiconductor device. BACKGROUND
[0002] Precise positioning of metal silicide by a "self-aligned silicide process (salicide)" avoids short circuit risk and reduces contact resistance, which is one of the key processes in advanced semiconductor manufacturing to improve device performance. Diffusion of metal silicide can cause PN junction leakage, which increases the static power current (IDDQ) of SRAM (static random access memory). Since the formation of self-aligned metal silicide is easily affected by factors such as step height (between the active region and the shallow trench isolation structure) and thermal annealing process temperature, the morphology and profile of the self-aligned metal silicide are not uniform, and the degree of downward diffusion of metal silicide in the edge region of the active region is deeper than that in the middle region of the active region.
[0003] After the preparation of the shallow trench isolation structure (STI) and before the formation of the self-aligned silicide on the surface of the active region, the wafer surface also undergoes a multi-pass wet cleaning process, which can cause the shallow trench isolation structure to be partially consumed, and the shallow trench isolation structure near the edge region of the active region is more severely consumed, resulting in a depression at the edge of the shallow trench isolation structure. In the subsequent metal wiring process, the CT (contact hole / conductive plug) contacts the active region ACT / polysilicon gate poly structure, and the connection resistance is high, so nickel platinum (NiPt) alloy is deposited, and silicon nickel (NiSi) low resistance is formed in the subsequent annealing process. During the NiPt deposition process, the depression at the edge of the active region fills in the NiPt, causing more severe downward diffusion of metal silicide at the edge of the active region, resulting in PN junction leakage and affecting device performance. SUMMARY
[0004] The present application provides a preparation method of a semiconductor device, which can solve the problem of severe downward diffusion of metal silicide at the edge of the active region caused by the depression at the edge of the shallow trench isolation structure, resulting in PN junction leakage and affecting device performance.
[0005] The present application provides a preparation method of a semiconductor device, which can solve the problem of severe downward diffusion of metal silicide at the edge of the active region caused by the depression at the edge of the shallow trench isolation structure, resulting in PN junction leakage and affecting device performance.
[0006] A substrate is provided, and a first pad oxide layer and a hard mask layer are sequentially formed on the substrate;
[0007] The hard mask layer, the first pad oxide layer, and part of the thickness of the substrate are etched to form a plurality of trenches in the substrate;
[0008] forming a second liner oxide layer, wherein the second liner oxide layer covers the sidewalls and bottom wall of the trench and covers the side surface of the first liner oxide layer;
[0009] forming an auxiliary dielectric layer, wherein the auxiliary dielectric layer covers the second liner oxide layer, the side surface of the hard mask layer, and the upper surface of the hard mask layer;
[0010] forming an isolation material layer, wherein the isolation material layer covers the auxiliary dielectric layer and fills the remaining space of the trench;
[0011] The first liner oxide layer, the hard mask layer, the auxiliary dielectric layer on the upper surface of the substrate are removed, and the isolation material layer beyond the upper surface of the substrate is removed to obtain a shallow trench isolation structure in the trench.
[0012] Optionally, in the method for preparing the semiconductor device, the auxiliary dielectric layer is formed by a high-temperature chemical vapor deposition process.
[0013] Optionally, in the method for preparing the semiconductor device, the auxiliary dielectric layer is made of silicon dioxide.
[0014] Optionally, in the method for preparing the semiconductor device, the thickness of the auxiliary dielectric layer is 100 angstroms to 150 angstroms.
[0015] Optionally, in the method for preparing the semiconductor device, the second liner oxide layer is formed by a high-temperature furnace tube oxidation process.
[0016] Optionally, in the method for preparing the semiconductor device, the thickness of the second liner oxide layer is 40 angstroms to 50 angstroms.
[0017] Optionally, in the method for preparing the semiconductor device, the isolation material layer is formed by a high aspect ratio process.
[0018] Optionally, in the method for preparing the semiconductor device, after forming the shallow trench isolation structure, the method for preparing the semiconductor device further comprises:
[0019] A metal silicide layer is formed, where the metal silicide layer covers the surface of the active area between the shallow trench isolation structures.
[0020] Optionally, in the method for preparing the semiconductor device, the isolation material layer is made of silicon dioxide.
[0021] Optionally, in the method for preparing the semiconductor device, the material of the hard mask layer is silicon nitride.
[0022] The technical solution of this application has at least the following advantages:
[0023] The application can avoid the concave defect in the isolation material layer at the edge region of the active area (the edge region of the shallow trench isolation structure) by depositing a dense and uniform auxiliary medium layer in the trench before forming the isolation material layer, thereby avoiding the diffusion of the metal silicide layer formed on the surface of the active area to the concave position below the edge region of the active area, avoiding the PN junction leakage, and improving the electrical performance of the device. BRIEF DESCRIPTION OF DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the specific embodiments or prior art of the present application, the drawings needed in the specific embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0025] Figure 1 is a flowchart of the preparation method of the semiconductor device of the embodiment of the present application;
[0026] Figures 2-7 is a schematic diagram of the semiconductor structure in each process step of the preparation of the semiconductor device of the embodiment of the present application;
[0027] Among them, the sign explanation is as follows:
[0028] 10-substrate, 11-trench, 20-first pad oxide layer, 30-hard mask layer, 41-second pad oxide layer, 42-auxiliary medium layer, 43-isolation material layer, 40-shallow trench isolation structure. DETAILED DESCRIPTION
[0029] The technical solutions in the present application will be described clearly and completely below in combination with the drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0030] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.
[0031] In the description of the present application, it is necessary to point out that, unless explicitly defined and limited, the terms "mount", "connect", "connection" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or the internal communication of two elements, it can be wireless connection, or wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0032] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict.
[0033] The embodiment of the present application provides a preparation method of a semiconductor device, referring to Figure 1 , Figure 1 The flow chart of the preparation method of the semiconductor device of the embodiment of the present application is shown in FIG. 1, and the preparation method of the semiconductor device comprises the following steps:
[0034] Firstly, step S1 is performed: referring to Figure 2 , Figure 2 The semiconductor structure schematic diagram after forming the first pad oxide layer and the hard mask layer of the embodiment of the present application is shown in FIG. 2, and a substrate 10 is provided, and the first pad oxide layer 20 and the hard mask layer 30 are sequentially formed on the substrate 10.
[0035] In the embodiment, the material of the hard mask layer 30 is silicon nitride.
[0036] Then, step S2 is performed: referring to Figure 3 , Figure 3 The semiconductor structure schematic diagram after forming a plurality of grooves of the embodiment of the present application is shown in FIG. 3, and the hard mask layer 30, the first pad oxide layer 20 and part of the thickness of the substrate 10 are etched to form a plurality of grooves 11 in the substrate 10.
[0037] Then, step S3 is performed: referring to Figure 4 , Figure 4 The semiconductor structure schematic diagram after forming the second pad oxide layer of the embodiment of the present application is shown in FIG. 4, and the second pad oxide layer 41 is formed, which covers the side wall and bottom wall of the groove 11 and covers the side surface of the first pad oxide layer 20.
[0038] In the embodiment, the second pad oxide layer 41 is formed by high-temperature furnace tube oxidation process.
[0039] Preferably, the thickness of the second pad oxide layer 41 is 40 angstroms to 50 angstroms.
[0040] Further, step S4 is performed: referring to Figure 5 , Figure 5 is a schematic diagram of a semiconductor structure after forming an auxiliary dielectric layer in the embodiment of the present application. The auxiliary dielectric layer 42 is formed, covering the second liner oxide layer 41, the side surface of the hard mask layer 30, and the upper surface of the hard mask layer 30.
[0041] Preferably, the auxiliary dielectric layer 42 is formed by a high-temperature chemical vapor deposition process, wherein the process temperature is 800-1200°C, and the gases involved in the reaction at least include a silicon source gas and oxygen, wherein the flow rate of the silicon source gas is 50-200sccm, and the flow rate of the oxygen is 500-2000sccm.
[0042] In the embodiment, the material of the auxiliary dielectric layer 42 is silicon dioxide.
[0043] Preferably, the thickness of the auxiliary dielectric layer 42 is 100-150 angstroms.
[0044] Next, step S5 is performed: referring to Figure 6 , Figure 6 is a schematic diagram of a semiconductor structure after forming an isolation material layer in the embodiment of the present application. The isolation material layer 43 is formed, covering the auxiliary dielectric layer 42 and filling the remaining space of the trench 11.
[0045] Preferably, the isolation material layer 43 is formed by a high aspect ratio process (HARP).
[0046] In the embodiment, the material of the isolation material layer 43 is silicon dioxide. Specifically, the high aspect ratio process is used to deposit the isolation material layer 43 by thermal chemical vapor deposition (CVD), using a silicon-containing precursor (such as tetraethyl orthosilicate TEOS) and an oxygen-containing precursor (such as ozone O3) to react at a low temperature (for example, 300-500°C) to generate the isolation material layer 43. Unlike the plasma-enhanced CVD (PECVD) process, the high aspect ratio process does not require plasma bombardment, thereby reducing the risk of damage to the substrate 10.
[0047] Finally, step S6 is performed: referring to Figure 7 , Figure 7 is a schematic diagram of a semiconductor structure after forming a shallow trench isolation structure in the embodiment of the present application. The first liner oxide layer 20, the hard mask layer 30, the auxiliary dielectric layer 42 on the upper surface of the substrate 10 are removed, and the isolation material layer 43 beyond the upper surface of the substrate 10 is removed, to obtain the shallow trench isolation structure 40 in the trench 11.
[0048] Further, after forming the shallow trench isolation structure 40, the semiconductor device manufacturing method further comprises: forming a metal silicide layer (not shown) covering the active region surface between the shallow trench isolation structures 40.
[0049] In the present application, by depositing a dense and uniform auxiliary dielectric layer in the trench before forming the isolation material layer, the concave defect in the isolation material layer at the edge region of the active region (the edge region of the shallow trench isolation structure) caused by the subsequent multiple wet cleaning processes can be avoided, thus avoiding the diffusion of the metal silicide layer self-aligned deposited on the active region surface to the concave position below the edge region of the active region, avoiding the PN junction leakage, and improving the electrical performance of the device.
[0050] Obviously, the above embodiments are only examples for clearly illustrating the present application, and are not intended to limit the present application. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments are not required to be exhausted, and the obvious changes or variations derived therefrom are still within the protection scope of the present application.
Claims
1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, on which a first liner oxide layer and a hard mask layer are sequentially formed; etching the hard mask layer, the first liner oxide layer, and a partial thickness of the substrate to form a plurality of trenches in the substrate; forming a second liner oxide layer, wherein the second liner oxide layer covers the sidewalls and bottom wall of the trench and covers the side surface of the first liner oxide layer; forming an auxiliary dielectric layer, wherein the auxiliary dielectric layer covers the second liner oxide layer, the side surface of the hard mask layer, and the upper surface of the hard mask layer; forming an isolation material layer, wherein the isolation material layer covers the auxiliary dielectric layer and fills the remaining space of the trench; The first liner oxide layer, the hard mask layer, the auxiliary dielectric layer on the upper surface of the substrate are removed, and the isolation material layer beyond the upper surface of the substrate is removed to obtain a shallow trench isolation structure in the trench.
2. The method for preparing a semiconductor device according to claim 1, wherein: The auxiliary dielectric layer is formed by a high-temperature chemical vapor deposition process.
3. The method for preparing a semiconductor device according to claim 1, wherein: The auxiliary dielectric layer is made of silicon dioxide.
4. The method for preparing a semiconductor device according to claim 1, wherein: The auxiliary dielectric layer has a thickness of 100 angstroms to 150 angstroms.
5. The method for preparing a semiconductor device according to claim 1, wherein: The second liner oxide layer is formed by a high temperature furnace tube oxidation process.
6. The method for preparing a semiconductor device according to claim 1, wherein: The thickness of the second liner oxide layer is 40 angstroms to 50 angstroms.
7. The method for preparing a semiconductor device according to claim 1, wherein: The isolation material layer is formed by adopting a high aspect ratio process.
8. The method for preparing a semiconductor device according to claim 1, wherein: After forming the shallow trench isolation structure, the method for preparing the semiconductor device further includes: A metal silicide layer is formed, where the metal silicide layer covers the surface of the active area between the shallow trench isolation structures.
9. The method for manufacturing a semiconductor device according to claim 1, wherein: The isolation material layer is made of silicon dioxide.
10. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the hard mask layer is silicon nitride.