Semiconductor device manufacturing method for solving damage of grid polycrystalline silicon
By depositing a protective layer on the gate polysilicon layer, the corrosion problem of the gate polysilicon in the peripheral logic region by the phosphoric acid solution was solved, ensuring that the thickness and resistance value of the gate polysilicon met the design rules, and improving the performance and reliability of the semiconductor device.
Patent Information
- Application Number
- CN202510782354.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-11
- Publication Date
- 2025-10-17
AI Technical Summary
During the semiconductor device manufacturing process, when phosphoric acid solution removes the silicon nitride layer in the memory cell region, it causes corrosion damage to the gate polysilicon layer in the peripheral logic region, resulting in thinning of its thickness and increase in resistance, which affects the electrical performance and reliability of the device.
A protective layer is deposited on the gate polysilicon layer, and this protective layer is used in subsequent processes to protect the gate polysilicon of the peripheral logic region, preventing contact with phosphoric acid solution. This is achieved by protecting the gate polysilicon layer of the peripheral logic region when the hard mask layer is removed from the cell region.
It effectively prevents damage and thickness reduction of the gate polysilicon in the peripheral logic region, ensures that the resistance value meets the design requirements, and improves the performance and reliability of semiconductor devices, especially suitable for the manufacturing of embedded flash memory devices in advanced process nodes.
Smart Images
Figure CN120812940A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device manufacturing method for solving gate poly (GPL) damage, and is particularly suitable for the manufacturing process of embedded flash (Eflash) devices. BACKGROUND
[0002] In the manufacturing process of semiconductor devices, especially embedded flash devices, a plurality of thin film deposition, lithography, etching and other steps are usually involved. For example, in a typical 40 nanometer process node embedded flash (40Eflash) process flow, the flow may refer to the 90 nanometer process node flash process flow. After the gate poly deposition is completed, subsequent patterning and material removal processes need to be performed on the cell area (or Mcell area) and the peripheral logic area.
[0003] Specifically, when processing the cell area, it is usually necessary to remove a specific material layer in the area, such as a silicon nitride (SiN) layer. The removal of the silicon nitride layer is usually performed by chemical wet etching, for example, by immersing the wafer in a phosphoric acid (H3PO4) solution. However, the inventors have found in their research that when using a phosphoric acid solution to remove the silicon nitride layer in the cell area, the phosphoric acid solution will not only react with the target silicon nitride to be removed, but also cause undesirable corrosion of the gate poly layer that has been formed in the peripheral logic area. This corrosion will cause the gate poly layer in the peripheral logic area to thin, i.e., so-called gate poly damage. The thinning of the gate poly layer thickness will directly cause its resistance value to increase, resulting in a large deviation of the resistance value from the target value set in the engineering design rule (EDR). This deviation of the resistance value will affect the performance of the peripheral logic circuit, and may even cause the device to fail, thereby adversely affecting the yield and reliability of the product.
[0004] Therefore, how to effectively protect the gate poly layer in the peripheral logic area from chemical corrosion damage while performing the removal process of the specific layer (such as the silicon nitride layer) in the cell area, to prevent the thickness from thinning and the resistance from increasing, is a technical problem that needs to be solved in the current semiconductor manufacturing field, especially in the manufacturing of advanced process node flash memory. SUMMARY
[0005] The technical problem to be solved by the present application is that in the manufacturing process of the existing semiconductor device (especially embedded flash memory device), when a phosphoric acid solution is used to remove the hard mask layer (such as silicon nitride layer) of the memory cell region, the phosphoric acid solution will inevitably contact and corrode the gate polysilicon layer of the peripheral logic region, causing the gate polysilicon layer to thin, and thus its resistance value to increase, deviating from the target value of the engineering design rule (EDR), and finally affecting the electrical performance and reliability of the device.
[0006] To solve the above technical problem, the present application provides a semiconductor device manufacturing method for solving the damage of gate polysilicon.
[0007] According to one aspect of the present application, a semiconductor device manufacturing method for solving the damage of gate polysilicon is provided, which at least comprises:
[0008] Step one, depositing a gate polysilicon layer on a semiconductor substrate having a cell region and a peripheral logic region;
[0009] Step two, depositing a protection layer on the gate polysilicon layer;
[0010] Step three, processing the cell region, including: forming a photoresist pattern for defining the cell region; removing the protection layer in the cell region based on the photoresist pattern; and removing the gate polysilicon layer in the cell region;
[0011] Step four, removing the hard mask layer and the interlayer dielectric layer of the cell region, wherein when the hard mask layer of the cell region is removed, the gate polysilicon layer of the peripheral logic region is protected by the protection layer covering thereon;
[0012] Step five, after the peripheral logic region gate polysilicon etching process, removing the protection layer in the peripheral logic region.
[0013] Preferably, in step one, before depositing the gate polysilicon layer, a structure has been formed on the semiconductor substrate, including: a first gate oxide layer formed on the cell region, a second gate oxide layer formed on the peripheral logic region; a stack structure formed on the first gate oxide layer of the cell region, the stack structure including, from bottom to top, a floating gate layer, an inter-electrode dielectric layer, a control gate layer, and the inter-layer dielectric layer; etching the inter-layer dielectric layer of the cell region to form a first trench; forming a first side wall structure on the sidewall of the first trench; etching the control gate layer and the inter-electrode dielectric layer exposed at the bottom of the first trench to form a second trench; forming a second side wall structure on part of the sidewall of the second trench; etching the floating gate layer and the first gate oxide layer exposed at the bottom of the second trench to form a third trench; forming a tunnel oxide layer on the bottom wall and sidewall of the third trench; filling the third trench with a select gate; forming a select gate oxide layer on the select gate; then forming the hard mask layer on the select gate oxide layer, and the inter-layer dielectric layer remaining in the cell region; and, optionally, forming an oxide layer on the hard mask layer of the cell region; wherein the gate polysilicon layer is deposited on the uppermost oxide layer (if formed) or the hard mask layer (if not formed) of the cell region, and on the second gate oxide layer of the peripheral logic region.
[0014] Preferably, in step four, the hard mask layer is a silicon nitride layer.
[0015] Preferably, in step four, the silicon nitride layer of the cell region is removed using a phosphoric acid solution.
[0016] Preferably, the protective layer is a protective oxide layer.
[0017] Preferably, the protective oxide layer is a protective silicon oxide layer.
[0018] Preferably, the protective silicon oxide layer is formed by a plasma enhanced chemical vapor deposition process.
[0019] Preferably, in step three, the protective layer in the cell region is removed by a wet etching process.
[0020] Preferably, in step five, the protective layer in the peripheral logic region is removed in a wet stripping process after etching the gate polysilicon layer of the peripheral logic region.
[0021] Preferably, the semiconductor device is a flash memory device, such as a 40 nanometer process node embedded flash memory device. As described above, the semiconductor device manufacturing method of the present application to solve gate polysilicon damage has the following beneficial effects:
[0022] The application prevents damage and thickness thinning of the gate polysilicon in the peripheral logic area by depositing a protective layer on the gate polysilicon layer and using the protective layer to protect the gate polysilicon in the peripheral logic area in a specific process step of removing the hard mask layer in the cell area, thereby ensuring that the resistance value meets the design requirements, improving the performance and reliability of the semiconductor device, and being especially suitable for embedded flash memory device manufacturing of advanced process nodes. BRIEF DESCRIPTION OF DRAWINGS
[0023] Figure 1 A process flow of the application is shown.
[0024] Figure 2 Deposition of a gate polysilicon layer is shown.
[0025] Figure 3 Deposition of a protective layer on the gate polysilicon layer is shown.
[0026] Figure 4 Formation of a photoresist pattern for defining the cell area is shown.
[0027] Figure 5 Removal of the protective layer in the cell area is shown.
[0028] Figure 6 Removal of the gate polysilicon layer in the cell area is shown.
[0029] Figure 7 Removal of the hard mask layer in the cell area is shown.
[0030] Figure 8 Removal of the protective layer in the peripheral logic area is shown. DETAILED DESCRIPTION
[0031] The embodiments of the application will be described below with reference to specific examples. Those skilled in the art can easily understand other advantages and effects of the application from the content disclosed in the specification. The application can also be implemented or applied in different specific embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the application.
[0032] Reference will now be made to Figure 1 The embodiment of the application provides a semiconductor device manufacturing method for solving damage to gate polysilicon, which comprises at least the following steps:
[0033] Step one, depositing a gate polysilicon layer 115 on a semiconductor substrate 101 having a cell area and a peripheral logic area, to form a structure as shown in Figure 2 .
[0034] In some embodiments, in step one, before depositing the gate polysilicon layer 115, the following structures have been formed on the semiconductor substrate 101: a first gate oxide layer 103 is formed on the cell region, and a second gate oxide layer 102 is formed on the peripheral logic region; a stack structure is formed on the first gate oxide layer 103 of the cell region, which includes, from bottom to top, a floating gate layer 104, an inter-electrode dielectric layer 105, a control gate layer 106, and an interlayer dielectric layer 107; the interlayer dielectric layer 107 of the cell region is etched to form a first trench; a first side wall structure 108 is formed on the sidewall of the first trench; the control gate layer 106 and the inter-electrode dielectric layer 105 exposed at the bottom of the first trench are etched to form a second trench; a second side wall structure 109 is formed on part of the sidewall of the second trench; the floating gate layer 104 and the first gate oxide layer 103 exposed at the bottom of the second trench are etched to form a third trench; a tunnel oxide layer 110 is formed on the bottom wall and the sidewall of the third trench; a select gate 111 is formed in the third trench; a select gate oxide layer 112 is formed on the select gate 111; then a hard mask layer 113 is formed on the select gate oxide layer 112, and the remaining interlayer dielectric layer 107 in the cell region; and, optionally, an oxide layer 114 is formed on the hard mask layer 113 of the cell region; wherein the gate polysilicon layer 115 is deposited on the uppermost oxide layer 114 (if formed) or the hard mask layer 113 (if not formed) in the cell region, and on the second gate oxide layer 102 in the peripheral logic region. Through such a pre-process, a structural foundation is laid for the subsequent deposition of the gate polysilicon layer 115 and the distinction between the cell region and the peripheral logic region.
[0035] For example, the inter-electrode dielectric layer 105 can be a multi-layer structure, typically an oxide-nitride-oxide (ONO) stack structure. Specifically, the ONO stack structure can include, from bottom to top, a bottom oxide layer, a nitride layer, and a top oxide layer. The bottom oxide layer can be composed of silicon dioxide (SiO2) grown by, for example, thermal oxidation, or formed by a chemical vapor deposition (CVD) method, such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The nitride layer can be composed of silicon nitride (Si3N4) formed by, for example, LPCVD or PECVD, which is mainly used as a charge blocking layer in a floating gate type flash memory to prevent charge leakage from the floating gate, or as a charge trapping layer in a charge trapping type flash memory (such as SONOS type). The top oxide layer can be composed of silicon dioxide formed by, for example, a CVD method, such as high temperature oxide (HTO) deposition or CVD using tetraethyl orthosilicate (TEOS) as a precursor, for isolating the control gate and the nitride layer. Such an ONO structure is widely used in flash memory devices due to its excellent charge retention characteristics and reliability.
[0036] For example, the interlayer dielectric layer 107, which is located above the control gate layer 106 in this particular stack structure, functions more as a hard mask or a dielectric layer for process integration after being etched to form the first trench in the subsequent step. The interlayer dielectric layer 107 can be composed of a dielectric material suitable for serving as a hard mask or a protective layer 116 in the subsequent etching process. In one embodiment, the interlayer dielectric layer 107 can be silicon dioxide (SiO2), for example, formed by chemical vapor deposition (such as PECVD or LPCVD using a TEOS source, or high-density plasma chemical vapor deposition HDP-CVD). In another embodiment, the interlayer dielectric layer 107 can also be silicon nitride (Si3N4), for example, formed by LPCVD or PECVD. The material of the interlayer dielectric layer 107 is usually selected with consideration of its etching selectivity with respect to the material of the underlying control gate layer 106 (usually polysilicon) and the subsequent etching chemicals, to ensure accurate pattern transfer.
[0037] Step two, depositing a protective layer 116 on the gate polysilicon layer 115 to form a structure as shown in Figure 3 Step three, processing the cell region, including: forming a photoresist pattern for defining the cell region, forming a structure as shown in
[0038] In some embodiments, the protective layer 116 is a protective oxide layer.
[0039] Further, in some embodiments, the protective oxide layer is a protective silicon oxide layer. Such a protective silicon oxide layer has good insulating properties and process compatibility, and can effectively isolate the subsequent chemicals from affecting the gate polysilicon layer 115.
[0040] Further, in some embodiments, the protective silicon oxide layer is formed by a plasma-enhanced chemical vapor deposition (PECVD) process. The PECVD process is usually performed at a relatively low temperature, which helps to reduce the impact on the thermal budget of the underlying device structure, and can form a dense and uniform thin film to provide reliable protection. The thickness of the protective silicon oxide layer can be adjusted according to specific process requirements, for example, it can be several nanometers to several tens of nanometers, to ensure sufficient protection while not excessively increasing the difficulty of subsequent removal.
[0041] Step three, processing the cell region, including: forming a photoresist pattern for defining the cell region, forming a structure as shown in Figure 4 Step four, removing the protective layer 116 in the cell region based on the photoresist pattern, to form a structure as shown in Figure 5 Step five, removing the gate polysilicon layer 115 in the cell region, to form a structure as shown in Figure 6 Step three, processing the cell region, including: forming a photoresist pattern for defining the cell region, forming a structure as shown in
[0042] In some embodiments, in step three, the protective layer 116 in the cell region is removed by a wet etching process. In order to remove the protective layer 116 in the cell region by a wet etching process, a specific chemical etching solution can be used, which has high selectivity to the material of the protective layer 116, can accurately remove the exposed protective layer 116 in the cell region, has little effect on the underlying gate polysilicon layer 115 or the photoresist pattern, and is simple to operate and relatively controllable in cost. This step is to expose the gate polysilicon layer 115 in the cell region for subsequent removal.
[0043] In step four, the hard mask layer 113 and the interlayer dielectric layer 107 in the cell region are removed, and when the hard mask layer 113 in the cell region is removed, the gate polysilicon layer 115 in the peripheral logic region is protected by the protective layer 116 covering thereon, forming a structure as shown in Figure 7
[0044] In some embodiments, in step four, the hard mask layer 113 is a silicon nitride layer. Silicon nitride layer is widely used as a hard mask in semiconductor manufacturing, which has good etching selectivity and chemical stability, and can effectively protect the area covered in a specific process step.
[0045] Further, in some embodiments, in step four, a phosphoric acid solution is used to remove the silicon nitride layer in the cell region. Phosphoric acid is a commonly used wet etching solution for removing silicon nitride, which has good removal rate and selectivity to silicon nitride. However, phosphoric acid will also cause corrosion to polysilicon. In the method of the present application, since the gate polysilicon layer 115 in the peripheral logic region is covered by the protective layer 116, when the silicon nitride layer in the cell region is removed by phosphoric acid, the gate polysilicon layer 115 in the peripheral logic region will not directly contact the phosphoric acid, thereby avoiding damage.
[0046] In some embodiments, in step four, the gate polysilicon layer 115 in the peripheral logic region is prevented from being thinned in the removal of the hard mask layer 113 in the cell region by the protection of the protective layer 116. This is a key technical effect provided by the present application, which directly solves the problem of thinning of the gate polysilicon in the peripheral logic region caused by phosphoric acid corrosion in the prior art. The presence of the protective layer 116, such as the protective silicon oxide layer as described above, can effectively act as a physical barrier to block the contact between the corrosive chemicals such as phosphoric acid and the gate polysilicon in the peripheral logic region, thereby maintaining the original thickness of the gate polysilicon and ensuring the structural integrity thereof.
[0047] In some embodiments, in step four, the protection layer 116 protects the gate poly 115 in the peripheral logic region, so that the resistance of the gate poly 115 in the peripheral logic region is more closely matched to the target value of the engineering design rule (EDR). The thickness of the gate poly directly affects its conductive cross-sectional area, which in turn determines its resistance value. Since the thickness thinning is avoided, the resistance of the gate poly in the peripheral logic region can be more accurately controlled within the range required by the engineering design rule, which is crucial to ensure the normal operation and performance of the peripheral logic circuit. For example, in the original process, the resistance of the gate poly in the peripheral logic region can be larger than the EDR, while after using the method of the present application, the resistance of the gate poly in the peripheral logic region of the improved process can be closer to the target value of the EDR, improving the consistency and reliability of the electrical parameters of the device.
[0048] Step five, after the gate poly etching process in the peripheral logic region, the protection layer 116 in the peripheral logic region is removed, forming a structure as shown in Figure 8 .
[0049] In some embodiments, in step five, the protection layer 116 in the peripheral logic region is removed in the wet strip process after the gate poly 115 in the peripheral logic region is etched. This means that the removal of the protection layer 116 can be integrated into the existing process flow, such as the wet strip step after the gate poly etching (GPLET) is completed, and the residual protection layer 116 is removed at the same time. This not only avoids adding an additional dedicated etching step to remove the protection layer 116, simplifying the overall process flow, but also reduces the additional process cost and complexity, improving production efficiency.
[0050] In some embodiments, the semiconductor device manufactured using the above method is a flash memory device. This method is particularly suitable for the manufacturing process of flash memory devices that have high requirements for the thickness and resistance of the gate poly, as these parameters directly affect the programming and erasing characteristics of the flash memory cells and the performance of the peripheral drive circuit.
[0051] Further, in some embodiments, the flash memory device is a 40 nanometer process node embedded flash memory device. For advanced process nodes such as 40 nanometers, device sizes continue to shrink, and the thickness of each functional layer is also thinned accordingly, with a more stringent process window. Therefore, even a small damage to the gate poly can have a significant impact on its electrical performance. The protection method provided by the present application has important practical application value for such advanced node embedded flash memory devices (such as 40Eflash), which can effectively solve the problem of thinning of the gate poly thickness, thereby improving product yield and reliability.
[0052] In summary, the application effectively prevents the damage and thickness thinning of the gate polysilicon of the peripheral logic area by depositing a protective layer 116 on the gate polysilicon layer 115 and using the protective layer 116 to protect the gate polysilicon of the peripheral logic area in the subsequent process step of removing the hard mask layer 113 of the unit area, thereby ensuring that the resistance value of the gate polysilicon meets the design requirements, improving the performance and reliability of the semiconductor device, and being especially suitable for the manufacturing of embedded flash memory devices of advanced process nodes.
[0053] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the application, and only show the components related to the application in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The type, number and proportion of the components in actual implementation can be arbitrarily changed, and the component layout type can be more complex.
[0054] The above embodiments only illustratively explain the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the application should be covered by the claims of the application.
Claims
1. A method for manufacturing a semiconductor device to solve gate polysilicon damage, characterized in that: At least: Step 1: depositing a gate polysilicon layer on a semiconductor substrate having a cell region and a peripheral logic region; Step 2: depositing a protective layer on the gate polysilicon layer; Step 3: processing the unit area, including: forming a photoresist pattern for defining the cell area; removing the protective layer in the cell area based on the photoresist pattern; and removing the gate polysilicon layer in the cell area; Step 4: removing the hard mask layer and the interlayer dielectric layer of the cell area, wherein when the hard mask layer of the cell area is removed, the gate polysilicon layer of the peripheral logic area is protected by the protective layer covering the gate polysilicon layer; Step 5: After the gate polysilicon etching process in the peripheral logic area, remove the protection layer in the peripheral logic area.
2. The method for manufacturing a semiconductor device for solving gate polysilicon damage according to claim 1, wherein: In step 1, before depositing the gate polysilicon layer, the following structure has been formed on the semiconductor substrate: A first gate oxide layer is formed on the cell area, and a second gate oxide layer is formed on the peripheral logic area; A stacked structure is formed on the first gate oxide layer of the cell region, the stacked structure comprising a floating gate layer, an inter-electrode dielectric layer, a control gate layer and the inter-layer dielectric layer stacked in sequence from bottom to top; Etching the interlayer dielectric layer in the cell area to form a first trench; forming a first spacer structure on a sidewall of the first trench; Etching the control gate layer and the inter-electrode dielectric layer exposed at the bottom of the first trench to form a second trench; forming a second spacer structure on a portion of the sidewall of the second trench; Etching the floating gate layer and the first gate oxide layer exposed at the bottom of the second trench to form a third trench; forming a tunneling oxide layer on the bottom wall and sidewalls of the third trench; Filling the third trench to form a select gate; forming a select gate oxide layer on the select gate; Then, forming the hard mask layer on the select gate oxide layer and the remaining interlayer dielectric layer in the cell area; and, optionally forming an oxide layer on the hard mask layer of the cell region; The gate polysilicon layer is deposited on the uppermost oxide layer (if the oxide layer has been formed) or the hard mask layer (if the oxide layer has not been formed) in the cell area, and is deposited on the second gate oxide layer in the peripheral logic area.
3. The method for manufacturing a semiconductor device for solving gate polysilicon damage according to claim 1 or 2, characterized in that: In step 4, the hard mask layer is a silicon nitride layer.
4. The method for manufacturing a semiconductor device for solving gate polysilicon damage according to claim 3, wherein: In step 4, a phosphoric acid solution is used to remove the silicon nitride layer in the cell area.
5. The method for manufacturing a semiconductor device for solving gate polysilicon damage according to claim 1 or 2, characterized in that: The protective layer is a protective oxide layer.
6. The method for manufacturing a semiconductor device for solving gate polysilicon damage according to claim 5, wherein: The protective oxide layer is a protective silicon oxide layer.
7. The method for manufacturing a semiconductor device for solving gate polysilicon damage according to claim 6, wherein: The protective silicon oxide layer is formed by a plasma enhanced chemical vapor deposition process.
8. The method for manufacturing a semiconductor device for solving gate polysilicon damage according to claim 1 or 2, characterized in that: In step three, the protection layer in the cell area is removed by a wet etching process.
9. The method for manufacturing a semiconductor device for solving gate polysilicon damage according to claim 1 or 2, characterized in that: In step five, the protection layer in the peripheral logic region is removed in a wet stripping process after etching the gate polysilicon layer in the peripheral logic region.
10. The method for manufacturing a semiconductor device for solving gate polysilicon damage according to claim 1 or 2, characterized in that: The semiconductor device is a flash memory device.
11. The method for manufacturing a semiconductor device for solving gate polysilicon damage according to claim 10, wherein: The flash memory device is an embedded flash memory device of 40 nanometer process node.
12. The method for manufacturing a semiconductor device for solving gate polysilicon damage according to claim 1 or 2, characterized in that: In step 4, the protection layer is used to protect the gate polysilicon layer in the peripheral logic region from being thinned when the hard mask layer in the cell region is removed.
13. The method for manufacturing a semiconductor device for solving gate polysilicon damage according to claim 1, 2 or 12, characterized in that: In step four, the protection layer is used to protect the gate polysilicon layer in the peripheral logic region so that the resistance value of the gate polysilicon layer is more closely matched with the target value of the engineering design rule.