Manufacturing method of SGT device
The first oxide layer and polysilicon layer are formed in SGT device manufacturing through a one-step oxidation process, which solves the problems of complex HDP CVD process and wafer warping, and achieves the effect of simplifying the process flow and improving integration.
Patent Information
- Application Number
- CN202510811926.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-17
- Publication Date
- 2025-10-17
AI Technical Summary
In the existing SGT device manufacturing process, the HDP CVD process to fill the pits on both sides of the shield gate is complex and easily causes wafer warping. In addition, the thermal oxidation process causes the overlapping area between the polysilicon gate and the shield gate to increase, thereby increasing the gate-source capacitance.
A one-step oxidation process is used to form a first oxide layer and a polysilicon layer on the surface of the substrate. The excess part is removed by dry etching to form a second oxide layer to cover the polysilicon layer, eliminating the HDP filling and wet etching steps and reducing the overlapping area of the polysilicon gate and the shield gate.
The process flow is simplified, stress risk is reduced, the overlapping area between the polysilicon gate and the shield gate is reduced, and the device integration and cell size reduction effect are improved.
Smart Images
Figure CN120812970A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor devices, and in particular to a manufacturing method of an SGT device. BACKGROUND
[0002] In the manufacturing process of a split gate trench (SGT) semiconductor device, the formation of an inter poly oxide (IPO) layer is a crucial step. There are currently two main IPO fabrication processes in the industry: a thermal oxidation process and a high density plasma chemical vapor deposition (HDP CVD) process.
[0003] Before forming the IPO, the thermal oxidation process requires removing the oxide above the split gate and on the sidewall of the trench through a wet etching process or an etching process. This process easily leads to excessive exposure of the split gate poly (Poly) and the IPO formed after thermal oxidation is mostly in a hat-shaped morphology, which increases the overlapping area of the poly gate and the split gate, and further increases the gate-to-source capacitance (Cgs).
[0004] When the HDP CVD process is used to fill the recesses on both sides of the split gate, the oxide layer also needs to be etched back to make the split gate flush with the oxide on both sides. This process is not only complicated but also costly. In addition, in the HDP CVD process, the IPO needs to be completely filled in the trench and etched back to the required thickness, which is a complex process with high cost. Moreover, the stress in the HDP CVD process is large, which easily leads to wafer warping, increasing the risk of line breakage or short circuit, via connection failure, and other line connection risks in the wafer. SUMMARY
[0005] The present application provides a manufacturing method of an SGT device, which can solve the problem of complex process and wafer warping caused by the HDP CVD process for filling the recesses on both sides of the split gate in the related art.
[0006] In one aspect, the present application provides a manufacturing method of an SGT device, comprising: providing a substrate, the substrate having a trench formed therein, and a region on the substrate for forming a semiconductor device including a first region and a second region, the first region being used for forming an SGT device, and the second region being used for forming an isolation structure; forming a first oxide layer on the surface of the substrate and the inner wall and bottom of the trench; filling a poly silicon material in the trench, so that the trench and the first oxide layer are covered by the first poly silicon layer; etching to remove the first polysilicon layer outside the trench; etching to thin the first oxide layer and the first polysilicon layer; etching the first polysilicon layer in the first region trench to a preset etching depth; removing the first oxide layer of the first region trench sidewall so that the first polysilicon layer is exposed; forming a second oxide layer in the first region trench.
[0007] In some embodiments, the trench width after forming the first oxide layer is 1000 angstroms to 4000 angstroms.
[0008] In some embodiments, the forming a second oxide layer in the first region trench comprises: forming the second oxide layer by a thermal oxidation process.
[0009] In some embodiments, the forming a second oxide layer in the first region trench further comprises, before the forming the second oxide layer by a thermal oxidation process: ion implantation on the first polysilicon layer.
[0010] In some embodiments, the etching to thin the first oxide layer and the first polysilicon layer comprises: thinning the first oxide layer and the first polysilicon layer on the substrate surface by a dry etching process.
[0011] In some embodiments, the thickness of the first oxide layer after thinning is 500 angstroms to 2000 angstroms.
[0012] In some embodiments, the removing the first oxide layer of the first region trench sidewall comprises: removing the first oxide layer of the first region trench sidewall by a wet etching process.
[0013] In some embodiments, the etching the first polysilicon layer in the first region trench to a preset etching depth, the depth in the first region trench is 0.3 μm to 2 μm.
[0014] The technical scheme of the present application has at least the following advantages: one-step oxidation process can ensure that the exposed polysilicon is completely oxidized to form IPO, reducing the overlapping area between the polysilicon gate and the shielding gate, thereby eliminating the subsequent HDP filling and wet process, reducing the complexity of the process flow; at the same time, since the subsequent HPP filling is not required, the stress during the wafer fabrication process can be reduced; after depositing the first oxide layer in the trench, the width is controlled to a smaller size, the gate width is narrowed, the cell size can be further reduced, and the integration of the device is improved. BRIEF DESCRIPTION OF DRAWINGS
[0015] In order to more clearly illustrate the technical solutions in the specific embodiments or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the prior art description. Obviously, the drawings described below are some embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without creative effort based on these drawings belong to the protection scope of the present application.
[0016] Figure 1 is a flow chart of a manufacturing method of an SGT device provided by an exemplary embodiment of the present application; Figure 2 is a structural cross-sectional view of a substrate with trenches formed provided by an exemplary embodiment of the present application; Figure 3 is a structural cross-sectional view after a first oxide layer is formed provided by an exemplary embodiment of the present application; Figure 4 is a structural cross-sectional view after a first polysilicon layer is formed provided by an exemplary embodiment of the present application; Figure 5 is a structural cross-sectional view after the first polysilicon layer outside the trenches is etched away provided by an exemplary embodiment of the present application; Figure 6 is a structural cross-sectional view after the first polysilicon layer inside the trenches is weakened provided by an exemplary embodiment of the present application; Figure 7 is a structural cross-sectional view before the first polysilicon layer is etched provided by an exemplary embodiment of the present application; Figure 8 is a structural cross-sectional view after the first oxide layer is etched provided by an exemplary embodiment of the present application; Figure 9 is a structural cross-sectional view after a second oxide layer is formed provided by an exemplary embodiment of the present application; Figure 10 is a structural cross-sectional view after ion implantation before the second oxide layer is formed provided by an exemplary embodiment of the present application; Figure 11 is an SEM image of an SGT device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0017] The technical solutions in the present application will be described clearly and completely below in conjunction with the drawings. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the protection scope of the present application.
[0018] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.
[0019] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements inside, it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0020] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict.
[0021] Reference Figure 1 It shows the flow chart of the manufacturing method of the SGT device provided by an exemplary embodiment of the present application, as shown in Figure 1 It includes: Step S201, providing a substrate, a trench is formed in the substrate, and the area on the substrate for forming a semiconductor device includes a first area and a second area, the first area is used for forming an SGT device, and the second area is used for forming an isolation structure; Reference Figure 2 It shows the structure sectional view of the substrate provided by an exemplary embodiment of the present application, as shown in Figure 2 It includes: For example, a n (negative) type silicon substrate 101 is selected, a plurality of trenches 102 with a width of 0.9 μm and a depth of 6 μm are formed in the substrate 101 by dry etching; the area on the substrate 101 for forming a semiconductor device includes a first area and a second area, the first area is used for forming an SGT device, and the second area is used for forming an isolation structure.
[0022] More specifically, the first region is used to form an active region of the SGT device, the second region isolation structure includes a dummy region and a guard ring region; the guard ring region includes a pull-out region and a termination ring region. The dummy region is an auxiliary filling structure for process uniformity or to achieve thermal equilibrium; the guard ring region can be used to improve the voltage resistance of the active region of the device or to isolate external interference.
[0023] Step S202, forming a first oxide layer on the surface of the substrate and the inner wall and bottom of the trench; Optionally, the width of the trench after being covered with the first oxide layer is 1000 angstroms to 4000 angstroms.
[0024] Optionally, the first oxide layer can be formed by a thermal oxidation process, or can be formed by a thermal oxidation and chemical vapor deposition process.
[0025] Referring to Figure 3 which shows a structure cross-sectional view after the first oxide layer is formed according to an example embodiment of the present application, as shown in Figure 3 includes: For example, the first oxide layer 103 is formed on the surface of the substrate 101 and in the trench 102 by a low-pressure chemical vapor deposition method, the first oxide layer 103 is a silicon dioxide layer, and the width of the trench 102 after being covered with the first oxide layer 103 is 2000 angstroms.
[0026] Step S203, filling the trench with a polysilicon material so that the trench and the first oxide layer are covered with a first polysilicon layer; Referring to Figure 4 which shows a structure cross-sectional view after the first polysilicon layer is formed according to an example embodiment of the present application, as shown in Figure 4 includes: For example, the trench 102 is filled with polysilicon by an HDPCVD process, and the first polysilicon layer 104 is formed to cover the first oxide layer 103 on the surface of the substrate after the filling.
[0027] Step S204, etching to remove the first polysilicon layer outside the trench; Referring to Figure 5 which shows a structure cross-sectional view after the first polysilicon layer outside the trench is etched according to an example embodiment of the present application, as shown in Figure 5 includes: For example, the first polysilicon layer 105 outside the trench 102 is etched to be removed by a polysilicon etching process, and the first polysilicon layer 104 is located in the trench 102 after the etching, and the height of the first polysilicon layer 104 is lower than the height of the first oxide layer 103 on the surface of the substrate 101.
[0028] Step S205, etching to thin the first oxide layer and the first polysilicon layer; Optionally, the first oxide layer and the first polysilicon layer on the substrate are etched by a dry etching process.
[0029] Optionally, the thickness of the thinned first oxide layer is between 500 angstroms and 2000 angstroms.
[0030] Referring to Figure 6 , a cross-sectional view of a structure after the first polysilicon layer in the trench is weakened is shown, as Figure 6 shown, comprising: Optionally, the thickness of the first oxide layer 103 and the first polysilicon layer 104 on the substrate 101 is etched by a dry etching process. When the thickness of the first oxide layer 103 is etched to 700 angstroms, the etching of the first oxide layer 103 is stopped, and the first polysilicon layer 104 in the trench 102 is continuously etched, so that the height of the first polysilicon layer 104 is flush with the surface of the substrate 101.
[0031] Optionally, the surface of the etched first polysilicon layer 104 is smoothed and leveled by a chemical mechanical polishing process, and a shielding gate electrode is formed at the bottom of the trench 102.
[0032] Step S206, etching the first polysilicon layer in the first region trench to a preset etching depth; Optionally, the preset etching depth includes a depth of 0.3 μm to 2 μm in the first region trench after etching.
[0033] Referring to Figure 7 , a cross-sectional view of a structure before etching the first polysilicon layer is shown, as Figure 7 shown, comprising: Optionally, the surface of the etched first polysilicon layer 104 is smoothed and leveled by a chemical mechanical polishing process, and a shielding gate electrode is formed at the bottom of the trench 102.
[0034] Step S207, removing the first oxide layer on the side wall of the first region trench to expose the first polysilicon layer; Optionally, the first oxide layer on the side wall of the first region trench can be removed by a wet etching process.
[0035] Referring to Figure 8 , a cross-sectional view of a structure after etching the first oxide layer is shown, as Figure 8 shown, comprising: Optionally, the surface of the etched first polysilicon layer 104 is smoothed and leveled by a chemical mechanical polishing process, and a shielding gate electrode is formed at the bottom of the trench 102.
[0036] Step S208 , forming a second oxide layer in the trench in the first region.
[0037] Optionally, the second oxide layer may be formed by a thermal oxidation process.
[0038] Optionally, before forming the second oxide layer through the thermal oxidation process, the method further includes: performing ion implantation on the first polysilicon layer.
[0039] Reference Figure 9 as well as Figure 10 , Figure 9 is a cross-sectional view of a structure after the second oxide layer is formed, provided by an exemplary embodiment of the present application; Figure 10 FIG. 1 is a cross-sectional view of a structure after ion implantation before the second oxide layer is formed, provided by an exemplary embodiment of the present application; Figure 9 and with Figure 10 Shown include: Exemplarily, after step S207 is completed, the photoresist on the second region is removed, and the sidewalls of the trench 102 and the first polysilicon layer 104 are oxidized by a thermal oxidation process to form a second oxide layer 106, which is an IPO layer; and at the same time, a gate oxide layer 107 is formed on the exposed sidewalls of the trench 102. Figure 10 As shown, before the thermal oxidation process forms the second oxide layer 106, the process further includes: performing silicon ion implantation on the first polysilicon layer 104 to increase the oxide thickness and ensure that the first polysilicon layer 104 is completely oxidized into the IPO layer.
[0040] Reference Figure 11 , Figure 11 This is a SEM image of a product manufactured by a manufacturing method of an SGT device provided by an exemplary embodiment of the present application. Figure 11 As shown: After manufacturing using the manufacturing method provided in this application, a one-step oxidation process can ensure that all the exposed polysilicon is oxidized to form IPO, reducing the overlapping area between the polysilicon gate and the shielding gate. This process step is simple, eliminating the subsequent HDP filling and wet steps, and reducing stress during the wafer tape-out process; at the same time, the gate width becomes narrower, which can further reduce the cell size and improve the device integration.
[0041] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.
Claims
1. A method for manufacturing an SGT device, characterized in that: include: Providing a substrate having a trench formed therein, wherein a region on the substrate for forming a semiconductor device includes a first region and a second region, the first region being used to form an SGT device, and the second region being used to form an isolation structure; forming a first oxide layer on the surface of the substrate and the inner wall and bottom of the trench; filling a first polysilicon layer in the trench so that the trench and the first oxide layer are covered by the first polysilicon layer; Etching and removing the first polysilicon layer outside the trench; etching and thinning the first oxide layer and the first polysilicon layer; Etching the first polysilicon layer in the first regional trench to a preset etching depth; removing the first oxide layer on the sidewall of the trench in the first region so that the first polysilicon layer is exposed; A second oxide layer is formed in the first regional trench.
2. The manufacturing method according to claim 1, wherein After the first oxide layer is formed, the trench width is 1000 angstroms to 4000 angstroms.
3. The manufacturing method according to claim 1, wherein: The forming of the second oxide layer in the first regional trench comprises: The second oxide layer is formed by a thermal oxidation process.
4. The manufacturing method according to claim 3, wherein: Before forming the second oxide layer by the thermal oxidation process, the method further includes: Ion implantation is performed on the first polysilicon layer.
5. The manufacturing method according to claim 1, wherein The etching and thinning of the first oxide layer and the first polysilicon layer comprises: The first oxide layer and the first polysilicon layer on the surface of the substrate are thinned by a dry etching process.
6. The manufacturing method according to claim 5, wherein: The thickness of the first oxide layer after thinning is 500 angstroms to 2000 angstroms.
7. The manufacturing method according to claim 1, wherein: The removing of the first oxide layer from the sidewall of the trench in the first region comprises: The first oxide layer on the sidewall of the trench in the first region is removed by a wet etching process.
8. The manufacturing method according to claim 1, wherein: After etching the first polysilicon layer in the first regional trench to a preset etching depth, the depth in the first regional trench is 0.3 μm to 2 μm.