Semiconductor device
By adopting a design of conductors connected by inclined surfaces and a thickness difference of the insulating layer in a semiconductor device, the problem of insufficient voltage resistance of existing semiconductor devices is solved, the voltage resistance is improved, and the risk of device damage is reduced.
Patent Information
- Application Number
- CN202411112324.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-04-02
- Filing Date
- 2024-08-14
- Publication Date
- 2025-10-17
AI Technical Summary
Conventional semiconductor devices have insufficient endurance for applications such as power conversion and suffer from poor withstand voltage performance.
A semiconductor device design with a specific structure, including the connection of the conductor's connecting portion and the wiring portion with an inclined surface, combined with a design with a thickness difference of the insulating layer, reduces electric field concentration and improves voltage resistance.
By optimizing the structural design and reducing electric field concentration, the voltage resistance of the semiconductor device is improved and the risk of device damage is reduced.
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Figure CN120813006A_ABST
Abstract
Description
[0001] Cross Reference to Related Applications
[0002] This application claims priority to Japanese Patent Application No. 2024-059657 (Filing Date: April 2, 2024). This application incorporates the entire contents of the base application by reference thereto. TECHNICAL FIELD
[0003] Embodiments of the present application generally relate to semiconductor devices. BACKGROUND
[0004] Semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used in applications such as power conversion. The endurance of the semiconductor device is preferably high. SUMMARY
[0005] Embodiments provide a semiconductor device capable of improving endurance.
[0006] According to one embodiment, a semiconductor device has a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a conductor, and a second electrode. The first semiconductor region is provided over the first electrode. The first semiconductor region includes a first portion and a second portion which is located around the first portion along a surface perpendicular to a first direction from the first electrode toward the first semiconductor region. The second semiconductor region is provided over the first portion. The third semiconductor region is provided over the second semiconductor region. The conductor is provided over the first semiconductor region with an insulating layer interposed therebetween. The conductor includes a first gate electrode portion, a second gate electrode portion, a first wiring portion, a first connection portion, and a second connection portion. The first gate electrode portion is located over the first portion. The first gate electrode portion opposes the second semiconductor region in a second direction perpendicular to the first direction. The first gate electrode portion extends in a third direction perpendicular to the first direction and the second direction. The second semiconductor region is provided between the first gate electrode portion and the second gate electrode portion. The second gate electrode portion extends in the third direction. The first wiring portion is located over the second portion and extends in the third direction. The first connection portion is connected to between a first end portion of the first gate electrode portion in the third direction and an end portion of the first wiring portion in the third direction. The second connection portion is connected to between a second end portion of the second gate electrode portion in the third direction and the end portion of the first wiring portion. A position of the first wiring portion in the second direction is between a position of the first gate electrode portion in the second direction and a position of the second gate electrode portion in the second direction. The first connection portion and the second connection portion have inclined surfaces inclined with respect to the second direction and the third direction. The second electrode is provided over the second semiconductor region and the third semiconductor region. BRIEF DESCRIPTION OF DRAWINGS
[0007] Figure 1 is a plan view of a semiconductor device according to an embodiment.
[0008] Figure 2 is a plan view of a portion II of Figure 1 .
[0009] Figure 3 is a cross-sectional view of III-III of Figure 2 .
[0010] Figure 4 is a cross-sectional view of IV-IV of Figure 2 .
[0011] Figure 5 isFigure 2 V-V cross-sectional view.
[0012] Figure 6 It will Figure 2 An enlarged top view of a portion of the .
[0013] Figure 7 It is a cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment.
[0014] Figure 8 It is a plan view showing the manufacturing process of the semiconductor device according to the embodiment.
[0015] Figure 9 (a) and Figure 9 (b) is a cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment.
[0016] Figure 10 (a) and Figure 10 (b) is a cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment.
[0017] Figure 11 It is a plan view showing a portion of a semiconductor device according to a reference example.
[0018] Figure 12 (a) is a plan view showing a manufacturing process of a semiconductor device according to a reference example. Figure 12 (b) is a plan view showing the manufacturing process of the semiconductor device involved in the embodiment.
[0019] Figure 13 It is a plan view showing a portion of a semiconductor device according to a modification of the embodiment.
[0020] Figure 14 yes Figure 13 Sectional view XIV-XIV of . DETAILED DESCRIPTION
[0021] Below, various embodiments of the present invention are described with reference to the accompanying drawings. The accompanying drawings are schematic or conceptual drawings, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc. are not necessarily the same as in reality. In addition, even when representing the same part, there are cases where the size and ratio of each part are represented differently depending on the drawing. In this application specification and each figure, the same reference numerals are given to the same elements as those already described, and detailed descriptions are omitted as appropriate.
[0022] In the following description and drawings, n + 、n － and p +, the marks with "+" indicate that the impurity concentration is relatively high compared with the marks of any of those not having "+" and "-", and the marks with "-" indicate that the impurity concentration is relatively low compared with the marks of any of those not having "+" and "-". In the case where each region contains both the p-type impurity and the n-type impurity, these marks indicate the relative levels of the net impurity concentration after the mutual compensation of these impurities.
[0023] As for each embodiment described below, each embodiment can be implemented with the p-type and the n-type of each semiconductor region being inverted.
[0024] Figure 1 is a plan view of a semiconductor device according to the embodiment. Figure 2 is a plan view of a portion II of Figure 1 . Figure 3 is a III-III cross-sectional view of Figure 2 . Figure 4 is a IV-IV cross-sectional view of Figure 2 . Figure 5 is a V-V cross-sectional view of Figure 2 .
[0025] The semiconductor device 100 according to the embodiment is a MOSFET. As shown in Figures 1 to 5 , the semiconductor device 100 includes an n － -type (1st conductive type) drift region 1 (1st semiconductor region), a p-type (2nd conductive type) base region 2 (2nd semiconductor region), an n + -type source region 3 (3rd semiconductor region), a p + -type semiconductor region 4, an n + -type drain region 5, a conductor 10, an insulating layer 20, an insulating layer 25, a drain electrode 31 (1st electrode), a source electrode 32 (2nd electrode), a gate pad 33, and a wiring layer 33a. In Figure 2 , the insulating layer 20, the insulating layer 25, and the source electrode 32 are omitted, and the wiring layer 33a is indicated by a broken line.
[0026] In the description of the embodiment, an XYZ orthogonal coordinate system is used. A direction from the drain electrode 31 toward the n － -type drift region 1 is set as a Z direction (1st direction). Two directions perpendicular to the Z direction and orthogonal to each other are set as a Y direction (2nd direction) and an X direction (3rd direction). In addition, for the purpose of description, the direction from the drain electrode 31 toward the n － -type drift region 1 is referred to as "up", and the opposite direction thereof is referred to as "down". These directions are based on the drain electrode 31 and the n －The relative positional relationship of the drift region 1 is independent of the direction of gravity.
[0027] like Figure 1 As shown in FIG. 1 , a source electrode 32 and a gate pad 33 are provided on the upper surface of the semiconductor device 100. The source electrode 32 and the gate pad 33 are spaced apart from each other and are electrically isolated.
[0028] like Figure 2 As shown, the conductor 10 is provided below the source electrode 32 and the gate pad 33. The conductor 10 is electrically isolated from the source electrode 32. The conductor 10 is electrically connected to the gate pad 33 via a wiring layer 33a provided on the periphery of the semiconductor device 100.
[0029] like Figure 3 and Figure 4 As shown in FIG. 1 , a drain electrode 31 is provided on the lower surface of the semiconductor device 100. + The type drain region 5 is provided on the drain electrode 31 and is electrically connected to the drain electrode 31. － Type drift region 1 is set at n + Type drain region 5. － Type drift region 1 via n + The type drain region 5 is electrically connected to the drain electrode 31. － The n-type impurity concentration in the drift region 1 is lower than that in the n-type drift region 1. + The n-type impurity concentration in the drain region 5 is .
[0030] n － Type drift region 1 Figure 1 and Figures 3 to 5 As shown, it includes a first portion 1a and a second portion 1b. In the XY plane, the second portion 1b is located around the first portion 1a. The first portion 1a is located in the cell region. The cell region is the area where current primarily flows during operation of the semiconductor device 100. The second portion 1b is located in the termination region. The termination region is the area where the depletion layer extends toward the periphery of the semiconductor device 100 when the semiconductor device 100 reaches its breakdown voltage.
[0031] like Figure 3 As shown, the p-type base region 2 is provided on the first portion 1a. + Type source region 3 and p + The p-type semiconductor region 4 is provided on the p-type base region 2. + The p-type impurity concentration in the p-type semiconductor region 4 is higher than the p-type impurity concentration in the p-type base region 2 .
[0032] The conductor 10 is provided on the n － Type drift region 1. Figure 2As shown, the conductor 10 includes a plurality of gate electrode portions 11 , a plurality of wiring portions 12 , and a plurality of connection portions 13 .
[0033] like Figure 3 As shown, multiple gate electrode portions 11 are provided on the first portion 1a. Each gate electrode portion 11 extends in the X direction. The gate electrode portion 11 faces the p-type base region 2 in the Y direction via the insulating layer 20. In the Y direction, the multiple p-type base regions 2 and the multiple gate electrode portions 11 are alternately arranged.
[0034] like Figure 4 As shown, a plurality of wiring portions 12 are provided on the second portion 1b. Each wiring portion 12 extends in the X direction. In the Y direction, n － Part of the type drift region 1 and a plurality of wiring portions 12 are alternately arranged.
[0035] like Figure 2 As shown, the connection portion 13 is connected between the gate electrode portion 11 and the wiring portion 12, electrically connecting one end of the gate electrode portion 11 in the X direction to one end of the wiring portion 12 in the X direction. The connection portion 13 has a surface inclined with respect to the X and Y directions.
[0036] The other ends of the wiring portions 12 in the X direction are connected to each other in the Y direction, and are connected to the wiring layer 33 a .
[0037] The Y-direction position of one wiring portion 12 is between the Y-direction position of one gate electrode portion 11 and the Y-direction position of the adjacent gate electrode portion 11. When viewed from the X-direction, the plurality of gate electrode portions 11 and the plurality of wiring portions 12 are alternately arranged in the Y-direction.
[0038] like Figure 3 As shown, in the p-type base region 2, n + Type source region 3 and p + A source electrode 32 is provided on the p-type semiconductor region 4. The source electrode 32 is connected to the p-type base region 2 and the n-type semiconductor region 4. + Type source region 3 and p + The insulating layer 25 is provided between the conductor 10 and the source electrode 32. The conductor 10 and the source electrode 32 are electrically separated by the insulating layer 25.
[0039] Figure 6 It will Figure 2 An enlarged top view of a portion of the .
[0040] As a specific example related to the conductor 10, Figure 6As shown, the plurality of gate electrode portions 11 includes a first gate electrode portion 11a and a second gate electrode portion 11b. The plurality of wiring portions 12 includes a first wiring portion 12a. The first gate electrode portion 11a and the second gate electrode portion 11b are adjacent to each other in the Y direction. A position P2a of the first wiring portion 12a in the Y direction is between a position P1a of the first gate electrode portion 11a in the Y direction and a position P1b of the second gate electrode portion 11b in the Y direction.
[0041] The first gate electrode portion 11a includes a first end portion E1a in the X direction. The second gate electrode portion 11b includes a second end portion E1b in the X direction. The first wiring portion 12a includes an end portion E2a in the X direction. The plurality of connection portions 13 includes a first connection portion 13a and a second connection portion 13b. The first connection portion 13a is connected between the first end portion E1a of the first gate electrode portion 11a and the end portion E2a of the first wiring portion 12a. The second connection portion 13b is connected between the second end portion E1b of the second gate electrode portion 11b and the end portion E2a of the first wiring portion 12a.
[0042] The first gate electrode portion 11a has a side surface S1a parallel to the X direction. The second gate electrode portion 11b has a side surface S1b parallel to the X direction. The first connection portion 13a has a first inclined surface S2a inclined with respect to the X direction and the Y direction. The second connection portion 13b has a second inclined surface S2b inclined with respect to the X direction and the Y direction. The first inclined surface S2a is connected to the side surface S1a. The second inclined surface S2b is connected to the first inclined surface S2a. The side surface S1b is connected to the second inclined surface S2b.
[0043] An intermediate portion 14 is present between the gate electrode portion 11 and the connection portion 13, and between the wiring portion 12 and the connection portion 13, respectively. For example, as shown in FIG. 2, the intermediate portion 14 is present between the gate electrode portion 11 and the connection portion 13, and between the wiring portion 12 and the connection portion 13, respectively. Figure 5 As shown, a lower end of the intermediate portion 14 is located at a position lower than a lower end of the wiring portion 12. A position in the Z direction of a lower end of the gate electrode portion 11 and a position in the Z direction of a lower end of the connection portion 13 are substantially the same as a position in the Z direction of the lower end of the wiring portion 12. Therefore, the lower end of the intermediate portion 14 is located at a position lower than the lower end of the gate electrode portion 11 and the lower end of the connection portion 13.
[0044] As shown, the plurality of gate electrode portions 11 can further include a third gate electrode portion 11c. The plurality of wiring portions 12 can further include a second wiring portion 12b. The plurality of connection portions 13 can further include a third connection portion 13c and a fourth connection portion 13d. The second gate electrode portion 11b and the third gate electrode portion 11c are adjacent to each other in the Y direction. A position P2b of the second wiring portion 12b in the Y direction is between a position P1b of the second gate electrode portion 11b in the Y direction and a position P1c of the third gate electrode portion 11c in the Y direction. Figure 6 As shown, a lower end of the intermediate portion 14 is located at a position lower than a lower end of the wiring portion 12. A position in the Z direction of a lower end of the gate electrode portion 11 and a position in the Z direction of a lower end of the connection portion 13 are substantially the same as a position in the Z direction of the lower end of the wiring portion 12. Therefore, the lower end of the intermediate portion 14 is located at a position lower than the lower end of the gate electrode portion 11 and the lower end of the connection portion 13.
[0045] The third gate electrode portion 11c includes a third end portion E1c in the X direction. The second wiring portion 12b includes an end portion E2b in the X direction. The third connection portion 13c is connected between the second end portion E1b of the second gate electrode portion 11b and the end portion E2b of the second wiring portion 12b. The fourth connection portion 13d is connected between the third end portion E1c of the third gate electrode portion 11c and the end portion E2b of the second wiring portion 12b. The third connection portion 13c and the fourth connection portion 13d have inclined surfaces inclined with respect to the X direction and the Y direction.
[0046] As shown in FIG. 1, the semiconductor device 100 includes a semiconductor substrate 10, a drain electrode 31, a source electrode 32, a gate electrode portion 11, a wiring layer 33a, and a wiring layer 33b. Figure 2 As shown in FIG. 1, the semiconductor device 100 includes a semiconductor substrate 10, a drain electrode 31, a source electrode 32, a gate electrode portion 11, a wiring layer 33a, and a wiring layer 33b. Figure 6 As shown in FIG. 1, the semiconductor device 100 includes a semiconductor substrate 10, a drain electrode 31, a source electrode 32, a gate electrode portion 11, a wiring layer 33a, and a wiring layer 33b. － The p-type base region 2 is divided by the conductive body 10. Thus, compared with a case where the p-type base region 2 is not divided, it is possible to suppress variation in the range of the p-type base region 2. It is possible to suppress variation in the withstand voltage of the semiconductor device 100 caused by variation in the range of the p-type base region 2.
[0047] The operation of the semiconductor device 100 will be described. In a state where a positive voltage is applied to the drain electrode 31 with respect to the source electrode 32, a voltage exceeding a threshold value is applied to the conductive body 10. Thus, a channel (inversion layer) is formed in the p-type base region 2 opposite the gate electrode portion 11. Electrons flow from the source electrode 32 to the n － type drift region 1 through the channel, and the semiconductor device 100 becomes in an on state. Then, if the voltage applied to the conductive body 10 is reduced compared with the threshold value, the channel in the p-type base region 2 disappears, and the semiconductor device 100 becomes in an off state.
[0048] One example of the material of each constituent element will be described. The n － type drift region 1, the p-type base region 2, the n + type source region 3, the p + type semiconductor region 4, and the n + type drain region 5 include silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. In the case where silicon is used as a semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity. The conductive body 10 and the wiring layer 33a include a conductive material such as polysilicon. An impurity can be added to the conductive body 10. The insulating layer 20 and the insulating layer 25 include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The drain electrode 31, the source electrode 32, and the gate pad 33 include a metal such as titanium, gold, or aluminum.
[0049] Figure 7 ,Figure 9 (a) Figure 9 (b) Figure 10 (a) and Figure 10 (b) is a cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment. Figure 8 It is a plan view showing the manufacturing process of the semiconductor device according to the embodiment.
[0050] First, prepare the － Type drift regions 1 and n + The semiconductor substrate Sub of the drain region 5 is formed by reactive ion etching (RIE). Figure 7 As shown, in n － An opening 40 is formed on the upper surface of the drift region 1 .
[0051] like Figure 8 As shown, the opening 40 includes a plurality of first grooves 41, a plurality of second grooves 42, a plurality of third grooves 43, and an intermediate portion 44. The first grooves 41 are located above the first portion 1a. The second grooves 42 are located above the second portion 1b. The third grooves 43 are located between the ends of the first grooves 41 and the ends of the second grooves 42 in the Y direction. The side surfaces of the third grooves 43 are inclined with respect to the X and Y directions. The intermediate portion 44 is located between the first grooves 41 and the third grooves 43, or between the second grooves 42 and the third grooves 43.
[0052] By thermal oxidation, along n － An insulating layer 20 is formed on the upper surface of the drift region 1 and the inner surface of the opening 40. A conductive layer is formed on the insulating layer 20 to bury the opening 40. The upper surface of the conductive layer is retreated by wet etching or chemical dry etching (CDE). Figure 9 As shown in (a) of FIG. 1 , the conductor 10 is formed inside the opening 40 .
[0053] The conductor 10 formed inside the first trench 41 corresponds to the gate electrode portion 11. The conductor 10 formed inside the second trench 42 corresponds to the wiring portion 12. The conductor 10 formed inside the third trench 43 corresponds to the connecting portion 13. The conductor 10 formed inside the intermediate portion 44 corresponds to the intermediate portion 14.
[0054] In the region between the first trenches 41, p-type impurities and n-type impurities are sequentially ion-implanted to form a p-type base region 2 and an n-type base region 3. + Type source region 3. An insulating layer 25 is formed on the conductor 10. Figure 9 As shown in (b), a portion of the insulating layer 20 and a portion of the insulating layer 25 are removed to form an opening 50.
[0055] P-type impurity ions are implanted into the n-type + The region between the type source regions 3 forms a p + Type semiconductor region 4. Figure 10 As shown in (a), the source electrode 32 is formed by sputtering so as to fill the opening 50. + Until the type drain region 5 reaches a predetermined thickness, the n + The lower surface of the drain region 5 is ground. Figure 10 As shown in (b), after grinding, n + The drain electrode 31 is formed by sputtering on the lower surface of the type drain region 5. As described above, the semiconductor device 100 according to the embodiment is manufactured.
[0056] Figure 11 It is a plan view showing a portion of a semiconductor device according to a reference example.
[0057] exist Figure 11 In the semiconductor device 100r shown, the conductor 10r includes a gate electrode portion 11, a wiring portion 12, and a connection portion 13r. The connection portion 13r connects between the gate electrode portion 11 and the wiring portion 12. The orientation of the connection portion 13r differs from the orientation of the connection portion 13 in the semiconductor device 100 according to the embodiment. The side surfaces of the connection portion 13r are perpendicular to the X direction and parallel to the Y direction. Furthermore, the conductor 10r includes an intermediate portion 14r. The intermediate portion 14r is located between the gate electrode portion 11 and the connection portion 13r, or between the wiring portion 12 and the connection portion 13r.
[0058] Advantages of the embodiment will be described.
[0059] In the manufacture of the semiconductor device 100, when the conductor 10 is formed, as shown in FIG. Figure 7 and Figure 8 As shown, opening 40 is formed. Dry etching is used to form opening 40 in the semiconductor layer. Dry etching utilizes a plasma of a gas reactive with the semiconductor material. The semiconductor material and the gas radicals react, removing the semiconductor material and forming opening 40. In this case, the wide portion of opening 40 allows free radicals to enter the interior of the opening more easily than in the narrow portion, facilitating etching.
[0060] Figure 12 (a) is a plan view showing a manufacturing process of a semiconductor device according to a reference example. Figure 12 (b) is a plan view showing the manufacturing process of the semiconductor device involved in the embodiment.
[0061] When manufacturing the semiconductor device 100r, as shown in FIG. Figure 12As shown in (a), an opening 40r for forming the conductor 10r is formed. The opening 40r includes a first trench 41, a second trench 42, a third trench 43r, and an intermediate portion 44r.
[0062] The third trench 43r is located between the Y-direction end of the first trench 41 and the Y-direction end of the second trench 42. The side surfaces of the third trench 43r are perpendicular to the X-direction and parallel to the Y-direction. The intermediate portion 44r is located between the first trench 41 and the third trench 43r, or between the second trench 42 and the third trench 43r. A conductive layer containing polysilicon is embedded in the opening 40r to form the conductor 10r. At this time, a portion of the conductor 10r is located within the intermediate portion 44r. This portion of the conductor 10r corresponds to the intermediate portion 14r.
[0063] like Figure 11 As shown in FIG. 1 , the width of the middle portion 14r is wider than the widths of the gate electrode portion 11, the wiring portion 12, and the connection portion 13r. Figure 12 As shown, the width of the middle portion 44r in which the middle portion 14r is formed is also wider than the widths of the gate electrode portion 11, the wiring portion 12, and the connecting portion 13r. Therefore, etching is easier to perform in the middle portion 44r than in the first trench 41, the second trench 42, and the third trench 43r. The lower end of the middle portion 44r is formed deeper than the lower ends of the first trench 41, the second trench 42, and the third trench 43r. As a result, in the conductor 10r formed inside the opening 40r, the lower end of the middle portion 14r is located below the lower ends of other portions, such as the gate electrode portion 11, the wiring portion 12, and the connecting portion 13r. In other words, the lower end of the middle portion 14r protrudes downward relative to the lower ends of the other portions.
[0064] The further the lower end of the middle portion 14r protrudes downward, the more likely electric field concentration occurs near the lower end of the middle portion 14r. In other words, the electric field intensity near the lower end of the middle portion 14r becomes greater than the electric field intensity near the lower ends of other portions. If dielectric breakdown of the insulating layer 20 occurs near the lower end of the middle portion 14r, there is a risk of damage to the semiconductor device 100r.
[0065] In the semiconductor device 100, the connection portion 13 has an inclined surface inclined with respect to the X direction and the Y direction. In this case, when the conductor 10 is formed, as shown in FIG. Figure 12 As shown in (b) of FIG. 8 , the side surfaces of the third groove 43 are also inclined with respect to the X direction and the Y direction.
[0066] exist Figure 12 In the example shown in (a), the first groove 41 or the second groove 42 intersects the third groove 43r from a direction perpendicular to the third groove 43r. Figure 12In the example shown in (b), the first groove 41 or the second groove 42 intersects the third groove 43 from a direction that is not orthogonal to the third groove 43. Figure 12 In the case of the structure shown in (b), the area of the intermediate portion 44 located between them is Figure 12 The area of the intermediate portion 44r shown in (a) is smaller than that of the intermediate portion 44r. Therefore, during the manufacture of the semiconductor device 100, while etching in the intermediate portion 44 is easier than in the first trench 41, the second trench 42, and the third trench 43, the amount of etching in the intermediate portion 44r can be reduced compared to the amount of etching in the intermediate portion 44r. In the conductor 10, the amount of protrusion of the lower end of the intermediate portion 14 relative to other portions can be reduced, and the electric field concentration near the lower end of the intermediate portion 14 can be suppressed. The electric field intensity near the lower end of the intermediate portion 14 can be reduced, and damage to the semiconductor device 100 can be suppressed.
[0067] like Figure 6 As shown, the first inclined surface S2a of the first connecting portion 13a is not parallel to the second inclined surface S2b of the second connecting portion 13b. Preferably, the angle between the first inclined surface S2a and the second inclined surface S2b is greater than 90 degrees and less than 150 degrees. Within this angle range, the area of the intermediate portion 14 in the XY plane can be effectively reduced. In other words, the electric field intensity near the lower end of the intermediate portion 14 can be effectively reduced.
[0068] like Figure 5 As shown, the insulating layer 20 may include a first insulating region 21 and a second insulating region 22. The first insulating region 21 is located between the end E2a of the first wiring portion 12a and the second portion 1b. The second insulating region 22 is located between the other end E2b of the first wiring portion 12a in the Y direction and the second portion 1b. The thickness of the second insulating region 22 is greater than that of the first insulating region 21.
[0069] The portion of the conductor 10 closer to the outer periphery than the wiring portion 12 is raised upwards compared to the semiconductor region and is connected to the wiring layer 33a. Figure 5 As shown, a corner C is generated. Electric field concentration is more likely to occur at the corner C than at other portions. By making the second insulating region 22 thicker than the first insulating region 21 , electric field concentration near the corner C can be suppressed, further suppressing damage to the semiconductor device 100 .
[0070] like Figure 6As shown, the p-type base region 2 has a first surface S3a and a second surface S3b. The first surface S3a opposes the first gate electrode portion 11a in the Y direction. The second surface S3b opposes the second gate electrode portion 11b in the Y direction. The surface orientation of the first surface S3a and the surface orientation of the second surface S3b are preferably a {100} surface or a {110} surface. This is because, in the case where the semiconductor device 100 is in the on state, the mobility of electrons in the channel can be increased, and the on resistance of the semiconductor device 100 can be reduced. In this case, the surface orientation of the first inclined surface S2a and the surface orientation of the second inclined surface S2b are inclined with respect to the {100} surface or the {110} surface.
[0071] (Modified Example)
[0072] Figure 13 is a plan view showing a portion of the semiconductor device according to the modified example. Figure 14 is Figure 13 is a cross-sectional view taken along line XIV-XIV of Figure 13 In
[0073] In the semiconductor device 110 according to the modified example, as shown in Figure 13 A contact plug 33b is provided on the wiring portion 12. As shown in Figure 14 The wiring portion 12 is electrically connected to the wiring layer 33a via the contact plug 33b. The insulating layer 25 is provided between the wiring portion 12 and the wiring layer 33a.
[0074] In the semiconductor device 100, as shown in Figure 2 The end portions of the wiring portion 12 in the X direction are connected to each other. This is to form the wiring layer 33a and the conductive body 10 together. On the other hand, in the semiconductor device 110, as shown in Figure 13 The end portions E3 of the wiring portion 12 in the X direction are separated from each other in the Y direction. According to this configuration, when forming an opening for the wiring portion 12, the expansion of the width at the end portion of the opening can be suppressed. Thus, when forming the opening, the local progress of etching can be suppressed. As a result, as shown in Figure 14 The amount of protrusion of the lower end of the end portion E3 can be suppressed. The electric field intensity near the lower end of the end portion E3 can be reduced, and the occurrence of damage to the semiconductor device 110 can be suppressed.
[0075] In addition, according to the semiconductor device 110, the electric field intensity near the lower end of the end portion E3 can be reduced, and thus the relatively thick second insulating region 22 shown in Figure 5 is not needed.
[0076] Embodiments of the present application include the following features.
[0077] (Feature 1)
[0078] A semiconductor device, wherein:
[0079] a first electrode;
[0080] a first semiconductor region of a first conductivity type, provided over the first electrode, including a first portion and a second portion, the second portion being located around the first portion along a surface perpendicular to a first direction from the first electrode toward the first semiconductor region;
[0081] a second semiconductor region of a second conductivity type, provided over the first portion;
[0082] a third semiconductor region of the first conductivity type, provided over the second semiconductor region;
[0083] a conductor, provided over the first semiconductor region through an insulating layer; and
[0084] a second electrode, provided over the second semiconductor region and the third semiconductor region,
[0085] the conductor includes:
[0086] a first gate electrode portion, located over the first portion, facing the second semiconductor region in a second direction perpendicular to the first direction, and extending in a third direction perpendicular to the first direction and the second direction;
[0087] a second gate electrode portion, extending in the third direction, with the second semiconductor region provided between the second gate electrode portion and the first gate electrode portion;
[0088] a first wiring portion, located over the second portion, extending in the third direction;
[0089] a first connection portion, connected between a first end portion of the first gate electrode portion in the third direction and an end portion of the first wiring portion in the third direction; and
[0090] a second connection portion, connected between a second end portion of the second gate electrode portion in the third direction and the end portion of the first wiring portion,
[0091] a position of the first wiring portion in the second direction is between a position of the first gate electrode portion in the second direction and a position of the second gate electrode portion in the second direction, and the first connection portion and the second connection portion have inclined surfaces inclined with respect to the second direction and the third direction.
[0092] (Feature 2)
[0093] The semiconductor device according to claim 1, wherein
[0094] The conductive body includes an intermediate portion between the first connection portion, the second connection portion, and the end portion of the first wiring portion,
[0095] A lower end of the intermediate portion is located at a position lower than a lower end of the first wiring portion.
[0096] (Feature 3)
[0097] The semiconductor device according to claim 1 or 2, wherein
[0098] The first connection portion has a first inclined surface inclined with respect to the second direction and the third direction,
[0099] The second connection portion has a second inclined surface inclined with respect to the second direction and the third direction and connected to the first inclined surface,
[0100] An angle between the first inclined surface and the second inclined surface is greater than 90 degrees and less than 150 degrees.
[0101] (Feature 4)
[0102] The semiconductor device according to any one of claims 1 to 3, wherein
[0103] The insulating layer includes:
[0104] a first insulating region between the end portion of the first wiring portion and the second portion; and
[0105] a second insulating region between the other end portion of the first wiring portion in the third direction and the second portion,
[0106] A thickness of the second insulating region is greater than a thickness of the first insulating region.
[0107] (Feature 5)
[0108] The semiconductor device according to any one of claims 1 to 4, wherein
[0109] A length of the first wiring portion in the second direction is longer than a length of the first gate electrode portion in the second direction and longer than a length of the second gate electrode portion in the second direction.
[0110] (Feature 6)
[0111] The semiconductor device according to any one of claims 1 to 5, wherein
[0112] the first semiconductor region has a first surface facing the first gate electrode portion in the second direction,
[0113] a surface orientation of the first surface is a {100} surface or a {110} surface,
[0114] a surface orientation of the inclined surface is inclined with respect to the {100} surface and the {110} surface.
[0115] (Feature 7)
[0116] The semiconductor device according to any one of features 1 to 6, wherein
[0117] the electrically conductive body further includes:
[0118] a third gate electrode portion extending in the third direction, a further second semiconductor region being provided between the third gate electrode portion and the second gate electrode portion;
[0119] a second wiring portion located above the second portion;
[0120] a third connecting portion located between the second end portion and an end portion of the second wiring portion in the third direction; and
[0121] a fourth connecting portion located between a third end portion of the third gate electrode portion in the third direction and the end portion of the second wiring portion,
[0122] a position of the second wiring portion in the second direction is between a position of the second gate electrode portion in the second direction and a position of the third gate electrode portion in the second direction,
[0123] the third connecting portion and the fourth connecting portion have an inclined surface inclined with respect to the second direction and the third direction.
[0124] (Feature 8)
[0125] The semiconductor device according to any one of features 1 to 7, wherein
[0126] a plurality of gate electrode portions including the first gate electrode portion and the second gate electrode portion are arranged in the second direction above the first portion,
[0127] a plurality of wiring portions including the first wiring portion are arranged in the second direction above the second portion.
[0128] (Feature 9)
[0129] The semiconductor device according to feature 8, wherein
[0130] The plurality of gate electrode portions and the plurality of wiring portions are alternately arranged in the second direction when viewed from the third direction.
[0131] The relative levels of impurity concentration between the semiconductor regions in each of the above-described embodiments can be confirmed, for example, using a scanning capacitance microscope (SCM). Furthermore, the carrier concentration in each semiconductor region can be considered to be equal to the activated impurity concentration in each semiconductor region. Therefore, the relative levels of carrier concentration between the semiconductor regions can also be confirmed using the SCM. In addition, the impurity concentration in each semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS).
[0132] The above-described embodiments are illustrative and are not intended to limit the scope of the present application. The novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the present application. The embodiments and their modifications are included within the scope and spirit of the present application, and are included within the scope of the present application and its equivalents as recited in the claims. In addition, the above-described embodiments can be implemented in combination with each other.
Claims
1. A semiconductor device, wherein: have: 1st electrode; a first semiconductor region of a first conductivity type provided on the first electrode and including a first portion and a second portion, the second portion being located around the first portion along a plane perpendicular to a first direction from the first electrode toward the first semiconductor region; a second semiconductor region of a second conductivity type, provided on the first portion; a third semiconductor region of the first conductivity type, disposed on the second semiconductor region; a conductor provided on the first semiconductor region via an insulating layer; and a second electrode provided on the second semiconductor region and the third semiconductor region; The conductor comprises: a first gate electrode portion located on the first portion, facing the second semiconductor region in a second direction perpendicular to the first direction, and extending in a third direction perpendicular to the first and second directions; a second gate electrode portion extending in the third direction, wherein the second semiconductor region is provided between the second gate electrode portion and the first gate electrode portion; a first wiring portion located on the second portion and extending in the third direction; a first connecting portion connected between a first end portion of the first gate electrode portion in the third direction and an end portion of the first wiring portion in the third direction; and a second connecting portion connected between a second end portion of the second gate electrode portion in the third direction and the end portion of the first wiring portion; The position of the first wiring portion in the second direction is between the position of the first gate electrode portion in the second direction and the position of the second gate electrode portion in the second direction, and the first connecting portion and the second connecting portion have inclined surfaces inclined relative to the second direction and the third direction.
2. The semiconductor device according to claim 1, wherein The conductor includes an intermediate portion located between the first connecting portion, the second connecting portion, and the end portion of the first wiring portion. The lower end of the intermediate portion is located below the lower end of the first wiring portion.
3. The semiconductor device according to claim 1, wherein The first connecting portion has a first inclined surface inclined with respect to the second direction and the third direction. The second connecting portion has a second inclined surface that is inclined with respect to the second direction and the third direction and is connected to the first inclined surface. An angle between the first inclined surface and the second inclined surface is greater than 90 degrees and less than 150 degrees.
4. The semiconductor device according to claim 1, wherein The insulating layer comprises: a first insulating region located between the end portion of the first wiring portion and the second portion; and a second insulating region located between the second portion and the other end portion of the first wiring portion in the third direction; The thickness of the second insulating region is greater than the thickness of the first insulating region.
5. The semiconductor device according to claim 1, wherein The length of the first wiring portion in the second direction is longer than the length of the first gate electrode portion in the second direction, and is longer than the length of the second gate electrode portion in the second direction.
6. The semiconductor device according to claim 1, wherein The second semiconductor region has a first surface facing the first gate electrode portion in the second direction. The first surface has a plane orientation of {100} or {110}, The plane orientation of the inclined plane is inclined with respect to the {100} plane and the {110} plane.
7. The semiconductor device according to claim 1, wherein The conductor further comprises: a third gate electrode portion extending in the third direction, wherein another second semiconductor region is provided between the third gate electrode portion and the second gate electrode portion; a second wiring portion located on the second portion; a third connecting portion located between the second end portion and an end portion of the second wiring portion in the third direction; and a fourth connecting portion located between a third end portion of the third gate electrode portion in the third direction and the end portion of the second wiring portion; The position of the second wiring portion in the second direction is between the position of the second gate electrode portion in the second direction and the position of the third gate electrode portion in the second direction. The third connecting portion and the fourth connecting portion have inclined surfaces inclined with respect to the second direction and the third direction.
8. The semiconductor device according to claim 1, wherein On the first portion, a plurality of gate electrode portions including the first gate electrode portion and the second gate electrode portion are arranged in the second direction, On the second portion, a plurality of wiring portions including the first wiring portion are arranged in the second direction.
9. The semiconductor device according to claim 8, wherein When viewed from the third direction, the plurality of gate electrode portions and the plurality of wiring portions are alternately arranged in the second direction.
Citation Information
Patent Citations
Silk performance clothing and product, and method for manufacturing these
JP2024059657A