Semiconductor device

Abstract

Provided is a semiconductor device in which the reliability of a gate insulating layer is improved. According to one embodiment, a semiconductor device includes a first electrode, a second electrode, and a semiconductor layer having a first surface and a second surface between the first electrode and the second electrode. The semiconductor layer includes a plurality of first trenches and a second trench adjacent to the first trench located at an endmost portion. The semiconductor device includes: a first gate electrode located in a first trench and having a first length; a second gate electrode in the second trench and having a second length on the first trench side greater than a third length on the opposite side to the first trench; a first gate insulating layer between the first gate electrode and the semiconductor layer and having a first thickness; a second gate insulating layer having a second thickness between the second gate electrode and the semiconductor layer on the first trench side; and a second gate insulating layer between the second gate electrode and the semiconductor layer on the opposite side from the first trench and having a third thickness thicker than the second thickness.

Description

[0001] Related Application

[0002] This application claims priority from Japanese Patent Application No. 2024-062096 (Filing Date: April 8, 2024). This application includes the entire contents of the base application by reference to the base application. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0004] As an example of a power semiconductor device, a vertical trench gate type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in which a source electrode and a drain electrode are provided in a manner of sandwiching a semiconductor layer from above and below, and a gate electrode is provided in a trench, is known. In the vertical trench gate type MOSFET, an electric field concentration occurs in a trench at a tip end of a plurality of trenches arranged in parallel to each other. Due to the occurrence of the electric field concentration, the reliability of a gate insulating layer provided in the trench at the tip end becomes a problem. SUMMARY

[0005] One embodiment of the present application provides a semiconductor device in which the reliability of a gate insulating layer is improved.

[0006] The semiconductor device of one embodiment includes a first electrode, a second electrode, a semiconductor layer provided between the first electrode and the second electrode, a first semiconductor region of a first conductive type electrically connected to the second electrode, a second semiconductor region of a second conductive type provided between the first semiconductor region and the first electrode, a third semiconductor region of the first conductive type provided between the second semiconductor region and the first electrode, a first gate electrode provided in a first trench, a first field plate electrode provided in the first trench and between the first gate electrode and the second electrode, a second gate electrode provided in a second trench, a second field plate electrode provided in the second trench and between the second gate electrode and the second electrode, a first gate insulating layer provided between the first gate electrode and the semiconductor layer, a first field plate insulating layer provided between the first field plate electrode and the semiconductor layer, a second gate insulating layer provided between the second gate electrode and the semiconductor layer on a first trench side, a third gate insulating layer provided between the second gate electrode and the semiconductor layer on a side opposite to the first trench, a second field plate insulating layer provided between the second field plate electrode and the semiconductor layer, and a second electrode-to-electrode insulating layer provided between the second gate electrode and the second field plate electrode. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1A 、 Figure 1B is a schematic cross-sectional view of a semiconductor device of one embodiment.

[0008] Figure 2 is a schematic cross-sectional view of a part of a semiconductor device of one embodiment.

[0009] Figure 3 is a schematic plan view of a partial semiconductor device of an embodiment.

[0010] Figure 4 is an enlarged schematic sectional view of a partial semiconductor device of an embodiment.

[0011] Figure 5 is an enlarged schematic sectional view of a partial semiconductor device of an embodiment.

[0012] Figure 6 is a diagram for explaining a manufacturing method of a semiconductor device of an embodiment.

[0013] Figure 7 is a diagram for explaining a manufacturing method of a semiconductor device of an embodiment.

[0014] Figure 8 is a diagram for explaining a manufacturing method of a semiconductor device of an embodiment.

[0015] Figure 9 is a diagram for explaining a manufacturing method of a semiconductor device of an embodiment.

[0016] Figure 10 is a diagram for explaining a manufacturing method of a semiconductor device of an embodiment.

[0017] Figure 11 is a diagram for explaining a manufacturing method of a semiconductor device of an embodiment.

[0018] Figure 12 is a diagram for explaining a manufacturing method of a semiconductor device of an embodiment.

[0019] Figure 13 is a schematic sectional view of a partial semiconductor device of a first comparative example.

[0020] Figure 14 is a schematic sectional view of a partial semiconductor device of a second comparative example. DETAILED DESCRIPTION

[0021] Hereinafter, an embodiment of the present application will be described with reference to the accompanying drawings. In addition, in the following description, the same or similar components are marked with the same reference numerals, and a description thereof will be appropriately omitted.

[0022] In the present specification, in the case where there are n + shaped, n － shaped, n + shaped, n － shaped, p + shaped, p－ In this case, it means that the p-type impurity concentration becomes lower in the order of the p-type, the p + p-type, p － p-type, p

[0023] The impurity concentration of the semiconductor device can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). In addition, the relative levels of the impurity concentration of the semiconductor device can be determined, for example, from the levels of the carrier concentration obtained by Scanning Capacitance Microscopy (SCM). In addition, the width, depth, and the like of the impurity region of the semiconductor device can be measured, for example, by SIMS. In addition, the width, depth, and the like of the impurity region of the semiconductor device can be measured, for example, from the SCM image.

[0024] The qualitative analysis and the quantitative analysis of the chemical composition of the components constituting the semiconductor device in the present specification can be performed, for example, by SIMS, Energy Dispersive X-ray Spectroscopy (EDX), or Rutherford Back-Scattering Spectroscopy (RBS). In addition, in the measurement of the thickness of the components constituting the semiconductor device, the distance between the components, and the like, a Scanning Electron Microscope (SEM) or a Transmission Electron Microscope (TEM) can be used, for example.

[0025] The semiconductor device of the embodiment includes: a first electrode; a second electrode; and a semiconductor layer provided between the first electrode and the second electrode, having a first surface opposite to the first electrode, and a second surface opposite to the second electrode. The semiconductor layer includes: a plurality of first trenches provided on the first surface side, extending along a first direction parallel to the first surface, and repeatedly arranged in a second direction parallel to the first surface and perpendicular to the first direction; a second trench provided on the first surface side, extending along the first direction, and adjacent to a first trench located at a most end portion in the second direction among the plurality of first trenches in the second direction; a first semiconductor region of a first conductive form electrically connected to the second electrode; a second semiconductor region of a second conductive form provided between the first semiconductor region and the first surface, and provided between two first trenches; and a third semiconductor region of the first conductive form provided between the second semiconductor region and the first surface, and provided between two first trenches, electrically connected to the first electrode. The semiconductor device includes: a first gate electrode provided in the first trench, having a first length in a third direction perpendicular to the first direction and the second direction; a first field plate electrode provided in the first trench, and provided between the first gate electrode and the second surface; a second gate electrode provided in the second trench, a second length in the third direction of a portion of the second gate electrode on the first trench side being larger than a third length in the third direction of a portion of the second gate electrode on a side opposite to the first trench; a second field plate electrode provided in the second trench, and provided between the second gate electrode and the second surface; a first gate insulating layer provided between the first gate electrode and the semiconductor layer, having a first thickness; a first field plate insulating layer provided between the first field plate electrode and the semiconductor layer; a first electrode-to-electrode insulating layer provided between the first gate electrode and the first field plate electrode; a second gate insulating layer provided between the second gate electrode and the semiconductor layer on the first trench side, having a second thickness; a third gate insulating layer provided between the second gate electrode and the semiconductor layer on a side opposite to the first trench, having a third thickness thicker than the second thickness; a second field plate insulating layer provided between the second field plate electrode and the semiconductor layer; and a second electrode-to-electrode insulating layer provided between the second gate electrode and the second field plate electrode.

[0026] Hereinafter, a case where the first conductive form is n and the second conductive form is p will be described as an example. That is, a case of an n-channel type MOSFET in which an electron is used as a carrier will be described as an example.

[0027] The semiconductor device of the embodiment is a MOSFET 100. The MOSFET 100 is a vertical trench gate type MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

[0028] The trench in this specification refers to a groove-shaped, recess-shaped configuration that the semiconductor layer itself has, and a structure other than the semiconductor layer can be provided inside thereof. The trench is a part of the semiconductor layer.

[0029] Figure 1A 、 Figure 1B is a schematic view of a semiconductor device of an embodiment. Figure 1A is a surface view of the MOSFET 100. Figure 1B is a back surface view of the MOSFET 100.

[0030] As shown in Figure 1A , a source electrode 10, a gate electrode pad 12, and a gate electrode wiring 12x are provided on the surface side of the MOSFET 100. The gate electrode wiring 12x is connected to the gate electrode pad 12.

[0031] As shown in Figure 1B , a drain electrode 20 is provided on the back surface side of the MOSFET 100.

[0032] A plurality of transistors are provided under the source electrode 10. The gate electrode pad 12 and the gate electrode wiring 12x are electrically connected to the gate electrode of the transistors. A gate voltage for controlling the switching operation of the transistors is applied to the gate electrode pad 12.

[0033] Figure 2 is a schematic cross-sectional view of a part of the semiconductor device of the embodiment. Figure 2 is Figure 1A an AA' cross section of

[0034] Figure 3 is a schematic plan view of a part of the semiconductor device of the embodiment. Figure 3 is a plan view of a part corresponding to Figure 2 . Figure 3 is a view of a position corresponding to the first surface F1 of the semiconductor layer 30. Figure 3 is a view after a constituent element above the first surface F1 is removed.

[0035] The MOSFET 100 includes a source electrode 10 (first electrode), a drain electrode 20 (second electrode), a semiconductor layer 30, a first gate electrode 41, a second gate electrode 42, a first gate insulating layer 46, a second gate insulating layer 47, a third gate insulating layer 48, a first field plate electrode 51, a second field plate electrode 52, a first field plate insulating layer 56, a second field plate insulating layer 57, a first inter-electrode insulating layer 61, a second inter-electrode insulating layer 62, and an interlayer insulating layer 65.

[0036] The semiconductor layer 30 includes a cell trench 31 (first trench), a terminal trench 32 (second trench), an n + shaped drain region 33, an n－ The p-type drift region 34 (first semiconductor region), the p-type body region 35 (second semiconductor region) and the n-type + shaped source region 36 (third semiconductor region).

[0037] The semiconductor layer 30 is provided between the source electrode 10 and the drain electrode 20. The semiconductor layer 30 has a first surface ( Figure 2 Middle "F1") and second side ( Figure 2 The second surface F2 is opposite to the first surface F1.

[0038] First surface ( F1 ) faces source electrode 10 , and second surface ( F2 ) faces drain electrode 20 .

[0039] The first and second directions are parallel to the first plane F1. The second direction is perpendicular to the first direction. The third direction is perpendicular to the first plane F1. The third direction is perpendicular to the first and second directions.

[0040] Hereinafter, the term "depth" means the depth based on the first surface F1 , that is, the distance in the third direction based on the first surface F1 .

[0041] The semiconductor layer 30 is, for example, single crystal silicon (Si). When the semiconductor layer 30 is single crystal silicon, the surface of the semiconductor layer 30 is, for example, a surface inclined at 0 degrees or more and 8 degrees or less with respect to the (100) plane.

[0042] n + A drain region 33 in the shape of a MOSFET is provided in the semiconductor layer 30. The drain region 33 is in contact with the second surface F2. The drain region 33 is in contact with the drain electrode 20. The drain region 33 is electrically connected to the drain electrode 20.

[0043] The drain region 33 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The concentration of the n-type impurities is, for example, 1×10 18 cm －3 Above and 1×10 21 cm －3 the following.

[0044] n － A drift region 34 having a shape of φ(R) is provided in the semiconductor layer 30. The drift region 34 is provided between the drain region 33 and the first plane F1. The drift region 34 is provided on the drain region 33. The drift region 34 functions as a current path when the MOSFET 100 is turned on.

[0045] The drift region 34 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The concentration of the n-type impurities is, for example, 1×10 15 cm－3 Above and 1×10 18 cm －3 the following.

[0046] The thickness of the drift region 34 in the third direction is, for example, not less than 5 μm and not more than 15 μm.

[0047] A p-type body region 35 is provided in the semiconductor layer 30. The body region 35 is provided between the drift region 34 and the first face F1.

[0048] The body region 35 is provided between two adjacent cell trenches 31. The body region 35 is provided between the cell trench 31 and the termination trench 32.

[0049] The body region 35 is in contact with, for example, the source electrode 10 . The body region 35 is electrically connected to, for example, the source electrode 10 .

[0050] When the MOSFET 100 is turned on, a channel of an inversion layer is formed in the body region 35 facing the first gate electrode 41 .

[0051] The body region 35 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration is, for example, 1×10 16 cm －3 Above and 1×10 18 cm －3 the following.

[0052] n + A source region 36 having a shape of ? is provided in the semiconductor layer 30. The source region 36 is provided between the body region 35 and the first face F1.

[0053] The source region 36 is in contact with the first surface F1 , in contact with the source electrode 10 , and electrically connected to the source electrode 10 .

[0054] The source region 36 is disposed between two adjacent cell trenches 31 .

[0055] The source region 36 is, for example, Figure 2 As shown, the source region 36 is not provided between the cell trench 31 and the terminal trench 32. Figure 2 As shown, it is not provided between the terminal cell trench 31 and the adjacent cell trench 31. By not providing the source region 36 at the end, it is possible to promote the discharge of holes to the source electrode 10 during the off-state operation of the MOSFET 100, for example. Therefore, it is possible to suppress the destruction of the MOSFET 100 due to avalanche breakdown.

[0056] The source region 36 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The concentration of the n-type impurities is, for example, 1×10 19 cm－3 1 x 10 21 cm －3 The following.

[0057] The cell trench 31 is present in the semiconductor layer 30. The cell trench 31 is located on the first face Fl side of the semiconductor layer 30. The cell trench 31 is a groove formed in the semiconductor layer 30.

[0058] The cell trench 31 extends along the first direction. The plurality of cell trenches 31 are repeatedly arranged in the second direction. The plurality of cell trenches 31 are repeatedly arranged, for example, at a fixed pitch in the second direction.

[0059] The cell trench 31 reaches the drift region 34 through the body region 35. The depth of the cell trench 31 is, for example, 1 μm or more and 5 μm or less. The width of the cell trench 31 in the second direction is, for example, 0.3 μm or more and 1 μm or less.

[0060] The terminal trench 32 is present in the semiconductor layer 30. The terminal trench 32 is located on the first face Fl side of the semiconductor layer 30. The terminal trench 32 is a groove formed in the semiconductor layer 30.

[0061] The terminal trench 32 extends along the first direction. The terminal trench 32 is adjacent to the cell trench 31 located at the most end portion in the second direction among the plurality of cell trenches 31 in the second direction. The terminal trench 32 is provided outside the plurality of cell trenches 31. A trench is not provided, for example, on the side of the terminal trench 32 opposite to the plurality of cell trenches 31.

[0062] The terminal trench 32 reaches the drift region 34 deeper than the body region 35. The body region 35 is not provided, for example, outside the terminal trench 32. The side surface of the outside of the terminal trench 32 is in contact with the drift region 34, for example, over the entire surface.

[0063] The depth of the terminal trench 32 is, for example, 1 μm or more and 5 μm or less. The width of the terminal trench 32 in the second direction is, for example, 0.3 μm or more and 1 μm or less.

[0064] The width of the terminal trench 32 in the second direction is, for example, substantially equal to the width of the cell trench 31 in the second direction. The width of the terminal trench 32 in the second direction is, for example, 0.9 times or more and 1.1 times or less of the width of the cell trench 31 in the second direction.

[0065] The first gate electrode 41 is provided in the cell trench 31. The first gate electrode 41 is electrically connected to the gate electrode wiring 12x and the gate electrode pad 12, for example, using a contact structure not shown.

[0066] The first gate electrode 41 is an electrically conductive body. The first gate electrode 41 is, for example, polysilicon containing n-type impurities or p-type impurities.

[0067] The second gate electrode 42 is provided in the tip trench 32. The second gate electrode 42 is electrically connected to the gate electrode wiring 12x and the gate electrode pad 12, for example, using a contact structure not shown.

[0068] The second gate electrode 42 is an electric conductor. The second gate electrode 42 is, for example, polysilicon containing n-type impurities or p-type impurities.

[0069] The first gate insulating layer 46 is provided between the first gate electrode 41 and the semiconductor layer 30. The first gate insulating layer 46 is provided between the first gate electrode 41 and the body region 35. The first gate insulating layer 46 is provided between the first gate electrode 41 and the drift region 34. The first gate insulating layer 46 is provided between the first gate electrode 41 and the source region 36. The first gate insulating layer 46 is, for example, silicon oxide.

[0070] The second gate insulating layer 47 is provided between the second gate electrode 42 and the semiconductor layer 30 on the side of the cell trench 31 with respect to the second gate electrode 42. The second gate insulating layer 47 is provided between the second gate electrode 42 and the body region 35. The second gate insulating layer 47 is provided between the second gate electrode 42 and the drift region 34. The second gate insulating layer 47 is, for example, silicon oxide.

[0071] The third gate insulating layer 48 is provided between the second gate electrode 42 and the semiconductor layer 30 on the side opposite to the cell trench 31 with respect to the second gate electrode 42. The third gate insulating layer 48 is provided between the second gate electrode 42 and the drift region 34. The second gate electrode 42 is provided between the second gate insulating layer 47 and the third gate insulating layer 48 in the second direction. The third gate insulating layer 48 is, for example, silicon oxide.

[0072] The thickness of the third gate insulating layer 48 in the second direction is thicker than the thickness of the second gate insulating layer 47 in the second direction.

[0073] The first field plate electrode 51 is provided in the cell trench 31. The first field plate electrode 51 is provided between the first gate electrode 41 and the second face F2 in the third direction. The first field plate electrode 51 extends along the first direction.

[0074] The first field plate electrode 51 has a function of changing the electric field distribution within the drift region 34 at the time of the off operation of the MOSFET 100 to increase the withstand voltage of the MOSFET 100.

[0075] The first field plate electrode 51 is electrically connected to the source electrode 10, for example, using a contact structure not shown.

[0076] The first field plate electrode 51 is an electric conductor. The first field plate electrode 51 is, for example, polysilicon containing n-type impurities or p-type impurities.

[0077] The second field plate electrode 52 is provided in the tip trench 32. The second field plate electrode 52 is provided between the second gate electrode 42 and the second face F2 in the third direction. The second field plate electrode 52 extends along the first direction.

[0078] The second field plate electrode 52 has a function of changing an electric field distribution in the drift region 34 at the time of the off operation of the MOSFET 100 to increase the withstand voltage of the MOSFET 100.

[0079] The second field plate electrode 52 is electrically connected to the source electrode 10, for example, using a contact structure not shown.

[0080] The second field plate electrode 52 is an electric conductor. The second field plate electrode 52 is, for example, polysilicon containing n-type impurities or p-type impurities.

[0081] The first field plate insulating layer 56 is provided between the first field plate electrode 51 and the semiconductor layer 30. The first field plate insulating layer 56 is provided between the first field plate electrode 51 and the drift region 34. The first field plate insulating layer 56 is, for example, silicon oxide.

[0082] The thickness of the first field plate insulating layer 56 is, for example, thicker than the thickness of the first gate insulating layer 46. The thickness of the first field plate insulating layer 56 is, for example, 3 times or more and 30 times or less of the thickness of the first gate insulating layer 46.

[0083] The second field plate insulating layer 57 is provided between the second field plate electrode 52 and the semiconductor layer 30. The second field plate insulating layer 57 is provided between the second field plate electrode 52 and the drift region 34. The second field plate insulating layer 57 is, for example, silicon oxide.

[0084] The thickness of the second field plate insulating layer 57 is, for example, thicker than the thickness of the second gate insulating layer 47. The thickness of the second field plate insulating layer 57 is, for example, 3 times or more and 30 times or less of the thickness of the second gate insulating layer 47.

[0085] The first inter-electrode insulating layer 61 is provided between the first gate electrode 41 and the first field plate electrode 51. The first inter-electrode insulating layer 61 is, for example, silicon oxide.

[0086] The thickness of the first inter-electrode insulating layer 61 is, for example, thicker than the thickness of the first gate insulating layer 46 and the thickness of the first field plate insulating layer 56.

[0087] The second inter-electrode insulating layer 62 is provided between the second gate electrode 42 and the second field plate electrode 52. The second inter-electrode insulating layer 62 is, for example, silicon oxide.

[0088] The second inter-electrode insulating layer 62 may be continuous with the third gate insulating layer 48 , for example. The second inter-electrode insulating layer 62 is made of the same material as the third gate insulating layer 48 , for example.

[0089] The thickness of the second inter-electrode insulating layer 62 is, for example, thicker than the thickness of the second gate insulating layer 47 and the thickness of the second field plate insulating layer 57 .

[0090] The interlayer insulating layer 65 is provided between the first gate electrode 41 and the source electrode 10 . The interlayer insulating layer 65 is provided between the second gate electrode 42 and the source electrode 10 . The interlayer insulating layer 65 has a function of electrically isolating the first gate electrode 41 and the second gate electrode 42 from the source electrode 10 .

[0091] The interlayer insulating layer 65 is made of silicon oxide, for example.

[0092] Source electrode 10 is provided on the first surface ( F1 ) side of semiconductor layer 30 . Source electrode 10 is provided on first surface ( F1 ) of semiconductor layer 30 .

[0093] The source electrode 10 is electrically connected to the source region 36 and the body region 35. For example, the source electrode 10 is in contact with the source region 36 and the body region 35.

[0094] The source electrode 10 serves as a region for connecting a bonding wire, for example, when the MOSFET 100 is mounted.

[0095] The source electrode 10 is made of metal and has a stacked structure of, for example, titanium (Ti) and aluminum (Al).

[0096] The drain electrode 20 is provided on the second surface F2 side of the semiconductor layer 30 . The drain electrode 20 is provided on the second surface F2 of the semiconductor layer 30 . The drain electrode 20 is electrically connected to the drain region 33 . The drain electrode 20 is in contact with the drain region 33 .

[0097] The drain electrode 20 is made of metal and has a multilayer structure of a material selected from titanium (Ti), aluminum (Al), nickel (Ni), copper (Cu), silver (Ag), and gold (Au).

[0098] The gate electrode pad 12 is provided on the first surface F1 side of the semiconductor layer 30. The gate electrode pad 12 is provided on the first surface F1 of the semiconductor layer 30. The gate electrode pad 12 and the gate electrode wiring 12x are as shown in FIG. Figure 1A As shown, for example, the source electrode 10 is surrounded.

[0099] The gate electrode pad 12 is electrically connected to the first gate electrode 41 and the second gate electrode 42. The gate electrode pad 12 serves as a region for connecting a bonding wire when the MOSFET 100 is mounted, for example.

[0100] The gate electrode pad 12 is a metal. The gate electrode pad 12 is, for example, a laminated structure of titanium (Ti) and aluminum (Al). The material of the gate electrode pad 12 is, for example, the same as the material of the source electrode 10.

[0101] The gate electrode wiring 12x is electrically connected to the first gate electrode 41 and the second gate electrode 42. The gate electrode wiring 12x is used to electrically connect the gate electrode pad 12 to the first gate electrode 41 and the second gate electrode 42.

[0102] The gate electrode wiring 12x is a metal. The gate electrode wiring 12x is, for example, a laminated structure of titanium (Ti) and aluminum (Al). The material of the gate electrode wiring 12x is, for example, the same as the material of the source electrode 10 and the material of the gate electrode pad 12.

[0103] Figure 4 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the embodiment. Figure 4 is Figure 2 is an enlarged view of the part surrounded by the broken line in Figure 4 The illustration of the source electrode 10 and the interlayer insulating layer 65 is omitted in

[0104] The first gate electrode 41 has a first length L1 in the third direction (L1 in Figure 4 ). The second length L2 in the third direction of the first part of the second gate electrode 42 on the side of the cell trench 31 (L2 in Figure 4 ) is larger than the third length L3 in the third direction of the second part of the second gate electrode 42 on the side opposite to the cell trench 31 (L3 in Figure 4 ).

[0105] The second gate electrode 42 has the first part on the side of the cell trench 31 and the second part on the side opposite to the cell trench 31. The second length L2 in the third direction of the first part is larger than the third length L3 in the third direction of the second part.

[0106] The second length L2 is, for example, 1.2 times or more and 3 times or less of the third length L3.

[0107] The second length L2 is, for example, substantially the same as the first length L1. The second length L2 is, for example, 0.9 times or more and 1.1 times or less of the first length L1.

[0108] The surface on the side of the second face F2 of the second gate electrode 42 has a step St (an area surrounded by the broken line in Figure 4 ). The lower surface of the second gate electrode 42 has the step St.

[0109] The first gate insulating layer 46 has a first thickness T1 in the second direction (T1 in Figure 4The second gate insulating layer 47 has a second thickness ( Figure 4 The third gate insulating layer 48 has a third thickness in the second direction ( Figure 4 t3 in the diagram).

[0110] The first thickness t1 of the first gate insulating layer 46 is, for example, the thickness of the thinnest portion of the first gate insulating layer 46. The second thickness t2 of the second gate insulating layer 47 is, for example, the thickness of the thinnest portion of the second gate insulating layer 47. The third thickness t3 of the third gate insulating layer 48 is, for example, the thickness of the thinnest portion of the third gate insulating layer 48.

[0111] The third thickness t3 is thicker than the second thickness t2. For example, the third thickness t3 is 1.5 times or more and 5 times or less of the second thickness t2.

[0112] The second thickness t2 is, for example, substantially the same as the first thickness t1. The second thickness t2 is, for example, 0.9 times or more and 1.1 times or less of the first thickness t1.

[0113] The first thickness t1 is, for example, greater than or equal to 30 nm and less than or equal to 100 nm. The second thickness t2 is, for example, greater than or equal to 30 nm and less than or equal to 100 nm. The third thickness t3 is, for example, greater than or equal to 45 nm and less than or equal to 500 nm.

[0114] The first position ( Figure 4 At P1 in FIG, the distance in the third direction between the second gate electrode 42 and the second field plate electrode 52 is the first distance ( Figure 4 d1 in the second position in the second inter-electrode insulating layer 62 ( Figure 4 At P2 in FIG, the distance in the third direction between the second gate electrode 42 and the second field plate electrode 52 is the second distance ( Figure 4 d2 in the example).

[0115] The first position P1 is closer to the cell trench 31 than the second position P2 in the second direction. In other words, the second position P2 is farther from the cell trench 31 than the first position P1 in the second direction.

[0116] The first distance d1 is smaller than the second distance d2. In other words, the second distance d2 is larger than the first distance d1. The second distance d2 is, for example, 1.2 times or more and 2 times or less of the first distance d1.

[0117] Figure 5 This is an enlarged schematic cross-sectional view of a portion of a semiconductor device according to an embodiment. Figure 5 yes Figure 2 An enlarged view of the portion enclosed by the dotted line in FIG. Figure 5 The source electrode 10 and the interlayer insulating layer 65 are omitted in the figure.Figure 5 Is to express Figure 4 Same part of the diagram.

[0118] Figure 5 In the cross section parallel to the second direction and the third direction, when the second direction is defined as the left-right direction, the shape of the second gate electrode 42 is left-right asymmetric.

[0119] In a cross section parallel to the second direction and the third direction, a line segment passing through a position where the second gate electrode 42 has the maximum width in the second direction and drawn along the second direction in the second gate electrode 42 is defined as a first line segment ( Figure 5 LS1 in). Using the midpoint of the first line segment LS1 ( Figure 5 M in the third direction) and the second line segment extending along the third direction ( Figure 5 The second gate electrode 42 is virtually divided into left and right sides by the second line segment LS2. The second gate electrode 42 is divided into a first region 42a located on the side of the cell trench 31 across the second line segment LS2 and a second region 42b on the opposite side of the cell trench 31. In this case, the first area ( Figure 5 S1 in) is larger than the second area ( Figure 5 S2) in is large.

[0120] The first area S1 of the first region 42 a is, for example, 1.2 times or more and 5 times or less of the second area of ​​the second region 42 b .

[0121] Next, an example of a method for manufacturing a semiconductor device according to an embodiment will be described.

[0122] Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 ,and Figure 12 It is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. Figure 6 - Figure 12 Is related to the implementation method Figure 2 Corresponding cross-sectional view.

[0123] First, use known process technology to － The semiconductor layer 30 is formed into a unit trench 31 and an end trench 32 ( Figure 6 The cell trench 31 and the terminal trench 32 are formed simultaneously. A portion of the semiconductor layer 30 eventually becomes the drift region 34.

[0124] Next, a first field plate insulating layer 56 and a first field plate electrode 51 are formed in the cell trench 31 using a publicly known process technique. In addition, a second field plate insulating layer 57 and a second field plate electrode 52 are formed in the end trench 32 using a publicly known process technique. Figure 7

[0125] Next, a first silicon oxide film 70 is formed so as to bury a part of the cell trench 31 and the end trench 32. The first silicon oxide film 70 is formed, for example, by a chemical vapor deposition method (CVD method). A part of the first silicon oxide film 70 eventually becomes the first inter-electrode insulating layer 61, the second inter-electrode insulating layer 62, and the third gate insulating layer 48.

[0126] Next, a resist film 71 for patterning the first silicon oxide film 70 is formed on the first silicon oxide film 70. Figure 8 The resist film 71 covers a part of the first silicon oxide film 70 buried in the end trench 32, and exposes another part. In other words, an end portion of the resist film 71 is disposed in the end trench 32.

[0127] Next, a part of the first silicon oxide film 70 is removed with the resist film 71 as a mask. Figure 9 A part of the first silicon oxide film 70 is removed, for example, using a wet etching method.

[0128] By removing a part of the first silicon oxide film 70, the semiconductor layer 30 of both side surfaces of the upper portion of the cell trench 31 is exposed. In addition, the semiconductor layer 30 of the side surface of the upper portion of the cell trench 31 side of the end trench 32 is exposed. The side surface of the upper portion of the end trench 32 on the opposite side to the cell trench 31 is still covered with the first silicon oxide film 70. The first silicon oxide film 70 covering the side surface of the upper portion of the end trench 32 on the opposite side to the cell trench 31 eventually becomes the third gate insulating layer 48.

[0129] Next, the resist film 71 is removed. Next, a first gate electrode 41, a second gate electrode 42, a first gate insulating layer 46, and a second gate insulating layer 47 are formed using a publicly known process technique. Figure 10

[0130] Next, a p-shaped body region 35 and an n + shaped source region 36 are formed using a publicly known process technique. Figure 11

[0131] Next, a second silicon oxide film 72 is formed on the semiconductor layer 30. The second silicon oxide film 72 is formed, for example, by a CVD method. A part of the second silicon oxide film 72 eventually becomes the interlayer insulating layer 65.

[0132] ​​​Next, a second silicon oxide film 72 is formed to reach an opening portion 74 of a surface of the semiconductor layer 30. Figure 12 The opening portion 74 is formed, for example, using photolithography and a reactive ion etching method (RIE method). Further, for example, the configuration can also be such that the opening portion 74 penetrates the source region 36 by etching the semiconductor layer 30 at the bottom of the opening portion 74.

[0133] After that, the opening portion 74 is filled with a metal film using a publicly known process technique to form the source electrode 10. In addition, the drain region 33 and the drain electrode 20 are formed on the back surface side of the semiconductor layer 30 using a publicly known process technique.

[0134] By the above-described manufacturing method of the semiconductor device, the MOSFET 100 of the embodiment is manufactured. Figure 2

[0135] Next, the action and effects of the semiconductor device of the embodiment are described.

[0136] Figure 13 is a schematic cross-sectional view of a portion of a semiconductor device of a first comparative example. Figure 13 is a view corresponding to the semiconductor device of the embodiment. Figure 2

[0137] The MOSFET 901 of the first comparative example differs from the MOSFET 100 of the embodiment in that the length of the MOSFET 901 in the third direction of the second gate electrode 42 is fixed. In addition, the MOSFET 901 of the first comparative example differs from the MOSFET 100 of the embodiment in that the thickness of the third gate insulating layer 48 is the same as the thickness of the second gate insulating layer 47.

[0138] In the MOSFET 901, when the MOSFET 901 is in an off state, an electric field is concentrated outside the terminal trench 32. Specifically, the intensity of the electric field applied to the third gate insulating layer 48 between the drift region 34 outside the terminal trench 32 and the second gate electrode 42 becomes high. Therefore, the insulating breakdown of the third gate insulating layer 48 is easily generated, and the reliability of the gate insulating layer can be reduced.

[0139] Figure 14 is a schematic cross-sectional view of a portion of a semiconductor device of a second comparative example. Figure 14 is a view corresponding to the semiconductor device of the embodiment. Figure 2

[0140] ​​​The MOSFET 902 of the second comparative example differs from the MOSFET 100 of the embodiment in that the length of the second gate electrode 42 in the third direction is fixed. In addition, the MOSFET 902 of the second comparative example differs from the MOSFET 901 of the first comparative example in that the thickness of the third gate insulating layer 48 is thicker than the thickness of the second gate insulating layer 47.

[0141] In the MOSFET 902, since the thickness of the third gate insulating layer 48 is thicker than the thickness of the second gate insulating layer 47, the electric field strength applied to the third gate insulating layer 48 when the MOSFET 902 is in the off state becomes weak. Therefore, the reliability of the gate insulating layer is improved compared to the MOSFET 901 of the first comparative example.

[0142] The MOSFET 100 of the embodiment differs from the MOSFET 902 of the second comparative example in that Figure 4 the second length (L2 in FIG. 10) of the first portion of the second gate electrode 42 on the side of the unit trench 31 in the third direction is larger than the third length (L3 in FIG. 10) of the second portion of the second gate electrode 42 on the side opposite to the unit trench 31 in the third direction. Figure 4 Figure 4 In other words, the third length L3 is smaller than the second length L2.

[0143] Therefore, the area of the second gate electrode 42 facing the drift region 34 on the outside of the end trench 32 through the thin portion of the third gate insulating layer 48 becomes small. Thus, the capacitance between the second gate electrode 42 of the MOSFET 100 and the drift region 34 on the outside of the end trench 32 becomes small compared to the case of the MOSFET 902. Thus, the gate-drain capacitance of the MOSFET 100 becomes small.

[0144] In addition, in the MOSFET 100, the area of the second gate electrode 42 facing the drift region 34 on the outside of the end trench 32 through the thin portion of the third gate insulating layer 48 becomes small. Thus, the reliability of the gate insulating layer is improved compared to the MOSFET 902 of the first comparative example.

[0145] In addition, the MOSFET 100 of the embodiment differs from the MOSFET 902 of the second comparative example in that Figure 4 the second distance (d2 in FIG. 10) between the second gate electrode 42 and the second field plate electrode 52 at the second position (P2 in FIG. 10) away from the unit trench 31 is larger than the first distance (d1 in FIG. 10) between the second gate electrode 42 and the second field plate electrode 52 at the first position (P1 in FIG. 10) close to the unit trench 31. Figure 4 Figure 4 Figure 4 Figure 4 ​​​​d1) is large. Thus, the capacitance between the second gate electrode 42 and the second field plate electrode 52 of the MOSFET 100 is smaller than that of the MOSFET 902. The second field plate electrode 52 is electrically connected to the source electrode 10. Thus, the gate-source capacitance of the MOSFET 100 is small.

[0146] The MOSFET 100 of the embodiment has a smaller gate capacitance than the MOSFET 902 of the second comparative example. Thus, for example, the operating speed of the MOSFET 100 is increased, and the power consumption is reduced.

[0147] From the viewpoint of improving the reliability of the gate insulating layer, the third thickness t3 of the third gate insulating layer 48 is preferably 1.5 times or more, more preferably 2 times or more, and further preferably 3 times or more, the second thickness t2 of the second gate insulating layer 47.

[0148] From the viewpoint of reducing the gate capacitance and improving the reliability of the gate insulating layer, the second length L2 of the second gate electrode 42 is preferably, for example, 1.2 times or more, and more preferably 1.5 times or more, the third length L3 of the second gate electrode 42.

[0149] From the viewpoint of reducing the gate capacitance, the second distance d2 between the second gate electrode 42 and the second field plate electrode 52 is preferably 1.2 times or more, and more preferably 1.5 times or more, the first distance d1.

[0150] From the viewpoint of reducing the gate capacitance and improving the reliability of the gate insulating layer, Figure 5 The first area S1 of the first region 42a is preferably 1.2 times or more, and more preferably 1.5 times or more, the second area of the second region 42b.

[0151] In the embodiment, the case where the semiconductor layer is single-crystal silicon is described as an example, but the semiconductor layer is not limited to single-crystal silicon. For example, other single-crystal semiconductors such as single-crystal silicon carbide can also be used.

[0152] In the embodiment, the case where the first conduction type is n-type and the second conduction type is p-type is described as an example, but the structure can also be such that the first conduction type is p-type and the second conduction type is n-type.

[0153] The present application has been described with several embodiments, but these embodiments are presented by way of example only and are not intended to limit the scope of the application. These new embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the scope of the application. For example, a component of one embodiment can be substituted for or changed to a component of another embodiment. These embodiments and variations thereof are included in the scope, spirit of the application, and are included in the scope of the application and equivalents thereof recited in the claims.

Claims

1. A semiconductor device, characterized in that: have: a first electrode; a second electrode; a semiconductor layer disposed between the first electrode and the second electrode, having a first surface opposite to the first electrode and a second surface opposite to the second electrode, the semiconductor layer comprising: a plurality of first grooves provided on the first surface side, extending along a first direction parallel to the first surface, and repeatedly arranged in a second direction parallel to the first surface and perpendicular to the first direction; a second groove provided on the first surface side, extending along the first direction, and adjacent to the first groove located at the endmost portion of the plurality of first grooves in the second direction in the second direction; a first semiconductor region of a first conductive type electrically connected to the second electrode; a second semiconductor region of a second conductive type, disposed between the first semiconductor region and the first surface and between two of the first trenches; and a third semiconductor region of the first conductive type, disposed between the second semiconductor region and the first surface, and between two of the first trenches, and electrically connected to the first electrode; a first gate electrode disposed in the first trench and having a first length in a third direction perpendicular to the first direction and the second direction; a first field plate electrode disposed in the first trench and between the first gate electrode and the second surface; a second gate electrode disposed in the second trench, wherein a second length of a portion of the second gate electrode on the first trench side in the third direction is greater than a third length of a portion of the second gate electrode on a side opposite to the first trench in the third direction; a second field plate electrode disposed in the second trench and between the second gate electrode and the second surface; a first gate insulating layer, disposed between the first gate electrode and the semiconductor layer, and having a first thickness; a first field plate insulating layer, disposed between the first field plate electrode and the semiconductor layer; a first inter-electrode insulating layer disposed between the first gate electrode and the first field plate electrode; a second gate insulating layer, disposed between the second gate electrode and the semiconductor layer on the first trench side, and having a second thickness; a third gate insulating layer provided between the second gate electrode and the semiconductor layer on the opposite side of the first trench, and having a third thickness thicker than the second thickness; a second field plate insulating layer disposed between the second field plate electrode and the semiconductor layer; and A second inter-electrode insulating layer is provided between the second gate electrode and the second field plate electrode.

2. The semiconductor device according to claim 1, wherein The second length is greater than or equal to 1.2 times the third length.

3. The semiconductor device according to claim 1, wherein A surface of the second gate electrode on the second surface side has a height difference.

4. The semiconductor device according to claim 1, wherein The second length is greater than or equal to 0.9 times and less than or equal to 1.1 times the first length.

5. The semiconductor device according to claim 1, wherein The third thickness is greater than or equal to 1.5 times the second thickness.

6. The semiconductor device according to claim 1, wherein The second thickness is greater than or equal to 0.9 times and less than or equal to 1.1 times the first thickness.

7. The semiconductor device according to claim 1, wherein A first distance in the third direction between the second gate electrode and the second field plate electrode at a first position is smaller than a second distance in the third direction between the second gate electrode and the second field plate electrode at a second position, wherein the second position is a position farther away from the first trench in the second direction than the first position.

8. The semiconductor device according to claim 1, wherein The second distance is greater than or equal to 1.2 times the first distance.

9. The semiconductor device according to claim 1, wherein A width of the second trench in the second direction is not less than 0.9 times and not more than 1.1 times a width of the first trench in the second direction.

10. The semiconductor device according to claim 1, wherein In a cross section parallel to the second direction and the third direction, when the second direction is defined as a left-right direction, the shape of the second gate electrode is left-right asymmetric.

11. The semiconductor device according to claim 1, wherein In a cross-section parallel to the second direction and the third direction, when the second gate electrode is hypothetically divided into a first region on the first groove side and a second region on the opposite side of the first groove using a second line segment passing through the midpoint of the first line segment and extending along the third direction, the first area of ​​the first region is larger than the second area of ​​the second region, wherein the first line segment is a line segment that passes through the position where the second gate electrode has the maximum width in the second direction and is led out along the second direction in the second gate electrode.

12. The semiconductor device according to claim 11, wherein The first area is greater than or equal to 1.2 times the second area.

Images