Stacked shielded gate field effect transistor and method of making the same

Abstract

The application discloses a stacked shield gate field effect transistor and a preparation method thereof. In a trench of an SGT MOSFET, a control gate electrode and two shield gate electrodes are included, the two shield gate electrodes are located on the upper and lower sides of the control gate electrode, and the two shield gate electrodes share the control gate electrode. In the same cell width and drift resistance specification as the traditional SGT, the trench depth is increased, one shield gate electrode is arranged at each of the upper and lower ends of the control gate electrode, and the two shield gate electrodes share the same control gate electrode. The electric field distribution is expanded from the original single rectangle to double rectangle distribution, the electric field can be increased by nearly one time without changing the on-resistance, excellent performance advantages are obtained, more storage units can be accommodated in the same plane area, the storage density is significantly improved, the area utilization is improved, further, due to the shortened signal transmission path, the delay and energy loss of the switching application are reduced, and higher performance can be achieved at a lower working voltage.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to shielded gate trench MOSFET, specifically a stacked shielded gate field-effect transistor and its fabrication method. Background Technology

[0002] With the rapid development of semiconductor technology, field-effect transistors (FETs), as core components of electronic systems, have been widely used in power electronics, communications, computers, and many other fields, and are an indispensable part of modern electronic systems. As application demands continue to increase, lateral devices waste a large amount of chip area, so power devices are gradually shifting to vertical device structures. Against this backdrop, shielded gate trench MOSFETs (SGT MOSFETs) have emerged.

[0003] Shielded gate field-effect transistors (SFETs) optimize gate design by introducing a shielded gate structure inside the device, reducing switching losses and improving efficiency, making them widely used in low- and medium-voltage power conversion circuits.

[0004] The cross-section of a shielded gate trench MOSFET is as follows Figure 1 As shown, the shielding gate (ShieldPoly) introduced in the trench gate MOSFET acts as a field plate to provide lateral auxiliary depletion for the device, thereby achieving two-dimensional charge coupling in the drift region. This changes the electric field distribution of the device from a triangular shape in the trench gate MOSFET to an approximately rectangular shape, resulting in a higher breakdown voltage (BVDSS). This significantly increases the doping concentration in the drift region, thereby improving the breakdown voltage while reducing the drift resistance. Consequently, the chip area of ​​the SGT MOSFET device is significantly reduced for the same resistance specifications.

[0005] For a long time, vertical MOSFET devices, including VDMOS, Trench MOSFET, and SGT MOSFET, have achieved lower on-resistance by proportionally shrinking the cell size. This is achieved by reducing the cell width to increase cell (channel) density, thereby reducing channel resistance and improving operating current uniformity. However, performance improvements can only be achieved within a one-dimensional limit, where size reduction has reached a bottleneck. The trade-off between on-resistance and reverse blocking voltage has always been a crucial challenge for MOSFETs. Summary of the Invention

[0006] The problem this invention aims to solve is that in vertical MOSFET devices, the cell size of SGT MOSFET devices in a one-dimensional plane is already difficult to shrink further, requiring new designs to further improve the performance of field-effect transistors.

[0007] The technical solution of this invention is as follows: a stacked shielded gate field-effect transistor, increasing the trench depth of the SGT MOSFET, with one control gate electrode and two shielded gate electrodes vertically stacked in the trench, the two shielded gate electrodes located above and below the control gate electrode respectively and sharing the control gate electrode, the entire trench located in an N-type epitaxial layer, with silicon substrates on both the top and bottom of the N-type epitaxial layer, enabling the drain to be connected at both ends of the trench, the source region sandwiched in the N-type epitaxial layer, corresponding to both sides of the control gate electrode, the source region including two P-type body regions and one N+ source region, the N+ source region located between the two P-type body regions, and the source metal embedded in the source region to form a conformal contact.

[0008] Furthermore, the increased trench depth is more than 1.5 times the trench depth of an SGT MOSFET with a single shielded gate electrode and a control gate electrode having the same cell width and drift resistance.

[0009] Furthermore, the two shielding gate electrodes are of the same size and are symmetrically distributed on the upper and lower sides of the control gate electrode.

[0010] Furthermore, the two P-type body regions of the source region are symmetrically located above and below the N+ source region, and the control gate electrode is located in the middle of the P-type body region and the N+ source region in the trench depth direction.

[0011] Furthermore, the control gate electrode is led out from one end of the trench in the longitudinal direction to the surface of the silicon substrate and forms a gate region through a contact hole; the shield gate electrode is led out from at least the same end of the trench in the longitudinal direction to the surface of the silicon substrate and contacts the source metal through a contact hole; the source metal is led out from the surface of the silicon substrate.

[0012] As one example, the width of the shielding gate electrode gradually increases or decreases from the top and bottom towards the middle, controlling the direction of the gate electrode.

[0013] As one embodiment, the control gate electrode extends upward along the trench sidewall and concavely wraps around the shielding gate electrode located above the control gate electrode.

[0014] As an example, a P+ zone is provided at the bottom of the trench.

[0015] The present invention also provides a method for fabricating the above-mentioned stacked shielded gate field-effect transistor, comprising the following steps:

[0016] 1) Prepare a basic wafer. On a silicon substrate, the first to fifth epitaxial layers are grown sequentially using epitaxial technology. The first and fifth epitaxial layers are N-type epitaxial layers, the second and fourth epitaxial layers are P-type body regions, and the third epitaxial layer is an N+ source region. The basic wafer is thus obtained.

[0017] 2) Trenches are etched on the basic wafer, the trenches penetrating the first to fifth epitaxial layers;

[0018] 3) An oxide layer is grown in the trench;

[0019] 4) Etching of the oxide layer to form the first trench, wherein the thickness of the oxide layer between the bottom of the first trench and the bottom of the trench is h;

[0020] 5) Fill the first trench with polysilicon and etch the polysilicon to a height not exceeding the second epitaxial layer, i.e. the lower P-type body region, to obtain the first shielding gate electrode.

[0021] 6) Etch the oxide layer on the sidewall portion above the upper surface of the first shielding gate electrode to obtain a second trench, the width of which is greater than that of the first trench.

[0022] 7) Deposit an oxide layer in the second trench as a gate oxide layer, then fill the gate polysilicon and etch the gate polysilicon to a predetermined height to obtain a control gate electrode. The position of the control gate electrode corresponds to the second to fourth epitaxial layers in the trench depth direction.

[0023] 8) After the control gate electrode is formed, an oxide layer is re-deposited in the second trench until the trench is filled. Then, the oxide layer is etched according to the width of the first trench to form the third trench. An oxide layer is left between the bottom of the third trench and the control gate electrode as the gate oxide layer.

[0024] 9) Fill the third trench with polysilicon and etch the polysilicon to a thickness of h to obtain the second shielding gate electrode, so that the distance between the two shielding gate electrodes and the top and bottom surfaces of the trench is the same; when etching the polysilicon, the etching thickness is consistent with the oxide layer thickness on the left and right sides of the first and second shielding gates.

[0025] 10) An oxide layer is deposited to fill the trench, and an N-type epitaxial layer is grown on another silicon substrate. Then, the N-type epitaxial layer and the silicon substrate are bonded to the fifth epitaxial layer by silicon wafer bonding, forming a structure in which the entire trench is located in the N-type epitaxial layer and both the top and bottom surfaces are silicon substrates.

[0026] 11) Corresponding to the source region, etch trenches, deposit an isolation oxide layer, and then deposit metal to obtain the source metal;

[0027] 12) The stacked shielded gate field-effect transistor is obtained by the subsequent electrode process of the shielded gate field-effect transistor.

[0028] The Poisson equation states the relationship between the on-resistance and reverse breakdown voltage of a MOSFET: a higher resistivity results in a higher reverse breakdown voltage. However, applications often desire both high breakdown voltage and low resistivity. This invention improves upon this by increasing the trench depth without increasing the resistivity, designing a stacked shielded gate structure where two shielded gate electrodes share a single control gate electrode. This enhances the electric field distribution range. For example, compared to a conventional SGT with a single control gate and shielded gate, doubling the trench depth and adding a shielded gate results in a stacked SGT that nearly doubles the breakdown voltage.

[0029] While increasing the length of the shielding gate electrode (i.e., its height in the trench) is beneficial for optimizing the electric field distribution, excessively increasing the shielding gate electrode length can lead to increased parasitic capacitance and impaired switching performance. Furthermore, the improvement in electric field from increasing the shielding gate length is limited; after reaching an optimal value, further increases do not increase the breakdown voltage (BV) and may even decrease it. Additionally, the shielding gate length faces manufacturing limitations; excessively long shielding gate electrodes may reduce yield. Therefore, the traditional design for optimizing the shielding gate length of a single-shielded SGT has reached a bottleneck due to device performance and manufacturing process constraints. This invention does not consider changing the original SGT's shielding gate length to optimize the electric field distribution. Instead, it proposes a stacked shielding gate design, which can expand the electric field distribution of the SGT device and improve device performance while avoiding the problems caused by excessively increasing the shielding gate electrode length.

[0030] With the same cell width and drift resistance as traditional SGTs, the shielded gate field-effect transistor of this invention offers the following technical advantages:

[0031] 1) A shielded gate electrode is set at the upper and lower ends of the control gate electrode. Compared with the traditional SGT, the electric field distribution in the vertical region can be expanded from the original single rectangle to a double rectangle distribution. The field-effect transistor of the present invention improves the electric field distribution range and can increase the electric field by nearly 100% without changing the on-resistance, which has excellent performance advantages.

[0032] 2) Two shielded gate electrodes share the same control gate electrode, resulting in a channel density that is twice that of a traditional SGT, such as... Figure 3 and Figure 4 As shown, this can significantly reduce on-resistance, thereby reducing energy loss during conduction and improving device efficiency.

[0033] 3) By shortening the signal transmission path in the vertical direction, the vertical stacked structure SGT of this invention has a faster current transmission speed, reduces the delay and energy loss in switching applications, and can achieve higher performance at lower operating voltages.

[0034] 4) Due to the improved electric field distribution and channel density, the field-effect transistor of the present invention can accommodate more memory cells on the same planar area, thereby significantly improving the memory density and area utilization. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the cross-section of an existing shielded gate trench MOSFET and the corresponding electric field distribution.

[0036] Figure 2 This is a schematic diagram of the cross-section of the stacked shielded gate field-effect transistor of the present invention and the corresponding electric field distribution.

[0037] Figure 3 This is a schematic diagram of the channel density of a traditional SGT.

[0038] Figure 4 This is a schematic diagram of the SGT channel density of the present invention.

[0039] Figure 5 This is a schematic diagram comparing the electric field distribution of the SGT of the present invention with that of a traditional single-shielded gate SGT.

[0040] Figure 6 This is a three-dimensional structural diagram of the SGT of the present invention.

[0041] Figure 7 This is a schematic diagram of the process for preparing the control gate electrode and the shielding gate electrode of the stacked shielded gate field-effect transistor of the present invention.

[0042] Figure 8 This is a schematic diagram illustrating the preparation of the source metal during the fabrication process of the stacked shielded gate field-effect transistor of the present invention.

[0043] Figure 9 The electric field distribution results are from the simulation experiment of the stacked shielded gate field-effect transistor of this invention.

[0044] Figure 10 This is a comparison of the breakdown voltage of the stacked shielded gate field-effect transistor of this invention and a conventional SGT.

[0045] Figure 11 This is an embodiment of a structural variation of the stacked shielded gate field-effect transistor of the present invention. Detailed Implementation

[0046] The development of field-effect transistor (SGT) devices has progressed from one-dimensional to two-dimensional to three-dimensional (top-down view of the wafer). Currently, traditional SGTs still mostly use strip structures (one-dimensional). This invention proposes a reasonable stacking method and a feasible implementation scheme.

[0047] First, let's explain the several dimensions of the SGT device:

[0048] 1. Vertical direction

[0049] Corresponding to trench depth, which extends vertically downwards along the surface of the semiconductor substrate, the depth of the trench directly affects the device's withstand voltage and on-resistance.

[0050] 2. Lateral direction

[0051] The corresponding trench width affects the size of the carrier channel and the device integration density.

[0052] 3. Vertical direction

[0053] The corresponding trench length (Length) is the direction of current flow and corresponds to the effective conduction area of ​​the device.

[0054] like Figure 2 As shown, the stacked shielded gate field-effect transistor of the present invention increases the trench depth compared with the traditional SGT. A control gate electrode 101 and two shielded gate electrodes 102 are vertically stacked in the trench. The two shielded gate electrodes 102 are located above and below the control gate electrode 101 respectively and share the control gate electrode 101. The entire trench is located in an N-type epitaxial layer 105. The N-type epitaxial layer 105 is surrounded by silicon substrates 106, so that the drain is connected at the top and bottom ends of the trench. The source region is sandwiched in the N-type epitaxial layer 105 and is located on both sides of the control gate electrode. The source region includes two P-type body regions 104 and one N+ source region 103. The N+ source region 103 is located between the two P-type body regions 104. The source metal 107 is embedded in the source region to form a conformal contact. In the SGT trench of this invention, a shielding gate electrode 102 is respectively provided at the upper and lower ends of the control gate electrode 101. Compared with the conventional SGT, this invention deepens the trench depth to achieve a stacked shielding gate structure. In the vertical depth direction of the trench, the electric field distribution of this invention can be expanded from the original single rectangle to a double rectangle distribution. Doubling the trench depth doubles the electric field distribution. The breakdown voltage BV is the area enclosed by the electric field and the depletion layer thickness, i.e. Figure 1 , 2 The orange portion of the electric field distribution shows that the present invention improves the voltage withstand capability of the device.

[0055] This invention increases the trench depth to increase the shielded gate electrode. The increased trench depth is at least 1.5 times the trench depth of a single shielded gate electrode and a control gate electrode in an SGT MOSFET with the same cell width and drift resistance, preferably doubled. As mentioned earlier, the increase in shielded gate length has a limited effect on improving the electric field. This invention preferably designs the shielded gate length to the optimal value for a single shielded gate, and then places two shielded gate electrodes above and below the control gate electrode to form a stacked structure, thus doubling the electric field distribution. Although a new shielded gate could be stacked on top of this, considering the increased process and packaging difficulties associated with further deepening the trench, this invention prefers a scheme of stacking two shielded gate electrodes, such as... Figure 5 The figure shows a comparison of the electric field distribution between a traditional single-shielded gate SGT and the stacked shielded gate SGT of the present invention.

[0056] Furthermore, the two shielding gate electrodes 102 are of the same size and are symmetrically distributed on the upper and lower sides of the control gate electrode 101.

[0057] Preferably, the two P-type body regions 104 are symmetrically located above and below the N+ source region 103, and the control gate electrode 101 is located in the middle of the P-type body region 104 and the N+ source region 103 in the trench depth direction.

[0058] As an example, such as Figure 6 As shown, other structural details of the stacked shielded gate field-effect transistor include: a control gate electrode 101 extending from one end of the trench in the longitudinal direction to the surface of the silicon substrate, forming a gate region through a contact hole; a shielded gate electrode 102 extending from at least the same end of the trench in the longitudinal direction to the surface of the silicon substrate, contacting the source metal 107 through a contact hole; and the source metal 107 extending out of the silicon substrate surface. The shielded gate electrode 102 can be extended to either end of the trench in the longitudinal direction, sharing the same end as the control gate electrode 101 in the longitudinal direction. This facilitates the spatial layout of the SGT device in the longitudinal direction, saving space required for the electrodes. Considering current flow and conduction performance, the shielded gate electrode 102 can also be extended from both ends of the trench in the longitudinal direction, or an additional extension can be added in the middle of the trench in the longitudinal direction.

[0059] The following describes the fabrication method of the shielded gate field-effect transistor of the present invention, such as... Figure 7 and Figure 8 As shown.

[0060] 1) Prepare a basic wafer. On a silicon substrate, the first to fifth epitaxial layers are grown sequentially using epitaxial technology. The first and fifth epitaxial layers are N-type epitaxial layers, the second and fourth epitaxial layers are P-type body regions, and the third epitaxial layer is an N+ source region. The basic wafer is thus obtained.

[0061] 2) Trenches are etched on the basic wafer, the trenches penetrating the first to fifth epitaxial layers;

[0062] 3) An oxide layer is grown in the trench;

[0063] 4) Etching of the oxide layer to form the first trench, wherein the thickness of the oxide layer between the bottom of the first trench and the bottom of the trench is h;

[0064] 5) Fill the first trench with polysilicon and etch the polysilicon to a height not exceeding the second epitaxial layer, i.e. the lower P-type body region, to obtain the first shielding gate electrode.

[0065] 6) Etch the oxide layer on the sidewall portion above the upper surface of the first shielding gate electrode to obtain a second trench, the width of which is greater than that of the first trench.

[0066] 7) Deposit an oxide layer in the second trench as a gate oxide layer, then fill the gate polysilicon and etch the gate polysilicon to a predetermined height to obtain a control gate electrode. The position of the control gate electrode corresponds to the second to fourth epitaxial layers in the trench depth direction.

[0067] 8) After the control gate electrode is formed, an oxide layer is re-deposited in the second trench until the trench is filled. Then, the oxide layer is etched according to the width of the first trench to form the third trench. An oxide layer is left between the bottom of the third trench and the control gate electrode as the gate oxide layer.

[0068] 9) Fill the third trench with polysilicon and etch the polysilicon to a thickness of h to obtain the second shielding gate electrode, so that the distance between the two shielding gate electrodes and the top and bottom surfaces of the trench is the same; when etching the polysilicon, the etching thickness is consistent with the oxide layer thickness on the left and right sides of the first and second shielding gates.

[0069] 10) An oxide layer is deposited to fill the trench, and an N-type epitaxial layer is grown on another silicon substrate. Then, the N-type epitaxial layer and the silicon substrate are bonded to the fifth epitaxial layer by silicon wafer bonding, forming a structure in which the entire trench is located in the N-type epitaxial layer and both the top and bottom surfaces are silicon substrates.

[0070] 11) For example Figure 8 As shown, to prepare the source metal, trenches are etched at the corresponding source region positions, an isolation oxide layer is deposited, and then metal is deposited to obtain the source metal. Then, an oxide layer is deposited to fill the trenches.

[0071] 12) The stacked shielded gate field-effect transistor is obtained by the subsequent electrode process of the shielded gate field-effect transistor.

[0072] During the fabrication process, the control gate electrode, the shielding gate electrode, and the source metal are led out to the surface of the upper silicon substrate in accordance with the existing shielding gate electrode lead-out method.

[0073] In a preferred embodiment, the second to fourth epitaxial layers are located at the middle of the trench depth, and the first and second shielding gate electrodes have the same size and are symmetrically located above and below the control gate electrode.

[0074] In the shielded gate field-effect transistor of the present invention, the two shielded gate electrodes directly share the same control gate electrode, and the channel density is doubled compared with the traditional SGT, which can significantly reduce the on-resistance, thereby reducing the energy loss during conduction and improving the efficiency of the device.

[0075] like Figure 9 The figure shows the electric field distribution results of the simulation experiment of the stacked shielded gate field-effect transistor of the present invention. The green line represents the relationship curve between the electric field and the EPI epitaxial thickness of the present invention, and the red line represents the relationship curve between the electric field and the EPI epitaxial thickness of the ordinary SGT. It is obvious that the green line almost coincides with the red line in the direction where the thickness is >3. The corresponding structural position is the lower shielded gate electrode of the device of the present invention. This part has the same depletion condition as the ordinary SGT, and the breakdown voltage capability BV (the area enclosed by the electric field and thickness) is the same. In the direction where the thickness is <3, the green line is completely symmetrical with the curve in the direction where the thickness is >3. The corresponding structural position is that the upper and lower shielded gate electrodes of the present invention have achieved the same depletion. Therefore, the breakdown voltage capability BV of the entire device is the sum of the two parts, achieving a breakthrough voltage capability BV that is twice that of the ordinary SGT. Short-circuit the gate and source, apply a voltage to the drain, and observe the breakdown voltage of the device. Figure 10 As shown, the voltage withstand capability of the present invention and ordinary SGT is compared: the ordinary SGT with a withstand voltage of 60V can be increased to 120V through stacking and deformation, that is, the voltage withstand capability of the SGT of the present invention is increased by a factor of two.

[0076] Based on the stacked shielded gate field-effect transistor of this invention, it can also be modified by combining existing SGT devices to achieve different effects, such as... Figure 11 As shown. Figure 10 Methods 1 and 3 can improve the electric field curve and enhance the breakdown voltage; methods 2 and 4 can improve the capacitance characteristics and enhance the switching performance; method 5 can lead out the gate structure in the cell region to reduce the gate resistance; method 6 adds a P+ region at the bottom of the trench to increase the breakdown voltage and improve parasitic capacitance. In this invention, the width of the shielding gate can be deformed in various ways depending on the improvement purpose. It can gradually widen, narrow, or be wide in some places and narrow in others. The relationship between the deformation of the shielding gate width and the improvement of device performance is prior art and will not be described in detail here.

Claims

1. A stacked shielded gate field-effect transistor, characterized by: The trench depth of the SGT MOSFET is increased. A control gate electrode and two shield gate electrodes are vertically stacked in the trench. The two shield gate electrodes are located above and below the control gate electrode and share the control gate electrode. The entire trench is located in an N-type epitaxial layer. The N-type epitaxial layer is on both the top and bottom of the layer and is a silicon substrate. This allows the drain to be connected to the top and bottom of the trench. The source region is sandwiched in the N-type epitaxial layer and is located on both sides of the control gate electrode. The source region includes two P-type body regions and one N+ source region. The N+ source region is located between the two P-type body regions. The source metal is embedded in the source region to form a conformal contact.

2. The stacked shielded gate field-effect transistor according to claim 1, characterized in that... The increased trench depth is more than 1.5 times that of an SGT MOSFET with a single shielded gate electrode and a control gate electrode having the same cell width and drift resistance.

3. The stacked shielded gate field-effect transistor according to claim 1, characterized in that... The two shielding gate electrodes are of the same size and are symmetrically distributed on the upper and lower sides of the control gate electrode.

4. The stacked shielded gate field-effect transistor according to claim 1, characterized in that... The two P-type body regions of the source region are symmetrically located above and below the N+ source region, and the control gate electrode is located in the middle of the P-type body region and the N+ source region in the trench depth direction.

5. The stacked shielded gate field-effect transistor according to claim 1, characterized in that... The control gate electrode is led out from one end of the trench in the longitudinal direction to the surface of the silicon substrate, and forms the gate region through the contact hole; The shielding gate electrode extends from at least the same end in the longitudinal direction of the trench to the surface of the silicon substrate and contacts the source metal through a contact hole; the source metal extends out of the surface of the silicon substrate.

6. The stacked shielded gate field-effect transistor according to any one of claims 1-5, characterized in that... The width of the two shielding gate electrodes gradually increases or decreases from the top and bottom towards the middle, controlling the direction of the gate electrodes.

7. The stacked shielded gate field-effect transistor according to any one of claims 1-5, characterized in that... The control gate electrode extends upward along the trench sidewall and concavely wraps around the shielding gate electrode located above the control gate electrode.

8. The stacked shielded gate field-effect transistor according to any one of claims 1-5, characterized in that... A P+ zone is provided at the bottom of the trench.

9. A method for fabricating a stacked shielded gate field-effect transistor according to any one of claims 1-5, characterized in that: Includes the following steps: 1) Prepare a basic wafer. On a silicon substrate, the first to fifth epitaxial layers are grown sequentially using epitaxial technology. The first and fifth epitaxial layers are N-type epitaxial layers, the second and fourth epitaxial layers are P-type body regions, and the third epitaxial layer is an N+ source region. The basic wafer is thus obtained. 2) Trenches are etched on the basic wafer, the trenches extending from the fifth epitaxial layer to the interior of the first epitaxial layer; 3) An oxide layer is grown in the trench; 4) Etching of the oxide layer to form the first trench, wherein the thickness of the oxide layer between the bottom of the first trench and the bottom of the trench is h; 5) Fill the first trench with polysilicon and etch the polysilicon to a height not exceeding the second epitaxial layer, i.e. the lower P-type body region, to obtain the first shielding gate electrode; 6) Etch the oxide layer on the sidewall portion above the upper surface of the first shielding gate electrode to obtain a second trench, the width of which is greater than that of the first trench. 7) Deposit an oxide layer in the second trench as a gate oxide layer, then fill the gate polysilicon and etch the gate polysilicon to a predetermined height to obtain a control gate electrode. The position of the control gate electrode corresponds to the second to fourth epitaxial layers in the trench depth direction. 8) After the control gate electrode is formed, an oxide layer is re-deposited in the second trench until the trench is filled. Then, the oxide layer is etched according to the width of the first trench to form the third trench. An oxide layer is left between the bottom of the third trench and the control gate electrode as the gate oxide layer. 9) Fill the third trench with polysilicon and etch the polysilicon to a thickness of h to obtain the second shielding gate electrode, so that the distance between the two shielding gate electrodes and the top and bottom surfaces of the trench is the same; when etching the polysilicon, the etching thickness is consistent with the oxide layer thickness on the left and right sides of the first and second shielding gates. 10) An oxide layer is deposited to fill the trench, and an N-type epitaxial layer is grown on another silicon substrate. Then, the N-type epitaxial layer and the silicon substrate are bonded to the fifth epitaxial layer by silicon wafer bonding, forming a structure in which the entire trench is located in the N-type epitaxial layer and both the top and bottom surfaces are silicon substrates. 11) Corresponding to the source region, etch trenches, deposit an isolation oxide layer, and then deposit metal to obtain the source metal; 12) The stacked shielded gate field-effect transistor is obtained by the subsequent electrode process of the shielded gate field-effect transistor.

10. The method for fabricating a stacked shielded gate field-effect transistor according to claim 9, characterized in that: The second to fourth epitaxial layers are located in the middle of the trench depth. The first and second shielding gate electrodes have the same size and are symmetrically located above and below the control gate electrode.

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