Solar cells and photovoltaic modules

Abstract

The application relates to a solar cell and a photovoltaic module. The solar cell comprises a semiconductor substrate, a first doped semiconductor layer located on a first surface of a first polarity region and comprising a first sidewall, a stack layer located on the first surface of a second polarity region and comprising a first subpart covering the first sidewall, a conductive layer located on a side of the first doped semiconductor layer and the stack layer away from the semiconductor substrate and comprising a first conductive part and a second conductive part arranged at intervals, a separation opening being formed between the first conductive part and the second conductive part, and a plurality of insulating parts located on a side of the first sidewall facing the first subpart and in contact with the first subpart, a normal projection of at least part of the separation opening on the semiconductor substrate does not overlap with a normal projection of the first subpart on the semiconductor substrate, and the normal projection of the plurality of insulating parts on the semiconductor substrate is connected to the normal projection of the first subpart on the semiconductor substrate. Therefore, the solar cell and the photovoltaic module provided by the application can better balance the anti-hot spot performance and the cell efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photovoltaic, in particular to a solar cell and a photovoltaic module. BACKGROUND

[0002] A solar cell, also known as a photovoltaic cell, is a kind of semiconductor device that directly converts solar light energy into electrical energy. Since it is a green product that does not cause environmental pollution, and solar energy is a renewable resource, the solar cell is a new type of battery with broad development prospects.

[0003] In the related art, a heterojunction back contact (HBC) solar cell has metal electrodes arranged on the back surface of the cell, so that the light-receiving surface of the cell is not blocked by the metal electrodes, thereby increasing the light absorption area and improving the photoelectric conversion efficiency. However, the above-mentioned HBC cell cannot balance the hot spot resistance performance and the cell efficiency. SUMMARY

[0004] Therefore, it is necessary to provide a solar cell and a photovoltaic module, which can better balance the hot spot resistance performance and the cell efficiency.

[0005] In a first aspect, an embodiment of the present application provides a solar cell having a first polarity region and a second polarity region with opposite polarities, the solar cell comprising:

[0006] a semiconductor substrate comprising a first surface;

[0007] a first doped semiconductor layer arranged on the first surface and located in the first polarity region, the first doped semiconductor layer comprising a first sidewall connected between two surfaces of the first doped semiconductor layer on opposite sides in a thickness direction of the semiconductor substrate;

[0008] a stack layer arranged on the first surface and located in the second polarity region, the stack layer comprising a first subpart covering the first sidewall;

[0009] a conductive layer arranged on a side of the first doped semiconductor layer and the stack layer away from the semiconductor substrate, the conductive layer comprising a first conductive part and a second conductive part arranged at intervals, a separation opening being formed between the first conductive part and the second conductive part, the first conductive part being located in the first polarity region, and the second conductive part being located in at least the second polarity region;

[0010] a plurality of insulating parts arranged at intervals on a side of the first sidewall facing the first subpart and in contact with the first subpart, and at least part of the projection of the separation opening on the semiconductor substrate does not overlap with the projection of the first subpart on the semiconductor substrate, and is connected with the projection of the plurality of insulating parts on the semiconductor substrate.

[0011] The solar cell provided by the embodiment of the present application can prevent the excessive leakage current by arranging multiple insulation portions between the leakage path between the first doped semiconductor layer and the conductive layer at the first side wall, and by preventing the transmission of the leakage current between the first doped semiconductor layer and the conductive layer at the first side wall, thereby improving the open circuit voltage and the efficiency of the solar cell. In addition, the multiple insulation portions are arranged at intervals along the extension direction of the first opening portion, the multiple insulation portions corresponding to the same first opening portion are arranged discontinuously, and there is a gap between the adjacent two insulation portions. The region between the adjacent two insulation portions is in contact with the conductive layer to generate leakage, thereby improving the hot spot resistance and the reliability of the solar cell, and further balancing the hot spot resistance, the efficiency and the reliability of the solar cell.

[0012] In one of the embodiments, the insulation portion is arranged on the side of the first sub-portion away from the first side wall.

[0013] In one of the embodiments, the insulation portion is configured as an insulation opening, the insulation opening is arranged on the conductive layer and penetrates the conductive layer along the thickness direction of the semiconductor substrate, and the insulation opening is in communication with the isolation opening.

[0014] In one of the embodiments, the insulation portion is configured as an insulation protrusion.

[0015] In one of the embodiments, the isolation opening extends along the extension direction of the boundary line between the first polarity region and the second polarity region, the first polarity region includes a first sub-region and a second sub-region, the second sub-region is located between the first sub-region and the second polarity region, the stack layer includes a second sub-portion connected to the first sub-portion, the second sub-portion is arranged in the second sub-region, and is located on the side of the first doped semiconductor layer away from the semiconductor substrate.

[0016] The isolation opening includes a first opening portion, the first opening portion is located in the second sub-region, and the orthographic projection of the first opening portion on the semiconductor substrate is connected to the orthographic projection of the multiple insulation portions on the semiconductor substrate.

[0017] In one of the embodiments, the insulation portion includes a first sub-insulation portion and a second sub-insulation portion connected to each other, the first sub-insulation portion is in contact with the first sub-portion, and the second sub-insulation portion is in contact with the second sub-portion.

[0018] In one of the embodiments, in the same insulation portion, the size of the first sub-insulation portion along the extension direction of the boundary line is greater than the size of the remaining part of the insulation portion along the extension direction of the boundary line.

[0019] In one of the embodiments, the stack layer includes a third sub-portion, the third sub-portion is connected to the side of the first sub-portion away from the second sub-portion, and is arranged on the first surface of the second polarity region.

[0020] In the same insulating part, the insulating part comprises a first sub-insulating part and a third sub-insulating part connected in sequence, the first sub-insulating part is in contact with the first sub-region, and the third sub-insulating part is in contact with the third sub-region.

[0021] In one of the embodiments, the third sub-insulating part gradually decreases in size along the extension direction of the boundary line from the first sub-insulating part to the third sub-insulating part.

[0022] In one of the embodiments, the isolation opening comprises a second opening part, the first opening part and the second opening part are arranged along the extension direction of the boundary line, the second opening part is located in the second sub-region and the second polarity region, and the second opening part exposes part of the first sub-region.

[0023] In one of the embodiments, the sum of the areas of the orthographic projections of all the insulating parts located in the first polarity region, the first opening part and the second opening part located in the first polarity region on the semiconductor substrate is a first value, the sum of the areas of the orthographic projections of all the insulating parts located in the second polarity region and the second opening part located in the second polarity region on the semiconductor substrate is a second value, and the ratio of the second value to the first value ranges from 0.01 to 0.9.

[0024] In one of the embodiments, the isolation opening comprises a third opening part, the first opening part and the third opening part are arranged along the extension direction of the boundary line, the third opening part is located in the second sub-region, and the orthographic projection of the third opening part on the semiconductor substrate is arranged in a spaced manner with the orthographic projection of the insulating part on the semiconductor substrate.

[0025] In one of the embodiments, the sum of the areas of the orthographic projections of all the insulating parts and the first opening part on the semiconductor substrate is a third value, the area of the orthographic projection of the third opening part on the semiconductor substrate is a fourth value, and the ratio of the fourth value to the third value ranges from 0 to 0.5.

[0026] In one of the embodiments, the isolation opening comprises a second opening part and a third opening part, the first opening part, the second opening part and the third opening part are arranged along the extension direction of the boundary line, the second opening part is located in the second sub-region and the second polarity region, the second opening part exposes part of the first sub-region, the third opening part is located in the second sub-region, and the orthographic projection of the third opening part on the semiconductor substrate is arranged in a spaced manner with the orthographic projection of the insulating part on the semiconductor substrate.

[0027] The sum of the areas of the orthographic projections of all the insulating parts, the first opening part and the second opening part on the semiconductor substrate is a fifth value, the area of the orthographic projection of the third opening part on the semiconductor substrate is a fourth value, and the ratio of the fourth value to the fifth value ranges from 0 to 0.9.

[0028] In one of the embodiments, the first polarity region includes at least one first sub-polarity region, the second polarity region includes at least one second sub-polarity region, the first sub-polarity region and the second sub-polarity region are arranged alternately along the first direction, the first sub-polarity region is provided with a first sub-region and a second sub-region, and the second sub-region of the first sub-polarity region is located between the first sub-region of the first sub-polarity region and the second sub-polarity region.

[0029] The first conductive part includes at least one first sub-conductive part, and the second conductive part includes at least one second sub-conductive part. The first sub-conductive part is located in the first sub-polarity region, the second sub-conductive part is located in the second sub-polarity region, and a separation opening is provided between adjacent first sub-conductive parts and second sub-conductive parts. The first direction intersects the thickness direction of the semiconductor substrate.

[0030] In one of the embodiments, in at least part of the adjacent first sub-conductive part and the second sub-conductive part and the separation opening located between the adjacent first sub-conductive part and the second sub-conductive part, the separation opening is a first opening part, the first opening part extends along the second direction, the first opening part is provided corresponding to a plurality of insulating parts, the orthographic projection of the plurality of insulating parts on the semiconductor substrate is connected to one side of the orthographic projection of the first opening part on the semiconductor substrate along the first direction, and the plurality of insulating parts are arranged at intervals along the second direction. Any two of the first direction, the second direction and the thickness direction of the semiconductor substrate intersect.

[0031] In one of the embodiments, in at least part of the adjacent first sub-conductive part and the second sub-conductive part and the separation opening located between the adjacent first sub-conductive part and the second sub-conductive part, the separation opening is a second opening part, the second opening part extends along the second direction, and any two of the first direction, the second direction and the thickness direction of the semiconductor substrate intersect.

[0032] In one of the embodiments, in at least part of the adjacent first sub-conductive part and the second sub-conductive part and the separation opening located between the adjacent first sub-conductive part and the second sub-conductive part, the separation opening is a third opening part, the third opening part extends along the second direction, and any two of the first direction, the second direction and the thickness direction of the semiconductor substrate intersect.

[0033] In one of the embodiments, the sum of the areas of the orthographic projections of all the insulating parts and the first opening part in the first polarity region on the semiconductor substrate is a sixth value, the sum of the areas of the orthographic projections of all the insulating parts in the second polarity region on the semiconductor substrate is a seventh value, and the ratio of the seventh value to the sixth value ranges from 0.01 to 0.9.

[0034] In one embodiment, the orthographic projection of the insulating portion on the semiconductor substrate is a first orthographic projection, and the orthographic projection of the first opening portion on the semiconductor substrate is a second orthographic projection. In the connected first and second orthographic projections, the side of the first orthographic projection away from the second orthographic projection is an arc edge, and the arc edge protrudes in a direction away from the center of the first orthographic projection.

[0035] In one embodiment, the solar cell includes a first passivation layer disposed in a first polar region and located between a first surface and a first doped semiconductor layer; and / or,

[0036] The stacked layer includes a second passivation layer and a second doped semiconductor layer stacked along the direction away from the semiconductor substrate.

[0037] Secondly, embodiments of this application provide a photovoltaic module, including the solar cell of the first aspect. Attached Figure Description

[0038] Figure 1 A top view of a solar cell provided in an embodiment of this application.

[0039] Figure 2 Another top view of a solar cell provided in an embodiment of this application.

[0040] Figure 3 for Figure 1 A sectional view along the AA direction.

[0041] Figure 4 for Figure 3 A magnified structural diagram at point B.

[0042] Figure 5a This is a partially enlarged structural diagram of a solar cell provided in an embodiment of this application.

[0043] Figure 5b This is a partially enlarged structural diagram of a solar cell provided in an embodiment of this application.

[0044] Figure 6 A partial top view of the first doped semiconductor layer, the second doped semiconductor layer, and the conductive layer provided for embodiments of this application.

[0045] Figure 7 Another partial top view of the first doped semiconductor layer, the second doped semiconductor layer, and the conductive layer provided in the embodiments of this application.

[0046] Figure 8 Another partial top view of the first doped semiconductor layer, the second doped semiconductor layer, and the conductive layer provided in the embodiments of this application.

[0047] Figure 9Another partial top view of the first doped semiconductor layer, the second doped semiconductor layer and the conductive layer provided for the embodiments of the present application.

[0048] Figure 10 Another partial top view of the first doped semiconductor layer, the second doped semiconductor layer and the conductive layer provided for the embodiments of the present application.

[0049] Figure 11 Another partial top view of the first doped semiconductor layer, the second doped semiconductor layer and the conductive layer provided for the embodiments of the present application.

[0050] Figure 12 Another partial top view of the first doped semiconductor layer, the second doped semiconductor layer and the conductive layer provided for the embodiments of the present application.

[0051] Figure 13 Another partial top view of the first doped semiconductor layer, the second doped semiconductor layer and the conductive layer provided for the embodiments of the present application.

[0052] Figure 14 A top view of the conductive layer provided for the embodiments of the present application.

[0053] Figure 15 Another top view of the conductive layer provided for the embodiments of the present application.

[0054] Legend of reference signs:

[0055] 100, solar cell; 100a, first polarity region; 100a1, first sub-region; 100a2, second sub-region; 100b, second polarity region; 100c1, first sub-polarity region; 100c2, second sub-polarity region; 100c3, third sub-polarity region; 100c4, fourth sub-polarity region; 110, semiconductor substrate; 111, first face; 112, second face; 121, first doped semiconductor layer; 1211, first sidewall; 122, second doped semiconductor layer; 130, stack layer; 131, first sub-section; 132, second sub-section; 133, third sub-section; 140, conductive layer; 141, first conductive section; 142, second conductive section; 1431, first sub-conductive section; 1432, second sub-conductive section; 1433, third sub-conductive section; 1434, fourth sub-conductive section; 151, first passivation layer; 152, second passivation layer; 153, third passivation layer; 154, anti-reflection layer; 161, first electrode; 162, second electrode; 170, isolation opening; 171, first opening section; 172, second opening section; 173, third opening section; 180, insulating section; 180a, insulating opening; 180b, insulating protrusion; 181, first sub-insulating section; 182, second sub-insulating section; 183, third sub-insulating section; E, boundary line; X, first direction; Y, second direction; Z, third direction. DETAILED DESCRIPTION

[0056] In order to make the above objectives, features and advantages of the present application more clear and comprehensible, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced in a number of different ways beyond the specific embodiments described herein and by one of ordinary skill in the art without departing from the spirit and scope of the present application, and it is therefore intended that all such variations be considered as falling within the scope of the present application.

[0057] In the description of the present application, it should be understood that, if there are terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0058] In addition, if the terms "first", "second" appear, these terms are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implying the number of technical features indicated. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, if the term "multiple" appears, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise explicitly specified and limited.

[0059] In the present application, unless otherwise explicitly specified and limited, if the terms "mounting", "connecting", "connecting", "fixing" and the like appear, these terms should be interpreted broadly. For example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0060] In the present application, unless specifically stated and limited otherwise, if there is a description of a first feature "on" or "under" a second feature, etc., it can mean that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature "above", "over" and "on" the second feature can be that the first feature is directly above or obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "under" and "under" the second feature can be that the first feature is directly below or obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0061] It should be noted that if an element is referred to as "fixed to" or "provided on" another element, it can be directly on the other element or there can be a middle element. If an element is considered to be "connected" to another element, it can be directly connected to another element or there can be a middle element. If present, the terms "vertical", "horizontal", "up", "down", "left", "right" and similar expressions used in the present application are only for illustrative purposes and are not the only embodiment.

[0062] In the related art, during use, the HBC battery inevitably falls on dust, leaves, snow, birds, etc. The shaded part cannot normally perform photoelectric conversion and will become a load to consume the energy generated by other HBC batteries with light, causing local temperature rise and hot spot effect, which may cause the solder joints on the HBC battery to melt and damage the grid lines, resulting in the scrapping of the entire HBC battery, and in severe cases, a fire. The hot spot effect can be alleviated by designing a leakage channel on the back of the HBC battery to increase the reverse leakage current.

[0063] The HBC battery has an N-type region and a P-type region, and the HBC battery includes a semiconductor substrate having a first surface and a second surface arranged opposite to each other, a tunneling oxide layer and an N-type doped semiconductor layer arranged in sequence on the first surface of the N-type region, an intrinsic amorphous silicon layer and a P-type doped semiconductor layer arranged in sequence on the first surface of the P-type region, and part of the intrinsic amorphous silicon layer and the P-type doped semiconductor layer can extend to a side of the N-type doped semiconductor layer away from the semiconductor substrate.

[0064] The P-type doped semiconductor layer can be P-type amorphous silicon or P-type microcrystalline silicon, so that the carrier mobility of the P-type doped semiconductor layer is low, and the carrier needs to be transmitted by the conductive layer. Therefore, a transparent conductive layer is formed on the side of the N-type doped semiconductor layer and the P-type doped semiconductor layer away from the semiconductor substrate, and an isolation opening is provided on the transparent conductive layer. The isolation opening separates the transparent conductive layer into a first transparent conductive part and a second transparent conductive part, the first transparent conductive part is located in the N-type region, and the second transparent conductive part is located in the P-type region.

[0065] However, the thickness of the intrinsic amorphous silicon layer covering the sidewall of the N-type doped semiconductor layer is smaller than that of the intrinsic amorphous silicon layer in other regions, and if the conductive layer covers the P-type doped semiconductor layer at the sidewall, it is easy to cause leakage between the sidewall of the N-type doped semiconductor layer and the P-type doped semiconductor layer at the sidewall. In some examples, the isolation opening can expose the P-type doped semiconductor layer at the entire sidewall, so that the conductive layer does not cover the P-type doped semiconductor layer at the sidewall, thereby reducing the leakage between the sidewall of the N-type doped semiconductor layer and the P-type doped semiconductor layer at the sidewall, but at the same time, the reverse leakage current of the HBC cell is small, the hot spot resistance performance is poor, and the area of the P-type doped semiconductor layer exposed to the outside of the conductive layer is large, the area of the P-type doped semiconductor layer covered by the conductive layer is small, and the reliability of the cell is greatly affected. In other examples, the isolation opening can be arranged in the overlapping region of the P-type doped semiconductor layer and the N-type doped semiconductor layer, the isolation opening is completely staggered with the P-type doped semiconductor layer at the sidewall, and the conductive layer covers the P-type doped semiconductor layer at the entire sidewall, so that the reverse leakage between the sidewall of the N-type doped semiconductor layer and the P-type doped semiconductor layer at the sidewall is large, although the hot spot resistance performance is improved, and the area of the P-type doped semiconductor layer exposed to the outside of the conductive layer is reduced, the area of the P-type doped semiconductor layer covered by the conductive layer is increased, and the reliability of the cell can be improved, but the open-circuit voltage and the efficiency of the cell are reduced. Therefore, the hot spot resistance performance, the cell efficiency and the reliability of the HBC cell cannot be balanced.

[0066] To solve the above problems, the embodiments of the present application provide a solar cell and a photovoltaic module, which can better balance the hot spot resistance performance, the cell efficiency and the reliability of the cell.

[0067] The following will be combined with Figures 1-15 The solar cell and the photovoltaic module provided by the embodiments of the present application will be described.

[0068] Referring to Figure 1 The embodiments of the present application provide a solar cell 100, which includes a first polarity region 100a and a second polarity region 100b. The polarities of the first polarity region 100a and the second polarity region 100b are opposite, that is, the conductive types of the first polarity region 100a and the second polarity region 100b are opposite, one of the first polarity region 100a and the second polarity region 100b can be an N-type region, and the other can be a P-type region. The first polarity region 100a and the second polarity region 100b are arranged adjacent to each other, and have a boundary line E between them. The first polarity region 100a includes a first sub-region 100a1 and a second sub-region 100a2, and the second sub-region 100a2 can be located between the first sub-region 100a1 and the second polarity region 100b.

[0069] Referring to Figure 3 The solar cell 100 includes a semiconductor substrate 110, which can provide support for subsequently formed film layers. The semiconductor substrate 110 can be used to receive incident light and generate photo-generated carriers.

[0070] For example, referring to Figure 3 The semiconductor substrate 110 can have a first surface 111 and a second surface 112 oppositely arranged along a thickness direction (i.e., a third direction Z) of the semiconductor substrate 110, and at least one of the first surface 111 and the second surface 112 can be used to receive sunlight. Embodiments of the present application take the second surface 112 as an example for receiving sunlight, i.e., the second surface 112 is close to the light-receiving surface of the solar cell 100, and the first surface 111 is close to the back surface of the solar cell 100.

[0071] Referring to Figure 3 The solar cell 100 includes a first doped semiconductor layer 121, which is arranged on the first surface 111 and located in the first polarity region 100a. The first doped semiconductor layer 121 includes a third surface, a fourth surface, and a first side wall 1211, the third surface and the fourth surface are oppositely arranged along the thickness direction of the semiconductor substrate 110, and the first side wall 1211 is connected to the third surface and the fourth surface. In other words, the first side wall 1211 is connected between the surfaces on both sides of the first doped semiconductor layer 121 along the thickness direction of the semiconductor substrate 110.

[0072] Referring to Figure 3 The solar cell 100 includes a stack layer 130, which is arranged on the first surface 111 and located in the second polarity region 100b. The stack layer 130 includes a second passivation layer 152 and a second doped semiconductor layer 122, which are stacked in a direction away from the semiconductor substrate 110, and both the second passivation layer 152 and the second doped semiconductor layer 122 are located in the second polarity region 100b. The second passivation layer 152 can improve photoelectric conversion efficiency by reducing surface recombination rate, thereby improving the open-circuit voltage and conversion efficiency of the solar cell 100. The second passivation layer 152 can be in contact with the first surface 111 located in the second polarity region 100b. The area where the second passivation layer 152 is in contact with the first surface 111 defines the second polarity region 100b.

[0073] Referring to Figure 3 In the embodiment in which the first polarity region 100a includes a first sub-region 100a1 and a second sub-region 100a2, part of the stack layer 130 covers a side of the first doped semiconductor layer 121 away from the semiconductor substrate 110, and this part of the stack layer 130 is located in the second sub-region 100a2. The second sub-region 100a2 can be a region where the first doped semiconductor layer 121 and the stack layer 130 overlap along the thickness direction of the semiconductor substrate 110.

[0074] It should be noted that, referring to Figure 3 and Figure 4 , the stack layer 130 includes a first sub-section 131 covering the first side wall 1211, the first sub-section 131 has a thickness thinner than the thickness of the rest of the stack layer 130, the second passivation layer 152 in the first sub-section 131 has a thickness thinner than the thickness of the rest of the second passivation layer 152, the thinner second passivation layer 152 has a poor leakage current blocking effect between the first doped semiconductor layer 121 at the first side wall 1211 and the second doped semiconductor layer 122 in the first sub-section 131, and the leakage current between the first doped semiconductor layer 121 at the first side wall 1211 and the second doped semiconductor layer 122 in the first sub-section 131 leaks through the conductive layer 140 subsequently formed on the first sub-section 131. The first doped semiconductor layer 121 at the first side wall 1211, the first sub-section 131, and the conductive layer 140 on the first sub-section 131 form a leakage path.

[0075] Referring to Figure 3 , the solar cell 100 includes a conductive layer 140, which can be a transparent conductive layer. The conductive layer 140 is disposed on the side of the first doped semiconductor layer 121 and the stack layer 130 away from the semiconductor substrate 110, and includes a first conductive section 141 and a second conductive section 142 arranged at intervals, and a separation opening 170 formed between the first conductive section 141 and the second conductive section 142, the separation opening 170 extending through the conductive layer 140 along the thickness direction of the semiconductor substrate 110. The first conductive section 141 and the second conductive section 142 are separated by the separation opening 170, and the first conductive section 141 and the second conductive section 142 are insulated by the separation opening 170. The first conductive section 141 is located in the first polarity region 100a, and the second conductive section 142 is located in the second polarity region 100b. The conductive layer 140 has a high conductivity, which can timely guide the collected carriers out of the solar cell 100, thereby reducing the carrier recombination rate. In addition, the conductive layer 140 can also serve as an anti-reflection film to improve the light absorption rate of the solar cell 100.

[0076] For example, referring to Figure 1 and Figure 14 , the separation opening 170 extends along the extension direction of the boundary line E. The separation opening 170 includes at least one opening section, and when there are multiple opening sections, the multiple opening sections are arranged along the extension direction of the boundary line E. The multiple opening sections are arranged along the trajectory of the boundary line E. The opening section extends along the extension direction of the boundary line E.

[0077] For example, each of the opening portions is located at least partially in the first polarity region 100a, for example, each of the opening portions is located at least partially in the second sub-region 100a2. The opening portion can be a regular shape or an irregular shape continuously extending along the boundary line E.

[0078] It should be noted that the boundary line between the first polarity region 100a and the second polarity region 100b can be a continuous line, or the boundary line between the first polarity region 100a and the second polarity region 100b can be a plurality of discontinuous lines. In the embodiment in which the boundary line between the first polarity region 100a and the second polarity region 100b is a plurality of lines, the plurality of opening portions arranged along the extension direction of the boundary line E can be that a plurality of opening portions are arranged on one boundary line and arranged along the extension direction of the boundary line, or the plurality of opening portions are respectively located on different boundary lines.

[0079] Referring to Figure 4 The at least one opening portion includes a first opening portion 171, the first opening portion 171 is located in the first polarity region 100a, for example, the first opening portion 171 is located in the second sub-region 100a2, the orthographic projection of the first opening portion 171 on the semiconductor substrate 110 does not overlap with the orthographic projection of the first sub-portion 131 on the semiconductor substrate 110, and the conductive layer 140 is in contact with at least part of the first sub-portion 131.

[0080] Referring to Figure 4 and Figure 8The solar cell 100 includes a plurality of insulating portions 180, which are arranged on the side of the first side wall 1211 facing the first subportion 131 and in contact with the first subportion 131. The insulating portions 180 can be arranged on the side of the first subportion 131 facing the first side wall 1211 or the side of the first subportion 131 facing away from the first side wall 1211. The first opening portion 171 extends along the extension direction of the boundary line E, and the plurality of insulating portions 180 are arranged at intervals along the extension direction of the first opening portion 171, i.e., along the extension direction of the boundary line E. The orthographic projection of the insulating portions 180 on the semiconductor substrate 110 is connected to the orthographic projection of the first opening portion 171 on the semiconductor substrate 110. In this way, by arranging the plurality of insulating portions 180 between the leakage paths between the first doped semiconductor layer 121 and the conductive layer 140 at the first side wall 1211, the insulating portions 180 can hinder the transmission of the leakage current between the first doped semiconductor layer 121 and the conductive layer 140 at the first side wall 1211, and can reduce the leakage current between the first doped semiconductor layer 121 and the conductive layer 140 at the first side wall 1211, thereby preventing the leakage current from being too large, and facilitating the improvement of the open-circuit voltage and the efficiency of the solar cell 100. In addition, the plurality of insulating portions 180 are arranged at intervals along the extension direction of the first opening portion 171, and the plurality of insulating portions 180 corresponding to the same first opening portion 171 are arranged discontinuously, and there is a gap between the adjacent two insulating portions 180. The region between the adjacent two insulating portions 180 is in contact with the conductive layer 140 through the first subportion 131, thereby generating a leakage current, and thereby improving the hot spot resistance and the reliability of the solar cell 100, and thereby better balancing the hot spot resistance, the efficiency, and the reliability of the solar cell. In addition, by arranging the plurality of insulating portions 180 at intervals, compared with arranging the plurality of insulating portions 180 as an integral insulating structure, the region where the leakage occurs is separated by the plurality of insulating portions 180, and the leakage is prevented from being too concentrated, thereby preventing the local temperature from rising too much, and thereby facilitating the improvement of the uniformity of the reverse leakage current.

[0081] For example, the extension direction of the insulating portion 180 intersects the extension direction of the first opening portion 171, i.e., the extension direction of the insulating portion 180 intersects the extension direction of the boundary line E.

[0082] In some embodiments, referring to Figure 4 and Figure 8, the insulating part 180 is configured as an insulating opening 180a, the insulating opening 180a is arranged on the conductive layer 140, and the insulating opening 180a can penetrate the conductive layer 140 along the thickness direction of the semiconductor substrate 110, and the insulating opening 180a is in communication with the first opening part 171. In this way, by setting the insulating part 180 as the insulating opening 180a, part of the conductive layer 140 covering the first subpart 131 can be removed to form the insulating opening 180a, which cannot transmit the leakage current, thereby preventing the leakage current from being too large, which is conducive to improving the open circuit voltage and efficiency of the solar cell 100. In addition, the conductive layer 140 between the two adjacent insulating openings 180a is in contact with the first subpart 131 to cause leakage, thereby improving the hot spot prevention performance, and further balancing the hot spot prevention performance, cell efficiency and reliability of the cell. At this time, the insulating opening 180a is arranged on the side of the first subpart 131 away from the first side wall 1211. Secondly, the implementation of arranging the insulating opening 180a in the conductive layer 140 balances the hot spot prevention performance and the cell efficiency, without changing the film layer structure of the solar cell 100. Only by designing the pattern of the isolation opening 170 and the insulating opening 180a on the conductive layer 140, the size of the reverse leakage current can be controlled, the reverse leakage and the cell efficiency are balanced, which is conducive to simplifying the preparation process of the solar cell and reducing the preparation cost.

[0083] For example, the position, distribution and area ratio of each opening part of the isolation opening 170 can be controlled to achieve the effect of high cell efficiency, improved hot spot prevention performance and reliability.

[0084] In some embodiments, referring to Figure 5a , the insulating part 180 is configured as an insulating protrusion 180b, which can be used to separate the first side wall 1211 and the conductive layer 140, and hinder the transmission of the leakage current between the first doped semiconductor layer 121 of the first side wall 1211 and the conductive layer 140 corresponding to the insulating protrusion 180b, thereby preventing the leakage current from being too large, which is conducive to improving the open circuit voltage and efficiency of the solar cell 100. In addition, the region between the two adjacent insulating protrusions 180b corresponds to the part of the conductive layer 140 and the first side wall 1211 where no insulating protrusion 180b is arranged, and the part of the conductive layer 140 is in contact with the first subpart 131 to cause leakage, thereby improving the hot spot prevention performance, and further balancing the hot spot prevention performance and the cell efficiency of the cell. Secondly, by reducing the leakage current through the insulating protrusion 180b, it is not necessary to arrange the insulating opening 180a on the conductive layer 140, which is conducive to improving the coverage area of the conductive layer 140 on the second doped semiconductor layer 122 and improving the reliability of the solar cell.

[0085] In some examples, the insulating protrusion 180b can be arranged on a side of the first sub-portion 131 facing the first sidewall 1211, and the insulating protrusion 180b is located between the first sidewall 1211 and the first sub-portion 131. In this way, the insulating protrusion 180b can hinder the transmission of the leakage current between the first doped semiconductor layer 121 and the first sub-portion 131 at the first sidewall 1211.

[0086] In some other examples, referring to Figure 5a , the insulating protrusion 180b can be arranged on a side of the first sub-portion 131 away from the first sidewall 1211, and the insulating protrusion 180b can be located between the first sub-portion 131 and the conductive layer 140, for example, the insulating protrusion 180b can be located between the first sub-portion 131 and the second conductive portion 142. In this way, the insulating protrusion 180b can hinder the transmission of the leakage current between the first sub-portion 131 and the conductive layer 140, in addition, the insulating protrusion 180b does not contact the first passivation layer 151 and the second passivation layer 152, and is not easy to contaminate the first passivation layer 151 and the second passivation layer 152, which is conducive to ensuring the passivation effect of the first passivation layer 151 and the second passivation layer 152. The embodiments of the present application are described by taking the example that the insulating protrusion 180b is arranged on the side of the first sub-portion 131 away from the first sidewall 1211.

[0087] For example, referring to Figure 5b , part of the insulating protrusion 180b can be located between the first opening portion 171 and the stacked layer 130, and part of the first opening portion 171 covers part of the insulating protrusion 180b. In this way, the orthographic projection of the first opening portion 171 on the semiconductor substrate 110 and the orthographic projection of the insulating protrusion 180b on the semiconductor substrate 110 are more likely to be connected, which is conducive to reducing the difficulty of manufacturing the insulating protrusion 180b. The extension length of the insulating protrusion 180b can be set according to requirements, and the embodiments of the present application do not limit this.

[0088] For example, referring to Figure 8The first opening portion 171 can be at least one, and when the first opening portion 171 is multiple, the multiple first opening portions 171 are arranged at intervals along the boundary line E. The first opening portion 171 and the multiple insulating portions 180 are arranged correspondingly. The orthographic projection of the multiple insulating portions 180 on the semiconductor substrate 110 is connected to the orthographic projection of the corresponding first opening portion 171 on the semiconductor substrate 110. The orthographic projection of the insulating portion 180 on the semiconductor substrate 110 is a first orthographic projection, and the orthographic projection of the first opening portion 171 on the semiconductor substrate 110 is a second orthographic projection. In the connected first orthographic projection and second orthographic projection, the first orthographic projection extends in a direction away from the second orthographic projection, and the first orthographic projection is in a strip shape, so that the size of the first orthographic projection in the direction away from the second orthographic projection is greater than the size of the first orthographic projection in the extension direction of the second orthographic projection, which is conducive to connecting more first orthographic projections on the second orthographic projection, improving the setting density of the insulating portion 180, and making the distribution of the first orthographic projection in the extension direction of the second orthographic projection more uniform, which is conducive to improving the uniformity of the leakage current.

[0089] In some embodiments, referring to Figure 3 and Figure 4 , in the implementation in which the first polarity region 100a includes the first sub-region 100a1 and the second sub-region 100a2, the stack layer 130 includes a second part 132 connected to the first part 131, the second part 132 is arranged in the second sub-region 100a2, and the second part 132 is located on the side of the first doped semiconductor layer 121 away from the semiconductor substrate 110. The first opening portion 171 is located in the second sub-region 100a2. In this way, the first opening portion 171 is located in the second part 132 away from the semiconductor substrate 110. The first opening portion 171 is arranged in the overlapping area of the stack layer 130 and the first doped semiconductor layer 121, and the film layer between the first opening portion 171 and the semiconductor substrate 110 has a larger thickness, which is conducive to reducing the damage proportion of the film layer between the first opening portion 171 and the semiconductor substrate 110 in the process of forming the first opening portion 171.

[0090] In some embodiments, referring to Figure 3 and Figure 4 , the stack layer 130 includes a third part 133 connected to the side of the first part 131 away from the second part 132, and the third part 133 is arranged on the first surface 111 of the second polarity region 100b.

[0091] In some embodiments, referring to Figure 5a, the insulation portion 180 comprises a first sub-insulation portion 181 and a second sub-insulation portion 182 connected to each other, the first sub-insulation portion 181 is in contact with the first sub-portion 131, and the second sub-insulation portion 182 is in contact with the second sub-portion 132, so that the insulation portion 180 extends from the first sub-portion 131 to the second sub-portion 132, compared with arranging the insulation portion 180 only on the first sub-portion 131, it is beneficial to reduce the difficulty of arranging the insulation portion 180.

[0092] In some embodiments, in the same insulation portion 180, the insulation portion 180 comprises a first sub-insulation portion 181 and a third sub-insulation portion 183 connected to each other, the first sub-insulation portion 181 is in contact with the first sub-portion 131, and the third sub-insulation portion 183 is in contact with the third sub-portion 133, so that the insulation portion 180 extends from the first sub-portion 131 to the third sub-portion 133, compared with arranging the insulation portion 180 only on the first sub-portion 131, it is beneficial to reduce the difficulty of arranging the insulation portion 180.

[0093] In some embodiments, in the same insulation portion 180, the size of the first sub-insulation portion 181 along the extension direction of the boundary line is greater than the size of the rest of the insulation portion 180 along the extension direction of the boundary line, that is, the width of the first sub-insulation portion 181 is greater than the width of the rest of the insulation portion 180, the first sub-insulation portion 181 is the main part of the insulation portion 180 that plays a role in reducing the leakage current, so that by setting the width of the first sub-insulation portion 181 to be larger, it is beneficial to better reduce the leakage current, and in addition, by setting the width of the rest of the insulation portion 180 to be smaller, it is beneficial to improve the transmission of carriers between the second conductive portion 142 and the second doped semiconductor layer 122.

[0094] In some embodiments, the size of the third sub-insulation portion 183 along the extension direction of the boundary line gradually decreases from the first sub-insulation portion 181 to the third sub-insulation portion 183, so that the width of the end of the third sub-insulation portion 183 close to the first sub-insulation portion 181 is larger, which is beneficial to reduce the difference in width between the end of the third sub-insulation portion 183 close to the first sub-insulation portion 181 and the first sub-insulation portion 181, and is beneficial to prevent stress concentration between the two, and in addition, the width of the end of the third sub-insulation portion 183 away from the first sub-insulation portion 181 is smaller, which can further be beneficial to improve the transmission of carriers between the second conductive portion 142 and the second doped semiconductor layer 122.

[0095] In some embodiments, referring to Figure 3 and Figure 11The isolation opening 170 includes a second opening portion 172. The first opening portion 171 and the second opening portion 172 are arranged along the extension direction of the boundary line E. The second opening portion 172 extends along the extension direction of the boundary line E. The second opening portion 172 is in a strip shape. The second opening portion 172 has a simple shape, which is conducive to reducing the difficulty of setting the second opening portion 172. The second opening portion 172 is located in the second sub-region 100a2 and the second polarity region 100b. The second opening portion 172 exposes part of the first sub-region 131. In this way, the second opening portion 172 can expose more first sub-regions 131. The reverse leakage current can be reduced by setting the second opening portion 172.

[0096] It should be noted that, in the embodiments of the present application, the second opening portion 172 and / or the insulating portion 180 can be set to prevent the leakage current from being too large. Figures 6-13 In some embodiments, the second doped semiconductor layer 122 can extend from the second sub-polarity region 100c2 to part of the first sub-polarity region 100c1. In the drawings, part of the second doped semiconductor layer 122 extending to the first sub-polarity region 100c1 is not shown.

[0097] Referring to Figure 11 In the embodiments in which the second opening portion 172, the first opening portion 171 and the insulating portion 180 are provided at the same time, the sum of the areas of the orthographic projections of all the insulating portions 180 located in the first polarity region 100a, the first opening portion 171 and the second opening portion 172 located in the first polarity region 100a on the semiconductor substrate 110 is a first value. The sum of the areas of the orthographic projections of all the insulating portions 180 located in the second polarity region 100b and the second opening portion 172 located in the second polarity region 100b on the semiconductor substrate 110 is a second value. The ratio of the second value to the first value can be in the range of 0.01-0.9. For example, the ratio of the second value to the first value can be 0.01, 0.1, 0.2, 0.4, 0.6, 0.8, 0.9 or any value in the range of 0.01-0.9.

[0098] Referring to Figure 6 and Figure 7 In the embodiments in which the second opening portion 172 is provided and the first opening portion 171 and the insulating portion 180 are not provided, the area of the orthographic projection of the second opening portion 172 located in the first polarity region 100a on the semiconductor substrate 110 is an eighth value. The area of the orthographic projection of the second opening portion 172 located in the second polarity region 100b on the semiconductor substrate 110 is a ninth value. The ratio of the ninth value to the eighth value is in the range of 0.01-0.9. For example, the ratio of the ninth value to the eighth value can be 0.01, 0.1, 0.2, 0.4, 0.6, 0.8, 0.9 or any value in the range of 0.01-0.9.

[0099] Referring toFigures 8-10 In the embodiment provided with the first opening part 171 and the insulating part 180 and without the second opening part 172, the sum of the areas of the orthographic projections of all the insulating parts 180 and the first opening part 171 on the semiconductor substrate 110 is a sixth value, the sum of the areas of the orthographic projections of all the insulating parts 180 on the semiconductor substrate 110 in the second polarity region 100b is a seventh value, and the ratio of the seventh value to the sixth value ranges from 0.01 to 0.9. For example, the ratio of the seventh value to the sixth value can be 0.01, 0.1, 0.2, 0.4, 0.6, 0.8, 0.9, or any value between 0.01 and 0.9.

[0100] In some embodiments, referring to Figure 3 and Figure 10 , the isolation opening 170 includes a third opening part 173, the first opening part 171 and the third opening part 173 are arranged along the extension direction of the boundary line E, and the third opening part 173 extends along the extension direction of the boundary line E. In this way, the third opening part 173 is in the shape of a strip, and the shape of the third opening part 173 is relatively simple. The third opening part 173 is located in the first polarity region 100a, for example, the third opening part 173 can be located in the second sub-region 100a2 of the first polarity region 100a, and the orthographic projection of the third opening part 173 on the semiconductor substrate 110 is spaced apart from the orthographic projection of the insulating part 180 on the semiconductor substrate 110 and does not overlap with the orthographic projection of the first sub-region 131 on the semiconductor substrate 110. In this way, the third opening part 173 cannot reduce the leakage current, and the leakage current of the solar cell 100 can be adjusted by adjusting the positions, distributions, and area ratios of the third opening part 173 and the insulating part 180 / second opening part 172.

[0101] Referring to Figure 10 , in the embodiment provided with the first opening part 171, the insulating part 180, and the third opening part 173 and without the second opening part 172, the sum of the areas of the orthographic projections of all the insulating parts 180 and the first opening part 171 on the semiconductor substrate 110 is a third value, the area of the orthographic projection of the third opening part 173 on the semiconductor substrate 110 is a fourth value, and the ratio of the fourth value to the third value ranges from 0 to 0.5. When the ratio of the fourth value to the third value is equal to 0, the third opening part 173 can not be provided. Figure 9 and Figure 10 For example, the ratio of the fourth value to the third value can be 0, 0.2, 0.4, 0.5, or any value between 0 and 0.5.

[0102] Referring to Figure 13In the embodiment in which the first opening portion 171, the second opening portion 172, the third opening portion 173, and the insulating portion 180 are provided, the first opening portion 171, the second opening portion 172, and the third opening portion 173 are arranged along the extension direction of the boundary line E, the sum of the areas of the orthogonal projections of all the insulating portions 180, the first opening portion 171, and the second opening portion 172 on the semiconductor substrate 110 is a fifth value, the area of the orthogonal projection of the third opening portion 173 on the semiconductor substrate 110 is a fourth value, and the ratio of the fourth value to the fifth value ranges from 0 to 0.9. When the ratio of the fourth value to the fifth value is equal to 0, the third opening portion 173 can not be provided. Figure 11 and Figure 12 For example, the ratio of the fourth value to the fifth value can be 0, 0.2, 0.4, 0.6, 0.8, 0.9, or any value between 0 and 0.9.

[0103] Referring to Figure 6 and Figure 7 In the embodiment in which the second opening portion 172 and the third opening portion 173 are provided and the first opening portion 171 and the insulating portion 180 are not provided, the size of the leakage current can be adjusted by adjusting the area ratio of the second opening portion 172. The area of the orthogonal projection of the second opening portion 172 on the semiconductor substrate 110 is a tenth value, the area of the orthogonal projection of the third opening portion 173 on the semiconductor substrate 110 is a fourth value, and the ratio of the fourth value to the tenth value ranges from 0.1 to 2. For example, the ratio of the fourth value to the tenth value can be 0.1, 0.2, 0.5, 1, 1.5, 2, or any value between 0.1 and 2.

[0104] Referring to Figure 1 and Figure 3 The solar cell 100 can have a first direction X, a second direction Y, and a third direction Z, and the first direction X, the second direction Y, and the third direction Z are all different. The first direction X, the second direction Y, and the third direction Z can be perpendicular to each other. For example, the third direction Z can be the thickness direction of the solar cell 100, and the first direction X and the second direction Y can be any two different directions perpendicular to the thickness direction of the solar cell 100. The first direction X can be the length direction of the solar cell 100, and the second direction Y can be the width direction of the solar cell 100. The length, width, and thickness in the embodiments of the present application are only for the convenience of description and do not mean any limitation on the size. For example, the width can be greater than, equal to, or less than the length. The directions of the solar cell 100 can be consistent with the directions of the film layers such as the semiconductor substrate 110.

[0105] In some embodiments, referring to Figure 1 and Figure 2, the first polarity region 100a includes at least one first sub-polarity region 100c1, the second polarity region 100b includes at least one second sub-polarity region 100c2, the first sub-polarity region 100c1 and the second sub-polarity region 100c2 are arranged alternately along the first direction X, the first sub-polarity region 100c1 is provided with a first sub-region 100a1 and a second sub-region 100a2, and the second sub-region 100a2 of the first sub-polarity region 100c1 is located between the first sub-region 100a1 of the first sub-polarity region 100c1 and the second sub-polarity region 100c2.

[0106] In some embodiments, referring to Figure 1 and Figure 2 , the first polarity region 100a includes a third sub-polarity region 100c3, and the third sub-polarity region 100c3 is connected to one end of each first sub-polarity region 100c1 along the second direction Y.

[0107] In some embodiments, referring to Figure 1 and Figure 2 , the first polarity region 100a includes a fourth sub-polarity region 100c4, and the fourth sub-polarity region 100c4 is connected to one end of each first sub-polarity region 100c1 along the second direction Y away from the third sub-polarity region 100c3, or the second polarity region 100b includes a fourth sub-polarity region 100c4, and the fourth sub-polarity region 100c4 is connected to one end of each second sub-polarity region 100c2 along the second direction Y away from the third sub-polarity region 100c3.

[0108] Referring to Figure 14 and Figure 15 , the first conductive part 141 includes at least one first sub-conductive part 1431, the second conductive part 142 includes at least one second sub-conductive part 1432, the first sub-conductive part 1431 and the second sub-conductive part 1432 are arranged alternately along the first direction X, the first sub-conductive part 1431 is located in the first sub-polarity region 100c1, and the second sub-conductive part 1432 is located in the second sub-polarity region 100c2. Figure 2 A disconnection gap 170 is arranged between adjacent first sub-conductive parts 1431 and second sub-conductive parts 1432.

[0109] In some embodiments, referring to Figure 14 and Figure 15 , the first conductive part 141 includes a third sub-conductive part 1433, and the third sub-conductive part 1433 is connected to one end of each first sub-conductive part 1431 along the second direction Y. The third sub-conductive part 1433 is located in the third sub-polarity region 100c3. Figure 2 In some embodiments, referring to Figure 14 and Figure 15The first conductive portion 141 includes a fourth sub-conductive portion 1434 connected to one end of each of the first sub-conductive portions 1431 away from the third sub-conductive portion 1433 along the second direction Y, or the second conductive portion 142 includes the fourth sub-conductive portion 1434 connected to one end of each of the second sub-conductive portions 1432 away from the third sub-conductive portion 1433 along the second direction Y. The fourth sub-conductive portion 1434 is located in a fourth sub-polarity region 100c4 (see FIG. 2) of the semiconductor substrate 110. Figure 2 ).

[0110] In some embodiments, referring to Figure 8 In the at least partially adjacent first sub-conductive portions 1431 and second sub-conductive portions 1432 and the isolation opening 170 between the adjacent first sub-conductive portions 1431 and second sub-conductive portions 1432, the isolation opening 170 is a first opening portion 171 extending along the second direction Y. The first opening portion 171 is provided corresponding to a plurality of insulating portions 180, a normal projection of the corresponding first opening portion 171 on the semiconductor substrate 110 is connected to a normal projection of the plurality of insulating portions 180 on the semiconductor substrate 110 on one side along the first direction X, and the plurality of insulating portions 180 are arranged at intervals along the second direction Y. For example, the number of first opening portions 171 can be at least one, and when there are a plurality of first opening portions 171, the plurality of first opening portions 171 can be arranged at intervals along the first direction X.

[0111] In some embodiments, referring to Figure 11 In the at least partially adjacent first sub-conductive portions 1431 and second sub-conductive portions 1432 and the isolation opening 170 between the adjacent first sub-conductive portions 1431 and second sub-conductive portions 1432, the isolation opening 170 is a second opening portion 172 extending along the second direction Y. For example, the number of second opening portions 172 can be at least one, and when there are a plurality of second opening portions 172, the plurality of second opening portions 172 can be arranged at intervals along the first direction X.

[0112] In some embodiments, referring to Figure 13 In the at least partially adjacent first sub-conductive portions 1431 and second sub-conductive portions 1432 and the isolation opening 170 between the adjacent first sub-conductive portions 1431 and second sub-conductive portions 1432, the isolation opening 170 is a third opening portion 173 extending along the second direction Y. For example, the number of third opening portions 173 can be at least one, and when there are a plurality of third opening portions 173, the plurality of third opening portions 173 can be arranged at intervals along the first direction X.

[0113] In some embodiments, referring to Figure 8 and Figure 9, the orthographic projection of the insulating part 180 on the semiconductor substrate 110 is a first orthographic projection, the orthographic projection of the first opening part 171 on the semiconductor substrate 110 is a second orthographic projection, in the connected first orthographic projection and second orthographic projection, the side of the first orthographic projection away from the second orthographic projection is an arc side (the arc side is convexly arranged towards the direction away from the center of the first orthographic projection) Figure 9 , or the side of the first orthographic projection away from the second orthographic projection is a straight side Figure 8 , wherein when the arc side is adopted, the arc side is more conducive to increasing the area of the insulating part 180, and the control effect of the single insulating part 180 on the leakage current can be improved, and when the straight side is adopted, the shape of the straight side is relatively simple, and the preparation difficulty of the insulating part 180 can be reduced.

[0114] Exemplarily, the insulating protrusion 180b can be prepared from an insulating material, and the material of the insulating protrusion 180b includes at least one of silicon dioxide, silicon nitride and silicon oxynitride.

[0115] The semiconductor substrate 110 provided by the embodiments of the present application is described below.

[0116] In some embodiments, the semiconductor substrate 110 can be a silicon substrate, and the material of the silicon substrate can include at least one of single crystal silicon and polycrystalline silicon. The embodiments of the present application are described by taking single crystal silicon as an example.

[0117] Exemplarily, the doping type of the semiconductor substrate 110 can be N-type doping, which can be realized by doping N-type ions, and the N-type ions can include at least one of phosphorus, arsenic and antimony. Alternatively, the doping type of the semiconductor substrate 110 is P-type doping, which can be realized by doping P-type ions, and the P-type ions can include at least one of aluminum and boron. The embodiments of the present application are described by taking the doping type of the semiconductor substrate 110 as N-type doping as an example.

[0118] In some embodiments, at least part of at least one of the first surface 111 and the second surface 112 can have a textured structure. The textured structure can be a pyramid textured structure, an etching pit textured structure, etc. The textured structure has a small reflectivity to incident light, so that the absorption and utilization rate of the incident light is large, and the photoelectric conversion efficiency of the solar cell 100 is high. In other embodiments, at least part of at least one of the first surface 111 and the second surface 112 can also not have a textured structure.

[0119] The first passivation layer 151 and the first doped semiconductor layer 121 provided by the embodiments of the present application are described below.

[0120] Referring to Figure 3In some embodiments, the solar cell 100 includes a first passivation layer 151 disposed on the first surface 111, the first passivation layer 151 is located in the first polarity region 100a, and the first passivation layer 151 is disposed between the first doped semiconductor layer 121 and the semiconductor substrate 110. The first passivation layer 151 can improve the photoelectric conversion efficiency by reducing the surface recombination rate, thereby improving the open circuit voltage and conversion efficiency of the solar cell 100. The first passivation layer 151 is in contact with the first surface 111 in the first polarity region 100a. The area where the first passivation layer 151 is in contact with the first surface 111 can define the first polarity region 100a.

[0121] For example, the material of the first doped semiconductor layer 121 includes doped polysilicon, doped amorphous silicon, or doped microcrystalline silicon. The doping type of the first doped semiconductor layer 121 is the same as or opposite to the doping type of the semiconductor substrate 110.

[0122] For example, the first passivation layer 151 can include tunneling oxide or intrinsic amorphous silicon.

[0123] For example, the first passivation layer 151 can include tunneling oxide, and the first doped semiconductor layer 121 can include doped polysilicon.

[0124] For example, the first passivation layer 151 can include intrinsic amorphous silicon, and the first doped semiconductor layer 121 can include a doped amorphous silicon layer or doped microcrystalline silicon.

[0125] The second passivation layer 152 and the second doped semiconductor layer 122 provided by the embodiments of the present application are described below.

[0126] The doping type of the second doped semiconductor layer 122 is opposite to the doping type of the first doped semiconductor layer 121. The doping type of one of the first doped semiconductor layer 121 and the second doped semiconductor layer 122 can be N-type doping, and the doping type of the other can be P-type doping.

[0127] In the embodiment in which part of the stack layer 130 extends to the second sub-region 100a2, the second passivation layer 152 and the second doped semiconductor layer 122 of the second sub-region 100a2 can be continuous along the first direction X, or the second passivation layer 152 and the second doped semiconductor layer of the second sub-region 100a2 are discontinuous along the first direction X, and the discontinuous area can be located below the isolation opening 170.

[0128] For example, the material of the second passivation layer 152 includes intrinsic amorphous silicon.

[0129] For example, the material of the second doped semiconductor layer 122 can include a doped amorphous silicon layer or doped microcrystalline silicon.

[0130] The conductive layer 140 provided by the embodiments of the present application is described below.

[0131] In some embodiments, the first conductive part 141 can be located in the first polarity region 100a and not extend to the second polarity region 100b. Part of the first conductive part 141 can cover the side of the second doped semiconductor layer 122 of the second sub-region 100a2 facing away from the semiconductor substrate 110.

[0132] In some embodiments, the second conductive part 142 can be located in the second polarity region 100b and part of the second conductive part 142 can extend to the second sub-region 100a2. In this way, by extending the second conductive part 142 from the second polarity region 100b to the second sub-region 100a2, the second conductive part 142 can have a larger setting area, which can increase the contact area between the second conductive part 142 and the second doped semiconductor layer 122, and is conducive to improving the conduction of the second conductive part 142 to the charge carriers and improving the efficiency of the solar cell 100.

[0133] For example, the material of the conductive layer 140 and the material of the semiconductor substrate 110 can include one or more of zinc oxide, indium oxide, and tin oxide. The doping elements in the conductive layer 140 include one or more of gallium (Ga), tin (Sn), titanium (Ti), zirconium (Zr), molybdenum (Mo), cerium (Ce), fluorine (F), tungsten (W), and aluminum (Al).

[0134] The first electrode 161 and the second electrode 162 provided by the embodiments of the present application are described below.

[0135] In some embodiments, referring to Figure 3 , the solar cell 100 includes the first electrode 161. The first electrode 161 is located on the side of the first conductive part 141 facing away from the semiconductor substrate 110. The first conductive part 141 is ohmically connected to the first electrode 161. The first electrode 161 can collect and transport charge carriers. The first electrode 161 can be located in the first polarity region 100a (e.g., the first sub-region 100a1).

[0136] In some embodiments, referring to Figure 3 , the solar cell 100 includes the second electrode 162. The second electrode 162 is located on the side of the second conductive part 142 facing away from the semiconductor substrate 110. The second conductive part 142 is ohmically connected to the second electrode 162. The second electrode 162 can collect and transport charge carriers. The second electrode 162 can be located in the second polarity region 100b. The first electrode 161 and the second electrode 162 can be spaced apart.

[0137] For example, the material of at least one of the first electrode 161 and the second electrode 162 includes a conductive metal such as silver, copper, tin, etc.

[0138] The following describes the film layer of the second surface 112 provided by the embodiments of the present application.

[0139] In some embodiments, referring to Figure 3 The solar cell 100 includes a third passivation layer 153, and the third passivation layer 153 is located on the second surface 112.

[0140] For example, the third passivation layer 153 includes one or more of intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped microcrystalline silicon or doped amorphous silicon, a composite layer of tunneling oxide and doped polycrystalline silicon, silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride.

[0141] In some embodiments, referring to Figure 3 The solar cell 100 includes an anti-reflection layer 154, and the anti-reflection layer 154 is located on the side of the third passivation layer 153 away from the semiconductor substrate 110.

[0142] For example, the anti-reflection layer 154 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium fluoride, and transparent conductive oxide.

[0143] The following describes a photovoltaic module provided by the embodiments of the present application.

[0144] The embodiments of the present application also provide a photovoltaic module, which can include the solar cell 100. The solar cell 100 in the photovoltaic module can be at least one. The embodiments of the present application take the solar cell 100 in the photovoltaic module as an example to describe the case of multiple solar cells 100, and the multiple solar cells 100 jointly constitute a cell string layer.

[0145] In some embodiments, the photovoltaic module can include a first encapsulant and a second encapsulant located on both sides of the cell string layer, and the first encapsulant and the second encapsulant encapsulate the cell string layer to protect the cell string layer. The first encapsulant and the second encapsulant can include an encapsulating adhesive layer and a cover plate, the encapsulating adhesive layer is located on the side of the cover plate facing the cell string layer, the cover plate can protect the cell string layer, and the encapsulating adhesive layer can be used to connect the cover plate and the cell string layer.

[0146] For example, the solar cell 100 can include a back contact (BC) cell, a heterojunction back contact (HBC) cell, a hybrid full passivated back contact (hybrid HBC) cell, an interdigitated back contact (IBC) cell, etc.

[0147] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, it is to be understood that the application embraces all such possible combinations.

[0148] The above-described embodiments only express several implementation manners of the application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that, for ordinary skilled persons in the art, some modifications and improvements can be made without departing from the concept of the application, and these all belong to the protection scope of the application. Therefore, the patent protection scope of the application should be subject to the appended claims.

Claims

1. A solar cell having a first polarity region and a second polarity region with opposite polarities, characterized in that, The solar cell includes: Semiconductor substrate, including a first surface; A first doped semiconductor layer is disposed on the first surface and located in the first polar region. The first doped semiconductor layer includes a first sidewall, which is connected between the two surfaces of the first doped semiconductor layer along the thickness direction of the semiconductor substrate. A stacked layer is disposed on the first surface and located in the second polarity region; the stacked layer includes a first portion covering the first sidewall; A conductive layer is disposed on the side of the first doped semiconductor layer and the stacked layer away from the semiconductor substrate. The conductive layer includes a first conductive portion and a second conductive portion disposed at intervals. An isolation opening is formed between the first conductive portion and the second conductive portion. The first conductive portion is located in the first polarity region, and the second conductive portion is at least located in the second polarity region. Multiple insulating portions are spaced apart on the side of the first sidewall facing the first portion, and all are in contact with the first portion; at least a portion of the orthographic projection of the isolation opening on the semiconductor substrate does not overlap with the orthographic projection of the first portion on the semiconductor substrate, and is connected to the orthographic projection of the multiple insulating portions on the semiconductor substrate.

2. The solar cell according to claim 1, characterized in that, The insulating portion is located on the side of the first portion away from the first sidewall.

3. The solar cell according to claim 1, characterized in that, The insulating portion is configured as an insulating opening, which is disposed on the conductive layer and penetrates the conductive layer along the thickness direction of the semiconductor substrate. The insulating opening communicates with the isolation opening.

4. The solar cell according to claim 1, characterized in that, The insulating portion is configured as an insulating protrusion.

5. The solar cell according to any one of claims 1-4, characterized in that, The isolation opening extends along the extension direction of the boundary line between the first polar region and the second polar region. The first polar region includes a first sub-region and a second sub-region. The second sub-region is located between the first sub-region and the second polar region. The stacked layer includes a second portion connected to the first portion. The second portion is disposed in the second sub-region and is located on the side of the first doped semiconductor layer away from the semiconductor substrate. The isolation opening includes a first opening located in the second sub-region. The orthographic projection of the first opening on the semiconductor substrate is connected to the orthographic projection of the plurality of insulating portions on the semiconductor substrate.

6. The solar cell according to claim 5, characterized in that, The insulating portion includes a first sub-insulating portion and a second sub-insulating portion connected together, the first sub-insulating portion being in contact with the first portion, and the second sub-insulating portion being in contact with the second portion.

7. The solar cell according to claim 6, characterized in that, In the same insulating portion, the dimension of the first sub-insulating portion along the extension direction of the boundary line is greater than the dimension of the remaining portion of the insulating portion along the extension direction of the boundary line.

8. The solar cell according to claim 5, characterized in that, The stacked layer includes a third portion, which is connected to the side of the first portion away from the second portion and is disposed on the first surface of the second polarity region; In the same insulating portion, the insulating portion includes a first sub-insulating portion and a third sub-insulating portion connected together, the first sub-insulating portion being in contact with the first sub-part, and the third sub-insulating portion being in contact with the third sub-part.

9. The solar cell according to claim 8, characterized in that, The dimension of the third sub-insulating portion along the extension direction of the boundary line gradually decreases from the first sub-insulating portion to the third sub-insulating portion.

10. The solar cell according to claim 5, characterized in that, The isolation opening includes a second opening, the first opening and the second opening are arranged along the extension direction of the boundary line, the second opening is located in the second sub-region and the second polarity region, and the second opening exposes a portion of the first portion.

11. The solar cell according to claim 10, characterized in that, The sum of the areas of the orthographic projections of all the insulating portions, the first opening, and the second opening located in the first polarity region onto the semiconductor substrate is a first value; the sum of the areas of the orthographic projections of all the insulating portions and the second opening located in the second polarity region onto the semiconductor substrate is a second value; and the ratio of the second value to the first value is in the range of 0.01-0.

9.

12. The solar cell according to claim 5, characterized in that, The isolation opening includes a third opening, the first opening and the third opening are arranged along the extension direction of the boundary line, the third opening is located in the second sub-region, and the orthogonal projection of the third opening on the semiconductor substrate is spaced apart from the orthogonal projection of the insulating portion on the semiconductor substrate.

13. The solar cell according to claim 12, characterized in that, The sum of the areas of the orthographic projections of all the insulating portions and the first opening portion onto the semiconductor substrate is a third value, and the area of ​​the orthographic projection of the third opening portion onto the semiconductor substrate is a fourth value. The ratio of the fourth value to the third value is in the range of 0-0.

5.

14. The solar cell according to claim 5, characterized in that, The isolation opening includes a second opening and a third opening. The first opening, the second opening, and the third opening are arranged along the extension direction of the boundary line. The second opening is located in the second sub-region and the second polar region. The second opening exposes a portion of the first portion. The third opening is located in the second sub-region. The orthographic projection of the third opening on the semiconductor substrate is spaced apart from the orthographic projection of the insulating portion on the semiconductor substrate. The sum of the areas of the orthographic projections of all the insulating portions, the first opening, and the second opening on the semiconductor substrate is a fifth value, the area of ​​the orthographic projection of the third opening on the semiconductor substrate is a fourth value, and the ratio of the fourth value to the fifth value is in the range of 0-0.

9.

15. The solar cell according to claim 5, characterized in that, The first polarity region includes at least one first sub-polarity region, and the second polarity region includes at least one second sub-polarity region. The first sub-polarity region and the second sub-polarity region are arranged alternately along a first direction. The first sub-polarity region is provided with a first sub-region and a second sub-region. The second sub-region of the first sub-polarity region is located between the first sub-region and the second sub-polarity region of the first sub-polarity region. The first conductive portion includes at least one first sub-conductive portion, the second conductive portion includes at least one second sub-conductive portion, the first sub-conductive portion is located in the first sub-polarity region, the second sub-conductive portion is located in the second sub-polarity region, and the isolation opening is provided between adjacent first sub-conductive portions and second sub-conductive portions, and the first direction intersects with the thickness direction of the semiconductor substrate.

16. The solar cell according to claim 15, characterized in that, In at least partially adjacent first sub-conductive portions and second sub-conductive portions, and in the isolation opening located between the adjacent first sub-conductive portions and second sub-conductive portions, the isolation opening is the first opening, the first opening extends along a second direction, the first opening is correspondingly disposed with a plurality of insulating portions, the orthographic projection of the plurality of insulating portions on the semiconductor substrate is connected to one side of the orthographic projection of the first opening on the semiconductor substrate along the first direction, and the plurality of insulating portions are spaced apart along the second direction, and any two of the first direction, the second direction and the thickness direction of the semiconductor substrate intersect.

17. The solar cell according to claim 15, characterized in that, In at least partially adjacent first and second sub-conductive portions, and in the isolation opening located between the adjacent first and second sub-conductive portions, the isolation opening is a second opening extending along a second direction, wherein any two of the first direction, the second direction, and the thickness direction of the semiconductor substrate intersect.

18. The solar cell according to claim 15, characterized in that, In at least partially adjacent first and second sub-conductive portions, and in the isolation opening located between the adjacent first and second sub-conductive portions, the isolation opening is a third opening extending along a second direction, wherein any two of the first direction, the second direction, and the thickness direction of the semiconductor substrate intersect.

19. The solar cell according to claim 5, characterized in that, The sum of the areas of the orthographic projections of all the insulating portions and the first opening located in the first polarity region onto the semiconductor substrate is a sixth value, and the sum of the areas of the orthographic projections of all the insulating portions located in the second polarity region onto the semiconductor substrate is a seventh value. The ratio of the seventh value to the sixth value ranges from 0.01 to 0.

9.

20. The solar cell according to claim 5, characterized in that, The orthographic projection of the insulating portion on the semiconductor substrate is a first orthographic projection, and the orthographic projection of the first opening portion on the semiconductor substrate is a second orthographic projection. In the connected first orthographic projection and second orthographic projection, the side of the first orthographic projection away from the second orthographic projection is an arc edge, and the arc edge protrudes in a direction away from the center of the first orthographic projection.

21. The solar cell according to any one of claims 1-4, characterized in that, The solar cell includes a first passivation layer disposed in the first polar region and located between the first surface and the first doped semiconductor layer; and / or, The stacked layer includes a second passivation layer and a second doped semiconductor layer stacked along a direction away from the semiconductor substrate.

22. A photovoltaic module, characterized in that, Includes the solar cell described in any one of claims 1-21.

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