Manufacturing method of semiconductor device
By depositing an impurity-doped dielectric layer and performing heat treatment to form a shallow doped region in the manufacture of CMOS image sensors, the cost and process complexity issues of adding photolithography and ion implantation steps in the traditional method are solved, achieving low-cost, efficient white pixel suppression and improved imaging quality.
Patent Information
- Application Number
- CN202510779483.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-11
- Publication Date
- 2025-10-17
AI Technical Summary
In the existing CMOS image sensor manufacturing process, the formation of a shallow P-type doped region (Pin layer) requires the addition of special lithography and ion implantation steps, resulting in high costs, difficulty in controlling the process window, strict equipment limitations, and the possibility of introducing lattice damage.
After forming the photodiode region and gate structure on the semiconductor substrate, a doped dielectric layer containing predetermined doping elements is deposited and then diffused to the surface by heat treatment to form a shallow doping region, eliminating the need for special photolithography and ion implantation steps.
Simplify the process flow, reduce manufacturing costs, form a more uniform Pin layer coverage, effectively suppress white pixels, improve imaging quality, keep the photoelectric conversion characteristics unaffected, and have good process compatibility.
Smart Images
Figure CN120813076A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, and in particular to a manufacturing method of a semiconductor device. BACKGROUND
[0002] With the rapid development of semiconductor technology, the integration and performance of integrated circuits continue to improve according to Moore's Law. Among them, CMOS image sensors (CIS) as a kind of key semiconductor device, in the field of computer vision, mobile communication, security monitoring, medical imaging and consumer electronics have been widely used, and the market demand for the performance of CIS is also increasing.
[0003] Among the many performance parameters of CIS, white pixel (WP) is a key indicator that affects image quality. White pixel usually refers to a pixel point whose output signal (for example, represented by digital signal DN value) is significantly higher than the average output value of its surrounding pixels under dark field conditions. For example, sometimes in the industry, the pixel whose DN value under dark field is 50 DN higher than the average value of the surrounding pixels is defined as white pixel. The existence of white pixel will seriously reduce the dynamic range and signal-to-noise ratio of the image sensor, affecting the imaging quality.
[0004] Studies have shown that one of the main causes of white pixels is the defects existing in the semiconductor material (such as silicon substrate) or the interface with the surface dielectric layer (such as silicon oxide, OX), such as metal ion contamination or lattice defects. These defects can form deep level traps or generate recombination centers in the semiconductor band gap, which greatly increases the probability of electron-hole pair generation under dark field (i.e. dark current), or reduces the collection efficiency of photo-generated carriers under light, which macroscopically shows abnormally high dark signal output, that is, white pixel is formed. In particular, the surface state or defect at the silicon (Si) / silicon oxide (OX) interface contributes significantly to the dark current.
[0005] In order to suppress white pixels caused by Si / OX interface defects, the prior art usually introduces a very shallow P-type doping layer (i.e. P layer in Pin structure, or called surface P-type pinning layer) between the active region (usually N-type photosensitive region) of photodiode (PD) and Si / OX interface. This shallow P-type doping region can effectively isolate the N-type photosensitive region from the Si / OX interface that generates dark current, reduce the influence of surface defects on device performance, and effectively suppress the generation of white pixels.
[0006] In the conventional CMOS image sensor manufacturing process, forming such a shallow P-type doped region (Pin layer) usually requires a dedicated photolithography (PH) and ion implantation (IMP) step. Specifically, the implantation area is defined by a photolithography process, and then P-type dopants (such as boron ions) are implanted into the extremely shallow surface layer of the substrate using an ion implanter. However, this traditional method has some shortcomings:
[0007] 1. High cost: The addition of a dedicated photolithography and ion implantation step means that additional processes such as photo mask, photoresist coating / development / etching, ion implantation, etc. are required, which undoubtedly increases the complexity of the process flow and manufacturing cost.
[0008] 2. Process window control: Ion implantation to achieve an extremely shallow and precisely controlled doping concentration distribution requires high equipment capability and process control, especially at advanced process nodes. Ion implantation may introduce additional lattice damage, which needs to be repaired by subsequent annealing.
[0009] 3. Equipment limitations: The energy, dose, and angle control capabilities of ion implantation equipment may limit the optimization potential of Pin layer depth and doping distribution.
[0010] Therefore, in the continuous pursuit of higher performance and lower cost of CIS product development, the industry urgently needs a new Pin shallow layer technology solution that can effectively suppress white pixels while simplifying the process flow and reducing manufacturing costs. SUMMARY
[0011] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a semiconductor device manufacturing method for solving the problem that in the prior art CMOS image sensor manufacturing process, forming such a shallow P-type doped region (Pin layer) usually requires a dedicated photolithography and ion implantation step, and this traditional method has some shortcomings.
[0012] To achieve the above-mentioned purposes and other related purposes, the present application provides a semiconductor device manufacturing method, comprising:
[0013] Step one, forming a photodiode region and a gate structure on a semiconductor substrate;
[0014] Step two, forming a sidewall structure on the sidewall of the gate structure;
[0015] Step three, forming a source / drain region in the semiconductor substrate;
[0016] Step four, depositing a doped dielectric layer containing a predetermined doping element on the semiconductor substrate; and
[0017] Step five, performing a heat treatment on the semiconductor substrate to diffuse the predetermined dopant element in the doped dielectric layer to the surface region of the semiconductor substrate, thereby forming a shallow doped region on the surface of the photodiode region.
[0018] Preferably, the semiconductor device is a CMOS image sensor.
[0019] Preferably, in step four, the depositing step specifically comprises depositing a self-aligned doped silicon oxide layer as the doped dielectric layer.
[0020] Preferably, in step four, the predetermined dopant element is boron.
[0021] Preferably, in step five, the shallow doped region formed is a shallow P-type doped region.
[0022] Preferably, in step five, the shallow P-type doped region formed has a dopant dose of 2 to 7E11 atoms / cm 2 order of magnitude.
[0023] Preferably, in step five, the heat treatment comprises a rapid thermal annealing process.
[0024] Preferably, in step four, the doped dielectric layer is one or a combination of oxide, silicon nitride or polysilicon.
[0025] Preferably, in step four, the depositing employs one of chemical vapor deposition, atomic layer deposition or furnace tube deposition process.
[0026] Preferably, the method does not perform additional photolithography and ion implantation steps for forming the shallow doped region after step two and before step four.
[0027] As described above, the method for manufacturing a semiconductor device of the present application has the following beneficial effects:
[0028] By omitting the dedicated Pin photolithography and ion implantation steps, the process flow is simplified, equipment usage time and material consumption are reduced, and manufacturing cost is directly lowered; the Pin layer formed by thermal diffusion can more uniformly and conformally cover on the Si / OX interface, and can have better interface coverage effect than the Pin layer formed by ion implantation which is limited by implantation energy and angle; the method of the present application can be conveniently integrated into existing CMOS (especially CIS) process flow, for example by replacing a certain existing dielectric layer with a doped dielectric layer, without substantially modifying the process flow or adding additional complex modules, and is fully compatible with the conventional process; by optimizing the doping concentration of the doped dielectric layer and the subsequent heat treatment conditions, the dose of the Pin layer formed can be precisely controlled (such as controlled at 5E11 atoms / cm 2The magnitude and the depth of the doping ensure that the photoelectric conversion characteristics of the photodiode are not adversely affected while effectively suppressing white pixels. BRIEF DESCRIPTION OF DRAWINGS
[0029] Figure 1 A process flow of the present application is shown in the figure;
[0030] Figure 2 A process flow of the present application is shown in the figure;
[0031] Figure 3 A process flow of the present application is shown in the figure; DETAILED DESCRIPTION
[0032] The present application will be described in greater detail by way of specific embodiments, and as such, those skilled in the art can easily understand other advantages and purposes of the present application from the description disclosed herein. The present application can also be implemented or applied in other different embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application.
[0033] Referring to Figure 1 , the present application provides a method for manufacturing a semiconductor device, comprising the following steps:
[0034] Step one, forming a photodiode region 102 and a gate structure on a semiconductor substrate 101. This step is a conventional step in the manufacture of CMOS image sensors and other semiconductor devices, and is used to define the active area and control gate of the device.
[0035] Step two, forming a sidewall structure on the sidewall of the gate structure. The sidewall structure is usually used for subsequent source / drain implantation or other self-aligned processes.
[0036] Step three, forming a source / drain region in the semiconductor substrate 101. The source and drain regions are formed on both sides of the gate structure by ion implantation or other methods.
[0037] Step four, depositing a doped dielectric layer 103 containing a predetermined doping element on the semiconductor substrate 101, forming a structure as shown in Figure 2 .
[0038] In some embodiments, in step four, the deposition step specifically includes: depositing a self-aligned boron-doped silicon oxide (SABDoping OX) layer as the doped dielectric layer 103. Depositing a boron-doped silicon oxide layer using the SAB process can achieve self-aligned deposition of the doping element source, simplify subsequent processing, and the layer can cover the device surface including the photodiode region 102.
[0039] In some embodiments, the method does not perform additional photolithography (PH) and ion implantation (IMP) steps for forming the shallow doped region 104 after step ii and before step iv. This is a key feature of the present application, by omitting the conventional Pin lithography and ion implantation steps, the process flow is significantly simplified. Compared with the conventional process which requires a dedicated Pin lithography and implantation, the method of the present application reduces one lithography and ion implantation procedure, thus directly reduces the manufacturing cost and improves the production efficiency.
[0040] In some embodiments, step iv is performed after step iii. Arranging the deposition of the doped dielectric layer 103 after the source / drain region formation ensures that the doped dielectric layer 103 covers the formed device structure and diffuses the dopant to the desired surface area of the substrate 101 through subsequent thermal treatment, while avoiding the impact of the deposition step on the previous source / drain region formation process, ensuring the compatibility of the process flow.
[0041] In some embodiments, in step iv, the predetermined dopant element is boron (B). Boron as a P-type dopant is suitable for forming a P-type pinning layer (i.e. Pin layer) on the surface of the N-type light-sensing region (part of the photodiode region 102). Of course, other suitable P-type dopant elements can also be selected as the predetermined dopant element according to the specific device design requirements, such as BF2, etc.
[0042] In some embodiments, in step iv, the doped dielectric layer 103 is one or a combination of oxide (OX), silicon nitride (SiN) or polysilicon (Poly). This means that the doping source is not limited to doped silicon oxide (such as SAB B Doping OX), but can also be doped silicon nitride, doped polysilicon, or a stack structure thereof. Selecting different dielectric materials can adjust the source of the dopant element and the subsequent diffusion behavior, increasing the flexibility of process design. For example, a boron-doped silicon oxide layer, a boron-doped silicon nitride layer or a boron-doped polysilicon layer can be used as the doped dielectric layer 103.
[0043] In some embodiments, in step iv, the deposition uses one of chemical vapor deposition (CVD), atomic layer deposition (ALD) or furnace deposition process. These are all mature thin film deposition techniques in semiconductor manufacturing. For example, a boron-doped silicon oxide layer can be deposited using a CVD method (such as atmospheric pressure CVD, low pressure CVD, plasma enhanced CVD, etc.), or an ALD method can be used to precisely control the thickness and composition of the doped dielectric layer 103, or a furnace diffusion process can be used to simultaneously deposit and dope (such as a furnace process using a boron-containing source gas). The choice of deposition method can be determined according to cost, required film quality (such as uniformity, conformality), and integration with other process steps.
[0044] Step five, heat-treating the semiconductor substrate 101 to diffuse the predetermined dopant element in the doped dielectric layer 103 to the surface region of the semiconductor substrate 101, thereby forming a shallow doped region 104 at the surface of the photodiode region 102, forming a structure as shown in Figure 3
[0045] In some embodiments, in step five, the shallow doped region 104 formed is a shallow P-type doped region (Pin). This shallow P-type doped region formed by diffusion is located at the interface between the N-type photo-sensing region of the photodiode and the overlying dielectric layer (typically silicon oxide). Its role is to effectively isolate the N-type photo-sensing region from the defects and interface states present at the semiconductor surface (Si / OX interface), which are one of the main causes of dark current and white pixels (WP). By forming a Pin layer, the surface recombination probability can be significantly reduced, blocking the dark current path caused by surface defects, thereby effectively suppressing the generation of white pixels, improving the imaging quality of the CMOS image sensor, especially in dark light environments.
[0046] In some embodiments, in step five, the shallow P-type doped region formed has a dopant dose in the order of 2 to 7E11 atoms / cm 2 The inventors have found through experiments and simulations that using a Pin layer with this dose level (5E11 atoms / cm 2 order) can effectively suppress white pixels and enhance the ability to block surface defects while having no significant negative impact on other key performance parameters of the device itself (such as the quantum efficiency of the photodiode, full well capacity, dynamic range, etc.). This indicates that the present method can achieve a good balance between improving white pixel performance and maintaining overall device performance.
[0047] In some embodiments, in step five, the heat treatment includes a rapid thermal anneal (RTA) process. RTA has the characteristics of fast temperature rise rate, short processing time, and low thermal budget, making it very suitable for shallow junction formation. By precisely controlling the temperature and time of RTA, the boron element in the doped dielectric layer 103 (such as SAB B Doping OX) can be effectively driven out and diffused to the extremely shallow surface region of the underlying silicon substrate 101 (for example, forming a Pin layer with a depth in the range of tens of nanometers or shallower), while limiting excessive longitudinal and lateral diffusion of the dopant into the substrate 101, thereby forming a steep and shallow doping distribution. Of course, other heat treatment methods that can achieve the diffusion of dopants from the dielectric layer to the surface of the substrate 101 can also be used, such as traditional furnace anneal (Furnace Anneal), but the annealing conditions need to be carefully optimized to control the diffusion depth and thermal budget.
[0048] In some embodiments, the semiconductor device is a CMOS image sensor (CIS). The method of the present application is particularly suitable for the fabrication of CMOS image sensor chips with stringent white pixel requirements, and can effectively improve product performance and yield.
[0049] Further, the method of the present application is highly process compatible. The deposition step of the doped dielectric layer 103 can be easily integrated into existing CMOS process flow. For example, replacing SAB OX (self-aligned blocking oxide) with SAB B Doping OX (self-aligned boron-doped oxide) is a specific example, which shows that the method of the present application can be achieved by replacing one thin film layer in the original process module (e.g. SAB Loop) without changing the main structure of the original process module. More generally, the formation of the doped dielectric layer 103 is not limited to SAB Loop, but can also be in any other suitable process loop (Loop), as long as the deposited doped dielectric layer can directly or indirectly contact the surface of the target pixel area (photodiode area 102), and the doped element can be diffused to the surface of the substrate 101 by a subsequent heat treatment step to form the desired Pin layer.
[0050] In summary, the present application provides an innovative and low-cost Pin shallowing process. Compared with the conventional method of forming Pin layer by additional lithography and ion implantation, the method of the present application forms Pin layer by depositing a doped dielectric layer (e.g. boron-doped silicon oxide) in the standard process flow, and then diffusing the dopant to the surface of the substrate 101 by heat treatment, which has the following outstanding advantages:
[0051] 1. Significant cost reduction: By eliminating the dedicated Pin lithography and ion implantation steps, the process flow is simplified, the equipment usage time and material consumption are reduced, and the manufacturing cost is directly reduced.
[0052] 2. Enhanced defect blocking capability: The Pin layer formed by thermal diffusion can more uniformly and conformally cover the Si / OX interface, and can have better interface coverage than the Pin layer formed by ion implantation limited by implantation energy and angle. This helps to more effectively block surface defects from the Si / OX interface, and thus can obtain stronger white pixel suppression capability than the conventional method. In theory, the diffusion-formed junction can better "pin" the surface potential.
[0053] 3. Good process compatibility: The method of the present application can be easily integrated into existing CMOS (especially CIS) process flow, for example by replacing a certain existing dielectric layer with the doped dielectric layer 103, without significantly changing the process flow or adding additional complex modules, and is fully compatible with the conventional process.
[0054] 4. Little impact on device performance: By optimizing the doping concentration of the doped dielectric layer 103 and the subsequent thermal treatment conditions, the dose (e.g. controlled at the order of 5E11 atoms / cm 2 ) and the junction depth of the formed Pin layer can be precisely controlled, ensuring that the photoelectric conversion characteristics of the photodiode and other key performance indicators are not significantly adversely affected while effectively suppressing white pixels.
[0055] In summary, the present application effectively overcomes the shortcomings of the prior art and has a high industrial utilization value.
[0056] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and only show the components related to the present application in the diagrams, rather than being drawn according to the number, shape and size of the components when actually implemented. The actual implementation of each component can be arbitrarily changed in terms of type, number and proportion, and the component layout pattern can be more complex.
[0057] The above embodiments only illustratively explain the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: At least: Step 1: forming a photodiode region and a gate structure on a semiconductor substrate; Step 2: forming a sidewall structure on the sidewall of the gate structure; Step 3: forming source / drain regions in the semiconductor substrate; Step 4: depositing a doping medium layer containing a predetermined doping element on the semiconductor substrate; and Step 5: performing heat treatment on the semiconductor substrate to diffuse the predetermined doping element in the doping medium layer to the surface area of the semiconductor substrate, thereby forming a shallow doping region on the surface of the photodiode region.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The semiconductor device is a CMOS image sensor.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: In step 4, the deposition step specifically includes: depositing a self-aligned doped silicon oxide layer as the doped medium layer.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: In step 4, the predetermined doping element is boron.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: In step five, the shallow doped region formed is a shallow P-type doped region.
6. The method for manufacturing a semiconductor device according to claim 1, wherein: In step 5, the doping dose of the shallow P-type doping region is 2 to 7E11 atoms / cm 2 Magnitude.
7. The method for manufacturing a semiconductor device according to claim 1, wherein: In step five, the heat treatment includes rapid thermal annealing.
8. The method for manufacturing a semiconductor device according to claim 1, wherein: In step 4, the doped dielectric layer is a combination of one or more of oxide, silicon nitride, and polysilicon.
9. The method for manufacturing a semiconductor device according to claim 1, wherein: In step 4, the deposition is carried out by one of chemical vapor deposition, atomic layer deposition or furnace deposition processes.
10. The method for manufacturing a semiconductor device according to claim 1, wherein: The method does not perform additional photolithography and ion implantation steps for forming the shallow doped region after step 2 and before step 4.