Solar cell and photovoltaic module

Abstract

The invention provides a solar cell and a photovoltaic module, and belongs to the technical field of semiconductors. The solar cell comprises a silicon substrate, and the surface of the silicon substrate comprises a plurality of first recessed areas which respectively extend in a first direction to form a strip shape and are distributed at intervals in a second direction intersecting with the first direction; and a plurality of first convex areas, and the first convex areas are adjacent to the first concave areas. The first concave area and the first convex area on the surface of the silicon substrate form the first texture structure, so that the light trapping effect is ensured, and meanwhile, due to the lack of a corner angle structure of a traditional tower footing structure, a film layer can be uniformly deposited on the silicon substrate, and the quality of the deposited film layer is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular, the present application relates to a solar cell and a photovoltaic module. BACKGROUND

[0002] In the process of producing a solar cell, it is usually necessary to perform alkali etching on a silicon substrate to obtain a polished surface with a traditional tower base structure. The morphology of the polished surface affects the quality of the film deposited thereon, thereby affecting the passivation effect, and also affects the light trapping effect, thereby affecting the light utilization rate of the solar cell. Therefore, the polished surface of the silicon substrate has an important influence on the efficiency of the solar cell. SUMMARY

[0003] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, the present application provides a solar cell and a photovoltaic module.

[0004] In order to achieve the above-mentioned purpose, the technical scheme of the present application is as follows:

[0005] According to an embodiment of the present application, a solar cell is provided, comprising: a silicon substrate, wherein the silicon substrate comprises two opposite surfaces, at least one surface having a first texture structure, the first texture structure comprising: a plurality of first recessed regions; and a plurality of first protruding regions, the first protruding regions being adjacent to the first recessed regions.

[0006] According to an embodiment of the present application, each of the first recessed regions extends in a first direction in a strip shape, and the plurality of first recessed regions are spaced apart in a second direction intersecting the first direction.

[0007] According to an embodiment of the present application, the first recessed region has a protruding portion extending in the second direction, and the first recessed region is divided into a multi-segment structure by the protruding portion.

[0008] According to an embodiment of the present application, the multi-segment structure is at least one of a bamboo joint shape and a skewer shape; and / or, a projection of the protruding portion on the first recessed region is at least one of a cross shape, a straight line shape and a curved line shape.

[0009] According to an embodiment of the present application, the height of the protruding portion is lower than the height of the first protruding region adjacent to the protruding portion.

[0010] According to embodiments of the present application, at least part of the first recessed regions has first pits distributed in a dot shape along the first direction; and / or, at least part of the plurality of first recessed regions has at least one second pit, the second pit has a morphology of one or more combinations of a cross shape, a line shape, and a groove shape; and / or, a cross-sectional shape of the first recessed region has one or more combinations of a V shape, an arc shape, a rectangular shape, and a trapezoidal shape; and / or, a position where the first recessed region and the first protruding region are connected has third pits discontinuously distributed along the first direction, and adjacent third pits have protrusions therebetween.

[0011] According to embodiments of the present application, the number of first pits in one first recessed region is 1-30; and / or, the number of second pits is less than the number of first pits.

[0012] According to embodiments of the present application, the spacing between adjacent first protruding regions in the second direction is 1-10 μm, and the depth of the first recessed region is 0.2-2 μm; and / or, the spacing between two adjacent first recessed regions is 2-10 μm; and / or, within a width range of 100 μm along the second direction, the number of first recessed regions is 3-20.

[0013] According to embodiments of the present application, the surface of the silicon substrate further comprises at least one crack randomly distributed on the surface of the silicon substrate.

[0014] According to embodiments of the present application, the projection of the first protruding region in the extension direction of the surface of the silicon substrate has at least one of a straight line shape, a broken line shape, a curve shape, a sugar-cane shape, and a dot shape.

[0015] According to embodiments of the present application, the surface of the silicon substrate further comprises a second texture structure, the second texture structure comprises a second recessed region, the second recessed region comprises a plurality of sub-recessed structures, and the plurality of sub-recessed structures are distributed in a non-linear shape; wherein the depth of the second recessed region is less than the depth of the first recessed region.

[0016] According to embodiments of the present application, the first texture structure further comprises a first side wall located between the first recessed region and the first protruding region; the first side wall has a wrinkle part.

[0017] According to embodiments of the present application, the wrinkle part comprises a plurality of layered structures protruding from the first side wall, the plurality of layered structures are stacked in a linear lateral texture along the thickness direction of the silicon substrate; and / or, the wrinkle part comprises a plurality of dot-shaped protrusions, the plurality of dot-shaped protrusions are stacked into a scale-shaped protrusion structure on the first side wall; and / or, the first side wall further comprises a plurality of steps stacked into a ladder-shaped structure along the thickness direction of the silicon substrate.

[0018] According to embodiments of the present application, the extension length of the layered structure along the surface direction of the silicon substrate is greater than the thickness of the layered structure; and / or, the height of the scale-shaped protrusion structure protruding away from the first side wall is 0.1-1 μm.

[0019] According to the embodiments of the present application, the first texture structure further comprises: a ramp adjacent to the first sidewall, the surface of the ramp has a hill stripe, and the hill stripe is intersected or offset with the linear transverse texture.

[0020] According to the embodiments of the present application, the slope angle of the first sidewall is greater than the slope angle of the surface of the ramp; and / or, the slope angle of the first sidewall is greater than or equal to 25° and less than or equal to 75°, and the slope angle of the surface of the ramp is less than 25° and greater than 2°.

[0021] According to the embodiments of the present application, the first recessed area or the first protruding area is in an island shape, and the first sidewall extends in a ring shape or a C shape.

[0022] According to the embodiments of the present application, the first sidewall further comprises: a first sidewall bifurcation structure comprising a first sub-sidewall extending into the first recessed area; and / or, the first sidewall further comprises: a second sidewall bifurcation structure comprising a second sub-sidewall extending into the first protruding area.

[0023] According to the embodiments of the present application, the first sub-sidewall and / or the second sub-sidewall respectively has a plurality of dot-shaped protrusions, a plurality of layered structures and / or a plurality of steps.

[0024] According to the embodiments of the present application, one side of the first recessed area is adjacent to one first sidewall, and the other side can be adjacent to another first sidewall or a ramp.

[0025] According to the embodiments of the present application, the surface of the silicon substrate further comprises a second texture structure; the flatness of the second texture structure is greater than the flatness of the first sidewall and less than the flatness of the first recessed area.

[0026] According to the embodiments of the present application, at least part of the first texture structure and / or the second texture structure has a ramp, the surface of the ramp has a sub-structure with an arc-shaped contour or a polygonal contour, the sub-structure has a plurality of second recessed areas, and the second recessed areas are overlapped to form a second protruding area.

[0027] According to the embodiments of the present application, the area with the sub-structure with the arc-shaped contour accounts for 3-40% of the width or area of the surface of the silicon substrate.

[0028] According to the embodiments of the present application, at least part of the second protruding area has a protruding end protruding outwardly from the silicon substrate, and the surface of the protruding end is a smooth transition surface.

[0029] According to an embodiment of the present application, the first sidewall extends along a first direction, and the extension length along the first direction is greater than or equal to 2 μm and less than or equal to 300 μm; and / or, along a second direction intersecting the first direction, the width of the first sidewall is 0.5-3 μm, and the depth along the thickness direction of the silicon substrate is 0.1-10 μm; and / or, within a width range of 100 μm along the second direction, the number of the first sidewalls is 1-200; and / or, the uniformity of the film layer on the silicon substrate is less than 10%, and the film layer comprises a doped conductive layer and / or a passivation or anti-reflection layer.

[0030] According to an embodiment of the present application, the solar cell further comprises a plurality of electrodes on the surface of the silicon substrate, each of the electrodes extending along a same or substantially same direction as the first direction and being spaced apart along the second direction; wherein along the second direction, one electrode covers 1-20 first recessed regions.

[0031] According to an embodiment of the present application, the solar cell further comprises a laminated film arranged on at least one side of the silicon substrate; the laminated film comprises a doped conductive layer extending along the first direction and being spaced apart along the second direction, and the first texture structure is on the surface of the silicon substrate corresponding to the doped conductive layer; and a passivation or anti-reflection layer on the surface of the doped conductive layer away from the silicon substrate; wherein along the second direction, the number of the first recessed regions on one doped conductive layer is 10-100.

[0032] According to an embodiment of the present application, the doped conductive layer comprises N-type doped conductive layers and P-type doped conductive layers arranged alternately on one side of the silicon substrate; wherein the first recessed regions in the first texture structure corresponding to the P-type doped conductive layer are more sparse than the first recessed regions in the first texture structure corresponding to the N-type doped conductive layer; and / or, the roughness of the first sidewall in the first texture structure corresponding to the N-type doped conductive layer is greater than the roughness of the first sidewall in the first texture structure corresponding to the P-type doped conductive layer; and / or, the number of the first sidewalls in the first texture structure corresponding to the P-type doped conductive layer is less than the number of the first sidewalls in the first texture structure corresponding to the N-type doped conductive layer.

[0033] According to an embodiment of the present application, the doped conductive layer is a first doped conductive layer arranged on one side surface of the silicon substrate, the first doped conductive layer is located on the back surface of the cell, and there is a first interval between adjacent first doped conductive layers. The laminated film further comprises: a second doped conductive layer arranged on the other side surface of the silicon substrate, and the second doped conductive layer is located on the front surface of the cell. The first texture structure is located on the silicon substrate corresponding to the first doped conductive layer and on the silicon substrate corresponding to the first interval. The first recessed areas corresponding to the first interval on the one side surface of the silicon substrate are more densely distributed than the first recessed areas corresponding to the first doped conductive layer. The roughness of the first side walls corresponding to the first interval on the one side surface of the silicon substrate is greater than the roughness of the first side walls corresponding to the first doped conductive layer. The number of the first side walls corresponding to the first interval on the one side surface of the silicon substrate is greater than the number of the first side walls corresponding to the first doped semiconductor layer.

[0034] According to an embodiment of the present application, the doped conductive layer is a second doped conductive layer arranged on the other surface of the silicon substrate, the second doped conductive layer is located on the front surface of the cell, and there is a second interval between adjacent second doped conductive layers. The laminated film further comprises: a first doped conductive layer arranged on one side surface of the silicon substrate, and the first doped conductive layer is located on the back surface of the cell. The first texture structure is located on the silicon substrate corresponding to the first doped conductive layer and on the silicon substrate corresponding to the second doped conductive layer. The first recessed areas corresponding to the second doped conductive layer on the other side surface of the silicon substrate are more sparsely distributed than the first recessed areas corresponding to the first doped conductive layer on the one side surface of the silicon substrate. The number of the first side walls corresponding to the second doped conductive layer on the other side surface of the silicon substrate is less than the number of the first side walls corresponding to the first doped conductive layer on the one side surface of the silicon substrate. The roughness of the first side walls corresponding to the first doped conductive layer on the one side surface of the silicon substrate is greater than the roughness of the first side walls corresponding to the second doped conductive layer on the other side surface of the silicon substrate.

[0035] According to an embodiment of the present application, the doped conductive layer is a first doped conductive layer arranged on one side surface of the silicon substrate, the first doped conductive layer is located on the back surface of the cell, and the first doped conductive layer has a first interval region between adjacent first doped conductive layers. The stack film further comprises: a second doped conductive layer extending along the first direction and spaced apart on the other side surface of the silicon substrate along the second direction, the second doped conductive layer is located on the front surface of the cell, and the second doped conductive layer has a second interval region between adjacent second doped conductive layers. The first texture structure is located on the respective silicon substrate surface of the first doped conductive layer, the second doped conductive layer, the first interval region, and the second interval region. The first recessed regions corresponding to the first texture structure on the first interval region on the one side surface of the silicon substrate are more densely distributed than the first recessed regions corresponding to the first texture structure on the first doped conductive layer. And / or, the first recessed regions corresponding to the first texture structure on the first interval region on the other side surface of the silicon substrate are more densely distributed than the first recessed regions corresponding to the first texture structure on the second doped conductive layer. And / or, the number of first side walls corresponding to the first texture structure of the first interval region on the one side surface of the silicon substrate is greater than the number of first side walls corresponding to the first texture structure of the first doped conductive layer. And / or, the roughness of the first side walls corresponding to the first texture structure of the first interval region on the other side surface of the silicon substrate is greater than the roughness of the first side walls corresponding to the first texture structure of the second doped conductive layer.

[0036] According to an embodiment of the present application, the second doped conductive layer is a P-type doped conductive layer. The first recessed regions corresponding to the first texture structure on the second doped conductive layer on the other side surface of the silicon substrate are more sparsely distributed than the first recessed regions corresponding to the first texture structure on the first doped semiconductor layer on the one side surface of the silicon substrate. And / or, the roughness of the first side walls corresponding to the first texture structure of the first doped conductive layer on the one side surface of the silicon substrate is greater than the roughness of the first side walls corresponding to the first texture structure of the second doped semiconductor layer on the other side surface of the silicon substrate. And / or, the number of first side walls corresponding to the first texture structure on the second doped semiconductor layer on the other side surface of the silicon substrate is less than the number of first side walls corresponding to the first texture structure on the first doped semiconductor layer on the one side surface of the silicon substrate.

[0037] According to an embodiment of the present application, the solar cell further comprises: a stack film arranged on both side surfaces of the silicon substrate, the stack film comprising: a first doped conductive layer arranged on one side surface of the silicon substrate, the first doped conductive layer having a first texture structure on the respective silicon substrate surface of the first doped conductive layer; a second doped conductive layer arranged on the other side surface of the silicon substrate, the other side surface of the silicon substrate corresponding to the second doped conductive layer having a pyramid structure; and a passivation or anti-reflection layer located on the surface of the doped conductive layer away from the silicon substrate.

[0038] According to the embodiment of the application, the solar cell is provided, and the solar cell comprises the solar cell as described above.

[0039] According to the solar cell provided by the embodiment of the application, the surface of the silicon substrate comprises the first recessed area and the first raised area adjacent to the first recessed area, and the first recessed area and the first raised area form the first texture structure. The first recessed area extends in a strip shape and / or forms a sidewall with a concave-convex structure. The light trapping effect is ensured, and the film layer is uniformly deposited on the silicon substrate due to the lack of the traditional tower base corner, so that the quality of the deposited film layer is improved, the passivation effect is improved, the electrical contact performance is improved, and the conversion efficiency of the cell is improved. Correspondingly, the photovoltaic module comprising the solar cell has high conversion efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0040] The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application taken with reference to the accompanying drawings, in which:

[0041] Figure 1 The optical microscope image of the first texture structure of the silicon substrate according to the embodiment of the application is shown in FIG. 1;

[0042] Figure 2 The optical microscope three-dimensional topography image of the silicon substrate according to the embodiment of the application is shown in FIG. 2, in which (a) is a continuous distribution of the first recessed area, and (b) is a non-continuous distribution of the first recessed area;

[0043] Figure 3 The topography schematic diagram of the first recessed area according to the embodiment of the application is shown in FIG. 3;

[0044] Figure 4 The optical microscope three-dimensional topography image of the silicon substrate according to another embodiment of the application is shown in FIG. 4, in which (a) is a bamboo joint-shaped multi-section structure, (b) is a sugar-cane-shaped multi-section structure, (c) is a cross-shaped protruding part, (d) is a first raised area in a combination of a straight line shape and a curve shape, (e) is a point-shaped first raised area, (f) is a polyline-shaped first raised area, and (g) is a sugar-cane-shaped first raised area;

[0045] Figure 5 The perspective view of Figure 4 is shown in FIG. 5;

[0046] Figure 6 The scanning electron microscope (SEM) image of the first recessed area according to another embodiment of the application is shown in FIG. 6, in which the first recessed area is in a bamboo joint shape;

[0047] Figure 7 The SEM image of the first recessed area according to another embodiment of the application is shown in FIG. 7, in which the first recessed area is in a sugar-cane shape;

[0048] Figure 8 The topography schematic diagram of the protruding part in the first recessed area according to the embodiment of the application is shown in FIG. 8.

[0049] Figure 9 A schematic view of the topography of the first protrusion region of an embodiment of the present application;

[0050] Figure 10 A three-dimensional optical microscope topography of a silicon substrate of yet another embodiment of the present application, wherein (a) is a first pit in a dot-like distribution, (b) is a second pit in a groove shape, (c) is a second pit in a line shape, (d) is a second pit in a cross shape, and (e) is a third recessed region;

[0051] Figure 11 A perspective view of Figure 10 ;

[0052] Figure 12 A plot of the height variation of the first recessed region at a sampling position of yet another embodiment of the present application;

[0053] Figure 13 A cross-sectional SEM view of the first recessed region of still another embodiment of the present application, wherein (a) is a cross-sectional SEM view, and (b) is an optical microscope view;

[0054] Figure 14 An optical microscope view of a silicon substrate of yet another embodiment of the present application, wherein (a) is a crack located in the first recessed region, (b) is a crack located in the first protrusion region, and (c) is a crack located in the third recessed region;

[0055] Figure 15 A top view SEM view of the first side wall of another embodiment of the present application;

[0056] Figure 16 An enlarged partial SEM view of the wrinkle portion of another embodiment of the present application, wherein (a) is a side view of the wrinkle portion comprising a plurality of layered structures, (b) is a top view of the wrinkle portion comprising a plurality of dot-like protrusions, (c) is a combination of the layered structure and a step, and (d) is a combination of the dot-like protrusion and a step;

[0057] Figure 17 A top view SEM view of the first side wall extending continuously or discontinuously in still another embodiment of the present application, wherein (a) is extending continuously in a line shape, (b) is extending discontinuously in a line shape, (c) is extending in a ring shape, and (d) is extending in a C shape, respectively.

[0058] Figure 18 A top view SEM view of the first side wall bifurcation structure and the second side wall bifurcation structure of yet another embodiment of the present application;

[0059] Figure 19 A top view SEM view of the first texture structure of still another embodiment of the present application;

[0060] Figure 202 is a top view SEM image of a second texture structure according to another embodiment of the present application, wherein (a) and (b) are examples of different morphologies of the second recessed area, (c) is the second texture structure marked with (a), and (d) is the second texture structure marked with (b);

[0061] Figure 21 This is a side SEM image of a second texture structure according to another embodiment of the present application;

[0062] Figure 22 This is a side view SEM of a film layer on a silicon substrate according to an embodiment of the present application;

[0063] Figure 23 This is a schematic diagram of the overall structure of a solar cell according to an embodiment of the present application;

[0064] Figure 24 This is a schematic diagram of the overall structure of a solar cell according to another embodiment of the present application;

[0065] Figure 25 This is a schematic diagram of the overall structure of a solar cell according to another embodiment of the present application;

[0066] Figure 26 This is a schematic diagram of the overall structure of a solar cell according to another embodiment of the present application.

[0067] In the above drawings, the meanings of the reference numerals are as follows:

[0068] 100: silicon substrate;

[0069] T1: first texture structure;

[0070] 110: first recessed area;

[0071] 111: protrusion, 112: first concave, 113: second concave;

[0072] 114: third pit, 115: convex;

[0073] 120: first raised area;

[0074] 121: gentle slope, 1211: gently sloping surface, 1212: gently hillock stripes;

[0075] 130: cracks;

[0076] 140: first side wall,

[0077] 141: folds;

[0078] 1411: layered structure, 1412: dot-like protrusions;

[0079] 142: steps;

[0080] 150: first side wall bifurcation structure;

[0081] 151: first sub side wall;

[0082] 160: second side wall bifurcation structure;

[0083] 161: second sub side wall;

[0084] T2: second texture structure;

[0085] 210: second recessed area;

[0086] 211: sub recessed structure,

[0087] 220: second protruded area;

[0088] 221: protruded end;

[0089] 102: laminated film;

[0090] 1021: first doped conductive layer, 1022: second doped conductive layer;

[0091] 1031: first interface passivation layer; 1032: second interface passivation layer;

[0092] 104: passivation or anti-reflective layer;

[0093] 1041: first passivation or anti-reflective layer, 1042: second passivation or anti-reflective layer

[0094] 200: electrode;

[0095] 201: first electrode, 202: second electrode;

[0096] S1: first aspect, S2: second direction. DETAILED DESCRIPTION

[0097] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to specific embodiments and drawings.

[0098] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that one or more embodiments can be practiced without these specific details. In other instances, well-known structures and features often are not described in detail in order to avoid obscuring aspects of the present application.

[0099] The terms used herein are merely used to describe specific embodiments, and are not intended to limit the present application. The term "comprising" used herein indicates the presence of a feature, step, operation, but does not exclude the presence or addition of one or more other features.

[0100] In the event that a phrase similar to "at least one of A, B, and C, etc." is used herein, it is intended that the phrase be interpreted to mean that an item, feature, structure, or means for at least one of A, B, and C is included in the present application, and it is also intended that the phrase be interpreted to mean that at least one of A, B, and C is included in the present application. It is further intended that the phrase be interpreted to mean that at least one of A, B, and C is included in the present application, but it is not intended that the phrase be interpreted to mean that at least one of A, B, and C is included in the present application.

[0101] In the present application, the relative position between two components (e.g. film layers or regions) such as "on", "above" or "over" can refer to the two components being in direct contact or can refer to the two components being in indirect contact. Similarly, in the present application, the relative position between two components such as "under", "below" or "underneath" can refer to the two components being in direct contact or can refer to the two components being in indirect contact. For example, when one component (e.g. film layer or region) is referred to as "on" another component, it can be directly on the other component, or there can be intervening components between the two. On the other hand, when a component is referred to as "directly on" another component, then there are no intervening components between the two. In addition, when one component is referred to as "on" another component, the two are in a top and bottom relationship in a plan view, and the component can be above or below the other component, so the top and bottom relationship depends on the orientation of the device.

[0102] In a solar cell, the surface morphology of the silicon substrate has an effect on the reflectivity of light and the deposition quality of film layers. A polished surface is more conducive to the deposition of high-quality film layers than a textured surface, but its reflectivity is increased and the light trapping effect is poorer.

[0103] It is found in the process of implementing the concept of the present application that the conventional tower base structure formed on a polished surface presents many corners, which will affect the deposition of film layers to some extent and is not conducive to the further improvement of the electrical performance of a solar cell.

[0104] Specifically, according to some embodiments of the present application, a solar cell is provided, comprising: a silicon substrate, the silicon substrate comprising two opposite surfaces, at least one surface having a first texture structure.

[0105] According to some embodiments of the present application, the silicon substrate can be an N-type, P-type or intrinsic type crystalline silicon substrate, can be selected from one of a semiconductor material such as single crystal silicon, polycrystalline silicon, microcrystalline silicon, and further can be selected as an N-type or P-type single crystal silicon substrate, and the conversion efficiency of a cell based on a single crystal silicon substrate is higher than that of other types such as a polycrystalline silicon cell.

[0106] By introducing donor impurities such as phosphorus (P), arsenic (As) or antimony (Sb) in Group VA elements into the semiconductor materials, N-type crystalline silicon substrates are obtained, or by introducing acceptor impurities such as boron (B), aluminum (Al) or gallium (Ga) in Group IIIA elements into the semiconductor materials, P-type crystalline silicon substrates are obtained.

[0107] According to some embodiments of the present application, the first texture structure can be distributed on one surface of the silicon substrate, or on both opposite surfaces of the silicon substrate. When the silicon substrate is applied to a solar cell, the surface with the first texture structure can be the back surface or the light-receiving surface. Further, the first texture structure can be distributed on the at least one surface in an entire surface or a local manner, which can be selected according to actual application scenarios.

[0108] In order to illustrate the first texture structure of the silicon substrate, Figure 1 is an optical microscope image of the silicon substrate according to an embodiment of the present application; Figure 2 is a three-dimensional topography image of the silicon substrate according to an embodiment of the present application; as Figure 1 and Figure 2 As shown in FIG. 1, the first texture structure T1 includes a plurality of first recessed regions 110 and a plurality of first protruding regions 120, wherein the first protruding regions 120 are adjacent to the first recessed regions 110.

[0109] According to some embodiments of the present application, the first recessed regions 110 each extend into a strip shape along a first direction S1, and the plurality of first recessed regions 110 are spaced apart along a second direction S2 intersecting the first direction S1.

[0110] It is found by the present application that by selecting appropriate process conditions in the alkali polishing process, such as controlling the polishing temperature, time and composition of the polishing solution, the inhibition effect on specific crystal phases can be exerted, the influencing factor of the line marks on the original silicon wafer in the polishing process is increased, the first texture structure of the polished surface is controlled, and the surface of the silicon substrate has first recessed regions extending into a strip shape and first protruding regions adjacent to the first recessed regions. Since the first texture structure presents a generally linear extension structure, the corners are weakened, so that there are fewer or even no corners of the traditional tower foundation structure, which is beneficial to the more uniform deposition of the film layer such as the doped conductive layer, the passivation or anti-reflection layer and the like on the silicon substrate, improves the quality of the deposited film layer, can take into account the light trapping effect at the same time, improves the passivation effect and electrical contact performance, thereby improving the conversion efficiency of the solar cell.

[0111] Because the film layers, such as a stacked film including a doped conductive layer and a passivation or anti-reflection layer, are conformally deposited on the silicon substrate 100, the same first texture structure can be observed on the surface of the solar cell. Therefore, the structure on the surface of the silicon substrate of the present application can be directly measured by testing the first texture structure in the solar cell product, or it can be measured by removing the stacked film on the cell surface to expose the surface of the silicon substrate, using, for example, a scanning electron microscope (SEM) or an optical microscope.

[0112] According to some embodiments of the present application, the first recessed area 110 may extend continuously and / or discontinuously in a strip shape along the first direction S1. Figure 2 As shown, (a) shows that the first recessed area 110 extends continuously into a strip shape, while (b) shows that the first recessed area 110 extends discontinuously into a strip shape. However, this is not limiting. It is understood that, subject to actual process constraints, individual first recessed areas 110 may be partially distributed in a non-strip shape, such as in an island shape. The "strip shape" mentioned above means that the extension length of the first recessed area 110 in the first direction S1 is greater than its width in the second direction S2. For example, the ratio of the length to the width of the first recessed area 110 can be at least greater than 2:1, 5:1, 10:1, or 20:1, and further, can be less than 200:1, 100:1, or 50:1, etc.

[0113] According to some embodiments of the present application, Figure 2 As shown in FIG. 2( b ), the first recessed area 110 has a protruding portion 111 extending along the second direction. The first recessed area 110 is divided into a multi-segment structure by the protruding portion 111 .

[0114] Thus, by configuring the first recessed region 110 as a multi-segment structure including the protrusions 111, surface roughness is increased. This multi-segment structure of the first recessed region 110, when applied to a light-receiving region, can enhance light trapping. The light-receiving region corresponds to the front and / or back of the battery, and can at least correspond to the non-electrode region of the surface. Furthermore, when depositing a film or forming an electrode on the silicon substrate 100, this multi-segment structure helps disperse stress, promotes uniform film growth, and improves electrode quality, thereby facilitating passivation and electrical contact performance.

[0115] According to some embodiments of the present application, the height of the protrusion 111 can be lower than the height of the first raised region 120, especially the height of the first raised region 120 adjacent to the protrusion 111. Here, the "height" refers to the dimension in the direction away from the surface of the silicon substrate 100. In this way, the protrusion 111 does not bring about sharp edges, thereby ensuring the deposition quality of the film layer, while the protrusion 111 applied to the light receiving area has a positive effect on the light trapping effect, the light receiving area corresponding to the front and / or back surface of the cell, and can at least correspond to the non-electrode area of the surface.

[0116] According to some embodiments of the present application, the multi-segment structure can be in a combination of one or more of a plurality of patterns such as a bamboo joint shape, a sugar cane shape, etc. Figure 3 is a schematic diagram of the topography of the first recessed region of an embodiment of the present application; wherein the dashed box shows the area where the first recessed region 110 is located, and the multi-segment structure can be in a bamboo joint shape as shown in Figure 3 , or a sugar cane shape as shown in Figure 3 , or a combination of the bamboo joint shape and the sugar cane shape as shown in Figure 3 It can be understood that Figure 3 only schematically illustrates the multi-segment structure in different patterns in the same figure, and one or more of the patterns can be combined in one or more first recessed regions 110 according to actual conditions. Of course, it is not limited thereto, and the first recessed region can also adopt a multi-segment structure of other types of patterns, or the first recessed region can be in a continuous strip shape as shown in Figure 3 .

[0117] Exemplarily, Figure 4 is an optical microscope three-dimensional topography of a silicon substrate of another embodiment of the present application; Figure 5 is a perspective view of Figure 4 , as shown in Figure 4 and Figure 5 , wherein the (a) figures of both show that the multi-segment structure can be in a bamboo joint shape, and the (b) figures show that the multi-segment structure can be in a sugar cane shape. Of course, it is not limited thereto, and can also be other regular or irregular shapes. The multi-segment structure with a suitable topography is beneficial to further reduce the edge structure while having a suitable surface roughness, thereby improving the deposition quality of the film layer on the silicon substrate 100 and the quality of the electrode produced.

[0118] According to some embodiments of the present application, in order to characterize the multi-segment structure in the bamboo joint shape, the sugar cane shape, etc. described above, the optical microscope described above can be used for characterization, but it is not limited thereto, and the scanning electron microscope (SEM) can also be used to observe the multi-segment structure described above. Exemplarily, Figure 6 is a scanning electron microscope (SEM) figure of the first recessed region in a bamboo joint shape of still another embodiment of the present application, as shown in Figure 6As shown, the multi-segment structure can be in the shape of a bamboo joint; or Figure 7 This is an SEM image of the first concave area in the shape of a candied haws, as shown in FIG. Figure 7 As shown, the multi-segment structure can be in the shape of a candied haws.

[0119] According to some embodiments of the present application, the projection of the protrusion 111 on the first recessed area 110 may be in at least one of a cross shape, a straight line shape, a curve shape, and the like. Figure 8 Schematic diagram of the morphology of the protrusion in the first concave area of ​​the embodiment of the present application; wherein the dotted box shows the area where the first concave area 110 is located, and the protrusion 111 can be as follows Figure 8 The straight line shown on the left, or Figure 8 The cross shape shown in the second left, or the curve shape shown in the third left of 8, or Figure 8 The right side shows a combination of straight line, cross and curve. It can be understood that Figure 8 The protrusions 111 of different patterns are only schematically illustrated in the same drawing, and one or more patterns may be combined in one or more first recessed areas 110 according to actual conditions.

[0120] For example, Figure 4 As shown in FIG. 1 , FIG. (a) shows a curved protrusion 111, FIG. (b) shows a protrusion 111 that is a combination of a straight line and a curved line, and FIG. (c) shows a cross-shaped protrusion 111. It is worth mentioning that the cross-shaped protrusion is conducive to further improving the surface roughness, thereby improving the light trapping effect when the protrusion 111 is applied to the light-receiving area. The light-receiving area corresponds to the front and / or back of the battery, and can at least correspond to the non-electrode area of ​​the surface.

[0121] According to some embodiments of the present application, the first texture structure T1 of the present application includes a first raised area 120, and the projection of the first raised area 120 in the surface extension direction of the silicon substrate 100 is at least one of a straight line, a broken line, a curve, a candied haws shape, and a dot shape. Figure 9 FIG. 1 is a schematic diagram of the morphology of the first convex region of the embodiment of the present application; wherein the dotted box shows the area where the first concave region 110 is located. The first convex region 120 can be as follows Figure 9 The straight line shown on the left, or Figure 9 The second one from the left is in the shape of a candied haws, or as Figure 9 The curve shown in the third left, or Figure 9 The second right broken line, or Figure 9 The combination of straight line and dot-shaped protrusions is shown on the right. It can be understood that Figure 9The first protruding regions 120 of different patterns are only schematically illustrated in the same figure, and one or more of the patterns can be combined in one or more first protruding regions 120 according to actual conditions.

[0122] For example, as shown in the figures, Figure 4 For example, as shown in the figures,

[0123] According to some embodiments of the present application, a solar cell is also provided, which comprises at least one silicon substrate having a first texture structure, Figure 10 A three-dimensional optical microscope topography of the silicon substrate according to another embodiment of the present application, Figure 11 A three-dimensional optical microscope topography of the silicon substrate according to another embodiment of the present application, Figure 10 A perspective view of the silicon substrate according to another embodiment of the present application; as Figure 10 A perspective view of the silicon substrate according to another embodiment of the present application; as Figure 11 As shown in the (a) figure of the silicon substrate according to another embodiment of the present application, the first texture structure T1 comprises a plurality of first recessed regions 110, each of which extends in a strip shape along a first direction S1 and is spaced apart along a second direction S2 intersecting the first direction S1. At least part of the first recessed regions 110 have a plurality of first pits 112, which are distributed in a point shape along the first direction and have no extension along the first direction. The bottom surface of the first pits 112 relative to other regions of the first recessed regions 110 is recessed towards the inside of the silicon substrate, forming a hole structure nested in the first recessed regions 110. At this time, the orifice of the first pits 112 is located at the bottom wall of the first recessed regions 110.

[0124] By arranging the first pits 112 in a point shape in the first recessed regions 110, the surface roughness of the first recessed regions 110 can be further increased. When the first recessed regions 110 having the first pits 112 are applied to a light-receiving region, the light-trapping effect can be improved, and the electrical contact performance of the electrode can also be effectively improved. The light-receiving region corresponds to the front surface and / or the back surface of the cell, and can at least correspond to the non-electrode region of the surface.

[0125] Optionally, the number of the first pits 112 in the first recessed region 110 is more than 1, and further optionally is 1-30, for example, 1, 2, 4, 5, 8, 10, 13, 15, 18, 20, 22, 25, 28, 30, etc. By controlling the number of the first pits 112 in a proper range, the surface roughness can be controlled in a proper range, so as to avoid adversely affecting the deposition of the film layer on the silicon substrate 100.

[0126] Of course, it is not limited to this, and at least part of the first recessed region 110 can also have at least one second pit 113 with other topographies such as cross-shaped, linear, or groove-shaped, etc. The at least one second pit 113 can be randomly distributed, and has an extension in the distribution direction, for example, the first direction S1, i.e., the extension size of the second pit is greater than the size of the first pit. Exemplarily, again as shown in Figure 10 and Figure 11 The second pit 113 shown in the (b) view of the two is groove-shaped, the second pit shown in the (c) view is linear, and the second pit shown in the (d) view is cross-shaped. Alternatively, at least part of the first recessed region 110 can also have a combination of the first pit 112 and the second pit 113; the bottom surface of the above-mentioned “second pit 113” is recessed towards the inside of the silicon substrate relative to the bottom surface of the other regions of the first recessed region 110, forming a hole structure nested in the first recessed region 110, and at this time, the aperture of the second pit 113 is located at the bottom wall of the first recessed region 110. By providing the second pit 113, the light trapping effect can be improved when applied to the light receiving region.

[0127] Further optionally, the number of the second pits 113 is less than the number of the first pits 112, so as to control the surface roughness of the silicon substrate 100 in a proper range. Alternatively, at least part of the first recessed region 110 can not have pits, for example, does not have the first pit 112 or the second pit 113.

[0128] According to still some embodiments of the present application, the present application also provides a solar cell comprising at least one silicon substrate with a first texture structure, such as Figures 1 to 10As shown, the first texture structure of the present application includes a plurality of first recessed regions 110, each extending in a first direction S1 in a strip shape and being spaced apart along a second direction S2 intersecting the first direction S1. The spacing of adjacent first protruding regions 120 in the second direction S2 can be 0.5-10 μm, for example, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc., and further, the spacing can be 1-10 μm. It can be understood that, in the case where no first sidewall is provided between the first recessed region 110 and the first protruding region 120 or the first recessed region 110 and the first sidewall have no obvious boundary, the spacing is the width of the first recessed region 110; and in the case where a first sidewall is further provided between the first recessed region 110 and the first protruding region 120, the spacing includes the sum of the width of the first recessed region 110 and the width of the first sidewall.

[0129] And / or, the depth of the first recessed region 110 is 0.1-10 μm, for example, 0.1 μm, 0.2 μm, 0.4 μm, 0.6 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, 2.0 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc., and further, the depth can be 0.2-2 μm. Here, the "depth" of the first recessed region 110 refers to the dimension in the thickness direction of the silicon substrate 100.

[0130] In this way, by setting the first recessed region 110 in the micron-level size range, on the one hand, it is conducive to obtaining a suitable surface roughness, so that when the first recessed region 110 is applied to a light-receiving region, a certain light-trapping effect can be ensured, wherein the light-receiving region corresponds to the front and / or back surface of the cell and can at least correspond to the non-electrode region of the surface; on the other hand, it makes it easy to conformally deposit a relatively thin film layer, for example, a nanometer-level thick film layer, on the silicon substrate 100; and on the other hand, it makes it easy to deposit or print an electrode of high quality on the silicon substrate 100.

[0131] According to some embodiments of the present application, the spacing between two adjacent first recessed regions 110 on the silicon substrate 100 of the present application can be 0.5-10 μm, for example, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc., and further, the spacing can be 2-10 μm. By regulating the spacing of the first recessed region 110 within a suitable range, it is conducive to regulating the surface of the silicon substrate 100 to a suitable surface roughness, so that when the first recessed region 110 with a suitable spacing is applied to a light-receiving region, the light-trapping effect and the deposition effect of the film layer can be taken into account, wherein the light-receiving region corresponds to the front and / or back surface of the cell and can at least correspond to the non-electrode region of the surface.

[0132] According to some embodiments of the present application, on the surface of the silicon substrate 100 of the present application, within a width of 100 μm along the second direction, the number of first recessed regions 110 can be 1 to 40, for example, 1, 2, 5, 10, 15, 18, 20, 25, 30, 35, 40, etc.; the number of first recessed regions 110 can further be 3 to 20. Similarly, by controlling the distribution density of the first recessed regions 110 within a suitable range, it is helpful to control the surface roughness of the silicon substrate 100 to a suitable level. Therefore, when the first recessed regions are used in the light-receiving area, both the light trapping effect and the film deposition effect can be taken into account.

[0133] According to some embodiments of the present application, the width, depth, spacing, and distribution number of the first recessed regions 110 on the surface of the silicon substrate 100 are measured without limitation. Those skilled in the art can perform the measurements using conventional methods in the art. For example, the measurements can be made directly on a solar cell product using an optical microscope or by removing the laminate film on the cell surface to expose the silicon substrate surface. The height fluctuations of the first recessed regions 110 and the first raised regions 120 can be quantified. Specifically, a cross-section can be taken along the second direction S2, and the average height or 50% median height at the intersection of the cross-section and the silicon substrate surface is used as the zero point. The portion below the zero point is the recessed region, and the portion above the zero point is the first raised region. The position of the first strip-shaped recessed region 110 is determined within the recessed region. The distance between the valley tops at the location of the first recessed region 110 is used as its width, and the distance between the valley top and valley bottom is used as its depth, with the valley bottom being farther from the zero point than the valley top. Further optionally, two adjacent first depressed areas 110 are determined within the depressed area, and the distance between the adjacent valley tops of the two first depressed areas 110 is used as the spacing. Further optionally, the number of first depressed areas 110 within the depressed area is counted within a unit size range, such as 100 μm, as the distribution number.

[0134] For example, Figure 12 This is a height variation curve of the first recessed area at the sampling position according to another embodiment of the present application, as shown in FIG. Figure 12 As shown, it can be seen that the depth of the first recessed area 110 is 0.28-0.78 μm and the width is between 2-10 μm.

[0135] According to some further embodiments of the present application, the present application further provides a solar cell, comprising a silicon substrate having at least one surface with a first texture structure, Figure 13 This is a characterization diagram of the arc-shaped first concave area of ​​another embodiment of the present application, wherein (a) is a cross-sectional SEM image and (b) is an optical microscope image. Figure 13 As shown, combined Figure 1The first texture structure of the present application includes a plurality of first recessed areas 110, each extending in a strip shape along a first direction S1 and spaced apart along a second direction S2 intersecting the first direction S1. The cross-sectional shape of the first recessed areas 110 includes a V-shape and / or an arc. Of course, this is not limiting. The cross-sectional shape of the first recessed areas 110 may also be other shapes, such as a rectangle, a trapezoid, or any combination of such other shapes with a V-shape or an arc.

[0136] Furthermore, if Figure 13 As shown in Figure (b), third pits 114 may be present at the junction of the first recessed region 110 and the first raised region, discontinuously distributed along the first direction. In this case, there is no clear boundary between the lowest point of the first recessed region and the sidewall. These third pits 114 are recessed toward the silicon substrate along the normal to the sidewall of the first recessed region 110, forming a pore structure nested within the sidewall of the first recessed region 110. In this case, the openings of the third pits 114 are located within the sidewall of the first recessed region 110. Protrusions 115 are located between adjacent third pits 114. The cross-section of the first recessed region 110 at the protrusions 115 may be V-shaped and / or arc-shaped, and / or the cross-section of the first recessed region 110 at the third pits 114 may be V-shaped and / or arc-shaped, and / or the cross-section of the first recessed region 110 at the third pits 114 may be V-shaped and / or arc-shaped, and / or the cross-section of the remaining portion of the first recessed region 110 excluding the protrusions 115 and the third pits 114 may be V-shaped and / or arc-shaped.

[0137] In this way, by setting the cross section of the first recessed region 110 to a suitable shape, the growth stress of the film layer on the silicon substrate 100 is relieved, and the deposition of the film layer on the silicon substrate 100 is not likely to be adversely affected.

[0138] According to some further embodiments of the present application, in addition to the first texture structure described above, the surface of the silicon substrate 100 of the present application may further include a first texture structure T2, wherein the first texture structure T2 includes a second recessed region 210. Here, the second texture structure is different from the first texture structure. For example, the first texture structure may be used to represent a deep line mark region, while the second texture structure may be used to represent a shallow line mark region.

[0139] Because the film layers, such as a stacked film including a doped conductive layer and a passivation or anti-reflection layer, are conformally deposited on the silicon substrate 100, the same second texture structure can be observed on the surface of the solar cell. Therefore, the structure on the silicon substrate surface of the present application can be directly tested by testing the second texture structure in the solar cell product, or it can be tested after removing the stacked film from the cell surface to expose the silicon substrate surface. Testing methods, such as scanning electron microscopy (SEM) or optical microscopy, can be used to obtain the structure.

[0140] According to embodiments of the present application, the first and second texture structures are microstructures, where the "microstructure" refers to at least one texture structure with a one-dimensional size in the micro-nano level, for example, in the order of hundreds of nanometers, several microns or ten microns, etc. The one-dimensional size may, for example, be the width along the surface direction of the silicon substrate, or the depth along the thickness direction of the silicon substrate, etc.

[0141] Exemplarily, the one-dimensional size of the second recessed area 210 in the second texture structure T2 along the surface direction of the silicon substrate can be greater than or equal to the one-dimensional size of the first recessed area 110 in the first texture structure T1 along the second direction, for example, the width of the first recessed area 110 along the second direction S2 can be greater than or equal to 1 μm, and further optionally in the range of 1-10 μm, and the one-dimensional size of the second recessed area 210 along the surface direction of the silicon substrate can be greater than or equal to 1 μm, and further optionally in the range of 1-15 μm.

[0142] Exemplarily, the depth of the second recessed area 210 in the second texture structure T2 recessed towards the interior of the silicon substrate 100 is less than the depth of the first recessed area 110 in the first texture structure T1 recessed towards the interior of the silicon substrate 100, for example, the depth of the first recessed area 110 is in the range of 0.2-2 μm, and the depth of the second recessed area 210 is in the range of 0.1-1 μm. As Figure 10 and Figure 11 As shown in (e) of FIG. 1, the position of the second recessed area 210 is shown, and the second recessed area 210 of the silicon substrate 100 can include a plurality of sub-recessed structures 211 distributed in a non-linear manner, where the depth of the second recessed area 210 is less than the depth of the first recessed area 110. In this way, the first and second recessed areas 110 and 210 can more effectively play a role in regulating the surface topography of the silicon substrate 100, and the balance between the film quality and light trapping effect can be considered.

[0143] According to embodiments of the present application, the second recessed area in the second texture structure T2 has no extension, and the first recessed area 110 in the first texture structure T1 has an extension along the first direction, exemplarily, the extension length of the first recessed area 110 in the first texture structure T1 along the first direction is greater than the one-dimensional size of the second recessed area in the second texture structure T2 along the surface direction of the silicon substrate, for example, the extension length of the first recessed area 110 in the first texture structure T1 along the first direction is greater than 30 μm.

[0144] According to embodiments of the present application, the area ratio of the first recessed area 110 is less than the area ratio of the second recessed area 210; and / or, the area ratio of the first recessed area 110 can be in the range of 5%-48%, for example, 5%, 8%, 10%, 15%, 17%, 20%, 22%, 25%, 28%, 30%, 32%, 35%, 37%, 40%, 42%, 45%, 48%, etc., and more preferably in the range of 17-37%.

[0145] By controlling the area proportion of the first recessed region 110 and the second recessed region 210 within the above range, the regulation effect on the surface morphology of the battery body I is more favorable, and when the first recessed region 110 and the second recessed region 210 are applied to the light receiving surface, the light trapping effect, passivation and electrical contact performance can be better balanced.

[0146] According to still another embodiment of the present application, the present application further provides a solar cell comprising at least one silicon substrate having a first texture structure, Figure 14 For the optical microscope image of the silicon substrate of another embodiment of the present application, as shown in Figure 14 The first texture structure T1 of the present application comprises at least one crack 130 randomly distributed on the surface of the silicon substrate 100. Further, the crack 130 can exist in at least one of the first recessed region 110, the first raised region 120 and the second recessed region 210. Exemplarily, Figure 14 (a) of FIG. shows that the crack 130 is located in the first recessed region 110, (b) of FIG. shows that the crack 130 is located in the first raised region 120, and (c) of FIG. shows that the crack 130 is located in the second recessed region 210. By providing the crack 130, the surface roughness is further increased.

[0147] According to some embodiments of the present application, as shown in Figure 14 Further, the extension direction of the crack 130 is the same or substantially the same as the first direction, so that when depositing a film layer on the silicon substrate 100, on the one hand, the area of the film layer deposition is increased, and the passivation effect is improved, and on the other hand, the first texture structure extending along other directions is avoided to be introduced on the surface of the silicon substrate, and the moire is improved. Here, the meaning of "substantially the same" indicates that the included angle between the extension direction of the crack 130 and the first direction is less than 45°, which can be less than 30°, and more can be less than 10°, etc. Further optionally, the morphology of the crack 130 can be at least one of a straight line, a curve, and a broken line.

[0148] The above is a description of the surface morphology of the silicon substrate 100 in the solar cell of the embodiment of the present application, and is not limited thereto. According to the above surface morphology of the silicon substrate 100 of the present application, the surface morphology of the silicon substrate 100 can be prepared by a polishing process, which can specifically include the following operations:

[0149] First, the original silicon substrate is polished by a polishing alkali solution. The polishing temperature is 50-80°C, for example, it can be 50°C, 55°C, 60°C, 65°C, 70°C, 75°C, 80°C, etc. The polishing time is 50-900 s, for example, it can be 50 s, 100 s, 200 s, 300 s, 350 s, 400 s, 450 s, 500 s, 550 s, 600 s, 700 s, 800 s, 900 s, etc. The polishing alkali solution includes 0.5-15 wt% (for example, it can be 0.5 wt%, 1 wt%, 5 wt%, 10 wt%, 13 wt%, 15 wt%, etc.) of NaOH and 0.1-2 wt% (0.1 wt%, 0.2 wt%, 0.5 wt%, 0.8 wt%, 1.0 wt%, 1.3 wt%, 1.5 wt%, 1.8 wt%, 2.0 wt%, etc.) of a polishing additive. The polishing additive can include a surfactant, a defoaming agent, a stabilizer, a corrosion inhibitor and a dispersant, so that the first recessed area in a strip-shaped distribution is formed by the synergistic effect of the additive and the polishing temperature and time through the inhibition of certain crystal phase.

[0150] Then, the polished silicon substrate 100 is cleaned and dried to obtain the silicon substrate with the first texture structure of the application. The cleaning can include ozone cleaning and mixed acid cleaning, for example, in sequence.

[0151] According to some embodiments of the application, the first texture structure T1 can include a first side wall 140 located between the first recessed area 110 and the first raised area 120, and the first side wall 140 has a wrinkle part 141. The above-mentioned "wrinkle part 141" can be a corrugated and / or wrinkled texture structure, for example, it can be a structure similar to a wrinkle or a scale.

[0152] The first recessed area can directly transition to the first raised area, and at this time, the first recessed area and the first side wall have no obvious boundary. Of course, the first recessed area can also transition to the first raised area through the first side wall, and at this time, the first recessed area and the first side wall have an obvious boundary.

[0153] The first side wall 140 has a wrinkle part 141, which is easy to appear in the case of a steep slope, where the steep slope refers to a slope structure with a side wall angle greater than or equal to 25°, for example, it can be 25°-75°. If the slope of the side wall on both sides of the first recessed area 110 is different, the first side wall 140 corresponding to the steep slope side will have a wrinkle part 141.

[0154] Because the silicon substrate is easily retained along the (111) crystal plane during anisotropic etching, the first sidewall 140 is more likely to retain an inclined surface, which is easy to form a structure with a large number of inclined surfaces. This will make it difficult for the passivation or anti-reflection layer on it to be evenly covered. In addition, the surface energy of the (111) crystal plane is relatively high, and defects are easily generated during the deposition of the film layer on it, thereby affecting the passivation effect. By forming the above-mentioned wrinkle portion 141 on the first sidewall 140, more (100) crystal planes will be retained on the first sidewall 140, and the passivation or anti-reflection layer formed thereon will be more uniform, making the dangling bonds on the silicon substrate more easily passivated, thereby effectively reducing surface recombination. At the same time, after reducing the proportion of the (111) crystal plane, the surface recombination rate is reduced, thereby improving the open circuit voltage and conversion efficiency. In addition, the above-mentioned wrinkle portion is also beneficial to improving the light trapping effect when applied to the light-receiving area, reducing reflection and increasing the short-circuit current. The light-receiving area corresponds to the front and / or back of the battery, and can at least correspond to the non-electrode area of ​​the surface.

[0155] In order to facilitate understanding of the applicability of the first sidewall 140 in the first texture structure T1 , the first recessed area 110 extending into a strip shape is taken as an example for description. Figure 15 This is a top SEM image of the first sidewall of another embodiment of the present application, as shown in FIG. Figure 15 As shown, the first texture structure T1 includes a first recessed region 110 and a first raised region 120, with the first raised region 120 adjacent to the first recessed region 110. It can be seen that the first recessed region 110 extends into a stripe shape. The first sidewall 140 has a wrinkle 141, which is easily visible in the SEM image due to the alternating light and dark contrast. Of course, this is not limiting; the first recessed region 110 can also be in an island, square, or other shape.

[0156] According to some embodiments of the present application, the wrinkle portion 141 may include multiple layered structures protruding from the first sidewall 140, stacked along the thickness direction of the silicon substrate to form a linear transverse texture, wherein the linear transverse texture extends in a direction different from the thickness direction of the silicon substrate. Optionally, the multiple layered structures extend along the first direction; and / or the wrinkle portion 141 may include multiple dot-shaped protrusions stacked on the first sidewall 140 to form a scale-like protrusion structure. The term "transverse" herein refers to a direction that is the same as or approximately the same as the direction in which the silicon substrate 100 extends. For example, the angle between the linear transverse texture and the silicon substrate can be greater, as long as the linear transverse texture extends in a direction different from the thickness direction of the silicon substrate.

[0157] By setting the wrinkle part to include a plurality of layered structures or a plurality of point-shaped protrusions, more (100) surfaces are retained, the passivation layer of the (100) surface is more uniform, the dangling bond is more easily passivated, and thus the wrinkle part is more conducive to passivating the surface of the silicon substrate, reducing the surface recombination rate of the carriers, thereby being conducive to improving the open-circuit voltage and conversion efficiency when applied to a solar cell. Moreover, the wrinkle part is more conducive to improving the light trapping effect when applied to a light receiving area, and also helps to improve the contact area with the electrode, thereby improving the collection and transport performance of the carriers. It is worth mentioning that the scale-shaped protrusion structure formed by a plurality of point-shaped protrusions is relatively compact, providing additional mechanical support for the wrinkle part, thereby increasing the mechanical stability of the first recessed area or the first protruding area when the wrinkle part is applied to the first recessed area or the first protruding area, and being conducive to reducing the fragment rate.

[0158] According to an embodiment of the present application, the first side wall 140 can further include a plurality of steps stacked into a ladder-shaped structure along the thickness direction of the silicon substrate, and further optionally, at least part of the plurality of layered structures 1411 or the plurality of point-shaped protrusions 1412 are distributed on the steps. By setting the ladder-shaped structure, the roughness of the first side wall 140 is further improved, thereby being more conducive to improving the light trapping effect when applied to a light receiving area, and further cooperating with the setting of the layered structure or the point-shaped protrusion, being conducive to better balancing the passivation effect and the light trapping effect.

[0159] Exemplarily, Figure 16 The enlarged partial SEM images of the wrinkle part of another embodiment of the present application, wherein (a) is a side view of the wrinkle part including a plurality of layered structures, (b) is a top view of the wrinkle part including a plurality of point-shaped protrusions, (c) is a combination of layered structures and steps, and (d) is a combination of point-shaped protrusions and steps. Figure 16 (a) shows that the wrinkle part 141 includes a plurality of layered structures 1411, and the plurality of layered structures 1411 are stacked into a linear lateral texture; (b) shows that the wrinkle part 141 includes a plurality of point-shaped protrusions 1412, and the plurality of point-shaped protrusions 1412 are stacked into a scale-shaped protrusion structure; (c) shows a combination of the plurality of layered structures 1411 stacked into a linear lateral texture and the plurality of steps 142 stacked into a ladder-shaped structure, and it can be observed that the layered structures 1411 are also distributed on the steps 142; (d) shows a combination of the point-shaped protrusions 1412 forming a scale-shaped protrusion structure and the plurality of steps 142 stacked into a ladder-shaped structure, and it can be observed that the point-shaped protrusions 1412 are also distributed on the steps 142.

[0160] According to some embodiments of the present application, when the first recessed area 110 extends continuously or discontinuously into a strip shape, the first sidewall 140 may extend continuously or discontinuously into a line shape. Of course, this is not limited to this. For example, when the first recessed area 110 is in the shape of an island, the first sidewall 150 may extend into a ring shape or a C shape, or when the first raised area 120 is in the shape of an island, the first sidewall 150 may extend into a ring shape or a C shape. Further optionally, the line shape includes a combination of one or more of a straight line shape, a curved line shape, and a broken line shape. The above-mentioned "line shape" means that the length of the first sidewall 150 in the extension direction is greater than the width perpendicular to its extension direction. For example, the ratio of its length to width may be at least greater than 5:1, 10:1, or 20:1, and further, may be less than 200:1, 100:1, etc. Generally speaking, the ratio of the length to width of a linear structure is greater than the ratio of the length to width of a strip-shaped structure. The width of the first sidewall 150 , unless otherwise specified, generally refers to the width of the first sidewall 150 directly measured by, for example, SEM at a top-down perspective on the silicon substrate or the battery surface.

[0161] For example, Figure 17 This is a top SEM image of a first sidewall extending continuously or discontinuously in another embodiment of the present application, wherein (a) is a linear continuous extension, (b) is a linear discontinuous extension, (c) is an extension in a ring shape, and (d) is an extension in a C shape. Figure 17 Figure (a) shows that the first recessed area 110 extends continuously into a strip shape, while the first sidewall 140 extends continuously in a linear shape. Specifically, it can extend into a combination of a straight line and a curved line. Figure (b) shows that the first recessed area 110 extends discontinuously into a strip shape, while the first sidewall 140 extends discontinuously in a linear shape. Specifically, it can extend into a combination of a straight line and a broken line. Figure (c) shows that the first recessed area 110 is in an island shape, while the first sidewall 140 extends into a ring shape. Figure (d) shows that the first raised area 120 is in an island shape, while the first sidewall 140 extends into a C-shape.

[0162] According to some embodiments of the present application, Figure 16 As shown in FIG. 1 (a), the wrinkled portion 141 may include multiple layered structures 1411 stacked along the thickness direction of the silicon substrate to form a linear transverse texture; the extension length of a single layered structure 1411 is greater than the thickness of the single layered structure 1411. Thus, in the layered stacking structure, by regulating the transverse dimension of the layered structure to be greater than the longitudinal dimension, it is beneficial to promote the dominance of the (100) crystal plane, reduce the proportion of the (111) crystal plane, and improve the uniformity and integrity of the passivation layer.

[0163] According to the embodiment of the present application, Figure 16As shown in Figure (b), the height of the flaky protrusion structure protruding in the direction away from the first side wall 140 is 0.1~1μm, for example, it can be 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1.0μm, etc. In this way, in the flaky protrusion structure, by regulating the height of its protrusion, it is beneficial to regulate the (100) crystal plane to have a suitable proportion, thereby improving the uniformity and integrity of the passivation layer.

[0164] According to some embodiments of the present application, the wrinkle portion 141 located on the first sidewall 140 may include multiple layered structures 1411 stacked along the thickness direction of the silicon substrate to form a linear transverse texture. The first texture structure T1 may also include: a gentle slope adjacent to the first sidewall 140, the other side of the gentle slope connected to a steep slope, and may also be connected to the first texture structure T2. The surface of the gentle slope has gentle hillock stripes, which intersect or are not aligned with the linear transverse texture. Here, the meaning of "gentle slope" refers to a slope structure with a slope angle or inclination greater than 0 and less than 25° based on the extension direction of the surface of the silicon substrate 100.

[0165] One side of the gentle slope is adjacent to the first side wall 140, and the other side of the gentle slope can be connected to the steep slope, that is, the gentle slope can be part of the first texture structure T1, and the corresponding first side wall has a different inclination angle, and only the first side wall corresponding to the steep slope has a wrinkle portion, and there is no wrinkle portion on the surface of the gentle slope; of course, the other side of the gentle slope can also be connected to the first texture structure T2, that is, the gentle slope is part of the first texture structure T2, and the corresponding first recessed area is located at the intersection of the first texture structure T1 and the first texture structure T2.

[0166] For example, Figure 16 As shown in FIG. 1 (a), taking the gentle slope as part of the first texture structure T1 as an example, the first texture structure T1 may include a gentle slope 121 adjacent to the first sidewall 140. The figure does not show the steep slope connected to the other side of the gentle slope 121. The gentle slope surface 1211 has gentle hillock stripes 1212, which intersect or are not aligned with the linear transverse texture.

[0167] In this way, since the gentle slope 121 is adjacent to the first side wall 140, and there are gentle hill stripes on the surface 1211 of the gentle slope that intersect or project the linear transverse lines, on the one hand, it is beneficial for light to reach the first side wall and the first recessed area smoothly when applied to the light receiving area, and after multiple refractions and reflections on the first side wall, the light trapping effect is improved. On the other hand, when making electrodes on the silicon substrate, it is beneficial to guide the electrode slurry to fully contact the first side wall, thereby improving the contact performance of the electrode.

[0168] According to some embodiments of the present application, the slope angle of the first side wall 140 is greater than the slope angle of the gently sloping surface 1211; and / or, the slope angle of the first side wall 140 can be, for example, greater than or equal to 25° and less than or equal to 75°, for example, it can be 25°, 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, etc.; and / or, the slope angle of the gently sloping surface 1211 can be, for example, less than 25° and greater than 2°, and further can be 3°, 5°, 8°, 10°, 12°, 15°, 18°, 20°, 23°, 24°, etc.

[0169] In this way, by setting the slope of the first sidewall within a suitable range, it is possible to better balance the light trapping effect when applied to the light-receiving area and the uniformity of the deposition of the film layer on the first sidewall, such as the passivation layer. By setting the slope of the gentle slope within a suitable range, it is possible to alleviate thermal stress concentration and avoid subsequent high-temperature processes that cause the film layer to break. As a result, the first sidewall is more conducive to improving the light trapping effect when applied to the light-receiving area, and the gentle slope is more conducive to improving the quality of the passivation layer, thereby balancing the passivation effect and the light trapping effect. The light-receiving area corresponds to the front and / or back of the battery, and can at least correspond to the non-electrode area of ​​the surface.

[0170] According to the embodiments of the present application, Figure 18 This is a top view SEM image of the first sidewall bifurcated structure and the second sidewall bifurcated structure according to another embodiment of the present application. Figure 18 As shown, the first side wall 140 is further provided with: a first side wall bifurcation structure 150, which includes a first sub-side wall 151 extending from the first side wall 140 toward the inside of the first recessed area 110; the first side wall 140 is further provided with: a second side wall bifurcation structure 160, which includes a second sub-side wall 161 extending from the first side wall 140 toward the inside of the first raised area 120.

[0171] In this way, by setting the first sidewall bifurcation structure 150 and / or the second sidewall bifurcation structure 160, it is beneficial to further increase the roughness of the first recessed area and / or the first raised area. On the one hand, it is beneficial to improve the light trapping effect when applied to the light receiving area, wherein the light receiving area corresponds to the front and / or back of the battery, and can at least correspond to the non-electrode area of ​​the surface. On the other hand, when making electrodes on the silicon substrate 100, it is beneficial to improve the bonding force of the electrode slurry, thereby improving the contact performance of the electrode.

[0172] Further optionally, the first sub-sidewall 151 and / or the second sub-sidewall 161 each have a plurality of dot-shaped protrusions, a plurality of layered structures, and / or a plurality of steps. The dot-shaped protrusions, layered structures, or steps on the first sidewall bifurcated structure 150 and the second sidewall bifurcated structure 160 can have similar extension directions and stacking morphologies as those on the first sidewall 140, and therefore are not further described here.

[0173] Thus, based on the point protrusions and / or layered structures on the first sub-side wall 151 and / or the second sub-side wall 161, it is beneficial to promote (100) the crystal plane to dominate, reduce (111) the crystal plane ratio, and improve the uniformity and integrity of the passivation layer. Thus, the balance between passivation effect and light trapping effect is considered.

[0174] According to some embodiments of the present application, one side of the first recessed area 110 is adjacent to a first side wall 140, and the other side can be adjacent to another first side wall 140 or adjacent to a gentle slope 121.

[0175] Exemplarily, Figure 19 A top view SEM of the first texture structure according to another embodiment of the present application is shown in FIG. 1C. As shown in FIG. 1C, one side of the first recessed area 110 is adjacent to a first side wall 140, and the other side can be adjacent to another first side wall 140. It can be understood that one of the first side walls 140 adjacent to the first recessed area 110 can be replaced by a gentle slope 121. Figure 19 Thus, in the case where the two sides of the first recessed area 110 are adjacent to the first side wall 140, the light trapping effect when applied to the light receiving area can be better improved, and in the case where one side of the first recessed area 110 is adjacent to the first side wall 140 and the other side is adjacent to the gentle slope 121, the film layer deposition uniformity is considered and the passivation effect is ensured.

[0176] According to an embodiment of the present application, the surface of the silicon substrate 100 can further include a first texture structure T2. Here, the first texture structure T2 is different from the first texture structure T1, for example, the first texture structure T1 can be used to represent a deep line mark area, and the first texture structure T2 can be used to represent a shallow line mark area, and for another example, the first texture structure T1 can be used to represent an abrupt slope area, and the first texture structure T2 can be used to represent a gentle slope area.

[0177] The flatness n3 of the first texture structure T2 is greater than the flatness n2 of the first side wall 140 and less than the flatness n1 of the first recessed area 110. Exemplarily, as shown in FIG. 1D,

[0178] Figure 19 As can be seen, the first texture structure T2 has a relatively gentle tower base structure, and the flatness n3 thereof is smaller than the flatness n1 of the relatively flat first recessed area 110, and the first side wall 140 has a wrinkle part 141, so that the flatness n2 thereof is smaller than the flatness n3 of the first texture structure T2, that is, the first recessed area 110 is the flattest, the first texture structure T2 is the second flattest, and the first side wall 140 is the roughest.

[0179] ​​At this time, since the second texture structure occupies most of the area of the surface of the silicon substrate, the flatness thereof needs to be ensured to facilitate the improvement of the deposition quality of the film layer, such as film layer uniformity, and also to ensure a certain degree of relief to balance the light trapping effect when applied to the light receiving area. The light receiving area corresponds to the front and / or back of the cell, and can at least correspond to the non-electrode area of the surface. Since the first side wall 140 is in a slope shape, in the process of forming the first side wall 140 by wet etching, it is easier to adsorb additives in the etching solution, which causes the (111) crystal plane to be easily etched, and more (100) and (110) crystal planes are retained. Since the (100) and (110) crystal planes are more conducive to the growth of the film layer thereon, they are also conducive to the growth quality of the film layer in the case of low flatness. Therefore, by controlling the flatness to satisfy the above relationship, the deposition uniformity of the film layer, such as the passivation or anti-reflection layer, can be balanced, while the passivation effect and the light trapping effect when applied to the light receiving area are ensured.

[0180] According to some embodiments of the present application, Figure 20 FIG. 2 shows a top SEM image of a second texture structure according to another embodiment of the present application, wherein (a) and (b) are different morphology examples of a second recessed area, (c) is a second texture structure marked on (a), and (d) is a second texture structure marked on (b). As shown in (a) and (b), at least part of the first texture structure T2 has an arc-shaped profile and / or a polygonal profile substructure, and the substructure has a second recessed area 210. Adjacent second recessed areas 210 overlap to form a second protruding area 220. The polygonal shape has a side length greater than 4, such as a pentagon, a hexagon, a heptagon, and the like. As shown in (c) and (d), the second recessed area 210 on the left side is in a staggered distribution, forming a staggered arc-shaped tower base structure. As shown in (e) and (f), the second recessed area 210 on the right side is in a strip-shaped tower base structure. Figure 20 Figure 20 As shown in (a) and (c) of FIG. 2, the plurality of second recessed areas 210 on the left side are in a staggered distribution, forming a staggered arc-shaped tower base structure. As shown in (b) and (d) of FIG. 2, the second recessed area 210 forms an independent arc-shaped tower base structure. Of course, it is not limited to the arc-shaped tower base structure, and the second recessed area 210 on the right side is in a strip-shaped tower base structure. Figure 20

[0181] In this way, at least part of the first texture structure T2 has an arc-shaped profile or a polygonal profile substructure. Compared with the traditional tower base structure, the average included angle is larger, the angle is more gentle, and it is more conducive to the improvement of the uniformity of the film layer quality, such as the passivation or anti-reflection layer, on the silicon substrate 100, thereby improving the passivation performance. It is worth mentioning that the second texture structure cooperates with the wrinkle part to balance the film layer uniformity, the passivation effect, and the light trapping effect when applied to the light receiving area.

[0182] According to some embodiments of the present application, Figure 21 FIG. 3 shows a side SEM image of a second texture structure according to another embodiment of the present application; and Figure 21 FIG. 4 shows a side SEM image of a second texture structure according to another embodiment of the present application.​​Figure 20 As shown in (a) and (b) of FIG. 1, the first texture structure T2 can also have a gentle slope, where the meaning of "gentle slope" is the same as the aforementioned and will not be repeated. Exemplarily, as shown in (a) and (b) of FIG. 2, the slope angle of the gentle slope is 16.9°. In this way, the sub-structure with the gentle slope can alleviate the thermal stress concentration problem and avoid the film layer from being broken due to subsequent high-temperature processes. Figure 21

[0183] According to some embodiments of the present application, the surface of the gentle slope of the first texture structure T1 and / or the second texture structure can further have a sub-structure with an arc-shaped profile or a polygonal profile. Similarly to the foregoing, the sub-structure has a plurality of second recessed regions 210, and the second recessed regions 210 can overlap to form a second protruding region 220. It can be understood that the gentle slope here can be part of the first texture structure T1 or part of the first texture structure T2.

[0184] According to some embodiments of the present application, the area ratio of the region where the sub-structure with the arc-shaped profile is located to the surface of the silicon substrate is 3% to 40%, for example, can be 3%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, etc. By adjusting the area ratio of the region where the sub-structure with the arc-shaped profile is located to the surface of the solar cell within the above suitable range, it is more conducive to ensuring the improvement of the passivation effect.

[0185] According to some embodiments of the present application, as shown in (a) and (b) of FIG. 3, at least part of the second protruding region 220 has a protruding end 221 protruding outwardly from the silicon substrate 100, and the surface of the protruding end 221 is a smooth transition surface. Figure 21 In this way, the second protruding region between adjacent second recessed regions has a smooth protruding structure, which can reduce defects such as lattice mismatch at the interface, thereby reducing the recombination loss and improving the passivation effect. Moreover, the smooth protruding structure is conducive to forming a more continuous film layer such as a passivation layer, reducing the leakage point, and when applied to the light-receiving region, it is also conducive to light scattering and trapping, increasing the path length of light in the cell, thereby improving the photoelectric conversion efficiency.

[0186] According to some embodiments of the present application, the first side wall 140 extends along a first direction, and in a second direction intersecting the first direction, the width of the first side wall 140 on the surface of the silicon substrate can be 0.5 to 3 μm, for example, can be 0.5 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2.0 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, etc. Exemplarily, as shown in (a) and (b) of FIG. 4, the width of the first side wall 140 on the surface of the silicon substrate is 1.5 μm. Figure 15 ​As shown, the width of the first sidewall 140 on the surface of the silicon substrate 100 is 2.428 μm, 2.926 μm. The depth of the first sidewall 140 in the thickness direction of the silicon substrate can be 0.1-10 μm, for example, 0.1 μm, 0.2 μm, 0.4 μm, 0.6 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, 2.0 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc. Within a width range of 100 μm along the second direction, the number of the first sidewall 140 can be 1-200, for example, 1, 2, 5, 10, 15, 18, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 90, 100, 110, 120, 130, 140, 150, 160, 170, 180, 200, etc. By controlling the size of the first sidewall within a suitable range, the balance between light trapping effect and passivation effect can be considered when the silicon substrate is applied to the light receiving area.

[0187] According to some embodiments of the present application, the first sidewall 140 extends along the first direction, and the extension length of the first sidewall 140 in the first direction S1 is greater than or equal to 2 μm, and further can be less than or equal to 300 μm, for example, 2 μm, 5 μm, 10 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm, etc. In this way, by setting the extension length of the first recessed area 110 in the first direction within the above suitable range, it is beneficial to guide the directional flow of the electrode paste when the electrode is made on the silicon substrate, and it is beneficial to shape the paste so that the paste is better combined on the silicon substrate, and the electrode pull-off force is improved. At the same time, it avoids the extension length of the first recessed area being too long to cause local stress concentration, and it is beneficial to reduce the risk of breakage.

[0188] According to some embodiments of the present application, since the film layer on the (111) crystal surface is generally thick, by setting the first texture structure with the first side wall, the proportion of the (111) crystal surface can be reduced, thereby facilitating the improvement of the uniformity of the film layer deposited on the silicon substrate or the uniformity of the film layer. And even in the case of reducing the thickness of the film layer on the silicon substrate, the uniformity of the film layer can still be controlled within a suitable range. The film layer includes but is not limited to one or more of the interface passivation layer, the doped conductive layer, the passivation layer, and the anti-reflection layer. For the measurement of the uniformity of the film layer on the surface of the silicon substrate, the present application does not make any limitation, and those skilled in the art can determine it by the conventional method in the art. For example, the thickness of the film layer such as the doped conductive layer, the passivation layer or the anti-reflection layer on the silicon substrate in the measurement area can be measured by SEM, and the uniformity of the film layer can be calculated according to the measured thickness. Specifically, a plurality of sampling points are selected randomly or at a fixed interval in the measurement area to measure the thickness, and the uniformity is calculated according to the maximum value, the minimum value and the average value such as the arithmetic mean value of the plurality of measured thicknesses, wherein the uniformity = (thickness maximum value - thickness minimum value) / (2 * average thickness).

[0189] According to some embodiments of the present application, the uniformity of the film layer such as the doped conductive layer, the passivation layer or the anti-reflection layer on the silicon substrate is less than 10%, for example, it can be 0%, 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, etc., and further can be less than 5%. Wherein with the increase of the uniformity value, the worse the uniformity of the film layer is.

[0190] Exemplarily, Figure 22 The side view SEM images of the film layer on the silicon substrate according to the embodiments of the present application are shown, wherein (a) is the film layer on the silicon substrate with the traditional tower base structure, and (b) is the film layer on the silicon substrate with the first texture structure of the present application. As shown in Figure 22 The uniformity of the doped conductive layer on the silicon substrate based on the traditional tower base structure and the doped conductive layer on the silicon substrate based on the first texture structure is comparable, and is close to 0% respectively; the uniformity of the passivation or anti-reflection layer on the silicon substrate based on the traditional tower base structure is 10%, and the uniformity of the passivation or anti-reflection layer on the silicon substrate based on the first texture structure is 4.8%. This shows that compared with the traditional tower base structure, the first texture structure of the present application can significantly improve the uniformity of the film layer on the silicon substrate, especially the passivation or anti-reflection layer.

[0191] According to some embodiments of the present application, further, in order to regulate the formation of the wrinkle part 141 on the first side wall 140 of the first texture structure T1 of the silicon substrate, before polishing the original silicon substrate with the polishing alkali solution, the operation of texturing the original silicon substrate can also be included. The specific operation of polishing is the same as described above, and will not be repeated here.

[0192] According to some embodiments of the present application, when texturing the original silicon substrate, the texturing temperature is 60-80℃, for example, it can be 60℃, 65℃, 70℃, 75℃, 80℃, etc., the texturing time is 100-1000 s, for example, it can be 100 s, 200 s, 300 s, 350 s, 400 s, 450 s, 500 s, 550 s, 600 s, 700 s, 800 s, 900 s, 1000 s, etc.; the texturing alkali solution includes 0.5-10wt% (for example, it can be 0.5wt%, 1wt%, 5wt%, 10wt%, etc.) NaOH and 0.1-2wt% (for example, it can be 0.1wt%, 0.2wt%, 0.5wt%, 0.8wt%, 1.0wt%, 1.3wt%, 1.5wt%, 1.8wt%, 2.0wt%, etc.) texturing additives. The texturing additives can include surfactants, defoamers, nucleating agents, corrosion inhibitors and dispersants.

[0193] According to the embodiments of the present application, as shown in Figure 23 The solar cell can further include: a plurality of electrodes 200 located on at least one surface of the silicon substrate 100, each of the electrodes 200 extending along a direction identical or substantially identical to the first direction S1 and being spaced apart along the second direction S2. Here, the direction identical or substantially identical means that the included angle between the extending direction of the electrode 200 and the first direction S1 is less than 45°, optionally less than 30°, and further optionally less than 10°. Here, the electrode 200 refers to a current collecting electrode which forms an ohmic contact with the doped semiconductor layer.

[0194] In this way, by setting the electrode 200 to be identical or substantially identical to the extending direction of the first recessed area 110 or the first side wall 140, the moire of the electrode 200 can be avoided, and the appearance of the moire will increase the local resistance of the electrode 200, which is easy to cause damage to the electrode 200.

[0195] It can be understood that when the solar cell is rectangular, the first direction S1 can be substantially parallel to the direction of the long side of the solar cell. At this time, further optionally, the electrode 200 can be a current collecting electrode, and the current collecting electrode is suitable for connecting a current collecting structure, such as a current collecting electrode or other current collecting structures such as a solder strip. When other current collecting structures are subsequently welded on the current collecting electrode or the current collecting electrode, since the application direction of the welding force is not consistent with the extending direction of the first recessed area, it is not easy to cause the cell to crack.

[0196] According to an embodiment of the present application, in the second direction S2, the number of first recessed regions 110 covered by one electrode 200 is 1 to 20, for example, 1, 2, 5, 8, 10, 12, 15, 18, or 20. By regulating the distribution density of the first recessed regions 110 within an appropriate range, it is advantageous to adjust the surface roughness of the silicon substrate 100 to an appropriate level, thereby taking into account the light trapping effect, film deposition quality, and electrode quality, and improving the electrical contact performance between the doped conductive layer and the electrode 200.

[0197] According to an embodiment of the present application, the electrode 200 may be made of copper, silver-coated copper, aluminum, or silver, and may be produced by printing, electrodeposition, or the like. For example, a metal paste may be printed onto the silicon substrate 100, and then the metal paste may be sintered to achieve metallization. The printing method may be, for example, screen printing or inkjet printing, with screen printing being preferred as the more cost-effective method.

[0198] According to further embodiments of the present application, the solar cell may further include a laminated film 102 disposed on at least one side of the silicon substrate 100, specifically, disposed within or on the surface of the silicon substrate 100. Because the surface of the silicon substrate 100 has a first texture structure T1, and a conformal structure exists after the laminated film is disposed on the surface of the silicon substrate 100, the solar cell also has the same or a similar first texture structure. Thus, the first texture structure based on the first recessed region 110 and the first raised region 120 of the silicon substrate 100 is conducive to improving the film formation quality of the doped conductive layer and enhancing the passivation effect.

[0199] Here, the laminated film 102 is adapted to selectively transport carriers, such as electrons or holes. When the laminated film 102 is adapted to selectively transport electrons, it is located in the N region; when it is adapted to selectively transport holes, it is located in the P region. Optionally, the laminated film 102 may include a doped conductive layer and a passivation or anti-reflection layer. Furthermore, the doped conductive layer may be made of at least one semiconductor material selected from the group consisting of single-crystal silicon, amorphous silicon, polycrystalline silicon, and microcrystalline silicon.

[0200] In some embodiments, for example, the doped conductive layer may be deposited on the surface of the silicon substrate 100 by a chemical vapor deposition process. In other embodiments, for example, the doped conductive layer may be obtained within the surface of the silicon substrate 100 by a doping process.

[0201] For the convenience of understanding the structure of the laminated film 102, the laminated film 102 can include a first doped conductive layer 1021, which is arranged on one side surface of the silicon substrate 100 or on the surface of the silicon substrate 100 in a full-area manner or in a spaced manner. The first doped conductive layer 1021 can be, for example, an N-type doped conductive layer, and the corresponding laminated film 102 is located in an N region, or the first doped conductive layer 1021 can be, for example, a P-type doped conductive layer, and the corresponding laminated film 102 is located in a P region; for example, N-type doping can be realized by introducing a donor impurity such as a VA element (e.g., phosphorus (P), arsenic (As), or antimony (Sb)) into a semiconductor material; or P-type doping can be realized by introducing an acceptor impurity such as a IIIA element (e.g., boron (B), aluminum (Al), or gallium (Ga)) into the aforementioned semiconductor material.

[0202] Further optionally, the laminated film 102 can further include a second doped conductive layer 1022, which is arranged on the same side or the opposite side of the silicon substrate 100 or on the surface of the silicon substrate 100. The second doped conductive layer 1022 and the first doped conductive layer 1021 are opposite in conductive type. For example, as shown in FIG. 1B, the first doped conductive layer 1021 and the second doped conductive layer 1022 are arranged on the opposite surfaces of the silicon substrate 100, and the corresponding solar cell is a double-sided contact cell; however, the first doped conductive layer 1021 and the second doped conductive layer 1022 can be arranged on the same surface of the silicon substrate 100 in an alternating manner, and the corresponding solar cell can be a back contact cell. Figure 22

[0203] At this time, the first texture structure T1 can be located on the surface of the silicon substrate 100 corresponding to the laminated film 102, for example, on the surface of the silicon substrate 100 corresponding to the first doped conductive layer 1021, or on the surfaces of the silicon substrate 100 corresponding to the first doped conductive layer 1021 and the second doped conductive layer 1022.

[0204] In another optional embodiment, the laminated film 102 can include a plurality of doped conductive layers arranged on one side surface of the silicon substrate 100 or on the surface of the silicon substrate 100, each extending in a direction substantially the same as the first direction S1 and being spaced apart along the second direction S2.

[0205] Further optionally, the plurality of doped conductive layers can be the first doped conductive layer 1021, which is further optionally an N-type or P-type doped polysilicon layer, to form a poly-finger structure in cooperation with the electrode 200. Alternatively, the plurality of doped conductive layers can include the first doped conductive layer 1021 and the second doped conductive layer 1022 arranged in an alternating manner, to form a back contact structure in cooperation with the electrode 200.

[0206] ​According to some embodiments of the present application, for the poly-finger structure or the back contact structure, the number of the first recessed regions on the doped conductive layer in the second direction is 10-100, for example, 10, 20, 30, 40, 50, 60, 80, 90, 100, etc. By setting the number of the first recessed regions 110 on the doped conductive layer in the above range, the passivation effect can be effectively improved.

[0207] According to some embodiments of the present application, the laminated film 102 can further include an interface passivation layer between the silicon substrate 100 and the doped conductive layer, for selectively passing the carriers and achieving the field passivation effect, and improving the carrier separation and collection efficiency. For example, the interface passivation layer can be aluminum oxide, silicon oxide, titanium oxide, amorphous silicon, etc., and can form a tunnel oxide passivation contact (TOPCon) structure or a heterojunction contact structure with the doped conductive layer.

[0208] At this time, the interface passivation layer can be prepared by low-temperature chemical vapor deposition (LPCVD), and the thickness can be 0.5-10 nm, for example, 0.5 nm, 1 nm, 2 nm, 4 nm, 6 nm, 8 nm, 10 nm, etc.

[0209] According to some embodiments of the present application, the laminated film 102 can further include a passivation or anti-reflection layer on the surface of the first doped conductive layer and / or the second doped conductive layer away from the silicon substrate 100. The passivation or anti-reflection layer can have the protection and passivation effects on the underlying silicon substrate or functional layer, for example, the P-type doped conductive layer or the N-type doped conductive layer, and the anti-reflection effect on the light incident to the first surface 101a or the second surface 101b. For example, the passivation or anti-reflection layer can be a single-layer film of silicon dioxide, aluminum oxide, silicon nitride or silicon oxynitride, or a laminated film of one or more combinations of the foregoing materials.

[0210] According to some embodiments of the present application, the laminated film 102 can further include a transparent conductive layer (not shown in the figure) on the surface of the first doped conductive layer and / or the second doped conductive layer away from the silicon substrate 100. The transparent conductive layer can improve the carrier transport effect of the laminated film 102. For example, the transparent conductive layer can be indium tin oxide (ITO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), carbon nanotubes or graphene, etc.

[0211] According to embodiments of the present application, the electrode 200 can include a first electrode 201 and a second electrode 202, wherein the first electrode 201 is located on a surface of the first doped conductive layer 1021 away from the silicon substrate 100 and in electrical contact with the first doped conductive layer 1021; and the second electrode 202 is located on a surface of the second doped conductive layer 1022 away from the silicon substrate 100 and in electrical contact with the second doped conductive layer 1022.

[0212] According to some embodiments of the present application, for example, in the case that the solar cell is a back contact cell, the stack film 102 can include N-type doped conductive layers and P-type doped conductive layers arranged alternately on one side of the silicon substrate. Due to the difference in the doping concentration between the P-type doped conductive layer and the N-type doped conductive layer, the passivation effect and the electrical contact performance are different. Therefore, the first texture structure T1 includes a plurality of first recessed regions 110 extending in a strip shape along the first direction S1. The first recessed regions 110 on the P-type doped conductive layer are more sparsely distributed than the first recessed regions 110 on the N-type doped conductive layer on the one side surface of the silicon substrate 100. This can be beneficial to the balance of the carrier transmission between the N-type stack film and the P-type stack film.

[0213] For example, the number of the first recessed regions 110 on the P-type doped conductive layer can be less than the number of the first recessed regions 110 on the N-type doped conductive layer; and / or, the distance between two adjacent first recessed regions 110 on the P-type doped conductive layer can be greater than the distance between two adjacent first recessed regions 110 on the N-type doped conductive layer; and / or, the number of the protrusions 111 in the first recessed regions 110 on the P-type doped conductive layer can be less than the number of the protrusions 111 in the first recessed regions 110 on the N-type doped conductive layer. Similarly, the number of the first protruded regions 120 has the same distribution rule as the number of the recesses including the first recess 112, the second recess 113 and / or the third recess 114 in the first recessed regions 110.

[0214] According to some embodiments of the present application, in the case that the solar cell is a back contact cell, the influence of the first texture structure on the passivation effect of the N-type doped conductive layer or the P-type doped conductive layer is more concerned. Since the N-type or P-type doped conductive layer can be deposited conformally on the surface of the silicon substrate 100, the surface of the N-type or P-type doped conductive layer also has a similar first texture structure as the surface of the silicon substrate 100, i.e., can have adjacent first recessed regions 110 and first protruded regions 120, and further can have first side walls 140 between the first recessed regions 110 and the first protruded regions 120, which will not be described one by one.

[0215] Since the doping concentration of the P-type doped conductive layer is lower than that of the N-type doped conductive layer, the passivation effect and the electrical contact performance are different. Therefore, in an optional embodiment, the roughness of the first sidewall in the first texture structure T1 corresponding to the N-type doped conductive layer on one side surface of the silicon substrate 100 can be greater than the roughness of the first sidewall in the first texture structure T1 corresponding to the P-type doped conductive layer, for example, the first sidewall corresponding to the N-type doped conductive layer can be provided with more layer structures, point protrusions or steps, etc. in number or size. This is more conducive to improving the passivation and contact effect of the P region and reducing the difference in passivation and contact performance between the P region and the N region.

[0216] In another optional embodiment, the number of the first sidewall 140 in the first texture structure T1 corresponding to the P-type doped conductive layer on one side surface of the silicon substrate can be greater than the number of the first sidewall 140 in the first texture structure T1 corresponding to the N-type doped conductive layer. This is more conducive to improving the light utilization of the P region and generating more photo-generated carriers. This can be conducive to the balance of carriers between the N region and the P region and improve the problem of current mismatch in different regions.

[0217] According to some embodiments of the present application, in the case of a bifacial contact solar cell, the laminated film 102 can include a first doped conductive layer 1021 and a second doped conductive layer 1022. The first doped conductive layer 1021 can be provided on one side of the surface of the silicon substrate 100, or the first doped conductive layer 1021 can be arranged at intervals on one side of the surface of the silicon substrate 100, and the first doped conductive layer 1021 between adjacent first doped conductive layers 1021 can have a first interval, which can form a poly-finger structure together with the electrode 200; the second doped conductive layer 1022 can be provided on the other side of the surface of the silicon substrate 100, or the second doped conductive layer 1022 can be arranged at intervals on the other side of the surface of the silicon substrate 100, and the second doped conductive layer 1022 between adjacent second doped conductive layers 1022 can have a second interval, which can form a poly-finger structure together with the electrode 200.

[0218] Similarly, the surface of the silicon substrate of the bifacial contact solar cell corresponding to the first doped conductive layer 1021 and the second doped conductive layer 1022 can also have a first texture structure T1, the first texture structure T1 including adjacent first recessed regions 110 and first protruding regions 120, further, the first recessed regions 110 can extend in a strip shape, and / or can also have first sidewalls 140 between the first recessed regions 110 and the first protruding regions 120, which will not be described one by one. At this time, for the bifacial contact solar cell, the front surface of the solar cell generally pays more attention to generating more photo-generated carriers, and the back surface of the solar cell pays more attention to the passivation and contact performance, therefore, the structure of the first texture structure T1 corresponding to the front surface or the back surface of the solar cell can be set to meet the different requirements for light trapping, passivation and contact performance at the front surface and the back surface of the solar cell.

[0219] In an alternative embodiment, as shown in FIG. 1B, the second doped conductive layer 1022 is formed on the other side surface of the silicon substrate 100, for example, by diffusing to form a doped conductive layer on the surface of the silicon substrate 100, and the first doped conductive layer 1021 is formed on the one side surface of the silicon substrate 100, for example, by diffusing to form a doped conductive layer on the surface of the silicon substrate 100. In this case, the first doped conductive layer 1021 is located on the front side of the cell, and the second doped conductive layer 1022 is located on the back side of the cell. Figure 23

[0220] Optionally, the first texture structure T1 of the present application can be located on the back side of the cell, that is, the one side surface of the silicon substrate corresponding to the first doped conductive layer 1021 has the first texture structure T1, and the front side of the cell has a pyramid structure, that is, the other side surface of the silicon substrate corresponding to the second doped conductive layer 1022 has a pyramid structure. In this way, the first texture structure T1 and the pyramid structure of the present application form a synergistic effect, which is beneficial to improve the light absorption of long-wave. The first texture structure T1 can include adjacent first recessed regions 110 and first raised regions 120, and further, the first recessed regions 110 can extend in a strip shape, and / or the first texture structure T1 can further include first side walls 140 between the first recessed regions 110 and the first raised regions 120, which will not be described one by one.

[0221] Further optionally, the pyramid structure includes a tower bottom and a tower top arranged along the direction away from the surface of the cell body, the horizontal size of the tower bottom is 0.5-2.5 μm, for example, it can be 0.5 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2.0 μm, 2.2 μm, 2.5 μm, etc., and / or the height between the tower bottom and the tower top is 0.5-2 μm, for example, it can be 0.5 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2.0 μm, etc.; and / or the top angle of the tower top is 70-85°, for example, it can be 70°, 72°, 75°, 78°, 80°, 82°, 85°, etc.

[0222] In another alternative embodiment, as shown in FIG. 1C, the first doped conductive layer 1021 is formed on the one side surface of the silicon substrate 100, for example, by diffusing to form a doped conductive layer on the surface of the silicon substrate 100, and the second doped conductive layer 1022 is formed on the other side surface of the silicon substrate 100, for example, by diffusing to form a doped conductive layer on the surface of the silicon substrate 100. In this case, the second doped conductive layer 1022 is located on the front side of the cell, and the first doped conductive layer 1021 is located on the back side of the cell. Figure 24 The overall structure of the solar cell of another embodiment of the present application is shown in FIG. 1C. Figure 24 ​As shown, the second doped conductive layer 1022 is located within the surface of the other side of the silicon substrate 100, for example, by doping the surface of the silicon substrate 100 through a diffusion process. In this case, the second doped conductive layer 1022 is located on the front side of the cell, while the first doped conductive layer 1021 is arranged at intervals on the back side of the cell. For example, the first doped conductive layer 1021 forms a poly-finger structure, and in this case, the first doped conductive layer 1021 is located on the surface of one side of the silicon substrate 100. The first texture structure T1 includes a plurality of first recessed regions 110 extending in a first direction S1 in a strip-shaped pattern, corresponding to the first doped semiconductor layer on the silicon substrate. The first recessed regions in the first texture structure T1 on the surface of the silicon substrate corresponding to the areas outside the poly-finger (i.e., the first spacers between adjacent first doped semiconductor layers) are denser than those in the first texture structure T1 corresponding to the first doped semiconductor layer (i.e., the poly-finger). This improves light trapping in areas outside the poly-finger, passivation in the poly-finger region, and film deposition quality.

[0223] In yet another optional embodiment, Figure 25 This is a schematic diagram of the overall structure of a solar cell according to another embodiment of the present application. Figure 25 As shown, the entire first doped conductive layer 1021 is located on one side of the silicon substrate 100. In this case, the first doped conductive layer 1021 is located on the back side of the cell, for example, the first doped conductive layer 1021 has a TOPCon structure. The second doped conductive layer 1022 is arranged at intervals on the front side of the cell, for example, the second doped conductive layer has a polyfinger structure. The first texture structure T1 may include a plurality of first recessed regions 110 extending in a first direction S1 in a strip shape, at least corresponding to the first doped conductive layer 1021 and the second doped conductive layer 1022 on the silicon substrate. Optionally, the second doped conductive layer 1022 is a P-type doped layer, and the first doped conductive layer 1021 is an N-type doped layer. The first texture structure T1 on the other side of the silicon substrate 100 corresponding to the second doped conductive layer 1022 is more sparsely distributed than the first texture structure T1 on the one side of the silicon substrate 100 corresponding to the first doped conductive layer 1021. This improves the passivation effect of the P-type doped layer and reduces the difference in passivation effect between the P and N regions. The dense distribution of the first recessed areas in the first texture structure T1 can, for example, have the same distribution pattern as described above in terms of the number of first recessed areas 110, the spacing between two adjacent first recessed areas 110, the number of protrusions 111, the number of pits, and the number of first protruding areas 120. This is more conducive to achieving a balanced passivation effect, film deposition quality, and light trapping effect in non-poly-finger laminated films.

[0224] According to some embodiments of the present application, when the solar cell is the above-mentioned double-sided contact cell, an optional implementation is as follows: Figure 24 As shown, the second doped conductive layer 1022 is located within the surface of the other side of the silicon substrate 100, for example, formed by doping the silicon substrate 100 through a diffusion process, and is located on the front side of the cell. The first doped conductive layer 1021 is arranged at intervals on the back side of the cell to form a poly-finger structure. In this case, the first texture structure T1 includes a first sidewall 140 located between the first recessed region 110 and the first raised region 120. The first texture structure T1 is located on at least the silicon substrate corresponding to the first doped semiconductor layer. In this case, the roughness of the first sidewall 140 of the first texture structure T1 on the silicon substrate surface outside the poly-finger region (i.e., the first spacer region) is greater than the roughness of the first sidewall 140 of the first texture structure T1 on the first doped semiconductor layer (i.e., the poly-finger region). This improves light trapping in non-poly-finger regions, passivation in the poly-finger region, and film deposition quality. And / or, the number of first sidewalls 140 in the first texture structure T1 on the surface of one side of the silicon substrate outside the corresponding poly-finger region (i.e., the first spacer region) is greater than the number of first sidewalls 140 in the first texture structure T1 on the corresponding first doped semiconductor layer (i.e., the poly-finger). In this case, more photogenerated carriers are generated in the non-poly-finger stacked film.

[0225] In another optional embodiment, Figure 25As shown, the first doped conductive layer 1021 is located on the surface of one side of the silicon substrate 100, and at this time, the first doped conductive layer 1021 is located on the back of the cell, and the second doped conductive layer 1022 is arranged on the front of the cell, for example, forming a poly-finger structure. The first texture structure T1 includes a first side wall 140 located between the first recessed area 110 and the first raised area 120, and the first texture structure T1 is located on both the front and back of the cell. Optionally, the second doped conductive layer 1022 is a P-type doped layer, and the first doped conductive layer 1021 is an N-type doped layer, at this time, the number of the first side wall 140 in the first texture structure T1 corresponding to the second doped conductive layer 1022 on the other side of the silicon substrate 100 is less than the number of the first side wall 140 in the first texture structure T1 on the one side of the silicon substrate 100 and located on the first doped conductive layer 1021; and / or, the roughness of the first side wall in the first texture structure T1 corresponding to the second doped conductive layer 1022 on the other side of the silicon substrate 100 is smaller than the roughness of the first side wall in the first texture structure T1 corresponding to the first doped conductive layer 1021 on the one side of the silicon substrate, and specifically, for example, the first side wall corresponding to the second doped conductive layer 1022 can be provided with a smaller number or size of layered structures, point-like protrusions or steps, etc. At this time, it is more conducive to the passivation effect of the P-type doped layer, and the difference in passivation effect between the P region and the N region is reduced.

[0226] According to some embodiments of the present application, in the case of a solar cell being a back contact cell, the stack film 102 can include a first doped conductive layer 1021 and a second doped conductive layer 1022, each being arranged in an interval on both sides of the surface of the silicon substrate 100, such as the two surfaces of the cell forming poly-finger respectively, the first texture structure T1 includes a plurality of first recessed regions 110 extending in a strip shape along the first direction S1, at least corresponding to the silicon substrate on the first doped conductive layer 1021 and the second doped conductive layer 1022. Taking the example that the first doped conductive layer 1021 is located at the back surface of the cell and the second doped conductive layer 1022 is located at the front surface of the cell, the first recessed regions in the first texture structure T1 on the area of the one side surface of the silicon substrate except the poly-finger are more dense than the first recessed regions in the first texture structure T1 on the first doped semiconductor layer (i.e. poly-finger); the first recessed regions in the first texture structure T1 on the area of the other side surface of the silicon substrate except the poly-finger are more dense than the first recessed regions in the first texture structure T1 on the second doped semiconductor layer (i.e. poly-finger), at this time, the light trapping effect is given priority. Further, when the second doped conductive layer is a P-type doped conductive layer, at this time, the sparseness degree and effect of the first texture structure T1 on the other side surface of the silicon substrate 100 corresponding to the second doped conductive layer 1022 are the same as the above-mentioned front surface poly-finger, back surface topcon cell, which will not be repeated here. The dense distribution of the first recessed regions in the first texture structure T1, for example, can be that the number of the first recessed regions 110, the distance between two adjacent first recessed regions 110, the number of the convex portions 111, and the number of the pits have the same distribution rules as above. Thus, it is more conducive to achieving better passivation effect, film deposition quality and light trapping effect on the front surface of the cell.

[0227] According to some embodiments of the present application, in the case of the solar cell being the above-mentioned dual-sided contact cell, the first doped conductive layer 1021 and the second doped conductive layer 1022 are each arranged in a spaced manner on both sides of the surface of the silicon substrate 100, such as forming poly-fingers on the two surfaces of the cell respectively. The first texture structure T1 includes the first side wall 140 located between the first recessed area 110 and the first raised area 120, and the first texture structure T1 is located on the silicon substrate corresponding to at least the poly-finger area of the front surface and the back surface of the cell. Taking the case of the first doped conductive layer 1021 being located on the back surface of the cell and the second doped conductive layer 1022 being located on the front surface of the cell as an example, the number of the first side walls in the first texture structure T1 on the area of the one side surface of the silicon substrate excluding the poly-finger is greater than the number of the first side walls in the first texture structure T1 on the first doped semiconductor layer (i.e., the poly-finger); at this time, the light trapping effect is given priority to, and more photo-generated carriers are generated on the front surface of the cell. And / or, the roughness of the first side walls in the first texture structure T1 on the area of the other side surface of the silicon substrate excluding the poly-finger is greater than the roughness of the first side walls in the first texture structure T1 on the second doped semiconductor layer (i.e., the poly-finger), and specifically, for example, the first side walls in the first texture structure T1 on the area excluding the poly-finger can be provided with a larger number or size of layered structures, point-shaped protrusions or steps, etc. At this time, the passivation and contact performance of the back surface of the cell are given priority to, and the passivation effect, film deposition quality and light trapping effect are better considered on the back surface of the cell.

[0228] Further, when the second doped conductive layer 1022 is a P-type doped conductive layer, the roughness of the first side walls in the first texture structure T1 on the one side surface of the silicon substrate 100 corresponding to the first doped conductive layer 1021 is greater than the roughness of the first side walls in the first texture structure T1 on the other side surface of the silicon substrate 100 corresponding to the second doped semiconductor layer 1022, and specifically, for example, the first side walls corresponding to the first doped conductive layer 1021 can be provided with a larger number or size of layered structures, point-shaped protrusions or steps, etc.; and / or, the number of the first side walls 140 corresponding to the second doped semiconductor layer 1022 is less than the number of the first side walls corresponding to the first doped semiconductor layer 1021. In this way, the passivation effect of the P-type doped layer is more favorable, and the difference in passivation effect between the P region and the N region is reduced.

[0229] In order to facilitate understanding of the overall structure of the solar cell of the present application, exemplary, the following is taken as an example in combination with the structure of a TOPCon cell, such as Figure 23As shown, the solar cell can include a silicon substrate 100, a laminated film 102, and an electrode 200, wherein the laminated film 102 can include a first doped conductive layer 1021 and a second doped conductive layer 1022, which are respectively arranged on both sides of the silicon substrate 100. A first texture structure T1 can be on the surface of the silicon substrate corresponding to the first doped conductive layer 1021, and the first texture structure T1 can include adjacent first recessed regions 110 and first raised regions 120. Further, the first recessed regions 110 can extend in a strip shape, and / or the first texture structure T1 can further include first side walls 140 between the first recessed regions 110 and the first raised regions 120, which will not be described one by one.

[0230] Optionally, the first doped conductive layer 1021 is an N-type doped polysilicon layer deposited on one side surface of the silicon substrate 100, and the second doped conductive layer 1022 is a P-type doped conductive layer formed in one side surface of the silicon substrate 100 by a boron diffusion process. Of course, it is not limited thereto, and in other embodiments, for example, the first doped conductive layer 1021 can also be obtained by P-type doping of the silicon substrate 100 by an aluminum-containing electrode.

[0231] The laminated film 102 can further include a first interface passivation layer 1031 between the silicon substrate 100 and the first doped conductive layer 1021. The laminated film 102 can further include a first passivation or anti-reflection layer 1041 and a second passivation or anti-reflection layer 1042, wherein the first passivation or anti-reflection layer 1041 is on the surface of the first doped conductive layer 1021 away from the silicon substrate 100, and the second passivation or anti-reflection layer 1042 is on the surface of the second doped conductive layer 1022 away from the silicon substrate 100.

[0232] For example, the following will be described in combination with a cell structure with TOPCon on both sides, as shown in Figure 25 The difference between the above-mentioned TOPCon cell mainly lies in that the laminated film 102 can include a plurality of second doped conductive layers 1022, each extending in a direction substantially the same as the first direction S1 and spaced apart along the second direction S2. The second doped conductive layer 1022 can be a doped polysilicon layer, and forms a poly-finger structure with the second electrode 202. At this time, the first texture structure T1 is located on both the first doped conductive layer 1021 and the second doped conductive layer 1022.

[0233] The interface passivation layer 103 can include a first interface passivation layer 1031 and a second interface passivation layer 1032, wherein the first interface passivation layer 1031 is between the first doped conductive layer 1021 and the silicon substrate 100; and the second interface passivation layer 1032 is between the second doped conductive layer 1022 and the silicon substrate 100.

[0234] For example, by selecting appropriate doped conductive layer and interface passivation layer materials, the present application can be widely applicable to a variety of solar cell types. Another example is other double-sided contact cells, such as heterojunction with intrinsic thin-layer (HJT) cells. In this case, the first doped conductive layer 1021 and the second doped conductive layer 1022 can be an N-type doped amorphous silicon layer and a P-type doped amorphous silicon layer, respectively, and the first interface passivation layer 1031 and the second interface passivation layer 1032 can be intrinsic amorphous silicon layers, respectively. In this case, the stacked film 102 can also include a first transparent conductive layer and a second transparent conductive layer, wherein the first transparent conductive layer is located on the surface of the first doped conductive layer 1021 away from the silicon substrate 100, and the second transparent conductive layer is located on the surface of the second doped conductive layer 1022 away from the silicon substrate 100. It is understood that a passivation or anti-reflection layer may not be provided.

[0235] Of course, it is not limited to this, and can also be a back contact battery, such as a back contact heterojunction (Heterojunction Back Contact, abbreviated as HBC) battery, a TBC (TopCon-Back Contact) battery, a hybrid BC battery such as a hybrid battery combined with TopCon-HJT (Heterojunction with Intrinsic Thin-layer, abbreviated as HJT), etc.

[0236] The following is an example of TBC battery. Figure 26 This is a schematic diagram of the overall structure of a solar cell according to another embodiment of the present application. Figure 26 As shown, the main difference from the above-mentioned TOPCon cell is that the stacked film 102 includes a first doped conductive layer 1021 and a second doped conductive layer 1022, which can be alternately distributed on one side of the silicon substrate. The two layers are N-type and P-type doped polysilicon layers, respectively. In this case, the first texture structure T1 can be located on both the first doped conductive layer 1021 and the second doped conductive layer 1022.

[0237] Further optionally, the stacked film 102 may further include a first interface passivation layer 1031 and a second interface passivation layer 1032. Both may be silicon oxide layers, thereby forming a tunneling oxide passivation contact structure between the first doped conductive layer 1021 and the first interface passivation layer 1031, and between the second doped conductive layer 1022 and the second interface passivation layer 1032.

[0238] Furthermore, the stacked film 102 may further include a passivation or anti-reflection layer 104 covering the first doped conductive layer 1021 and the second doped conductive layer 1022 , and may further cover the spacer between the first doped conductive layer 1021 and the second doped conductive layer 1022 .

[0239] Through testing the efficiency and open voltage of the TBC battery containing the first texture structure T1 and the TBC battery containing the traditional tower base structure, it is found that the battery containing the first texture structure T1 of the application has improved efficiency and open voltage, and the open voltage is 1.5 mV higher than that of the traditional tower base structure, and the battery efficiency can be improved by 0.05%. This shows that the first texture structure T1 of the application is beneficial to improve the film layer quality of the laminated film and improve the electrical contact performance between the electrode and the battery body due to the reduction of the corner structure.

[0240] Table 1

[0241]

[0242] According to an embodiment of the application, a photovoltaic module is provided, comprising: a silicon substrate as described above; or a plurality of the above-mentioned solar cells.

[0243] According to an embodiment of the application, the above-mentioned solar cells can be connected in series to form a solar cell string; and an encapsulation layer covering the outer periphery of the solar cell.

[0244] According to an embodiment of the application, the number of series-connected solar cells can be 4-80, for example, 4, 24, 54, 72, 78, etc. A plurality of solar cells can form a plurality of solar cell strings, the cells in a solar cell string are connected in series, and the solar cell strings can be connected in series or in parallel, and the solar cell strings are connected by bus bars.

[0245] According to an embodiment of the application, the encapsulation layer can include a back plate, an encapsulation adhesive film, a glass panel, etc. to improve the stability of the solar cell string. The glass panel is located on the front side of the solar cell string, and the back plate is located on the back side of the solar cell string, both of which play a protective role; the adhesive film is an adhesive film between the solar cell and the glass panel and the back plate, which plays a role of adhesion and fixation, and must be made of transparent material.

[0246] The above-described specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the application. It should be understood that the above-described specific embodiments are only for the specific embodiments of the application and are not intended to limit the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the application shall be included in the protection scope of the application.

Claims

1. A solar cell comprising: A silicon substrate, wherein the silicon substrate comprises two opposite surfaces, at least one of the surfaces having a first texture structure, the first texture structure comprising: a plurality of first recessed areas; and a plurality of first convex regions, wherein the first convex regions are adjacent to the first concave regions.

2. The solar cell according to claim 1, wherein Each of the first recessed areas extends in a strip shape along a first direction, and a plurality of the first recessed areas are distributed at intervals along a second direction intersecting the first direction.

3. The solar cell according to claim 2, wherein The first recessed area has a protruding portion extending along the second direction, and the first recessed area is divided into a multi-segment structure by the protruding portion.

4. The solar cell according to claim 3, wherein The multi-segment structure is in at least one of a bamboo joint shape and a candied haws shape; And / or, the projection of the protrusion on the first recessed area is at least one of a cross shape, a straight line shape, and a curved shape.

5. The solar cell according to claim 3 or 4, wherein The height of the protruding portion is lower than the height of the first protruding area adjacent to the protruding portion.

6. The solar cell according to claim 1 or 2, wherein: At least part of the first recessed area has first pits distributed in a dotted manner along the first direction; and / or, at least part of the plurality of first recessed areas has at least one second recessed pit, and the second recessed pit has a morphology of one or more combinations of a cross shape, a line shape, and a groove shape; and / or, the cross-sectional shape of the first recessed area has a morphology of one or more combinations of a V shape, an arc shape, a rectangle, and a trapezoid shape; And / or, the position where the first concave area and the first convex area are connected has third pits distributed discontinuously along the first direction, and there are protrusions between adjacent third pits.

7. The solar cell according to claim 6, wherein The number of the first pits located in one of the first recessed areas is 1 to 30; and / or the number of the second pits is smaller than the number of the first pits.

8. The solar cell according to claim 2, wherein The distance between adjacent first raised areas in the second direction is 1-10 μm, and the depth of the first recessed area is 0.2-2 μm; and / or, a distance between two adjacent first recessed areas is 2-10 μm; And / or, within a width range of 100 μm along the second direction, the number of the first recessed areas is 3 to 20.

9. The solar cell according to claim 1 or 2, wherein: The surface of the silicon substrate further includes: at least one crack randomly distributed on the surface of the silicon substrate.

10. The solar cell according to claim 2, wherein The projection of the first convex area in the surface extension direction of the silicon substrate is at least one of a straight line shape, a broken line shape, a curve shape, a candied haws shape, and a dot shape.

11. The solar cell according to claim 2, wherein The surface of the silicon substrate further includes a second texture structure, the second texture structure includes a second recessed area, and the second recessed area includes a plurality of sub-recessed structures distributed in a non-linear manner; Wherein, the depth of the second recessed area is smaller than the depth of the first recessed area.

12. The solar cell according to claim 1 or 2, wherein: The first texture structure further includes a first sidewall located between the first concave region and the first convex region; The first side wall has a corrugated portion.

13. The solar cell according to claim 12, wherein: The wrinkle portion includes a plurality of layered structures protruding from the first sidewall, wherein the plurality of layered structures are stacked along the thickness direction of the silicon substrate to form a linear transverse texture; And / or, the folded portion includes a plurality of dot-shaped protrusions stacked on the first side wall to form a scale-like protrusion structure; And / or, the first sidewall further includes a plurality of steps stacked into a stepped structure along the thickness direction of the silicon substrate.

14. The solar cell according to claim 13, wherein The extension length of the layered structure along the surface of the silicon substrate is greater than the thickness of the layered structure; And / or, a height of the scale-like protrusion structure protruding in a direction away from the first sidewall is 0.1-1 μm.

15. The solar cell according to claim 13, wherein The first texture structure further includes: a gentle slope adjacent to the first sidewall, wherein the surface of the gentle slope has gentle hillock stripes, and the gentle hillock stripes are intersecting or unequally aligned with the linear transverse texture.

16. The solar cell according to claim 15, wherein The slope angle of the first side wall is greater than the slope angle of the gently sloping surface; And / or, the slope angle of the first side wall is greater than or equal to 25° and less than or equal to 75°, and the slope angle of the gently sloping surface is less than 25° and greater than 2°.

17. The solar cell according to claim 12, wherein Part of the first concave area or the first convex area is in an island shape, and the first side wall extends into a ring shape or a C shape.

18. The solar cell according to claim 12, wherein The first sidewall is further provided with: a first sidewall bifurcated structure, the first sidewall bifurcated structure including a first sub-sidewall extending from the first sidewall toward the first recessed area; And / or, the first sidewall is further provided with: a second sidewall bifurcated structure, the second sidewall bifurcated structure comprising a second sub-sidewall extending from the first sidewall toward the first convex area.

19. The solar cell according to claim 18, wherein The first sub-side wall and / or the second sub-side wall respectively have a plurality of dot-shaped protrusions, a plurality of layered structures and / or a plurality of steps.

20. The solar cell according to claim 12, wherein One side of the first recessed area is adjacent to one of the first side walls, and the other side may be adjacent to another first side wall, or adjacent to a gentle slope.

21. The solar cell according to claim 12, wherein The surface of the silicon substrate further includes a second texture structure; The flatness of the second texture structure is greater than the flatness of the first sidewall and less than the flatness of the first recessed area.

22. The solar cell according to claim 21, wherein At least part of the first texture structure and / or the second texture structure has a gentle slope, the surface of the gentle slope has a substructure with an arc-shaped or polygonal contour, the substructure has a plurality of second concave areas, and the second concave areas overlap to form a second convex area.

23. The solar cell according to claim 22, wherein The width or area of ​​the region where the substructure with the arc-shaped profile is located accounts for 3% to 40% of the surface of the silicon substrate.

24. The solar cell according to claim 22 or 23, wherein At least a portion of the second convex region has a convex end convex toward the outside of the silicon substrate, and a surface of the convex end is a smooth transition surface.

25. The solar cell according to claim 12, wherein The first sidewall extends along a first direction, and an extension length in the first direction is greater than or equal to 2 μm and less than or equal to 300 μm; And / or, in a second direction intersecting with the first direction, the width of the first sidewall is 0.5-3 μm, and the depth in the thickness direction of the silicon substrate is 0.1-10 μm; and / or, within a width range of 100 μm along the second direction, the number of the first sidewalls is 1 to 200; And / or, the uniformity of the film layer located on the silicon substrate is less than 10%, and the film layer includes a doped conductive layer and / or a passivation or anti-reflection layer.

26. The solar cell according to claim 1, wherein The solar cell further comprises: a plurality of electrodes located on a surface of the silicon substrate, each of the plurality of electrodes extending in a direction that is the same as or substantially the same as the first direction, and spaced apart along the second direction; In the second direction, the number of the first recessed areas covered by one electrode is 1 to 20.

27. The solar cell according to any one of claims 1 to 26, wherein The solar cell further comprises: a laminated film provided on at least one side of the silicon substrate; The laminated film comprises: a doped conductive layer extending along the first direction and spaced apart along the second direction, wherein the first texture structure is located on a surface of the silicon substrate corresponding to the doped conductive layer; and a passivation or anti-reflection layer located on a surface of the doped conductive layer away from the silicon substrate; In the second direction, the number of the first recessed regions corresponding to one doped conductive layer is 10 to 100.

28. The solar cell according to claim 27, wherein The doped conductive layer includes an N-type doped conductive layer and a P-type doped conductive layer alternately arranged on one side of the silicon substrate; The first recessed regions in the first texture structure corresponding to the P-type doped conductive layer on one side surface of the silicon substrate are more sparsely distributed than the first recessed regions in the first texture structure corresponding to the N-type doped conductive layer; And / or, a roughness of a first sidewall in a first texture structure corresponding to the N-type doped conductive layer on one surface of the silicon substrate is greater than a roughness of a first sidewall in a first texture structure corresponding to the P-type doped conductive layer; And / or, the number of first sidewalls in the first texture structure corresponding to the P-type doped conductive layer on one side surface of the silicon substrate is less than the number of first sidewalls in the first texture structure corresponding to the N-type doped conductive layer.

29. The solar cell according to claim 27, wherein The doped conductive layer is a first doped conductive layer disposed on a surface of one side of the silicon substrate, the first doped conductive layer is located on the back side of the battery, and a first spacer is provided between adjacent first doped conductive layers. The laminated film further includes: A second doped conductive layer is entirely disposed on the other side of the silicon substrate, and the second doped conductive layer is located on the front side of the battery; In which, the first texture structure is located on the surface of the silicon substrate corresponding to the first doped conductive layer and the surface of the silicon substrate corresponding to the first spacer area, and the first recessed areas in the first texture structure corresponding to the first spacer area on one side surface of the silicon substrate are more densely distributed than the first recessed areas in the first texture structure corresponding to the first doped conductive layer; and / or, the roughness of the first side wall in the first texture structure corresponding to the first spacer area on one side surface of the silicon substrate is greater than the roughness of the first side wall in the first texture structure corresponding to the first doped conductive layer; and / or, the number of first side walls in the first texture structure corresponding to the first spacer area on one side surface of the silicon substrate is greater than the number of first side walls in the first texture structure corresponding to the first doped semiconductor layer.

30. The solar cell according to claim 27, wherein The doped conductive layer is a second doped conductive layer provided on the other surface of the silicon substrate, the second doped conductive layer is located on the front side of the battery, and a second spacer is provided between adjacent second doped conductive layers. The stacked film further includes: a first doped conductive layer, which is entirely provided on one surface of the silicon substrate, and the first doped conductive layer is located on the back side of the battery; In which, the first texture structure is located on the surface of the silicon substrate corresponding to the first doped conductive layer and the surface of the silicon substrate corresponding to the second doped conductive layer, and the first recessed area in the first texture structure corresponding to the second doped conductive layer on the other side surface of the silicon substrate is more sparsely distributed than the first recessed area in the first texture structure corresponding to the first doped conductive layer on one side surface of the silicon substrate; and / or, the number of first side walls in the first texture structure corresponding to the second doped conductive layer on the other side surface of the silicon substrate is less than the number of first side walls in the first texture structure corresponding to the first doped conductive layer on one side surface of the silicon substrate; and / or, the roughness of the first side wall in the first texture structure corresponding to the first doped conductive layer on one side surface of the silicon substrate is greater than the roughness of the first side wall in the first texture structure corresponding to the second doped conductive layer on the other side surface of the silicon substrate.

31. The solar cell according to claim 27, wherein The doped conductive layer is a first doped conductive layer disposed on a surface of one side of the silicon substrate, the first doped conductive layer is located on the back side of the battery, and a first spacer is provided between adjacent first doped conductive layers. The laminated film further includes: second doped conductive layers extending along the first direction and spaced apart along the second direction on the other surface of the silicon substrate, the second doped conductive layers being located on the front side of the battery, with second spacers being defined between adjacent second doped conductive layers; In which, the first texture structure is located on the surface of the silicon substrate corresponding to the first doped conductive layer, the second doped conductive layer, the first spacer and the second spacer, respectively. The first recessed areas in the first texture structure corresponding to the first spacer on one side of the silicon substrate are more densely distributed than the first recessed areas in the first texture structure corresponding to the first doped conductive layer; and / or, the first recessed areas in the first texture structure corresponding to the second spacer on the other side of the silicon substrate are more densely distributed than the first recessed areas in the first texture structure corresponding to the second doped conductive layer; and / or, the number of first side walls in the first texture structure corresponding to the first spacer on one side of the silicon substrate is greater than the number of first side walls in the first texture structure corresponding to the first doped conductive layer; and / or, the roughness of the first side wall in the first texture structure corresponding to the second spacer on the other side of the silicon substrate is greater than the roughness of the first side wall in the first texture structure corresponding to the second doped conductive layer.

32. The solar cell according to claim 31, wherein The second doped conductive layer is a P-type doped conductive layer; The first recessed regions in the first texture structure corresponding to the second doped conductive layer on the other side surface of the silicon substrate are more sparsely distributed than the first recessed regions in the first texture structure corresponding to the first doped semiconductor layer on one side surface of the silicon substrate; and / or the roughness of a first sidewall of a first texture structure corresponding to the first doped conductive layer on one surface of the silicon substrate is greater than the roughness of a first sidewall of a first texture structure corresponding to the second doped semiconductor layer on the other surface of the silicon substrate; And / or, the number of first side walls in the first texture structure corresponding to the second doped semiconductor layer on the other side surface of the silicon substrate is less than the number of first side walls in the first texture structure corresponding to the first doped semiconductor layer on one side surface of the silicon substrate.

33. The solar cell according to any one of claims 1 to 26, wherein The solar cell further comprises: a laminated film provided on both sides of the silicon substrate, The laminated film comprises: A first doped conductive layer is entirely disposed on one side surface of the silicon substrate, and the first texture structure is at least located on the surface of the silicon substrate corresponding to the first doped conductive layer; A second doped conductive layer is entirely disposed within the other side surface of the silicon substrate, and the second doped conductive layer has a pyramid structure on the other side surface of the silicon substrate corresponding to the second doped conductive layer; and a passivation or anti-reflection layer located on a surface of the doped conductive layer away from the silicon substrate.

34. A photovoltaic module comprising the solar cell according to any one of claims 1 to 33.

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