Shifting register unit and driving method thereof, gate driving circuit and display device

Abstract

The invention discloses a shift register unit and a driving method thereof, a gate driving circuit and a display device, and belongs to the technical field of display. In the shift register unit, a pre-charging circuit (01) can control the potential of a control node (P) based on gating signals provided by a plurality of gating ends (D0... Dm); the charging circuit (02) can control the potential of the pull-up node (Q) based on the potential of the control node (P) and a clock signal; the reset circuit (03) can control the potentials of the control node (P) and the pull-up node (Q) based on a reset signal; furthermore, each output circuit (04) in the plurality of output circuits (04) can control the connection and disconnection between the output ends (Scout1,..., Scoutn) and the output clock ends (CLKS1,..., CLKSn) based on the potential of the pull-up node (Q). Therefore, partition gating can be realized by flexibly setting the gating signals, so that the plurality of output units can flexibly output gate driving signals to the plurality of rows of pixels in each partition to drive the plurality of rows of pixels to emit light. That is, the shift register unit can flexibly refresh pixels according to display screen partitions.

Description

Shift register unit and driving method thereof, gate driving circuit, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0002] With the advancement of display technology, gate driver circuits are usually disposed on display panels using gate driver on array (GOA) technology to facilitate narrow frame design.

[0003] In the related art, the gate drive circuit usually includes multiple cascaded GOA units, which are connected one-to-one to multiple rows of pixels on the display panel and are used to transmit gate drive signals to the multiple rows of pixels row by row to light up the pixels row by row, that is, to achieve row-by-row scanning and refreshing, so that the display panel can display the picture.

[0004] However, the gate driving circuit in the related art has a single driving mode and cannot flexibly refresh different area partitions on the display panel according to the display image.

[0005] Summary of the Invention

[0006] Provided are a shift register unit and a driving method thereof, a gate driving circuit, and a display device. The technical solution is as follows:

[0007] In one aspect, a shift register unit is provided, comprising:

[0008] a precharge circuit, connected to at least two strobe terminals, a first clock terminal, a second clock terminal, and a control node, respectively, and configured to control the connection and disconnection between the first clock terminal and the control node in response to a strobe signal provided by each of the strobe terminals, a first clock signal provided by the first clock terminal, and a second clock signal provided by the second clock terminal;

[0009] a charging circuit, connected to the control node, the second clock terminal, the third clock terminal, the first power terminal, and the pull-up node, respectively, and configured to control the connection and disconnection between the first power terminal and the pull-up node in response to the potential of the control node and a third clock signal provided by the third clock terminal, and to control the connection and disconnection between the third clock terminal and the pull-up node in response to the second clock signal;

[0010] a reset circuit, connected to the reset terminal, the second power terminal, the control node, and the pull-up node, respectively, and configured to control the connection and disconnection between the second power terminal and the control node, and the connection and disconnection between the second power terminal and the pull-up node, in response to a reset signal provided by the reset terminal;

[0011] At least two output circuits are respectively connected to the pull-up node, at least two output clock terminals corresponding to each other, and at least two output terminals corresponding to each other. Each of the output circuits is used to control the connection and disconnection of a corresponding output clock terminal and an output terminal in response to the potential of the pull-up node, so as to output a gate drive signal through the output terminal.

[0012] Optionally, the pre-charging circuit includes:

[0013] a gating subcircuit, connected to the at least two gating terminals, the second clock terminal and the intermediate node respectively, and configured to control the connection and disconnection between the second clock terminal and the intermediate node in response to a gating signal provided by each of the gating terminals;

[0014] an auxiliary control subcircuit, connected to the first clock terminal, the second clock terminal, and the intermediate node, respectively, and configured to control the connection and disconnection between the second clock terminal and the intermediate node in response to a first clock signal;

[0015] The precharge subcircuit is connected to the intermediate node, the first clock terminal and the control node respectively, and is used to control the connection and disconnection of the first clock terminal and the control node in response to the potential of the intermediate node and the first clock signal.

[0016] Optionally, the gating subcircuit includes: at least two gating transistors;

[0017] The gates of the at least two gating transistors are connected to the at least two gating terminals in a one-to-one correspondence, the first electrodes of the at least two gating transistors are connected to the second clock terminal, and the second electrodes of the at least two gating transistors are connected to the intermediate node.

[0018] Optionally, the auxiliary control subcircuit includes: an auxiliary control transistor;

[0019] The gate of the auxiliary control transistor is connected to the first clock terminal, the first electrode of the auxiliary control transistor is connected to the second clock terminal, and the second electrode of the auxiliary control transistor is connected to the intermediate node.

[0020] Optionally, the pre-charging sub-circuit is further connected to the first power supply terminal and is used to store the potential of the control node based on the first power supply signal; the pre-charging sub-circuit includes: a first pre-charging transistor, a second pre-charging transistor and a first storage capacitor;

[0021] The gate of the first pre-charging transistor is connected to the intermediate node, the first electrode of the first pre-charging transistor is connected to the first clock terminal, and the second electrode of the first pre-charging transistor is connected to the control node;

[0022] The gate and the first electrode of the second pre-charging transistor are both connected to the first clock terminal, and the second electrode of the second pre-charging transistor is connected to the control node;

[0023] One end of the first storage capacitor is connected to the first power supply end, and the other end of the first storage capacitor is connected to the control node.

[0024] Optionally, the shift register unit further includes:

[0025] a pull-down control circuit, connected to the control node, the second clock terminal, the third clock terminal, the control power terminal, the pull-up node, and the pull-down node, respectively, and configured to control the connection and disconnection between the second clock terminal and the pull-down node in response to the potential of the control node and the third clock signal, control the connection and disconnection between the control power terminal and the pull-down node in response to the second clock signal, and control the connection and disconnection between the second clock terminal and the pull-down node in response to the potential of the pull-up node;

[0026] a pull-down circuit, connected to the pull-down node, the second power supply terminal, the pull-up node, and the at least two output terminals, respectively, and configured to control the connection and disconnection between the second power supply terminal and the pull-up node, and control the connection and disconnection between the second power supply terminal and each of the output terminals, in response to the potential of the pull-down node;

[0027] Wherein, the control power supply terminal is shared with the second clock terminal or the first power supply terminal.

[0028] Optionally, the pull-down control circuit is further connected to the second power supply terminal and is used to store the potential of the pull-down node based on the second power supply signal; the pull-down control circuit includes: a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, a fourth pull-down control transistor and a second storage capacitor;

[0029] The gate of the first pull-down control transistor is connected to the control node, the first electrode of the first pull-down control transistor is connected to the second electrode of the second pull-down control transistor, and the second electrode of the first pull-down control transistor is connected to the pull-down node;

[0030] The gate of the second pull-down control transistor is connected to the third clock terminal, and the first electrode of the second pull-down control transistor is connected to the second clock terminal;

[0031] The gate of the third pull-down control transistor is connected to the second clock terminal, the first electrode of the third pull-down control transistor is connected to the control power supply terminal, and the second electrode of the third pull-down control transistor is connected to the pull-down node;

[0032] The gate of the fourth pull-down control transistor is connected to the pull-up node, the first electrode of the fourth pull-down control transistor is connected to the second clock terminal, and the second electrode of the fourth pull-down control transistor is connected to the pull-down node;

[0033] One end of the second storage capacitor is connected to the second power supply end, and the other end of the second storage capacitor is connected to the pull-down node.

[0034] Optionally, the pull-down circuit includes: a first pull-down transistor, and at least two second pull-down transistors;

[0035] The gate of the first pull-down transistor is connected to the pull-down node, the first electrode of the first pull-down transistor is connected to the second power supply terminal, and the second electrode of the first pull-down transistor is connected to the pull-up node;

[0036] The gates of the at least two second pull-down transistors are both connected to the pull-down node, the first electrodes of the at least two second pull-down transistors are both connected to the second power supply terminal, and the second electrodes of the at least two second pull-down transistors are connected to the at least two output terminals in a one-to-one correspondence.

[0037] Optionally, the shift register unit further includes:

[0038] The first isolation circuit is connected between the control node and the pull-down control circuit and is also connected to the first power supply terminal, and is used to control the control node and the pull-down control circuit to be conductive in response to the first power supply signal.

[0039] Optionally, the first isolation circuit includes: a first isolation transistor;

[0040] A gate of the first isolation transistor is connected to the first power supply terminal, a first electrode of the first isolation transistor is connected to the control node, and a second electrode of the first isolation transistor is connected to the pull-down control circuit.

[0041] Optionally, the shift register unit further includes:

[0042] The second isolation circuit is connected between the pull-up node and the at least two output circuits and is also connected to the first power supply terminal, and is used to control the pull-up node and the at least two output circuits to be conductive in response to the first power supply signal.

[0043] Optionally, the second isolation circuit includes: at least two isolation sub-circuits;

[0044] The at least two isolation sub-circuits are connected to the at least two output circuits in a one-to-one correspondence, and are also connected to the first power supply terminal and the pull-up node. Each of the isolation sub-circuits is used to control the on / off connection between the pull-up node and the corresponding one of the output circuits in response to the first power supply signal.

[0045] Optionally, each of the isolation sub-circuits includes: a second isolation transistor;

[0046] A gate of the second isolation transistor is connected to the first power supply terminal, a first electrode of the second isolation transistor is connected to the pull-up node, and a second electrode of the second isolation transistor is connected to a corresponding one of the output circuits.

[0047] Optionally, the charging circuit includes: a first charging transistor, a second charging transistor and a third charging transistor;

[0048] The gate of the first charging transistor is connected to the control node, the first electrode of the first charging transistor is connected to the first power supply terminal, and the second electrode of the first charging transistor is connected to the first electrode of the second charging transistor;

[0049] The gate of the second charging transistor is connected to the third clock terminal, and the second electrode of the second charging transistor is connected to the pull-up node;

[0050] A gate of the third charging transistor is connected to the second clock terminal, a first electrode of the third charging transistor is connected to the third clock terminal, and a second electrode of the third charging transistor is connected to the pull-up node.

[0051] Optionally, the reset circuit includes: a first reset transistor and a second reset transistor;

[0052] The gate of the first reset transistor is connected to the reset terminal, the first electrode of the first reset transistor is connected to the second power supply terminal, and the second electrode of the first reset transistor is connected to the control node;

[0053] A gate of the second reset transistor is connected to the reset terminal, a first electrode of the second reset transistor is connected to the second power supply terminal, and a second electrode of the second reset transistor is connected to the pull-up node.

[0054] Optionally, each of the output circuits includes: an output transistor and a third storage capacitor;

[0055] The gate of the output transistor is connected to the pull-up node, the first electrode of the output transistor is connected to the corresponding output clock terminal, and the second electrode of the output transistor is connected to the corresponding output terminal;

[0056] One end of the third storage capacitor is connected to the pull-up node, and the other end of the third storage capacitor is connected to the corresponding output end.

[0057] Optionally, the shift register unit includes: four output circuits;

[0058] The precharge circuit is connected to the eight strobe terminals.

[0059] In another aspect, a method for driving a shift register unit is provided, for driving the shift register unit according to the above aspect; the method comprising:

[0060] In the reset phase, the reset circuit controls the second power supply terminal to be connected to the control node and the pull-up node in response to the reset signal provided by the reset terminal;

[0061] In the set phase, the precharge circuit controls the first clock terminal to be conductive with the control node in response to the first clock signal provided by the first clock terminal;

[0062] In a gating stage, the pre-charging circuit controls the connection between the first clock terminal and the control node in response to a gating signal provided by each of the at least two gating terminals and a second clock signal provided by the second clock terminal, and the charging circuit controls the connection between the third clock terminal and the pull-up node in response to the second clock signal provided by the second clock terminal;

[0063] In the input stage, the charging circuit controls the first power supply terminal to be connected to the pull-up node in response to the third clock signal provided by the third clock terminal and the potential of the control node;

[0064] In the output stage, each of the at least two output circuits controls a corresponding output clock terminal to be connected to a corresponding output terminal in response to the potential of the pull-up node.

[0065] In another aspect, a gate driving circuit is provided, the gate driving circuit comprising: a plurality of groups of shift register units, each group of the shift register units comprising: at least two shift register units as described in the above aspect;

[0066] Each group of shift register units shares a first clock terminal, a second clock terminal, a third clock terminal, an output clock terminal and a strobe terminal, and each group of shift register units is configured to receive different strobe signals provided by at least two of the strobe terminals.

[0067] In another aspect, a display device is provided, comprising: a display panel, and the gate driving circuit as described in the above-mentioned further aspect;

[0068] The display panel includes a plurality of pixels, and the gate driving circuit is connected to the plurality of pixels and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0070] FIG1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure;

[0071] FIG2 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0072] FIG3 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0073] FIG4 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0074] FIG5 is a schematic diagram of a circuit structure of a shift register unit provided by an embodiment of the present disclosure;

[0075] FIG6 is a schematic diagram of the circuit structure of another shift register unit provided by an embodiment of the present disclosure;

[0076] FIG7 is a schematic diagram of a circuit structure of another shift register unit provided in an embodiment of the present disclosure;

[0077] FIG8 is a schematic flow chart of a driving method of a shift register unit provided in an embodiment of the present disclosure;

[0078] FIG9 is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present disclosure;

[0079] FIG10 is a schematic structural diagram of another gate drive circuit provided by an embodiment of the present disclosure;

[0080] FIG11 is a schematic diagram of the working timing of a gate driving circuit provided by an embodiment of the present disclosure;

[0081] FIG12 is a schematic diagram of the working timing of another gate driving circuit provided by an embodiment of the present disclosure;

[0082] FIG13 is a timing diagram of a strobe signal provided by an embodiment of the present disclosure;

[0083] FIG14 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure;

[0084] FIG15 is a schematic diagram of a circuit structure of a pixel provided by an embodiment of the present disclosure;

[0085] FIG16 is a schematic diagram of the working timing of a pixel provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0086] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0087] It should be noted that the transistors used in all embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of the present disclosure are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. The source is referred to as the first electrode and the drain as the second electrode, or the drain is referred to as the first electrode and the source as the second electrode. According to the configuration in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end as the source, and the signal output end as the drain. Furthermore, the switching transistors used in the embodiments of the present disclosure may include either a P-type transistor or an N-type transistor, or a combination thereof. A P-type transistor is turned on when the gate voltage is low and turned off when the gate voltage is high, while an N-type transistor is turned on when the gate voltage is high and turned off when the gate voltage is low. Furthermore, multiple signals in each embodiment correspond to a first potential and a second potential. The first potential and the second potential merely represent that the potential of the signal has two different states and do not represent that the first potential or the second potential has a specific value.

[0088] High-end displays have very stringent requirements on image quality, especially professional gaming displays, which usually require a higher refresh rate. In order to better combine low power consumption and high refresh rate, partitioned high refresh technology (also known as intra-frame frequency conversion technology) is generally adopted, and high refresh is used separately for dynamic images. This technology requires that each GOA unit in the gate drive circuit can work flexibly and have random gating capabilities. In addition, with the increase in resolution and the popularity of virtual reality (VR) display, augmented reality (AR) and three-dimensional (3D) display applications, in order to reduce the amount of frame transmission data, the gate drive circuit is also required to have random gating capabilities.

[0089] At present, under one implementation, each GOA unit in the gate drive circuit provides a gate drive signal to the multi-row pixels in the display row by row, so that the multi-row pixels are turned on row by row, that is, real-time adjustment can not be achieved according to the picture to be displayed, and current display requirements cannot be met. Under another implementation, it is considered to partition the multi-row pixels, and accordingly, the multiple GOA units included in the gate drive circuit are also partitioned, so that a certain partition high refresh can be locally controlled. However, after the gate drive circuit is partitioned, because the GOA units of each partition are no longer cascaded, it is necessary to separately set the start-up signal end STU for the GOA units of each partition to drive the GOA units in the partition to work, and under some embodiments, it is also necessary to separately set a dummy (dummy) GOA for the GOA units of each partition. In this way, not only hardware complexity and cost are increased, but also the number of partitions can be limited.

[0090] Based on this, the embodiments of the present disclosure provide a decoder-type GOA unit. When applied to a gate drive circuit, it can enable the gate drive circuit to have random gating capabilities, which is particularly suitable for displays that require high refresh rates in different zones. Figure 1 is a schematic diagram of the structure of a shift register unit provided by an embodiment of the present disclosure. As shown in Figure 1, the shift register unit includes: a pre-charge circuit 01, a charging circuit 02, a reset circuit 03, and at least two output circuits 04.

[0091] The precharge circuit 01 is respectively connected to at least two strobe terminals D0 ... Dm, a first clock terminal CLK1, a second clock terminal CLK2, and a control node P, and is configured to control the connection and disconnection between the first clock terminal CLK1 and the control node P in response to a strobe signal provided by each of the at least two strobe terminals D0 ... Dm, a first clock signal provided by the first clock terminal CLK1, and a second clock signal provided by the second clock terminal CLK2. m is an integer greater than 1. For example, m can be 7, 9, or other integers.

[0092] For example, in the same time period, the potential of the first clock signal and the potential of the second clock signal are generally opposite. Therefore, assuming that the potential of the selection signal provided by any selection terminal is the first potential, the pre-charge circuit 01 can control the first clock terminal CLK1 to be conductive with the control node P when the potential of the first clock signal is the first potential and the potential of the second clock signal is the second potential, so that the first clock terminal CLK1 transmits the first clock signal of the first potential to the control node P; and can control the first clock terminal CLK1 to be conductive with the control node P when the potential of the second clock signal is the first potential and the potential of the first clock signal is the second potential, so that the first clock terminal CLK1 transmits the first clock signal of the second potential to the control node P. Assuming that the potential of the selection signal provided by each selection terminal is the second potential, the pre-charge circuit 01 can control the first clock terminal CLK1 to be connected to the control node P when the potential of the first clock signal is the first potential and the potential of the second clock signal is the second potential, so that the first clock terminal CLK1 transmits the first clock signal to the control node P; and can control the first clock terminal CLK1 to be disconnected from the control node P when the potential of the second clock signal is the first potential and the potential of the first clock signal is the second potential.

[0093] That is, the current shift register unit can be enabled or disabled by controlling the potential of the enable signal provided by each of the at least two enable terminals D0 ... Dm. If the current shift register unit is enabled, it can output a signal normally; if the current shift register unit is disabled, it will not output a signal, thereby achieving the purpose of controlling the refresh frequency.

[0094] Optionally, from the gate terminal D0 to the gate terminal Dm, the frequencies of the gate signals provided by the gate terminals may decrease in sequence, that is, the pulses of the gate signals provided by the gate terminals may decrease in sequence.

[0095] Optionally, in the disclosed embodiment, the first potential may be an effective potential, and the second potential may be an ineffective potential. For a P-type transistor in the circuit, the first potential may be a low potential relative to the second potential. For an N-type transistor in the circuit, the first potential may be a high potential relative to the second potential.

[0096] The charging circuit 02 is respectively connected to the control node P, the second clock terminal CLK2, the third clock terminal CLK3, the first power supply terminal VGL and the pull-up node Q, and is used to control the connection and disconnection of the first power supply terminal VGL and the pull-up node Q in response to the potential of the control node P and the third clock signal provided by the third clock terminal CLK3, and to control the connection and disconnection of the third clock terminal CLK3 and the pull-up node Q in response to the second clock signal.

[0097] For example, the charging circuit 02 can control the first power supply terminal VGL to be conductive with the pull-up node Q when the potential of the control node P is at a first potential and the potential of the third clock signal is at a first potential, so that the first power supply terminal VGL transmits the first power supply signal to the pull-up node Q. Furthermore, the charging circuit 02 can control the first power supply terminal VGL to be disconnected from the pull-up node Q when the potential of the control node P is at a second potential and / or the potential of the third clock signal is at a second potential. Similarly, the charging circuit 02 can control the third clock terminal CLK3 to be conductive with the pull-up node Q when the potential of the second clock signal is at a first potential, so that the third clock terminal CLK3 transmits the third clock signal to the pull-up node Q. Furthermore, the charging circuit 02 can control the third clock terminal CLK3 to be disconnected from the pull-up node Q when the potential of the second clock signal is at a second potential. The potential of the first power supply signal can be a low potential.

[0098] The reset circuit 03 is connected to the reset terminal TRS, the second power supply terminal VGH, the control node P and the pull-up node Q respectively, and is used to control the connection and disconnection of the second power supply terminal VGH and the control node P, and control the connection and disconnection of the second power supply terminal VGH and the pull-up node Q in response to the reset signal provided by the reset terminal TRS.

[0099] For example, the reset circuit 03 can control the second power supply terminal VGH to be conductive with the control node P and the pull-up node Q when the potential of the reset signal is a first potential, so that the second power supply terminal VGH transmits the second power supply signal to the control node P and the pull-up node Q; and can control the second power supply terminal VGH to be disconnected from the control node P and the pull-up node Q when the potential of the reset signal is a second potential. The potential of the second power supply signal is a high potential.

[0100] At least two output circuits 04 are respectively connected to the pull-up node Q, at least two corresponding output clock terminals CLKS1 ... CLKSn, and at least two corresponding output terminals Scout1 ... Scoutn. Each output circuit 04 is configured to control the connection and disconnection between a corresponding output clock terminal and an output terminal in response to the potential of the pull-up node Q, thereby outputting a gate drive signal through the output terminal. Here, n is an integer greater than 1. For example, n can be 2, 4, or other integers.

[0101] For example, each output circuit 04 can control a corresponding output clock terminal to be connected to an output terminal when the potential of the pull-up node Q is a first potential, so that the output clock terminal transmits an output clock signal to the output terminal; and can control a corresponding output clock terminal to be disconnected from the output terminal when the potential of the pull-up node Q is a second potential. The output terminal can be connected to a pixel in the display panel through a gate line and is used to output a gate drive signal to the pixel.

[0102] In summary, an embodiment of the present disclosure provides a shift register unit. The shift register unit includes a pre-charge circuit, a charging circuit, a reset circuit and at least two output circuits. Among them, the pre-charge circuit can control the potential of a control node based on the selection signal provided by multiple selection terminals; the charging circuit can control the potential of the pull-up node based on the potential of the control node and the clock signal; the reset circuit can control the potential of the control node and the pull-up node based on the reset signal; and thus, each of the multiple output circuits can control the on-off of the output terminal and the output clock terminal based on the potential of the pull-up node. In this way, partition selection can be achieved by flexibly setting the selection signal, so that multiple output units can flexibly output gate drive signals to multiple rows of pixels in each partition to drive multiple rows of pixels to emit light. That is, the shift register unit provided by the embodiment of the present disclosure can flexibly refresh pixels according to the display screen partition.

[0103] Alternatively, Figure 2 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure. As shown in Figure 2 , the shift register unit may further include: a pull-down control circuit 05 and a pull-down circuit 06 .

[0104] Among them, the pull-down control circuit 05 can be connected to the control node P, the second clock terminal CLK2, the third clock terminal CLK3, the control power supply terminal V1, the pull-up node Q and the pull-down node QB respectively, and can be used to control the on-off of the second clock terminal CLK2 and the pull-down node QB in response to the potential of the control node P and the third clock signal, control the on-off of the control power supply terminal V1 and the pull-down node QB in response to the second clock signal, and control the on-off of the second clock terminal CLK2 and the pull-down node QB in response to the potential of the pull-up node Q.

[0105] For example, the pull-down control circuit 05 can control the second clock terminal CLK2 to be conductive with the pull-down node QB when the potential of the control node P is at a first potential and the potential of the third clock signal is at a first potential, so that the second clock terminal CLK2 transmits the second clock signal to the pull-down node QB; and can control the second clock terminal CLK2 to be disconnected from the pull-down node QB when the potential of the control node P and / or the potential of the third clock signal is at a second potential. Similarly, the pull-down control circuit 05 can control the control power supply terminal V1 to be conductive with the pull-down node QB when the potential of the second clock signal is at a first potential, so that the control power supply terminal V1 transmits the control power supply signal to the pull-down node QB; and can control the control power supply terminal V1 to be disconnected from the pull-down node QB when the potential of the second clock signal is at a second potential. Similarly, the pull-down control circuit 05 can control the second clock terminal CLK2 to be connected to the pull-down node QB when the potential of the pull-up node Q is the first potential, so that the second clock terminal CLK2 transmits the second clock signal to the pull-down node QB; and can control the second clock terminal CLK2 to be disconnected from the pull-down node QB when the potential of the pull-up node Q is the second potential.

[0106] The control power supply terminal V1 can be shared with the second clock terminal CLK2 or the first power supply terminal VGL. It is understood that since the first power supply terminal VGL can continuously provide a low-potential first power signal, sharing the control power supply terminal V1 with the first power supply terminal VGL helps supplement the potential of the pull-down node QB during low-frequency driving.

[0107] For example, when driven at low frequency, the time that the potential of the second clock signal is at a low potential increases, and the potential of the pull-down node QB also continues to decrease accordingly. At this time, the leakage current of the low-potential first power supply signal through the pull-down control circuit 05 will compensate for the loss of the potential of the pull-down node QB, thereby ensuring that the potential of the pull-down node QB is better.

[0108] The pull-down circuit 06 can be connected to the pull-down node QB, the second power supply terminal VGH, the pull-up node Q and at least two output terminals Scout1...Scoutn respectively, and can be used to control the connection and disconnection of the second power supply terminal VGH and the pull-up node Q in response to the potential of the pull-down node QB, and control the connection and disconnection of the second power supply terminal VGH and each output terminal.

[0109] For example, the pull-down circuit 06 can control the second power supply terminal VGH to be connected to the pull-up node Q when the potential of the pull-down node QB is the first potential, and control the second power supply terminal VGH to be connected to each output terminal, so that the second power supply terminal VGH transmits the second power supply signal to the pull-up node Q and each output terminal; and can control the second power supply terminal VGH to be disconnected from the pull-up node Q when the potential of the pull-down node QB is the second potential, and control the second power supply terminal VGH to be disconnected from each output terminal.

[0110] Optionally, it can be seen from FIG. 2 that the shift register unit may further include: a first isolation circuit 07 .

[0111] The first isolation circuit 07 can be connected between the control node P and the pull-down control circuit 05 and can also be connected to the first power terminal VGL. It can be used to control the control node P and the pull-down control circuit 05 to be conductive in response to the first power signal.

[0112] It is understandable that by providing the first isolation circuit 07 , it is possible to prevent the pull-down control circuit 05 from malfunctioning due to leakage of the control node P, thereby ensuring better operating reliability of the pull-down control circuit 05 .

[0113] Optionally, it can be seen from FIG. 2 that the shift register unit may further include a second isolation circuit 08 .

[0114] The second isolation circuit 08 can be connected between the pull-up node Q and at least two output circuits 04, and can also be connected to the first power supply terminal VGL, and can be used to control the pull-up node Q and at least two output circuits 04 to be conductive in response to the first power supply signal.

[0115] Similar to the first isolation circuit 07, the provision of the second isolation circuit 08 can prevent malfunction of the output circuit 04 due to leakage at the pull-up node Q, thereby ensuring the high reliability of the output circuit 04. Furthermore, the potential change at the node connecting the second isolation circuit 08 to the output circuit 04 can be prevented from affecting the potential of the pull-up node Q, thereby ensuring the high stability of the potential of the pull-up node Q.

[0116] Alternatively, FIG3 illustrates a schematic structural diagram of another shift register unit, taking the example of a control power supply terminal V1 sharing the second clock terminal CLK2. FIG4 illustrates a schematic structural diagram of another shift register unit, taking the example of a control power supply terminal V1 sharing the first power supply terminal VGL. Referring to FIG3 and FIG4 , it can be seen that the precharge circuit 01 may include: a gating subcircuit 011, an auxiliary control subcircuit 012, and a precharge subcircuit 013.

[0117] The gating sub-circuit 011 can be connected to at least two gating terminals D0 ... Dm, the second clock terminal CLK2, and the intermediate node N, and can be used to control the connection and disconnection between the second clock terminal CLK2 and the intermediate node N in response to a gating signal provided by each gating terminal. The gating sub-circuit 011 can also be called a decoding circuit.

[0118] For example, the gating sub-circuit 011 can control the second clock terminal CLK2 to be connected to the intermediate node N when the potential of the gating signal provided by any gating terminal is the first potential, so that the second clock terminal CLK2 transmits the second clock signal to the intermediate node N; and can control the second clock terminal CLK2 to be disconnected from the intermediate node N when the potential of the gating signal provided by each gating terminal is the second potential.

[0119] The auxiliary control circuit 012 may be connected to the first clock terminal CLK1 , the second clock terminal CLK2 and the intermediate node N respectively, and may be used to control the connection and disconnection between the second clock terminal CLK2 and the intermediate node N in response to the first clock signal.

[0120] For example, the auxiliary control circuit 012 can control the second clock terminal CLK2 to be connected to the intermediate node N when the potential of the first clock signal is the first potential, so that the second clock terminal CLK2 transmits the second clock signal to the intermediate node N; and can control the second clock terminal CLK2 to be disconnected from the intermediate node N when the potential of the first clock signal is the second potential.

[0121] The precharge sub-circuit 013 can be connected to the intermediate node N, the first clock terminal CLK1 and the control node P respectively, and can be used to control the connection between the first clock terminal CLK1 and the control node P in response to the potential of the intermediate node N and the first clock signal.

[0122] For example, the pre-charging sub-circuit 013 can control the first clock terminal CLK1 to be connected to the control node P when the potential of the intermediate node N is the first potential and / or the potential of the first clock signal is the first potential, so that the first clock terminal CLK1 transmits the first clock signal to the control node P; and can control the first clock terminal CLK1 to be disconnected from the control node P when the potential of the intermediate node N is the second potential and the potential of the first clock signal is the second potential.

[0123] Optionally, it can be seen from FIG. 3 and FIG. 4 that the second isolation circuit 08 may include at least two isolation sub-circuits 081 .

[0124] The at least two isolation sub-circuits 081 may be connected to the at least two output circuits 04 in a one-to-one correspondence, and may also be connected to the first power supply terminal VGL and the pull-up node Q. Each isolation sub-circuit 081 may be configured to control the connection between the pull-up node Q and a corresponding output circuit 04 in response to the first power supply signal.

[0125] That is, in the embodiment of the present disclosure, for each output circuit 04 , an isolation sub-circuit 081 may be provided to isolate the pull-up node Q from the output circuit 04 , thereby ensuring that each output circuit 04 can operate reliably.

[0126] Alternatively, referring to Figures 2 to 4 , it can be seen that the shift register units shown therein each include four output circuits 04. Accordingly, the four output circuits 04 can be connected to four output clock terminals CLKS1, CLKS2, CLKS3, and CLKS4 in a one-to-one correspondence, and can be connected to four output terminals Scout(i), Scout(i+1), Scout(i+2), and Scout(i+3) in a one-to-one correspondence. i is an integer greater than 0 and less than or equal to n.

[0127] Furthermore, the second isolation circuit 08 may include four isolation sub-circuits 081 as shown in Figures 3 and 4. The nodes connecting the four isolation sub-circuits 081 to the four output circuits 04 are labeled Q1, Q2, Q3, and Q4, respectively, also referred to as output nodes. Based on this, it can be considered that each output circuit 04 controls the connection between the corresponding output clock terminal and the output terminal in response to the potential of the corresponding output node.

[0128] Alternatively, with continued reference to Figures 2 to 4 , it can be seen that in the shift register unit shown therein, the precharge circuit 01 is connected to eight strobe terminals D0, D1, D2, D3, D4, D5, D6, and D7. It is understandable that, with reference to Figures 3 and 4 , the strobe sub-circuit 011 included in the precharge circuit 01 may be connected to the eight strobe terminals D0 to D7.

[0129] 3 and 4 , it can be seen that the pre-charge sub-circuit 013 can also be connected to the first power supply terminal VGL and can be used to store the potential of the control node P based on the first power supply signal. In this way, the potential of the control node P can be maintained.

[0130] 3 and 4 , it can be seen that the pull-down control circuit 05 can also be connected to the second power supply terminal VGH and can be used to store the potential of the pull-down node QB based on the second power supply signal. In this way, the potential of the pull-down node QB can be maintained.

[0131] Alternatively, FIG5 shows a circuit structure diagram of a shift register unit based on FIG3 . FIG6 shows a circuit structure diagram of another shift register unit based on FIG4 . As shown in FIG5 and FIG6 , the gating subcircuit 011 may include: at least two gating transistors T11 ... T1m.

[0132] The gates of the at least two gating transistors T11...T1m can be connected to the at least two gating terminals D0...Dm in a one-to-one correspondence, the first electrodes of the at least two gating transistors T11...T1m can both be connected to the second clock terminal CLK2, and the second electrodes of the at least two gating transistors T11...T1m can both be connected to the intermediate node N.

[0133] It is understood that since the structures shown in Figures 3 and 4 both include eight gate terminals D0 to D7, the circuit structures shown in Figures 5 and 6 both include eight gate transistors T11 to T18. The gates of the eight gate transistors T11 to T18 can be connected to the eight gate terminals D0 to D7 in a one-to-one correspondence.

[0134] Optionally, with continued reference to FIG. 5 and FIG. 6 , it can be seen that the auxiliary control sub-circuit 012 may include: an auxiliary control transistor T20 .

[0135] A gate of the auxiliary control transistor T20 may be connected to the first clock terminal CLK1 , a first electrode of the auxiliary control transistor T20 may be connected to the second clock terminal CLK2 , and a second electrode of the auxiliary control transistor T20 may be connected to the intermediate node N.

[0136] Optionally, with continued reference to FIG. 5 and FIG. 6 , it can be seen that the pre-charging sub-circuit 013 may include: a first pre-charging transistor T31 , a second pre-charging transistor T32 , and a first storage capacitor Cst1 .

[0137] The gate of the first pre-charging transistor T31 may be connected to the middle node N, the first electrode of the first pre-charging transistor T31 may be connected to the first clock terminal CLK1 , and the second electrode of the first pre-charging transistor T31 may be connected to the control node P.

[0138] The gate and the first electrode of the second pre-charging transistor T32 may both be connected to the first clock terminal CLK1 , and the second electrode of the second pre-charging transistor T32 may be connected to the control node P.

[0139] One end of the first storage capacitor Cst1 may be connected to the first power terminal VGL, and the other end of the first storage capacitor Cst1 may be connected to the control node P. That is, the first storage capacitor Cst1 may be connected in series between the first power terminal VGL and the control node P.

[0140] Optionally, referring to FIG. 5 and FIG. 6 , it can be seen that the pull-down control circuit 05 may include: a first pull-down control transistor T41 , a second pull-down control transistor T42 , a third pull-down control transistor T43 , a fourth pull-down control transistor T44 and a second storage capacitor Cst2 .

[0141] The gate of the first pull-down control transistor T41 may be connected to the control node P, the first electrode of the first pull-down control transistor T41 may be connected to the second electrode of the second pull-down control transistor T42, and the second electrode of the first pull-down control transistor T41 may be connected to the pull-down node QB.

[0142] A gate of the second pull-down control transistor T42 may be connected to the third clock terminal CLK3 , and a first electrode of the second pull-down control transistor T42 may be connected to the second clock terminal CLK2 .

[0143] The gate of the third pull-down control transistor T43 can be connected to the second clock terminal CLK2, the first electrode of the third pull-down control transistor T43 can be connected to the control power supply terminal V1, and the second electrode of the third pull-down control transistor T43 can be connected to the pull-down node QB. For example, in FIG5 , the control power supply terminal V1 is the second clock terminal CLK2; in FIG6 , the control power supply terminal V1 is the first power supply terminal VGL.

[0144] A gate of the fourth pull-down control transistor T44 may be connected to the pull-up node Q, a first electrode of the fourth pull-down control transistor T44 may be connected to the second clock terminal CLK2 , and a second electrode of the fourth pull-down control transistor T44 may be connected to the pull-down node QB.

[0145] One end of the second storage capacitor Cst2 may be connected to the second power supply terminal VGH, and the other end of the second storage capacitor Cst2 may be connected to the pull-down node QB. That is, the second storage capacitor Cst2 may be connected in series between the second power supply terminal VGH and the pull-down node QB.

[0146] Optionally, with continued reference to FIG. 5 and FIG. 6 , it can be seen that the pull-down circuit 06 may include: a first pull-down transistor T50 , and at least two second pull-down transistors T51 . . . T5n.

[0147] The gate of the first pull-down transistor T50 may be connected to the pull-down node QB, the first electrode of the first pull-down transistor T50 may be connected to the second power supply terminal VGH, and the second electrode of the first pull-down transistor T50 may be connected to the pull-up node Q.

[0148] The gates of the at least two second pull-down transistors T51...T5n can be connected to the pull-down node QB, the first electrodes of the at least two second pull-down transistors T51...T5n can be connected to the second power supply terminal VGH, and the second electrodes of the at least two second pull-down transistors T51...T5n can be connected to the at least two output terminals Scout1...Scoutn in a one-to-one correspondence.

[0149] It is understood that because the structures shown in Figures 3 and 4 both include four output circuits O4 corresponding to the four output terminals Scout(i) to Scout(i+3), the circuit structures shown in Figures 5 and 6 both include four second pull-down transistors T51, T52, T53, and T54. The second electrodes of the four second pull-down transistors T51 to T54 can be connected to the four output terminals Scout(i) to Scout(i+3) in a one-to-one correspondence.

[0150] Optionally, with continued reference to FIG. 5 and FIG. 6 , it can be seen that the first isolation circuit 07 may include: a first isolation transistor T60 .

[0151] The gate of the first isolation transistor T60 can be connected to the first power supply terminal VGL, the first electrode of the first isolation transistor T60 can be connected to the control node P, and the second electrode of the first isolation transistor T60 can be connected to the pull-down control circuit O5. It is understood that here it can be connected to the gate of the first pull-down control transistor T41. In other words, the gate of the first pull-down control transistor T41 can be indirectly connected to the control node P through the first isolation transistor T60.

[0152] Optionally, with continued reference to FIG. 5 and FIG. 6 , it can be seen that each isolation sub-circuit 081 may include: a second isolation transistor T6x.

[0153] The gate of the second isolation transistor T6x can be connected to the first power supply terminal VGL, the first electrode of the second isolation transistor T6x can be connected to the pull-up node Q, and the second electrode of the second isolation transistor T6x can be connected to a corresponding output circuit O4. It can be understood that the second electrode can be connected to the output node.

[0154] For example, based on the structure including four isolation sub-circuits 081 shown in Figures 3 and 4, the circuit structure shown in Figures 5 and 6 includes four second isolation transistors T61, T62, T63, and T64. The four second isolation transistors T61 to T64 are connected to the four output nodes Q1 to Q4 of the four output circuits 04 in a one-to-one correspondence.

[0155] Optionally, with continued reference to FIG. 5 and FIG. 6 , it can be seen that the charging circuit 02 may include: a first charging transistor T71 , a second charging transistor T72 , and a third charging transistor T73 .

[0156] The gate of the first charging transistor T71 may be connected to the control node P, the first electrode of the first charging transistor T71 may be connected to the first power supply terminal VGL, and the second electrode of the first charging transistor T71 may be connected to the first electrode of the second charging transistor T72.

[0157] A gate electrode of the second charging transistor T72 may be connected to the third clock terminal CLK3 , and a second electrode of the second charging transistor T72 may be connected to the pull-up node Q.

[0158] A gate of the third charging transistor T73 may be connected to the second clock terminal CLK2 , a first electrode of the third charging transistor T73 may be connected to the third clock terminal CLK3 , and a second electrode of the third charging transistor T73 may be connected to the pull-up node Q.

[0159] Optionally, with continued reference to FIG. 5 and FIG. 6 , it can be seen that the reset circuit 03 may include: a first reset transistor T81 and a second reset transistor T82 .

[0160] The gate of the first reset transistor T81 may be connected to the reset terminal TRS, the first electrode of the first reset transistor T81 may be connected to the second power supply terminal VGH, and the second electrode of the first reset transistor T81 may be connected to the control node P.

[0161] A gate of the second reset transistor T82 may be connected to the reset terminal TRS, a first electrode of the second reset transistor T82 may be connected to the second power supply terminal VGH, and a second electrode of the second reset transistor T82 may be connected to the pull-up node Q.

[0162] Optionally, with continued reference to FIG. 5 and FIG. 6 , it can be seen that each output circuit 04 may include: an output transistor T9 x and a third storage capacitor Cst3 x.

[0163] The gate of the output transistor T9x may be connected to the pull-up node Q, the first electrode of the output transistor T9x may be connected to the corresponding output clock terminal, and the second electrode of the output transistor T9x may be connected to the corresponding output terminal.

[0164] One end of the third storage capacitor Cst3 x may be connected to the pull-up node Q, and the other end of the third storage capacitor Cst3 x may be connected to the corresponding output end.

[0165] It is understood that, based on the inclusion of the second isolation circuit 08, the gate of the output transistor T9x can be indirectly connected to the pull-up node Q via the second isolation transistor T6x. Furthermore, one end of the third storage capacitor Cst3x can be indirectly connected to the pull-up node Q via the second isolation transistor T6x. The connection node between the gate of the output transistor T9x, one end of the third storage capacitor Cst3x, and the second isolation transistor T6x is referred to as an output node.

[0166] For example, based on the structure including four output circuits O4 shown in Figures 3 and 4, the circuit structure shown in Figures 5 and 6 includes four output transistors T91, T92, T93, and T94, and four third storage capacitors Cst31, Cst32, Cst33, and Cst34. The gates of the four output transistors T91 to T94 are connected to the four output nodes Q1 to Q4 in a one-to-one correspondence, the first electrodes of the four output transistors T91 to T94 are connected to the four output clock terminals CLKS1 to CLKS4 in a one-to-one correspondence, and the second electrodes of the four output transistors T91 to T94 are connected to the four output terminals Scout(i) to Scout(i+3) in a one-to-one correspondence. One ends of the four third storage capacitors Cst31, Cst32, Cst33 and Cst34 are connected to the four output nodes Q1 to Q4 in a one-to-one correspondence, and the other ends of the four third storage capacitors Cst31, Cst32, Cst33 and Cst34 are connected to the four output terminals Scout(i) to Scout(i+3) in a one-to-one correspondence.

[0167] Combined with the above description, it can be seen that when the potential of the second clock signal provided by the second clock terminal CLK2 is the second potential (e.g., a high potential), the potential of the pull-down node QB can be maintained by the second storage capacitor Cst2. When driven at a low frequency, the time during which the potential of the second clock signal is at the first potential (e.g., a low potential) increases, causing the potential of the pull-down node QB to continue to decrease through the fourth pull-down control transistor T44. At this time, the structure shown in Figure 6 is relative to the structure shown in Figure 5. Since the first electrode of the third pull-down control transistor T43 is connected to the first power supply terminal VGL that continuously provides a low potential, the leakage current of the first power supply terminal VGL through the third pull-down control transistor T43 can compensate for the loss of the potential of the pull-down node QB, thereby ensuring that the potential stability of the pull-down node QB is better.

[0168] Furthermore, as can be seen from the foregoing, the presence of the third storage capacitor Cst3x in the output circuit 04 and the coupling effect of the capacitor can cause the potential of the output nodes (e.g., Q1 to Q4) to change. However, the disclosed embodiment provides a second isolation circuit 08, i.e., a second isolation transistor T6x, to isolate the pull-up node Q from the output node, thereby ensuring that the potential of the pull-up node Q is not affected by the capacitive coupling effect, thereby ensuring that the potential stability of the pull-up node Q is good.

[0169] Optionally, in one implementation, three clock signal lines may be provided in the display panel, connected to the first clock terminal CLK1, the second clock terminal CLK2, and the third clock terminal CLK3, respectively, to provide clock signals. Alternatively, in another implementation, four clock signal lines may be provided in the display panel, connected to the first clock terminal CLK1, the second clock terminal CLK2, and the third clock terminal CLK3, respectively, to provide clock signals. On this basis, as shown in FIG7 , in another circuit structure of a shift register unit, the first clock terminal CLK1 may be replaced by the clock terminal CLK2, the second clock terminal CLK2 may be replaced by the clock terminal CLK3, and the third clock terminal CLK3 may be replaced by the clock terminal CLK4.

[0170] It is understandable that the above implementation method is easier to wire, simplifies the process, saves costs, and facilitates narrow-frame design because it requires fewer clock signal lines. The other implementation method, on the other hand, has more clock signal lines, so it can ensure that the output waveforms can overlap well, meeting the output requirements of large-size and high PPI. PPI (pixels per inch) refers to the number of pixels that can be set in 1 inch of the display panel, which is used to represent the resolution.

[0171] Optionally, each transistor in the structures shown in Figures 5 to 7 is a P-type transistor. Accordingly, as described above, the first potential can be a low potential, and the second potential can be a high potential. Of course, in some other embodiments, each transistor can also be an N-type transistor. On this basis, as described above, the first potential can be a high potential, and the second potential can be a low potential; alternatively, some transistors can be P-type transistors and other transistors can be N-type transistors.

[0172] In summary, an embodiment of the present disclosure provides a shift register unit. The shift register unit includes a pre-charge circuit, a charging circuit, a reset circuit and at least two output circuits. Among them, the pre-charge circuit can control the potential of a control node based on the selection signal provided by multiple selection terminals; the charging circuit can control the potential of the pull-up node based on the potential of the control node and the clock signal; the reset circuit can control the potential of the control node and the pull-up node based on the reset signal; and thus, each of the multiple output circuits can control the on-off of the output terminal and the output clock terminal based on the potential of the pull-up node. In this way, partition selection can be achieved by flexibly setting the selection signal, so that multiple output units can flexibly output gate drive signals to multiple rows of pixels in each partition to drive multiple rows of pixels to emit light. That is, the shift register unit provided by the embodiment of the present disclosure can flexibly refresh pixels according to the display screen partition.

[0173] FIG8 is a flow chart of a driving method of a shift register unit provided by an embodiment of the present disclosure, the method being used to drive the shift register unit shown in any one of FIG1 to FIG7. As shown in FIG8, the method includes:

[0174] Step 801: Reset phase. The reset circuit controls the second power supply terminal to be connected to the control node and the pull-up node in response to the reset signal provided by the reset terminal.

[0175] That is, in the reset phase, the potential of the reset signal provided by the reset terminal may be the first potential.

[0176] Step 802: In the set phase, the precharge circuit controls the first clock terminal to be conductive with the control node in response to the first clock signal provided by the first clock terminal.

[0177] That is, in the set phase, the potential of the first clock signal provided by the first clock terminal may be the first potential.

[0178] Step 803, in the gating stage, the pre-charging circuit controls the connection between the first clock terminal and the control node in response to the gating signal provided by each of the at least two gating terminals and the second clock signal provided by the second clock terminal, and the charging circuit controls the connection between the third clock terminal and the pull-up node in response to the second clock signal provided by the second clock terminal.

[0179] That is, in the gating stage, the potential of the second clock signal provided by the second clock terminal may be the first potential.

[0180] Step 804 , in the input stage, the charging circuit controls the first power supply terminal and the pull-up node to be connected in response to the third clock signal provided by the third clock terminal and the potential of the control node.

[0181] That is, in the gating stage, the potential of the third clock signal provided by the third clock terminal may be the first potential.

[0182] Step 805 , in the output stage, each of the at least two output circuits controls a corresponding output clock terminal to be connected to a corresponding output terminal in response to the potential of the pull-up node.

[0183] It is understandable that since the driving method has substantially the same technical effects as those of the aforementioned shift register unit embodiment, the technical effects of the driving method will not be described repeatedly for the purpose of brevity.

[0184] FIG9 is a schematic diagram of a gate drive circuit according to an embodiment of the present disclosure. As shown in FIG9 , the gate drive circuit includes multiple groups of shift register units GOA, each group of shift register units GOA including at least two shift register units Gate GOA as shown in any one of FIG1 to FIG7 .

[0185] Among them, each group of shift register units GOA shares the first clock terminal CLK1, the second clock terminal CLK2, the third clock terminal CLK3, the output clock terminals CLKS1...CLKSn and the selection terminals D0...Dm, and each group of shift register units GOA is configured to receive different selection signals provided by at least two selection terminals.

[0186] For example, referring to Figure 9, it is a schematic diagram illustrating a structure of a gate drive circuit, taking the circuit structure of the shift register unit shown in Figure 5 as an example. In addition, taking the structure shown in Figure 7 as an example, Figure 10 also schematically illustrates a schematic diagram of the structure of another gate drive circuit.

[0187] In the gate drive circuits shown in FIG9 and FIG10 , each shift register unit is connected to four output terminals Scout(i) to Scout(i+3). For example, the first shift register unit Gate GOA(1) is connected to four output terminals Scout(1) to Scout(4); the second shift register unit Gate GOA(2) is connected to four output terminals Scout(5) to Scout(8); and so on. Furthermore, each group of shift register units GOA is connected to eight strobe terminals D0 to D7. The difference is that each shift register unit in the first group of shift register units GOA receives a strobe signal provided by the eight strobe terminals D0 to D7; and each shift register unit in the second group of shift register units GOA receives a strobe signal provided by the eight strobe terminals D0' and D1 to D7. The strobe signal provided by D0' is the inverse signal of the strobe signal provided by D0. For example, if the strobe signal provided by D0 is 1, indicating a high potential, then the strobe signal provided by D0' is 0, indicating a low potential. Furthermore, the difference between Figure 9 and Figure 10 is that:

[0188] Each group of shift register units GOA shown in FIG9 includes three shift register units, such as Gate GOA (1), Gate GOA (2), and Gate GOA (3). Furthermore, the first clock terminal CLK1, the second clock terminal CLK2, and the third clock terminal CLK3 in each shift register unit can be connected to three clock signal lines, which are also labeled CLK1 to CLK3. Accordingly, the four output clock terminals CLKS1 to CLKS4 corresponding to the four output terminals Scout(i) to Scout(i+3) can be connected to the 12 clock signal lines CLKE1 to CLKE12.

[0189] Each group of shift register units GOA shown in FIG10 includes four shift register units, such as Gate GOA (1), Gate GOA (2), Gate GOA (3), and Gate GOA (4). Furthermore, the first clock terminal CLK2, the second clock terminal CLK3, and the third clock terminal CLK4 in each shift register unit can be connected to four clock signal lines, which are also labeled CLK1 to CLK4. Accordingly, the four output clock terminals CLKS1 to CLKS4 corresponding to the four output terminals Scout(i) to Scout(i+3) can be connected to 16 clock signal lines CLKE1 to CLKE16.

[0190] For example, FIG5 is combined with the structure shown in FIG9 as an example, and FIG11 shows a signal timing diagram of another gate drive circuit. Taking the structure shown in FIG7 and FIG10 as an example, FIG12 shows an operating timing diagram of a gate drive circuit. In addition, FIG11 and FIG12 show the timing diagrams corresponding to the shift register unit connecting the pixels in rows 1 to 4 in the gate drive circuit. Referring to FIG11 and FIG12, it can be seen that the operation of each group of shift register units can be divided into five stages t01 to t05.

[0191] It is understood that, for the structure shown in FIG5 , the clock signal line connected to the first clock terminal may refer to the clock signal line CLK1 connected to the clock terminal CLK1; the clock signal line connected to the second clock terminal may refer to the clock signal line CLK2 connected to the clock terminal CLK2; and the clock signal line connected to the third clock terminal may refer to the clock signal line CLK3 connected to the clock terminal CLK3. For the structure shown in FIG7 , the clock signal line connected to the first clock terminal may refer to the clock signal line CLK2 connected to the clock terminal CLK2; the clock signal line connected to the second clock terminal may refer to the clock signal line CLK3 connected to the clock terminal CLK3; and the clock signal line connected to the third clock terminal may refer to the clock signal line CLK4 connected to the clock terminal CLK4.

[0192] The following description is made with reference to FIG11, taking the structure shown in FIG5 as an example:

[0193] Before stage t01, the reset terminal TRS may first provide a low-level reset signal, turning on both the first reset transistor T81 and the second reset transistor T82, thereby causing the second power terminal VGH to transmit a high-level second power signal to both the control node P and the pull-up node Q.

[0194] At stage t01, the clock signal line CLK1 connected to the first clock terminal CLK1 can provide a low-potential first clock signal, turning on both the auxiliary control transistor T20 and the second pre-charge transistor T32. This allows the first clock terminal CLK1 to transmit the low-potential first clock signal to the control node P, and the second clock terminal CLK2 to transmit the high-potential second clock signal to the intermediate node N. That is, at stage t01, the potential of the control node P can be set low. Accordingly, stage t01 is also referred to as the point P setting stage. Furthermore, referring to FIG11 , it can be seen that at stage t01, the eight selection terminals D0 to D7 all provide low-potential selection signals, meaning that the potentials of the selection signals are all set low, and the selection stage has not yet begun.

[0195] In phase t02, first, since each shift register unit is connected to eight select terminals D0 to D7, it can be seen that the select signals provided by the eight select terminals D0 to D7 can correspond to 256 states. Moreover, in phase t02, for the first 16 output terminals Scout (1) to Scout (16) connected to the first group of shift register units, the potentials of the select signals provided by the eight select terminals D0 to D7 are all high potentials. Accordingly, the eight select transistors T11 to T18 in the first group of shift register units can be turned off, and the potential of the intermediate node N can maintain the high potential of the previous stage. For the 16 output terminals Scout (17) to Scout (32) connected to the second group of shift register units, the potential of the select signal provided by the select terminal D0 among the eight select terminals D0 to D7 can be low potential, and the potentials of the select signals provided by the remaining select terminals can be high potentials. Accordingly, at least the selection transistor T11 in the second group of shift register units can be turned on, thereby enabling the second clock terminal CLK2 to transmit the second clock signal to the intermediate node N. Furthermore, referring to FIG11 , it can be seen that at stage t02 , because the clock signal line CLK2 connected to the second clock terminal CLK2 can provide a low-potential second clock signal, the potential of the intermediate node N can be lowered through the turned-on selection transistor T11.

[0196] At stage t03, the clock signal line CLK3 connected to the third clock terminal CLK3 can provide a low-level third clock signal, turning on the second charging transistor T72. Because the potential of the control node P can be maintained at the low level of the previous stage by the first storage capacitor Cst1, the first charging transistor T71 can also be turned on, thereby enabling the first power terminal VGL to transmit the low-level first power signal to the pull-up node Q. Because the four second isolation transistors T61 to T64 can remain on based on the low-level first power signal, the potentials of the four output nodes Q1 to Q4 can be further set low, thereby enabling the four output transistors T91 to T94 to be turned on. Furthermore, with the potentials of the control node P and the third clock signal all being low, and the potential of the pull-up node Q also being low, the first pull-down control transistor T41, the second pull-down control transistor T42, and the fourth pull-down control transistor T44 can all be turned on, thereby enabling the second clock terminal CLK2 to transmit the second clock signal to the pull-down control node QB. Since the potential of the second clock signal is high in phase t03 , the potential of the pull-down control node QB can be increased.

[0197] At stage t04, the potentials of the four output nodes Q1 to Q4 are further lowered sequentially due to the coupling effect of the third storage capacitor Cst3, fully turning on the four output transistors T91 to T94. The clock signal lines CLKE1 to CLKE4 connected to the four output clock terminals CLKS1 to CLKS4 sequentially provide low-potential clock signals. Consequently, low-potential signals can be sequentially output to the four output terminals Scout1 to Scout4.

[0198] At stage t05, the selection signal provided by selection terminal D0 of the eight selection terminals D0 to D7 jumps to a low level, enabling the second group of shift register units and de-enabling the first group of shift register units. At this point, the selection transistor T11 included in the second group of shift register units can be turned on, and the second clock terminal CLK2 can transmit a low-level second clock signal to the intermediate node N, lowering the level of the intermediate node N. Accordingly, the first pre-charge transistor T31 can be turned on, and the first clock terminal CLK1 can transmit a low-level first clock signal to the control node P, lowering the level of the control node P. Combined with the low-level third clock signal provided by the third clock terminal CLK3, the first pull-down control transistor T41 and the second pull-down control transistor T42 can be turned on. The second clock terminal CLK2 also transmits a low-level second clock signal to the pull-down control node QB, lowering the level of the pull-down control node QB. Accordingly, the first pull-down transistor T50 and the four second pull-down transistors T51 to T54 are all turned on, thereby causing the second power supply terminal VGH to output a high-potential second power supply signal to the pull-up node Q and the four output terminals Scout1 to Scout4, thereby setting the potential of the pull-up node Q and the potential of the signals output by the four output terminals Scout1 to Scout4 to high. Based on the high potential of the pull-up node Q, because the four second isolation transistors T61 to T64 can remain turned on based on the low-potential first power supply signal, the potential of the four output nodes Q1 to Q4 can be further increased. This phase t05 can also be called a reset phase, and this phase t05 can be repeated when the shift register unit is not selected.

[0199] It can be understood that, in conjunction with Figure 11, stage t05 can actually be divided into three stages t05a, t05b, and t05c that are executed in sequence. Figure 12 is similar to Figure 11 and will not be described in detail.

[0200] In stage t05a, the clock signal line CLK2 connected to the second clock terminal CLK2 can provide a low-potential second clock signal, while the potentials of the first clock signal and the third clock signal can both be high, and the potential of the selection signal provided by the selection terminal D0 can be low. Accordingly, the third pull-down control transistor T43 and the selection transistor T11 can both be turned on, thereby causing the second clock terminal CLK2 to transmit the low-potential second clock signal to the intermediate node N and the pull-down control node QB, respectively, i.e., setting the potentials of the intermediate node N and the pull-down control node QB to low. Accordingly, the first pre-charge transistor T31 can be turned on, thereby causing the first clock terminal CLK1 to transmit the first clock signal to the control node P. Since the potential of the first clock signal is high in stage t05a, the potential of the control node P can be high. Furthermore, the first pull-down transistor T50 and the four second pull-down transistors T51 to T54 can all be turned on, thereby causing the second power supply terminal VGH to output a high-potential second power supply signal to the pull-up node Q and the four output terminals Scout1 to Scout4. That is, the potential of the pull-up node Q and the potential of the signals output by the four output terminals Scout1 to Scout4 can all be set high. With the potential of the pull-up node Q set high, the four output transistors T91 to T94 can all be turned off.

[0201] In stage t05b, the clock signal line CLK3 connected to the third clock terminal CLK3 can provide a low-potential second clock signal, while the potential of the first clock signal and the potential of the second clock signal can both be high, and the potential of the gating signal provided by the gating terminal D0 can be low. Accordingly, the gating transistor T11 can be turned on, and then the second clock terminal CLK2 can transmit a high-potential second clock signal to the intermediate node N, that is, the potential of the intermediate node N is raised, so that the first pre-charge transistor T31 is turned off. In addition, because the potential of the first clock signal is high, the second pre-charge transistor T32 can also be turned off. It can be seen from this that in this stage t05b, the control node P can be in a floating state, maintaining the high potential of the previous stage (i.e., stage t05a). Accordingly, the first pull-down control transistor T41 can be turned off. And, under the storage effect of the second storage capacitor Cst2, the potential of the pull-down control node QB can also maintain the low potential of the previous stage (i.e., stage t05a).

[0202] In phase t05c, the clock signal line CLK1 connected to the first clock terminal CLK1 can provide a low-level first clock signal, while the second and third clock signals can both be high-level, and the selection signal provided by the selection terminal D0 can be low-level. Accordingly, the selection transistor T11, the auxiliary control transistor T20, and the second pre-charge transistor T32 can all be turned on, thereby causing the first clock terminal CLK1 to transmit the low-level first clock signal to the control node P, and causing the second clock terminal CLK2 to transmit the high-level second clock signal to the intermediate node N. This means that the control node P can be low-level and the intermediate node N can be high-level.

[0203] Moreover, taking the structure shown in FIG5 as an example, combined with the foregoing description, it can be seen that for multiple groups of shift register units GOA, the shift register unit Gate GOA in any group of shift register units GOA can be selected by controlling the potential of the selection signal provided by the eight selection terminals D0 to D7, so that the selected group of shift register units GOA can output the gate drive signal to the connected pixels through the output terminal, and the other groups of shift register units GOA that are not selected will not output the gate drive signal, thereby flexibly controlling the refresh frequency of the pixels connected to any group of shift register units.

[0204] FIG13 also illustrates a timing diagram of a strobe signal. Referring to FIG13 , it can be seen that, among the eight strobe terminals D0 through D7, the frequencies of the strobe signals provided by the first strobe terminal D0 through the eighth strobe terminal D7 can also be sequentially reduced as described above. In FIG13 , using the first strobe terminal D0 as an example, D0 may refer to a strobe signal with an inactive potential provided by strobe terminal D0, and De0 may refer to a strobe signal with an active potential provided by strobe terminal D0. The same applies to the other strobe terminals and will not be further described here.

[0205] It is understandable that since the gate driving circuit has substantially the same technical effects as those of the aforementioned shift register unit embodiment, the technical effects of the gate driving circuit will not be described repeatedly for the purpose of brevity.

[0206] FIG14 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG14 , the display device includes: a display panel 10 and a gate driving circuit 00 as shown in FIG9 or FIG10 .

[0207] The display panel 10 includes a plurality of pixels, and the gate driving circuit 00 is connected to the plurality of pixels and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

[0208] Optionally, Figure 15 shows a schematic diagram of the circuit structure of a pixel. As shown in Figure 15, the pixel may include a pixel circuit and a light-emitting element L1. The pixel circuit may include seven transistors M1 to M7 and a capacitor Cst. And the pixel circuit is respectively connected to six signal lines: a pull-up power line ELVDD, a gate line Scan(i), a reset control line Scan(i-1), a light-emitting control line EM(i), a data signal line Data, and a reset line Init. The pixel circuit of this architecture is also called a 7T-1C-6L (i.e., 7 transistors, 1 capacitor, and 6 signal lines) circuit architecture. In addition, the light-emitting element L1 is also connected to the pull-down power line ELVSS.

[0209] Among them, transistor M1 is a driving transistor, and transistors M2 through M7 are switching transistors. The gate-source voltage difference Vgs of transistor T1 can be stored in capacitor Cst, and the driving current I is determined based on grayscale data. Furthermore, transistors M2 and M7, under the control of signals provided by six signal lines, can control transistor M1 to output a driving current as a light-emitting driving signal to light-emitting element L1, allowing light-emitting element L1 to reliably emit light based on this light-emitting driving signal and the pull-down power signal provided by the pull-down power line ELVSS. Among transistors M2 through M7, M5 and M6 are primarily used to control the connection between transistor M1 and light-emitting element L1 based on a signal provided by the light-emitting control line EM(i), thereby blocking the driving current I or allowing the driving current I to flow into light-emitting element L1. Accordingly, it can be seen that the signal provided by the light-emitting control line EM(i) can be used for dimming.

[0210] Optionally, the light-emitting element L1 may be an organic light-emitting diode (OLED), and Figure 15 also schematically illustrates a parasitic capacitor Coled formed between the cathode and anode of the OLED. In addition, each transistor in the pixel shown in Figure 15 is a P-type transistor.

[0211] Taking the structure shown in Figure 15 as an example, Figure 16 schematically shows a working timing diagram of a pixel. Referring to Figure 16, it can be seen that the pixel light emission can include phase 1, phase 2 and phase 3.

[0212] In stage 1, the reset control line Scan(i-1) can provide a reset control signal with an effective potential, turning on transistor M4, thereby causing the reset line Init to output a reset signal to the gate of transistor M1 to reset the gate of transistor M1. In stage 2, the gate line Scan(i) can provide a gate drive signal with an effective potential, turning on transistors M2, M3, and M7, thereby causing the data line Data to output a data signal to the first electrode of transistor M1, causing the reset line Init to output a reset signal to the light-emitting element L1 to reset the light-emitting element L1 and turn on the gate and second electrode of transistor M1. In stage 3, the light-emitting control line EM(i) can provide a light-emitting control signal with an effective potential, turning on transistors M5 and M6, thereby causing transistor M1 to generate a drive current and output the drive current to the light-emitting element L1, thereby driving the light-emitting element L1 to emit light.

[0213] It can be seen from this that in the gate drive circuit provided by the embodiment of the present disclosure, the output terminal Scout(i) of the shift register unit can be connected to the gate line Scan(i) in the pixel shown in Figure 15, and is used to output the gate drive signal shown in Figure 16 to the gate line Scan(i), thereby driving the pixel to emit light.

[0214] Optionally, the display device described in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0215] It is understood that the terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0216] For example, the words “first”, “second” or “third” and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as “a” or “an” do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as “include” or “comprise” mean that the elements or objects appearing before “include” or “comprise” include the elements or objects listed after “include” or “comprise” and their equivalents, and do not exclude other elements or objects. “Up”, “down”, “left” or “right” are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. “Connected” means electrically connected. “And / or” means that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character “ / ” generally indicates that the objects related to each other are in an “or” relationship.

[0217] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A shift register unit, comprising: a precharge circuit, connected to at least two strobe terminals, a first clock terminal, a second clock terminal, and a control node, respectively, and configured to control the connection and disconnection between the first clock terminal and the control node in response to a strobe signal provided by each of the strobe terminals, a first clock signal provided by the first clock terminal, and a second clock signal provided by the second clock terminal; a charging circuit, connected to the control node, the second clock terminal, the third clock terminal, the first power terminal, and the pull-up node, respectively, and configured to control the connection and disconnection between the first power terminal and the pull-up node in response to the potential of the control node and a third clock signal provided by the third clock terminal, and to control the connection and disconnection between the third clock terminal and the pull-up node in response to the second clock signal; a reset circuit, connected to the reset terminal, the second power terminal, the control node, and the pull-up node, respectively, and configured to control the connection and disconnection between the second power terminal and the control node, and the connection and disconnection between the second power terminal and the pull-up node, in response to a reset signal provided by the reset terminal; At least two output circuits are respectively connected to the pull-up node, at least two output clock terminals corresponding to each other, and at least two output terminals corresponding to each other. Each of the output circuits is used to control the connection and disconnection of a corresponding output clock terminal and an output terminal in response to the potential of the pull-up node, so as to output a gate drive signal through the output terminal.

2. The shift register unit according to claim 1, wherein: The pre-charging circuit comprises: a gating subcircuit, connected to the at least two gating terminals, the second clock terminal and the intermediate node respectively, and configured to control the connection and disconnection between the second clock terminal and the intermediate node in response to a gating signal provided by each of the gating terminals; an auxiliary control subcircuit, connected to the first clock terminal, the second clock terminal, and the intermediate node, respectively, and configured to control the connection and disconnection between the second clock terminal and the intermediate node in response to a first clock signal; The precharge subcircuit is connected to the intermediate node, the first clock terminal and the control node respectively, and is used to control the connection and disconnection of the first clock terminal and the control node in response to the potential of the intermediate node and the first clock signal.

3. The shift register unit according to claim 2, wherein: The gating subcircuit includes: at least two gating transistors; The gates of the at least two gating transistors are connected to the at least two gating terminals in a one-to-one correspondence, the first electrodes of the at least two gating transistors are connected to the second clock terminal, and the second electrodes of the at least two gating transistors are connected to the intermediate node.

4. The shift register unit according to claim 2 or 3, wherein: The auxiliary control subcircuit includes: an auxiliary control transistor; The gate of the auxiliary control transistor is connected to the first clock terminal, the first electrode of the auxiliary control transistor is connected to the second clock terminal, and the second electrode of the auxiliary control transistor is connected to the intermediate node.

5. The shift register unit according to any one of claims 2 to 4, wherein: The pre-charging sub-circuit is further connected to the first power supply terminal and is used to store the potential of the control node based on the first power supply signal; The pre-charging sub-circuit comprises: a first pre-charging transistor, a second pre-charging transistor and a first storage capacitor; The gate of the first pre-charging transistor is connected to the intermediate node, the first electrode of the first pre-charging transistor is connected to the first clock terminal, and the second electrode of the first pre-charging transistor is connected to the control node; The gate and the first electrode of the second pre-charging transistor are both connected to the first clock terminal, and the second electrode of the second pre-charging transistor is connected to the control node; One end of the first storage capacitor is connected to the first power supply end, and the other end of the first storage capacitor is connected to the control node.

6. The shift register unit according to any one of claims 1 to 5, wherein: The shift register unit further includes: The pull-down control circuit is connected to the control node, the second clock terminal, the third clock terminal, the control power terminal, the pull-up node and the pull-down node respectively, and is used to control the connection and disconnection between the second clock terminal and the pull-down node in response to the potential of the control node and the third clock signal, control the connection and disconnection between the control power terminal and the pull-down node in response to the second clock signal, and control the connection and disconnection between the control power terminal and the pull-down node in response to the third clock signal. The potential of the pull-up node controls the connection between the second clock terminal and the pull-down node; a pull-down circuit, connected to the pull-down node, the second power supply terminal, the pull-up node, and the at least two output terminals, respectively, and configured to control the connection and disconnection between the second power supply terminal and the pull-up node, and control the connection and disconnection between the second power supply terminal and each of the output terminals, in response to the potential of the pull-down node; Wherein, the control power supply terminal is shared with the second clock terminal or the first power supply terminal.

7. The shift register unit according to claim 6, wherein: The pull-down control circuit is further connected to the second power supply terminal and is used to store the potential of the pull-down node based on the second power supply signal; The pull-down control circuit includes: a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, a fourth pull-down control transistor and a second storage capacitor; The gate of the first pull-down control transistor is connected to the control node, the first electrode of the first pull-down control transistor is connected to the second electrode of the second pull-down control transistor, and the second electrode of the first pull-down control transistor is connected to the pull-down node; The gate of the second pull-down control transistor is connected to the third clock terminal, and the first electrode of the second pull-down control transistor is connected to the second clock terminal; The gate of the third pull-down control transistor is connected to the second clock terminal, the first electrode of the third pull-down control transistor is connected to the control power supply terminal, and the second electrode of the third pull-down control transistor is connected to the pull-down node; The gate of the fourth pull-down control transistor is connected to the pull-up node, the first electrode of the fourth pull-down control transistor is connected to the second clock terminal, and the second electrode of the fourth pull-down control transistor is connected to the pull-down node; One end of the second storage capacitor is connected to the second power supply end, and the other end of the second storage capacitor is connected to the pull-down node.

8. The shift register unit according to claim 6 or 7, wherein: The pull-down circuit includes: a first pull-down transistor, and at least two second pull-down transistors; The gate of the first pull-down transistor is connected to the pull-down node, the first electrode of the first pull-down transistor is connected to the second power supply terminal, and the second electrode of the first pull-down transistor is connected to the pull-up node; The gates of the at least two second pull-down transistors are both connected to the pull-down node. The first electrodes of the second pull-down transistors are all connected to the second power supply end, and the second electrodes of the at least two second pull-down transistors are connected to the at least two output ends in a one-to-one correspondence.

9. The shift register unit according to any one of claims 6 to 8, wherein: The shift register unit further includes: The first isolation circuit is connected between the control node and the pull-down control circuit and is also connected to the first power supply terminal, and is used to control the control node and the pull-down control circuit to be conductive in response to the first power supply signal.

10. The shift register unit according to claim 9, wherein: The first isolation circuit includes: a first isolation transistor; A gate of the first isolation transistor is connected to the first power supply terminal, a first electrode of the first isolation transistor is connected to the control node, and a second electrode of the first isolation transistor is connected to the pull-down control circuit.

11. The shift register unit according to any one of claims 1 to 10, wherein: The shift register unit further includes: The second isolation circuit is connected between the pull-up node and the at least two output circuits and is also connected to the first power supply terminal, and is used to control the pull-up node and the at least two output circuits to be conductive in response to the first power supply signal.

12. The shift register unit according to claim 11, wherein: The second isolation circuit includes: at least two isolation sub-circuits; The at least two isolation sub-circuits are connected to the at least two output circuits in a one-to-one correspondence, and are also connected to the first power supply terminal and the pull-up node. Each of the isolation sub-circuits is used to control the on / off connection between the pull-up node and the corresponding one of the output circuits in response to the first power supply signal.

13. The shift register unit according to claim 12, wherein: Each of the isolation sub-circuits includes: a second isolation transistor; The gate of the second isolation transistor is connected to the first power supply terminal, and the second isolation transistor The first electrode of the second isolation transistor is connected to the pull-up node, and the second electrode of the second isolation transistor is connected to a corresponding one of the output circuits.

14. The shift register unit according to any one of claims 1 to 13, wherein: The charging circuit includes: a first charging transistor, a second charging transistor and a third charging transistor; The gate of the first charging transistor is connected to the control node, the first electrode of the first charging transistor is connected to the first power supply terminal, and the second electrode of the first charging transistor is connected to the first electrode of the second charging transistor; The gate of the second charging transistor is connected to the third clock terminal, and the second electrode of the second charging transistor is connected to the pull-up node; A gate of the third charging transistor is connected to the second clock terminal, a first electrode of the third charging transistor is connected to the third clock terminal, and a second electrode of the third charging transistor is connected to the pull-up node.

15. The shift register unit according to any one of claims 1 to 14, wherein: The reset circuit includes: a first reset transistor and a second reset transistor; The gate of the first reset transistor is connected to the reset terminal, the first electrode of the first reset transistor is connected to the second power supply terminal, and the second electrode of the first reset transistor is connected to the control node; A gate of the second reset transistor is connected to the reset terminal, a first electrode of the second reset transistor is connected to the second power supply terminal, and a second electrode of the second reset transistor is connected to the pull-up node.

16. The shift register unit according to any one of claims 1 to 15, wherein: Each of the output circuits comprises: an output transistor and a third storage capacitor; The gate of the output transistor is connected to the pull-up node, the first electrode of the output transistor is connected to the corresponding output clock terminal, and the second electrode of the output transistor is connected to the corresponding output terminal; One end of the third storage capacitor is connected to the pull-up node, and the other end of the third storage capacitor is connected to the corresponding output end.

17. The shift register unit according to any one of claims 1 to 16, wherein: The shift register unit includes: four output circuits; The precharge circuit is connected to the eight strobe terminals.

18. A method for driving a shift register unit, for driving the shift register unit according to any one of claims 1 to 17; the method comprising: In the reset phase, the reset circuit controls the second power supply terminal to be connected to the control node and the pull-up node in response to the reset signal provided by the reset terminal; In the set phase, the precharge circuit controls the first clock terminal to be conductive with the control node in response to the first clock signal provided by the first clock terminal; In a gating stage, the pre-charging circuit controls the connection between the first clock terminal and the control node in response to a gating signal provided by each of the at least two gating terminals and a second clock signal provided by the second clock terminal, and the charging circuit controls the connection between the third clock terminal and the pull-up node in response to the second clock signal provided by the second clock terminal; In the input stage, the charging circuit controls the first power supply terminal to be connected to the pull-up node in response to the third clock signal provided by the third clock terminal and the potential of the control node; In the output stage, each of the at least two output circuits controls a corresponding output clock terminal to be connected to a corresponding output terminal in response to the potential of the pull-up node.

19. A gate drive circuit, comprising: A plurality of groups of shift register units, each group of shift register units comprising: at least two shift register units according to any one of claims 1 to 17; Each group of shift register units shares a first clock terminal, a second clock terminal, a third clock terminal, an output clock terminal and a strobe terminal, and each group of shift register units is configured to receive different strobe signals provided by at least two of the strobe terminals.

20. A display device, comprising: A display panel, and a gate driving circuit as claimed in claim 19; The display panel includes a plurality of pixels, and the gate drive circuit is connected to the plurality of pixels. and is used to transmit gate driving signals to the multiple pixels to drive the multiple pixels to emit light.

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