Stress merging in semiconductor elements

Abstract

The techniques include a semiconductor element having improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region including at least one channel between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion truncation, and the second gate region includes a first gate surrounding the channel between the source region and the drain region. The self-aligned single diffusion truncation also includes a stressed dielectric material having a stress of about 500 MPa or greater.

Description

TECHNICAL FIELD

[0001] This application claims the benefit of and priority to U.S. Patent Application No. 63 / 487,501, filed February 28, 2023, entitled “STRESS INCORPORATION IN SEMICONDUCTOR DEVICES,” the entire contents of which are incorporated herein by reference.

[0002] The present technology relates to semiconductor processing methods. More specifically, the present technology relates to methods for incorporating increased stress in doped regions of semiconductor elements. BACKGROUND

[0003] Integrated circuits have evolved into complex devices which can include millions of transistors, capacitors and resistors on a single chip. During the evolution of integrated circuits, the functional density (i.e., the number of interconnected elements per chip area) has generally increased while the geometry size has decreased. Transistors are circuit components or elements that are typically formed on a semiconductor element. Depending on the circuit design, many transistors can be formed on a semiconductor element in addition to capacitors, inductors, resistors, diodes, wires, or other elements. Integrated circuits include field-effect transistors (FETs), in which current flows through a semiconductor channel between a source and a drain in response to a voltage applied to a control gate.

[0004] Integrated circuits are made possible by processes that produce complex patterned layers of material on a substrate surface. Producing patterned material on a substrate requires controlled methods for forming and removing material. As element sizes continue to shrink, film properties can have a greater influence on element performance. As elements shrink and more complex patterning schemes are employed in the industry, deposition of thin films becomes a challenge. In addition, as material thicknesses continue to shrink, post-deposition properties of thin films can have a greater influence on element performance. These challenges include deposition of void-free and stressed films.

[0005] Accordingly, there is a need for high quality elements and structures with improved mobility, and methods of manufacturing such elements. The present technology addresses these and other needs. SUMMARY

[0006] Embodiments of the present technology include a semiconductor element with improved stress in a channel region. Embodiments of the semiconductor element include a substrate, a source region, a drain region, a channel region including at least one channel between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion cut in a p-MOS region, and the second gate region includes a first gate that surrounds the channel between the source region and the drain region. The self-aligned single diffusion cut also includes a stressed dielectric material having a compressive stress greater than or about 500 MPa.

[0007] In embodiments, the channel region has a compressive stress greater than or about 500 MPa. In further embodiments, the semiconductor element also includes a third gate region, where the second gate region is disposed between the first gate region and the third gate region. In more embodiments, the third gate region includes a second self-aligned single diffusion cut. Additional embodiments include a channel region having a first channel region stress at a first location and a second channel region stress at a second location within the channel region spaced apart from the first location, where the first channel region stress and the second channel region stress differ by about 30% or less. Embodiments include a channel region including a plurality of horizontally extending channels. In embodiments, the semiconductor element is a nanosheet field effect transistor or a complementary field effect transistor. In further embodiments, the semiconductor element is a fully wrapped gate complementary metal oxide semiconductor.

[0008] Embodiments include a second gate region having a tensile stress dielectric material or high energy implant with a tensile stress greater than or about 500 MPa. In additional embodiments, a third gate region includes a compressive stress dielectric material with a compressive stress greater than or about 500 MPa. In further embodiments, the third gate region includes a compressive stress dielectric material. In more embodiments, the self-aligned diffusion cut defines a volume, where the stressed dielectric material occupies greater than or about 90% by volume of the volume. In embodiments, the stressed dielectric material is generally void or seam free. Embodiments include a stressed dielectric material occupying greater than or about 98% by volume of the self-aligned diffusion cut volume. In additional embodiments, the stressed dielectric material has a compressive stress greater than or about 1000 MPa, the channel region is a p-channel metal oxide semiconductor, and the channel region has a compressive stress greater than or about 600 MPa.

[0009] Embodiments of the present technology also include a semiconductor processing system. The semiconductor processing system includes a first processing chamber; a second processing chamber; a third processing chamber; and a system controller. In embodiments, the system controller is configured to pattern a substrate in the first processing chamber, etch a shallow trench isolation in a first gate region of a semiconductor element, wherein the first gate region is a p-MOS region in the second processing chamber, and fill the shallow trench isolation with a stressed dielectric material having a compressive stress of at least about 500 MPa in the third processing chamber.

[0010] Embodiments of the present technology also include a method of forming a semiconductor element with improved stress in a channel region. The method includes etching a shallow trench isolation in a first gate region of a semiconductor element. The semiconductor element includes a substrate, a source region, a drain region, a channel region including at least one channel between the source and the drain, the first gate region, and a second gate region. The second gate region includes a first gate surrounding the channel between the source region and the drain region. The method includes filling the shallow trench isolation with a stressed dielectric material having a stress of at least about 500 MPa.

[0011] In embodiments, the semiconductor element exhibits a first amount of stress in the channel region prior to etching and filling, and a second amount of stress in the channel region after etching and filling, wherein a percentage change from the first amount of stress to the second amount of stress is greater than or about 10%, or the semiconductor element exhibits a first hole mobility prior to etching and filling, and a second hole mobility after etching and filling, wherein a percentage change from the first hole mobility to the second hole mobility is greater than or about 10%. In further embodiments, the semiconductor element includes a third gate region, the second gate region disposed between the first gate region and the third gate region. Embodiments include etching the third gate region during etching the first gate region, or the third gate region is masked during etching the first gate region and undergoes patterning and etching after etching the first gate region, thereby forming a second shallow trench isolation in the third gate region. In more embodiments, the shallow trench isolation is filled with a compressive stress dielectric material, and the second shallow trench isolation is filled with a compressive stress dielectric material, a tensile stress dielectric material, or a high energy implant.

[0012] Such technology can provide numerous benefits over known technology. For example, embodiments of the present technology produce a desired stress level in a channel region of a semiconductor transistor without changing the composition of adjacent source and drain regions. In addition, the present technology produces channel region stress from existing diffusion cut-offs, thereby allowing for more compact elements with improved stress. Thus, the present technology can provide improved stress without requiring additional channels or diffusion cut-offs of increased size. These and other embodiments, along with many of their advantages, are described in more detail in conjunction with the drawing figures, wherein like numbers represent similar structural elements throughout the drawing figures, and BRIEF DESCRIPTION OF DRAWINGS

[0013] A further understanding of the nature and advantages of the disclosed technology may be obtained by reference to the remaining portions of the specification and drawings.

[0014] Figure 1 Illustrated is a top plan view of an exemplary processing chamber according to some embodiments of the present technology.

[0015] Figure 2 Illustrated are selected operations in a method of formation according to some embodiments of the present technology.

[0016] Figures 3A to 3E Illustrated is a cross-sectional view of an exemplary semiconductor structure according to some embodiments of the present technology.

[0017] Figure 4 Illustrated is a cross-sectional view of an exemplary semiconductor structure according to some embodiments of the present technology.

[0018] Figure 5 Illustrated are selected operations in a method of formation according to some embodiments of the present technology.

[0019] Figure 6 Illustrated are selected operations in a method of formation according to some embodiments of the present technology.

[0020] Several of the drawings are schematic. It should be understood that the drawings are for illustrative purposes and should not be considered to be drawn to scale unless specifically indicated as such. Furthermore, as schematic diagrams, these drawings are provided to aid understanding and may not include all aspects or information compared to realistic representations, and may include exaggerated material for illustrative purposes.

[0021] In the drawings, similar components and / or features may have the same reference number. Furthermore, various components of the same type may be distinguished by following the reference number with a letter that distinguishes the similar components. If only the first reference number is used in the specification, the description applies to any similar component having the same first reference number, regardless of the letter. DETAILED DESCRIPTION

[0022] The present technology includes electronic elements and methods of forming electronic elements having one or more self-aligned single diffusion breaks. Such electronic elements can include semiconductor transistors such as n-channel and p-channel MOSFETs, FinFETs, fully wrapped gate FETs, and nanosheet FETs, and other types of transistors, as well as products having such channel regions. In the prior art, stress levels in transistor channels can be controlled by changing the composition of the semiconductor material in the channel and the composition of the material in adjacent source and drain regions. In many cases, changing the composition of these doped regions of the transistor to give the channel region the desired amount of stress results in less than desirable transistor performance in other respects, such as lower thermal budgets and / or increased resistance at the interface between the contacts and the doped regions. Controlling channel region stress by changing the composition of the doped regions also limits the types of materials that can be used for the doped regions. For example, modern PMOS transistors often use doped silicon germanium (SiGe) semiconductors in the doped regions of the transistor. When the germanium to silicon ratio is too high, lattice mismatch creates defects in the material, which reduces the channel region stress below an acceptable level.

[0023] Another prior art method of increasing stress in the channel region of a transistor is to deposit a stressed conductive material in a contact trench above the channel region. Stress from the conductive material is transmitted downward to impart the desired stress in the doped material of the channel region. These prior art methods also require careful selection and deposition of the conductive material in the contact trench to meet stress requirements and other requirements for the conductivity, chemical reactivity, encapsulation, thermal budget, and other requirements of the material. In many cases, in order to meet stress requirements, there must be compromises in the selection of the conductive material in certain respects that are less than ideal. Changes in the method or composition of the stressed material create additional stress that reduces the performance of the material in other respects, such as conductivity.

[0024] However, as increasingly complex gate and channel surface orientations have emerged, the prior art methods have proven to be increasingly ineffective. That is, gate orientations of multi-channel semiconductor nanostructures, such as fully wrapped gates, complementary FETs, nanosheets, and nanowire orientations, just as examples, hinder the effectiveness of prior stress imparting. For example, prior methods for increasing stress can impart sufficient stress at the upper gate and / or lower gate, but cannot provide the necessary stress to gates disposed therebetween. Furthermore, in addition to unfavorable surface orientations, multi-channel semiconductor nanostructures also exhibit unfavorable hole and / or electron mobilities, at least in part due to poor stress uniformity. Such hole mobility deficiencies are particularly evident in comparison to traditional gates and favorable channel orientations, such as fin field-effect transistors (FinFETs).

[0025] Efforts to modify channel strain in multi-channel semiconductor nanostructures specifically include source and drain regions formed through epitaxial growth processes. However, epitaxial coalescence suffers from the disadvantage of misregistration during and after formation due to complex geometry and surface orientation, particularly in p-type metal oxide semiconductor (PMOS) regions. Such misregistration pulls the epitaxially grown material away from the gate and creates a misregistration seam, resulting in relaxation of channel stress over time. Methods have been sought to improve epitaxial coalescence defects as a means of providing consistent channel stress. However, none of the existing methods have proven sufficient to provide consistent stress and / or improve electron and hole mobility.

[0026] The present technology overcomes these challenges by providing consistent stress channels with improved hole and / or electron mobility. By utilizing one or more self-aligned single diffusion cuts with a dielectric stress film, a stress channel region can be provided without the need to alter the composition of the transistor doped regions. In embodiments of the present technology, stress results from the deposition of a stressed material in one or more self-aligned single diffusion cuts adjacent to one or more doped regions of a transistor. The stressed material can initially apply stress to the one or more self-aligned single diffusion cuts, which in turn can transmit a portion of the stress to the channel region of the transistor.

[0027] While the remaining content will routinely identify specific metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide semiconductors (CMOSs), and components thereof, it will be readily understood that these elements and methods are equally applicable to other field-effect transistors and orientations thereof as processes for forming such elements. Accordingly, the technology should not be considered limited to use with these particular elements or methods. The present disclosure will discuss one possible semiconductor element that can include one or more components that utilize one or more self-aligned single diffusion cuts according to embodiments of the present technology, after which additional variations and adaptations of the device according to embodiments of the present technology are described.

[0028] Figure 1A top plan view of a multi-chamber processing system 100 is shown, which can be configured to implement aspects or operations in accordance with some embodiments of the present technology. The multi-chamber processing system 100 can be configured to perform one or more fabrication processes on a single substrate, such as any number of semiconductor substrates, to form a semiconductor device. The multi-chamber processing system 100 can include some or all of a transfer chamber 106, a buffer chamber 108, single wafer load locks 110 and 112 (although dual load locks can also be included), processing chambers 114, 116, 118, 120, 122, and 124, pre-heat chambers 123 and 125, and robots 126 and 128. The single wafer load locks 110 and 112 can include heating elements 113 and can be attached to the buffer chamber 108. The processing chambers 114, 116, 118, and 120 can be attached to the transfer chamber 106. The processing chambers 122 and 124 can be attached to the buffer chamber 108. Two substrate transfer platforms 102 and 104 can be disposed between the transfer chamber 106 and the buffer chamber 108 and can facilitate transfers between the robots 126 and 128. The platforms 102, 104 can be open to the transfer chamber and the buffer chamber, or the platforms can be selectively isolated or sealed from the chambers to allow different operating pressures to be maintained between the transfer chamber 106 and the buffer chamber 108. The transfer platforms 102 and 104 can each include one or more tools 105, such as for orientation or measurement operations.

[0029] The operation of the multi-chamber processing system 100 can be controlled by a computer system 130. The computer system 130 can include any device or combination of devices configured to implement the operations described below. Thus, the computer system 130 can be a controller or array of controllers, and / or a general purpose computer configured with software stored on a non-transitory computer readable medium that, when executed, can perform the operations described for the methods in accordance with embodiments of the present technology. Each of the processing chambers 114, 116, 118, 120, 122, and 124 can be configured to perform one or more process steps in the fabrication of semiconductor structures. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 can be constructed to perform a variety of substrate processing operations including dry etching processes, cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and any number of other substrate processes.

[0030] Figure 2Illustrative operations in method 200 according to some embodiments of the present technology are illustrated. The method can be performed in various processing chambers, including the processing chamber 100 described above. Method 200 may include a number of optional operations that may or may not be specifically associated with some embodiments of the method according to the present technology. For example, various operations are described to provide for a wider range of structure formation, but these operations are not critical to the technology or can be performed through readily understood alternative methods.

[0031] The method 200 may include additional operations prior to initiating the listed operations. For example, the additional processing operations may include forming structures on the semiconductor substrate, which may include forming and removing materials. The previous processing operations may be performed in the chamber in which the method 200 may be performed, or the processing may be performed in one or more other processing chambers before the substrate is transferred to the semiconductor processing chamber in which the method 200 may be performed. Regardless, the method 200 may optionally include transferring the semiconductor substrate to a processing region of a semiconductor processing chamber, such as the processing chamber 100 described above or another chamber that may include the components described above. The substrate may be deposited on a substrate support, which may be a susceptor, such as the substrate support 104, and may reside in a processing region of the chamber, such as the processing region 120 described above. The method 200 describes Figures 3A to 3E The operations schematically shown in FIG will be described in conjunction with the operations of method 200. It should be understood that Figures 3A to 3E Only partial schematics are shown, and the semiconductor substrate may include other components as shown in the figures and alternative components of any size or configuration that may still benefit from aspects of the present technology.

[0032] The method 200 may or may not involve developing the semiconductor structure as an optional operation of a particular manufacturing operation. It should be understood that the method 200 may be performed on any number of semiconductor structures 300 or substrates 302, such as Figures 3A to 3E As shown, an exemplary structure including an exemplary structure on which a selectively deposited material may be formed. Figure 3A As shown, substrate 302 may have multiple layers of material deposited thereon. Substrate 302 may be any number of materials, such as a base wafer or substrate made of silicon or silicon-containing materials, germanium, other substrate materials, and one or more materials that may form thereon during semiconductor processing.

[0033] Structure 300 can illustrate a partial view of a substrate that can be used in embodiments for n-channel and p-channel MOSFETs, FinFETs, fully-enclosed gate FETs, complementary metal-oxide-semiconductor, and nanosheet FETs, among other types of semiconductor transistor structures. The material layers can be fabricated through any number of methods, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (TECVD), plasma-enhanced chemical vapor deposition (PECVD), plasma enhanced atomic layer deposition (PEALD), or any other formation technique. In embodiments, the plasma-enhanced chemical vapor deposition can be performed in a process chamber, such as process chamber 100 previously described. The substrate layers can include silicon oxide and silicon nitride, silicon oxide and silicon, silicon nitride and silicon, silicon and doped silicon, or any number of other materials.

[0034] As shown in FIG. 3, Figure 3A Structure 300 is provided, which includes a substrate 302 that has undergone source / drain 304 formation. In embodiments, the formation of source / drain 304 can include epitaxial growth of a doped silicon material, such as a silicon-germanium material. However, it should be understood that the source / drain region 304 can be formed from any suitable deposition and patterning process, as the present technology does not require strict source / drain 304 formation (e.g., attempting to solidify epitaxial growth defects) to preserve hole or electron mobility. Further, structure 300 contains a plurality of gate regions 306 and interlayer dielectric / pseudo-gate regions 308, which can be formed in a manner as known in the art and discussed above.

[0035] In implementations, the substrate 300 can be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate that is entirely composed of a semiconductor material. The bulk semiconductor substrate can include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer can include one or more materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In implementations, the semiconductor material is silicon (Si). In one or more implementations, the semiconductor substrate 300 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more implementations, the substrate 300 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although some examples of materials that can form a substrate are described herein, any material that can be used as a foundation upon which passive and active electronic elements (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic elements, or any other electronic elements) can be constructed are within the spirit and scope of the present disclosure.

[0036] In implementations, the semiconductor material can be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In implementations, the substrate can be doped by using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor that is produced by doping an intrinsic semiconductor with an electron donor element during fabrication. The n-type term comes from the negative charge of the electron. In an n-type semiconductor, electrons are the majority carriers, and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of holes (or electron holes). In contrast to n-type semiconductors, the hole concentration is greater than the electron concentration in p-type semiconductors. In a p-type semiconductor, holes are the majority carriers, and electrons are the minority carriers. As noted above, in implementations, the present technology can provide improved mobility in both p-type and n-type semiconductors. However, in implementations, p-type semiconductors can experience further improved hole mobility.

[0037] However, in operation 201, the method 200 can include patterning one or more mask layers 310 deposited on the substrate 302 over the source / drain regions 304 and over a portion of the gate regions 306. For example, in an implementation, the substrate 302 can be loaded into a load lock 110, 112 and transferred by a robot 106, 108 to a processing chamber, such as the processing chamber 114, in which the mask deposition process is performed. That is, as shown, the one or more mask layers 310 are patterned over five of the seven gate regions 306 shown, with the remaining two gate regions 306 exposed. However, as will be discussed in greater detail below, it should be appreciated that the patterned mask layers 310 can be disposed over one or more gate regions 306 or spaced apart as desired to provide the necessary stress (as will be shown in Figure 4 more clearly below) on the channel regions 316.

[0038] As shown in Figure 3B operation 202, the method 200 can include etching the structure 300. In an implementation, such an operation can include transferring the substrate 302 to a second processing chamber 116 configured for an etching process. For example, in one implementation, one or more of inductively coupled plasma (ICP) etching, reactive ion etching (RIE), or capacitively coupled plasma (CCP) etching is used to form the shallow trench isolation or via 312. Moreover, since the mask layers 310 are aligned with the gate regions 306, the shallow trench isolation 312 can be formed in and self-aligned with the gate regions, thus considered a self-aligned shallow trench isolation or self-aligned diffusion cut-off. Moreover, as shown, in Figure 3B operation 202, the self-aligned diffusion cut-off 312 defines a volume from a top surface 332 of the structure to a bottom 334 of the diffusion cut-off 312.

[0039] As shown in Figure 3CAs shown, after etching 202, structure 300 may optionally undergo passivation and / or oxidation prior to operation 203 and removal of mask layer 310. Nevertheless, in operation 204, etched substrate 302 may be transferred to a third processing chamber 118 configured for deposition and / or filling processes, including chambers for chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), plasma enhanced atomic layer deposition (PEALD), or the like, wherein self-aligned diffusion stop 312 is filled with a stressed dielectric material 314.

[0040] Nevertheless, the etched and filled substrate 302 can be transferred to a fourth processing chamber 120, such as a processing chamber configured for polishing (including chemical mechanical polishing), and undergo a polishing operation 205, such as chemical mechanical polishing (CMP), on the top surface 332 of the structure 300. Figure 3D ). Figure 3D Another view of Figure 3E , wherein the interlayer dielectric 308 and the gate region 306 have been removed for clarity. Figure 4 A cross-sectional view of an exemplary embodiment is shown, such as along Figure 3E A cross-sectional view along line AA'. Figure 4 The source / drain regions 304, gate region 306, and channel region 316 are more clearly shown. As shown, in one embodiment, the structure 300 can be in a horizontal all-around gate orientation with a plurality of horizontally extending channels 326 in the channel region 316. For example, in one embodiment, the channels 326 can be substantially parallel to the top surface 336 of the substrate 302. However, unlike conventional processes, the present technique continues to fill the self-aligned diffusion stop with the stressed dielectric material 314 in operation 204.

[0041] That is, the present technology has surprisingly found that excellent electron and / or hole mobility can be achieved even in structures having an unfavorable channel surface orientation by utilizing a stressed dielectric material 314 to fill the self-aligned diffusion cutoff 312. Further, by utilizing a stressed dielectric material in the self-aligned diffusion cutoff, the present technology has found that compressive stress is transferred from the stressed material to the adjacent channel region without suffering the channel stress relaxation exhibited in the prior art.

[0042] For example, the present technology has found that, after filling, one or more channel regions 316 Figure 3E In Figure 4 is illustrated more clearly) in the channel region 316 increases from a first stress level of a lower stress to a second stress level of a higher stress. In embodiments, the percentage change in stress of the channel region 316 from the first stress level to the second stress level can be greater than or about 0.1%, such as greater than or about 1%, greater than or about 2%, greater than or about 5%, greater than or about 10%, greater than or about 25%, greater than or about 50%, greater than or about 75%, greater than or about 100%, or greater, or any range or value therebetween. In additional embodiments, the first stress level in the channel region 316 can be less than or about 10 MPa, less than or about 5 MPa, less than or about 1 MPa, or less. In further embodiments, the second stress level in the channel region 316 can be greater than or about 100 MPa, such as greater than or about 200 MPa, such as greater than or about 300 MPa, such as greater than or about 400 MPa, such as greater than or about 500 MPa, such as greater than or about 600 MPa, such as greater than or about 700 MPa, such as greater than or about 750 MPa, or any range or value therebetween.

[0043] Furthermore, in embodiments, the present technology has found that such stress can be evenly distributed throughout the channel region 316. That is, as noted above, previous attempts have utilized a stressed material above and below the channel region. However, conventional technology can limit stress modification of the top side 318 of the channel region 316 and / or the bottom side 320 of the channel region 316. Thus, conventional technology can not provide consistent stress across the channel. In contrast, in embodiments, the present technology can have a first channel stress at a first location 322 in the channel region 316 (shown merely by way of example as adjacent to the bottom 320 of the channel region 316, it being understood that the first location 322 can be at any location within the channel region 316) and a second channel stress at a second location 324 in the channel region 316. As shown, the first location 322 is spaced apart from the second location 424 in a vertical direction for example purposes. However, in embodiments, the regions can be spaced apart horizontally, or both vertically and horizontally. Nonetheless, the first channel stress can differ from the second channel stress by less than or about 30%, such as less than or about 27.5%, less than or about 25%, less than or about 22.5%, less than or about 20%, less than or about 17.5%, less than or about 15%, less than or about 12.5%, less than or about 10%, or any range or value therein.

[0044] Furthermore, as noted above, increased stress in the channel region can increase the mobility of charge carriers in the channel, which can also increase the drive current through the channel region. In particular, the increased stress generated in the channel region in embodiments of the present technology can increase the drive current through the transistor channel, such as the p-MOS drive current in embodiments, by greater than or about 1%, such as greater than or about 5%, greater than or about 10%, greater than or about 15%, greater than or about 20%, greater than or about 25%, greater than or about 30%, greater than or about 35%, greater than or about 40%, greater than or about 45%, greater than or about 50%, greater than or about 55%, or any range or value therein. In embodiments, the increased stress in the channel region can result in further increases in hole mobility, such as greater than or about 10%, greater than or about 20%, greater than or about 30%, greater than or about 40%, greater than or about 50%, greater than or about 60%, greater than or about 70%, greater than or about 80%, greater than or about 90%, greater than or about 100%, greater than or about 110%, greater than or about 120%, greater than or about 130%, greater than or about 140%, greater than or about 150%, or any range or value therein. The increase in drive current and hole mobility through the channel region can improve transistor performance in a number of ways, including but not limited to increasing switching speed and / or reducing power consumption. Embodiments of the present technology can achieve such improvements in semiconductor element performance without limiting the types of materials used in the elements, which can create new processing issues or detract from performance in other aspects of the elements.

[0045] Nonetheless, in embodiments, the amount of stress in the stressed dielectric material can depend on the amount of stress imparted to the channel region of the semiconductor element as a result of depositing the stressed material. In embodiments, this can involve determining a desired amount of stress in one or more channel regions 316. Exemplary stressed materials can include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbon nitride, silicon carbon oxide, silicon dioxide, aluminum oxide, and carbon-containing organic materials, as well as other types of dielectric materials and combinations of the foregoing. The present technology allows for selection of a stressed material primarily based on the ability of the stressed material to induce a certain amount of persistent stress in an adjacent layer without the need for any heating operations or oxidation after filling.

[0046] The stressed dielectric material can be filled into the self-aligned diffusion cutoff 312 using atomic layer deposition, plasma-enhanced atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, among other types of deposition methods. Nonetheless, to deposit the stressed dielectric material, the deposition of the stressed dielectric material can be performed using increased radio frequency power, higher deposition temperatures, higher kinetic plasma levels, or combinations of the foregoing. Thus, in embodiments, the deposition process can be performed at a deposition temperature greater than or about 150 °C, such as greater than or about 200 °C, such as greater than or about 250 °C, such as greater than or about 300 °C, such as greater than or about 350 °C, such as greater than or about 400 °C, such as greater than or about 450 °C, such as greater than or about 500 °C, such as greater than or about 550 °C, such as greater than or about 600 °C, such as up to about 700 °C, such as less than or about 650 °C, or any range or value therein.

[0047] In embodiments, the stressed dielectric material can be characterized by a stress greater than or about 500 MPa, such as greater than or about 1 GPa, such as greater than or about 1.5 GPa, such as greater than or about 2 GPa, such as greater than or about 2.25 GPa, such as greater than or about 2.5 GPa, such as greater than or about 2.75 GPa, such as greater than or about 3 GPa, or any range or value therein. For purposes of the present disclosure, a higher stress material is characterized by a positive or negative stress absolute value that is greater in absolute value than a lower stress material. The convention used herein is that a positive stress is characterized as a tensile stress, a negative stress is characterized as a compressive stress, and no stress (i.e., 0 GPa) is characterized as a neutral stress. A positive stress (i.e., a tensile stress) is characterized by an outward push resulting from expansion of the material. A negative stress (i.e., a compressive stress) is characterized by an inward pull resulting from contraction of the material. Thus, a "compressive stress" value used herein can refer to a negative value in absolute value (e.g., a 250 MPa compressive stress can also be read as -250 MPa), and a "tensile stress" value used herein can refer to a positive value in absolute value (e.g., a 250 MPa tensile stress refers to 250 MPa).

[0048] Further, in embodiments, the deposited material has a thickness that can be about 1 nanometer or greater, such as about 2.5 nanometers or greater, such as about 5 nanometers or greater, such as about 7.5 nanometers or greater, such as about 10 nanometers or greater, such as about 12.5 nanometers or greater, such as about 15 nanometers or greater, such as about 17.5 nanometers or greater, such as about 20 nanometers or less, or any range or value therein. For example, although the self-aligned diffusion break 312 has been discussed thus far as being filled with a stressed dielectric material, the present disclosure has found that the above stress levels and improved mobility can be achieved when the stressed dielectric material is used as a stress liner for the self-aligned diffusion break 312. Thus, in some aspects, a thin liner of the stressed dielectric material can partially or completely coat the interior surface of the self-aligned diffusion break 312, followed by filling the remaining portion of the trench with an unstressed material, a conductive material, or the like.

[0049] However, it should be understood that, in embodiments, the self-aligned diffusion break 312 is filled with the stressed dielectric material such that greater than or about 90 volume percent of the volume defined by the self-aligned diffusion break is occupied by the stressed dielectric material, such as greater than or about 92 volume percent, greater than or about 94 volume percent, greater than or about 96 volume percent, greater than or about 98 volume percent, greater than or about 99 volume percent, or the like, or any range or value therein. In embodiments, the volume defined by the self-aligned diffusion break can be completely occupied by the stressed dielectric material, and there are no voids or seams. That is, the present technology has found that even small voids in the self-aligned diffusion break can result in a significant decrease in the average channel stress. For example, voids or seams having a feature size less than or about 3 nanometers or less, such as less than or about 2 nanometers or less than about 1 nanometer, can result in a decrease in the average channel stress of greater than 60 percent.

[0050] Thus, in embodiments, to achieve a high volume percentage and reduce voids and seams, the filling step 204 can include forming only a thin layer of the stressed dielectric material, etching back portions of the fill material, followed by filling another thin layer of the stressed dielectric material, repeated in an in-situ looping fashion until the self-aligned diffusion break filling is complete. Such a process can be particularly useful in high aspect ratio diffusion breaks, as the looping process can avoid pinch-offs, allowing voids and seams to occupy a lower volume, while the stressed dielectric material occupies a higher volume.

[0051] Nonetheless, as discussed above, the present technology has found that even a thin layer of the stressed dielectric material can be effective to apply stress when used in a self-aligned diffusion break. Thus, the above thickness can represent the entire width of the self-aligned diffusion break. In such a case, the self-aligned diffusion break can define a channel length L defined as L = W - 2t, where W is the width of the self-aligned diffusion break and t is the thickness of the stressed dielectric material. Figure 4The distance between the source and drain regions shown. The characteristic length of the channel length L is less than or about 35 nanometers, such as less than or about 30 nanometers, less than or about 25 nanometers, less than or about 20 nanometers or less, or any range or value therebetween. Due to the small channel length and the large diffusion cutoff depth, the self-aligned diffusion cutoff can be considered to be characterized by a high aspect ratio. Furthermore, in an embodiment, only a single self-aligned diffusion cutoff is used in structure 300, rather than a double diffusion cutoff, while still applying the necessary stress, thereby allowing for a reduction in size while maintaining effectiveness.

[0052] Furthermore, although the illustrated embodiment Figures 3A to 3E The three gate regions 306 in the embodiment contain two single self-aligned diffusion stops 312 on opposite sides thereof and Figure 4 3. The structure 300 includes two single self-aligned diffusion stops 312 on opposite sides of a single gate region 306 in the structure 300, but it should be understood that the self-aligned diffusion stops can be placed so that there are any number of gate regions 306 between a pair of diffusion stops. For example, one gate region 306 can be disposed between a pair of diffusion stops, such as two gate regions, three gate regions, four gate regions, five gate regions, six gate regions, seven gate regions, or more, depending on the desired stress in the channel region 316 in the structure 300. For example, the number of channel regions 304 disposed between opposing self-aligned diffusion stoppers 312 may be selected to maintain a channel stress greater than or about 350 MPa, such as greater than or about 400 MPa, greater than or about 450 MPa, greater than or about 500 MPa, greater than or about 550 MPa, such as greater than or about 650 MPa, such as greater than or about 750 MPa, such as greater than or about 850 MPa, such as greater than or about 1000 MPa, or higher, or any range or value therebetween.

[0053] As described above, in embodiments, the stress applied by the stressed dielectric material may be compressive stress, which can significantly improve mobility and drive current. However, in embodiments, the improvements are specific to hole mobility and p-MOS drive current. Thus, in one or more embodiments, the patterning discussed above is specific to single diffusion cutoff patterning in p-MOS regions. For example, see Figure 5 In embodiments where both the p-MOS and n-MOS regions need to be improved, method 500 may include operations 506 to 510, wherein operation 506 occurs at Figure 2after operation 205. That is, as shown, the method 500 can include a second patterning operation 506, which is performed in the same manner as step 201, except that the material is patterned to be disposed on the n-MOS region. In such embodiments, the substrate 302 can be transferred from the processing chamber 120 back to the processing chamber 114 for the second patterning step. Subsequently, at operation 507, the substrate can be transferred from the processing chamber 114 to the etching chamber 116, where etching can be performed. After the second etching process 507, an optional passivation / oxidation step can be performed at operation 508, followed by a transfer to the processing chamber 118 for stress dielectric filling, which can be performed in the same or similar manner as the etching and filling operations 202 and 203 by utilizing the second patterning operation 506. Of course, it should be understood that, in embodiments, the method operations 506-510 can be performed in whole or in part prior to steps 201-205. Nonetheless, after the second deposition filling operation 509, the substrate 302 can be transferred back to the processing chamber 120 for a second polishing operation 510.

[0054] Furthermore, the stressed dielectric material described above can still be used to fill the self-aligned diffusion cut 312 that has been formed. However, to further improve the n-MOS region, a tensile stress dielectric material can be utilized (or a tensile stress can be induced in the stress dielectric material). For example, by way of example only, a high oxygen deposition environment or UV curing can be utilized. Nonetheless, it has been discovered that depositing a tensile stress dielectric material in the single self-aligned diffusion cut in the n-MOS region can further improve the electron mobility and n-MOS current drive without adversely affecting the hole mobility and p-MOS current drive characteristics described above.

[0055] Accordingly, in addition to the improvements described above, the increased stress in the channel region is believed to increase the mobility of the charge carriers in the channel, thereby increasing the drive current through the n-MOS channel region. In embodiments, the increased stress created in the channel region by embodiments of the present technology can increase the drive current through the transistor channel by greater than or about 1%, such as greater than or about 5%, greater than or about 10%, greater than or about 15%, greater than or about 20%, greater than or about 25%, greater than or about 30%, greater than or about 35%, greater than or about 40%, greater than or about 45%, greater than or about 50%, greater than or about 55%, or greater, or any range or value therein. The increase in drive current through the channel region and hole mobility can improve transistor performance in a number of ways, including but not limited to increasing switching speed and / or reducing power consumption.

[0056] Figure 6An alternative method of increasing electron mobility and n-MOS current drive is illustrated in method 600. That is, operations 201-205 can be performed in the same manner as method 200. After operation 205, the method can include transferring the substrate back to processing chamber 114 for operation 606 to deposit a second patterned mask. After the mask is deposited, at operation 607, the substrate can be transferred to processing chamber 116 to etch the second patterned mask, thereby exposing the self-aligned diffusion cutoff 312 in the n-MOS region. The self-aligned diffusion cutoff is etched at operation 607 according to any of the methods described above. However, the etching herein removes the stressed dielectric fill from the self-aligned diffusion cutoff in the n-MOS region. Subsequently at 608, the structure 300 is subjected to optional passivation / oxidation operations. Nonetheless, the substrate 302 is transferred to fill / deposition chamber 118 where the etched diffusion cutoff is exposed to a high energy ion implant at operation 609, which releases the compressive stress previously introduced into the diffusion cutoff. Suitable high energy implants can include silicon, germanium, xenon, indium, or the like. Nonetheless, as described above, the high energy implant can reduce the stress in the n-MOS region in a similar manner as the tensile stress dielectric fill, such as back to the first stress value, thereby increasing electron mobility and n-MOS drive current without affecting the increase in hole mobility and p-MOS drive current imparted by the compressive stress dielectric fill. Finally, the substrate 302 can be transferred to processing chamber 120 where the substrate can be polished at operation 610.

[0057] In the foregoing description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of various embodiments of the present technology. It will be apparent, however, to one skilled in the art that certain embodiments can be practiced without some or all of these specific details, or with some additional details, or in some other manner.

[0058] Having disclosed several embodiments, those skilled in the art will further appreciate that the technology can be practiced with various modifications and alterations, and equivalents. Furthermore, the purpose of the foregoing description is to illustrate the principles of the technology. Therefore, it will be understood that the foregoing description and the examples are intended to be illustrative, and not in limitation of the scope of the technology.

[0059] Where a numerical range is provided, it is understood that, unless the context clearly dictates otherwise, every intervening value between the upper and lower limits of that range is also specifically disclosed, accurate to the nearest fraction of the unit of the lower limit. Any narrower range between any given value or ungiven intervening value in a given range and any other given value or intervening value in that given range is included. The upper and lower limits of such smaller ranges may independently be included in or excluded from that range, and each range in which either, none, or both limits are included in or excluded from that smaller range is also included in the technology, subject to any specifically excluded limits in the stated range. When the stated range includes one or both limits, ranges excluding one or both of those limits are also included.

[0060] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a gate region" includes a plurality of such regions and reference to "the gate region" includes reference to one or more gate regions and equivalents thereof known to those skilled in the art, and so forth.

[0061] In addition, the words “comprise,” “comprising,” “contain,” “containing,” “include,” and “including” as used in this specification and the following claims are intended to specify the presence of stated features, integers, components, or operations, but do not preclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. A semiconductor element, comprising: substrate; source region; drain region; a channel region, the channel region comprising at least one channel located between the source and the drain; a first gate region comprising a self-aligned single-diffused cutoff in a p-MOS region, wherein the self-aligned single-diffused cutoff comprises a stressed dielectric material, and wherein the stressed dielectric material is characterized by a compressive stress greater than or about 500 MPa; and A second gate region in the n-MOS region includes a first gate surrounding the channel between the source region and the drain region. 2 . The semiconductor device of claim 1 , wherein the channel region is characterized by a compressive stress greater than or about 500 MPa. 3 . The semiconductor device according to claim 1 , further comprising a third gate region, wherein the second gate region is disposed between the first gate region and the third gate region. 4 . The semiconductor device of claim 3 , wherein the third gate region comprises a second self-aligned single diffusion termination in the p-MOS region.

5. The semiconductor device of claim 3 , wherein the channel region has a first channel region stress at a first location within the channel region and a second channel region stress at a second location spaced apart from the first location, wherein the first channel region stress is characterized by a percentage change of greater than or approximately 30% relative to the second channel region stress. The semiconductor device according to claim 5 , wherein the channel region comprises a plurality of horizontally extending channels.

7. The semiconductor device of claim 5, wherein the semiconductor device is a gate-all-around complementary metal oxide semiconductor.

8. The semiconductor device of claim 4, wherein the second self-aligned single diffusion stop comprises a tensile stressed dielectric material characterized by a tensile stress of greater than or about 500 MPa.

9. The semiconductor device of claim 4, wherein the third gate region comprises a third self-aligned diffusion stop, the third self-aligned diffusion stop comprising a compressive stress dielectric material characterized by a compressive stress greater than or approximately 500 MPa. 10 . The semiconductor device of claim 8 , wherein the second self-aligned single diffusion termination comprises a tensile stressed dielectric material or a high energy implant.

11. The semiconductor device of claim 1, wherein the self-aligned diffusion stop defines a volume, and wherein the stressed dielectric material occupies approximately 90 volume percent or more of the volume.

12. The semiconductor device of claim 11, wherein the stressed dielectric material is substantially free of voids or seams. 13 . The semiconductor device of claim 12 , wherein the stressed dielectric material occupies greater than or about 98 volume % of the volume.

14. The semiconductor device of claim 1, wherein the stressed dielectric material has a compressive stress greater than or about 1000 MPa, the channel region is a p-channel metal oxide semiconductor, and the channel region has a compressive stress greater than or about 600 MPa.

15. A semiconductor processing system, comprising: a first processing chamber; a second processing chamber; a third processing chamber; and a system controller configured to pattern a substrate in the first processing chamber, etching a shallow trench isolation in a first gate region of the semiconductor device in the second processing chamber, wherein the first gate region is a p-MOS region, The shallow trench isolation is filled in the third processing chamber with a stressed dielectric material having a compressive stress of at least about 500 MPa.

16. A method of forming a semiconductor device, the method comprising: etching a shallow trench isolation (STI) in a first gate region of a semiconductor device, wherein the first gate region is a p-MOS region, wherein the semiconductor device comprises a substrate, a source region, a drain region, a channel region comprising at least one channel between the source and the drain, the first gate region, and a second gate region in an n-MOS region comprising a first gate surrounding the channel between the source and the drain regions; and The shallow trench isolation is filled with a compressive stress dielectric material having a stress of at least about 500 MPa.

17. The method of claim 16, wherein the channel region is characterized by a first stress before etching, wherein the channel region is characterized by a second stress after filling, and wherein the first stress is characterized by a percentage change of greater than or about 10% relative to the second stress, or wherein the channel region is characterized by a first hole mobility before etching, and by a second hole mobility after filling, and wherein the first hole mobility is characterized by a percentage change of greater than or about 10% relative to the second hole mobility. 18 . The method of claim 16 , further comprising a third gate region, the second gate region being disposed between the first gate region and the third gate region.

19. The method of claim 18, further comprising: The third gate region is etched during the etching of the first gate region, or the third gate region is masked during the etching of the first gate region, and the third gate region is patterned and etched after etching the first gate region to form a second shallow trench isolation in the third gate region.

20. The method of claim 19, further comprising: The shallow trench isolation is filled with a compressive stress dielectric material, and the second shallow trench isolation is filled with a compressive stress dielectric material, a tensile stress dielectric material or a high energy implant.

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