Integrated circuit quality test method and system

Abstract

The invention relates to the technical field of integrated circuit quality testing, in particular to an integrated circuit quality testing method and system, and the method comprises the following steps: executing a preset testing instruction set, and carrying out the electrical parameter testing of an integrated circuit chip; when it is detected that any electrical parameter value of the chip deviates from a preset range, recording an initial electrical parameter measurement value when the electrical parameter deviates from the preset range, an identifier of a test instruction sequence and a pin number of the abnormal chip; according to the recorded identification of the test instruction sequence and the chip pin number, repeatedly executing the test instruction sequence, and when the test instruction sequence is repeatedly executed, adjusting the test condition to change the electrical margin of the chip so as to measure and obtain a secondary verification electrical parameter measurement value; by introducing secondary verification and an electrical margin adjustment mechanism, false electrical parameter abnormity caused by signal coupling noise and real physical defects of the chip can be effectively distinguished.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit quality testing, and in particular to an integrated circuit quality testing method and system. Background Art

[0002] Functional testing is an indispensable part of the production and quality verification of integrated circuits. This test relies on a set of predetermined test vector files, which clearly specify the input signals that the chip should receive and the expected output results at each timing node. This file serves as the core basis for verifying the correctness of chip functions. Its development and verification usually consumes a lot of resources. Once put into use, it is regarded as a stable and reliable test benchmark. In order to continuously reduce manufacturing costs and improve product competitiveness, companies often migrate mature and mass-produced chips from the original process nodes to more advanced process nodes. This process upgrade aims to achieve higher performance, lower power consumption and a better cost structure through smaller feature sizes, and is a common business strategy adopted by the semiconductor industry.

[0003] However, process migration can bring unexpected physical effects. The reduced circuit size and wire spacing of the new process significantly increase the parasitic capacitance between adjacent signal lines, making it more susceptible to signal coupling noise. For example, a level jump on a signal line may induce unexpected voltage fluctuations on its adjacent signal line, affecting signal integrity. If test vectors developed based on the old process are continued to be used, coupling noise issues may be exposed in the new process. Certain specific signal combinations in the original test sequence may induce strong coupling noise, causing abnormal fluctuations in signals that should have been stable. This noise is the manifestation of physical effects under specific logical stimuli, rather than chip design or functional defects.

[0004] During electrical parameter testing, coupled noise can further erode the parameter safety margins originally set based on older processes. Due to inevitable minor variations in the manufacturing process, the noise impact on different chips is statistically distributed, causing some chips' measured parameters to exceed the original tolerance range.

[0005] As a result, a batch of chips that function normally in real applications are mistakenly classified as failing due to test parameter violations caused by coupled noise. This not only results in reduced yield and financial losses, but also increases the difficulty of diagnosis because the problem cannot be classified as a clear hardware defect. This phenomenon has systematic and statistical characteristics, posing a persistent challenge to production quality and cost control.

[0006] Existing testing methods are inadequate when dealing with signal integrity issues caused by process migration. There is an urgent need for a testing strategy that can identify and avoid misjudgments caused by coupled noise. Summary of the Invention

[0007] The purpose of the present invention is to solve the shortcomings of the prior art and to propose an integrated circuit quality testing method and system.

[0008] In a first aspect, the present invention provides a method for testing the quality of an integrated circuit, the method comprising the following steps: Execute the preset test instruction set to perform electrical parameter tests on integrated circuit chips; When it is detected that any electrical parameter value of the chip deviates from a preset range, the initial electrical parameter measurement value when the electrical parameter deviates from the preset range, the identifier of the test instruction sequence, and the chip pin number where the abnormality occurs are recorded; Repeating the test instruction sequence according to the recorded identifier of the test instruction sequence and the chip pin number, and adjusting the test conditions to change the electrical margin of the chip when repeatedly executing the test instruction sequence, so as to measure and obtain a secondary verification electrical parameter measurement value; Determining, based on a relationship between the initial electrical parameter measurement value and the secondary verification electrical parameter measurement value, whether the electrical parameter anomaly is caused by signal coupling noise or a real physical defect of the chip, to obtain a determination result; The chips are classified according to the judgment result.

[0009] In a second aspect, an integrated circuit quality testing system is provided, the system comprising: an initial test module, configured to execute a preset test instruction set to perform electrical parameter testing on an integrated circuit chip; and when any electrical parameter value of the chip is detected to deviate from a preset range, not immediately determining the chip as a defective product, but recording the initial electrical parameter measurement value when the electrical parameter deviated from the preset range, an identifier of the test instruction sequence, and the chip pin number where the abnormality occurred; A repeat execution module, configured to repeatedly execute the test instruction sequence according to the identifier of the recorded test instruction sequence and the chip pin number; a condition adjustment module, configured to adjust test conditions to change the electrical margin of the chip when repeatedly executing the test instruction sequence; A secondary measurement module, configured to measure the electrical parameters of the chip again under the adjusted test conditions to obtain secondary verified electrical parameter measurement values; a judgment module, configured to judge, based on a relationship between the initial electrical parameter measurement value and the secondary verification electrical parameter measurement value, whether the electrical parameter anomaly is caused by signal coupling noise or a real physical defect of the chip, so as to obtain a judgment result; The classification processing module is used to classify the chips according to the judgment result.

[0010] Compared with the prior art, the present invention has the following beneficial effects: By introducing a secondary verification and electrical margin adjustment mechanism, it is possible to effectively distinguish between false electrical parameter anomalies caused by signal coupling noise and real physical defects in the chip. Specifically, when an abnormality occurs in the electrical parameters of the chip, the method does not immediately determine it as a defective product, but records relevant information and repeatedly executes the test instruction sequence in a targeted manner, while adjusting the test conditions to change the electrical margin of the chip, thereby obtaining a secondary verification electrical parameter measurement value. By comparing the relationship between the initial measurement value and the secondary verification measurement value, the root cause of the anomaly can be accurately determined. This innovative method overcomes the problem in the prior art that signal coupling noise is caused by process migration, which in turn causes a large number of functionally intact chips to be misjudged as defective products, significantly improves the accuracy of the test and the production yield, and avoids unnecessary production losses and diagnostic troubles. Accordingly, the present application can effectively solve the problems of yield decline and troubleshooting difficulties in the prior art, and provides a more reliable solution for quality control of integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Flow chart of the method of the present invention.

[0012] Figure 2 Schematic diagram of the system structure of the present invention.

[0013] In the figure: 201, initial test module; 202, repeated execution module; 203, condition adjustment module; 204, secondary measurement module; 205, judgment module; 206, classification processing module. DETAILED DESCRIPTION

[0014] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention.

[0015] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0016] Functional testing is an essential step in the production and quality verification of integrated circuits (ICs). It relies on a set of predetermined test instructions that specify the input signals a chip should receive and the output results it should produce at specific moments. However, with the continuous advancement of semiconductor manufacturing technology, chip designs often migrate from mature production processes to more advanced and sophisticated process nodes. While these process upgrades are intended to improve performance and reduce costs, they can also have unintended physical consequences. Specifically, the smaller circuit dimensions and closer wire spacing of newer processes make it more likely that charges between adjacent signal lines will interact, generating a phenomenon known as "signal coupling noise." When test instructions designed for older processes are used, certain signal combinations within the newer process can induce significant signal coupling noise, leading to unusual fluctuations in chip electrical parameters during testing. These anomalies are not actual defects in the chip itself, but rather spurious issues caused by the interaction between the test instructions and the physical characteristics of the newer process. These anomalies often result in perfectly functional chips being mistakenly classified as defective, resulting in unnecessary production losses and diagnostic difficulties.

[0017] To this end, this application Figure 1 A method for testing the quality of an integrated circuit is shown, the method comprising the following steps: S101, executing a preset test instruction set to perform electrical parameter testing on the integrated circuit chip; This step can be accomplished by loading a pre-designed test instruction sequence into automatic test equipment (ATE), which then applies stimulus signals to the chip under test while measuring the chip's response signals. For example, a test instruction set might include a series of test vectors used to verify the functionality of a chip's logic gates, memory cells, or interface circuits. During the test, the ATE monitors the chip's electrical parameters, such as output voltage, input current, and propagation delay, in real time and compares them to pre-set acceptable ranges.

[0018] S102, when it is detected that any electrical parameter value of the chip deviates from the preset range, recording the initial electrical parameter measurement value when the electrical parameter deviates from the preset range, the identifier of the test instruction sequence, and the chip pin number where the abnormality occurs; When ATE detects that an electrical parameter value exceeds its preset upper or lower limit, the system will not immediately determine that the chip is defective. Instead, the system will accurately record the specific electrical parameter measurement value when the anomaly occurs, which is the initial electrical parameter measurement value. At the same time, for subsequent tracing and analysis, the system will also record the unique identifier of the test instruction sequence that caused the anomaly and the specific number of the chip pin where the anomaly occurred. For example, if the output voltage of an output pin of a chip is lower than the preset minimum qualified voltage when executing a specific test instruction sequence, the output voltage value, the identifier of the test instruction sequence, and the number of the output pin will be recorded.

[0019] S103, repeatedly executing the test instruction sequence according to the recorded identifier of the test instruction sequence and the chip pin number, and adjusting the test conditions to change the electrical margin of the chip during the repeated execution of the test instruction sequence, so as to obtain a secondary verification electrical parameter measurement value; After recording the initial anomaly information, the test system will target and repeatedly execute the test instruction sequence that caused the anomaly. During the repeated execution of this sequence, the test conditions will be purposefully adjusted to change the chip's electrical margin. For example, the electrical margin can be changed by slightly increasing or decreasing the test voltage, changing the frequency of the test signal, or adjusting the test environment temperature. Under these adjusted test conditions, the chip's electrical parameters will be measured again to obtain secondary verification electrical parameter measurement values. For example, if the initial anomaly was due to low output voltage, then during the secondary verification, you can try to measure the output voltage again under the condition of slightly increasing the supply voltage.

[0020] S104. Based on the relationship between the initial electrical parameter measurement value and the secondary verification electrical parameter measurement value, determine whether the electrical parameter anomaly is caused by signal coupling noise or a real physical defect of the chip to obtain a determination result. After obtaining the initial and secondary verification electrical parameter measurements, the system analyzes the relationship between them. If the electrical parameter anomaly is caused by signal coupling noise, adjusting the test conditions (for example, by changing the electrical margin) may mitigate or enhance the effect of this noise, resulting in a significant trend in the secondary verification electrical parameter measurement compared to the initial value. For example, if increasing the supply voltage restores a low output voltage to the normal range, this likely indicates that the anomaly is caused by signal coupling noise. Conversely, if the electrical parameter anomaly is caused by a real physical defect in the chip (such as a short circuit, open circuit, or transistor failure), the defect's impact typically remains unchanged even with adjustments to the test conditions, and the secondary verification electrical parameter measurement may show little change from the initial value or remain abnormal. Through this comparison and analysis, the system can identify the root cause of the anomaly and arrive at a clear diagnosis.

[0021] S105: Classify the chips according to the judgment result.

[0022] Based on these judgments, the chip is classified accordingly. If the results indicate that the anomaly is caused by signal coupling noise and the chip itself is functionally intact, the chip can be classified as a qualified product or a specific grade of qualified product, thus avoiding unnecessary scrapping. If the results indicate that the anomaly is caused by a real physical defect in the chip, the chip is classified as a defective product and may be sent to the failure analysis department for further diagnosis to identify the specific defect type and location. This classification mechanism ensures the accuracy of test results and improves production yield.

[0023] The integrated circuit quality testing method of this application introduces an innovative secondary verification mechanism that can effectively distinguish whether electrical parameter anomalies occurring during integrated circuit testing are due to signal coupling noise or actual physical defects. Conventional testing methods often directly reject chips when electrical parameters deviate from a preset range. This results in a large number of chips that are functional but affected by signal coupling noise being mistakenly scrapped, causing significant production losses. Instead of immediately rejecting a chip as defective upon detecting an anomaly, this application records the initial anomaly information and then repeatedly executes a targeted test instruction sequence, adjusting test conditions to alter the chip's electrical margin, thereby obtaining secondary verification electrical parameter measurements. By comparing the initial and secondary verification measurements, this application can accurately determine the root cause of the anomaly. For example, if adjusting the electrical margin alleviates or eliminates the anomaly, it indicates that it is likely caused by signal coupling noise. Conversely, if the anomaly persists, it is more likely a true physical defect. This method avoids misjudgments caused by signal coupling noise in traditional testing, significantly improves test accuracy and production yield, and provides a more sophisticated and efficient solution for integrated circuit quality control.

[0024] As an embodiment of the present invention, when the chip is classified as a non-conforming product, the method further includes the following steps: Adjust the test conditions to a preset limit margin state to change the electrical margin of the chip; Under the adjusted test conditions, the electrical parameters of the chip are measured again to obtain the limit recovery value; The extreme recovery value refers to the electrical parameter value measured under the extreme margin state. It can more realistically reflect the performance of the chip under extreme conditions, help to remove noise interference, and reveal the physical properties of the chip itself.

[0025] Furthermore, the residual deviation and noise deviation of the chip are calculated based on the initial electrical parameter measurement values, the limit recovery value, and the ideal design specification value of the chip; Initial electrical parameter measurements are those made when an anomaly is first detected under standard test conditions; extreme recovery values ​​are electrical parameter values ​​measured under extreme margin conditions; and ideal design specifications are the standard electrical parameter values ​​that the chip should achieve under ideal operating conditions. Residual deviation can be understood as the inherent deviation between the chip's electrical parameters and the ideal design specifications after eliminating the effects of noise, primarily reflecting the degree of physical defects in the chip. Noise deviation, on the other hand, is the deviation in electrical parameters caused by signal coupling noise or other environmental factors. It reflects the chip's sensitivity to noise or performance fluctuations under non-ideal conditions.

[0026] Therefore, the failure components of the chip can be quantitatively judged based on the residual deviation and noise deviation; Quantitative judgment involves numerically assessing the respective proportions and severity of physical defects and noise in chip failures. For example, different thresholds or judgment rules can be set to categorize chip failures as "primarily caused by physical defects," "primarily caused by noise," or "a combination of physical defects and noise."

[0027] Finally, the chips are classified and processed in a refined manner based on the quantitative judgment results.

[0028] Refined classification involves further subdividing non-conforming chips into different subcategories based on the quantitative determination of failure components, such as "hard failure (serious physical defects)," "soft failure (noise-sensitive)," and "marginal failure (minor physical defects but susceptible to noise)." This refined classification helps provide a more accurate basis for subsequent chip disposition, such as scrapping, downgrading, repair, or further analysis.

[0029] Specifically, when a chip is initially judged to be substandard, the basic solution can only provide a macroscopic judgment result. However, this solution adjusts the test conditions to the extreme margin state, changing the chip's electrical margin, thereby more thoroughly exposing the chip's inherent physical defects and weakening or amplifying the impact of noise. Therefore, the extreme recovery value obtained under the extreme margin state, combined with the initial electrical parameter measurements and the ideal design specification values, can accurately separate the chip's residual deviation and noise deviation. The residual deviation directly reflects the degree of physical defects in the chip itself, while the noise deviation quantifies the impact of external interference on chip performance. It is precisely through this quantitative analysis of failure components that this solution can deeply reveal the root cause of chip failure, thereby achieving a more accurate quantitative judgment of the failure components of substandard chips and conducting refined classification processing based on this.

[0030] Through the above technical solution, the present application can significantly improve the level of refinement of integrated circuit quality testing. Compared with only making a preliminary judgment on noise or physical defects, this solution makes the failure cause analysis of non-conforming chips more in-depth and accurate by introducing limit margin testing and quantitative calculation of residual deviation and noise deviation. This not only helps to more accurately identify the actual physical defect level and sensitivity to noise of the chip, but also provides more guiding data for defect tracing and process optimization in the production process. In addition, through quantitative judgment and refined classification of failure components, differentiated treatment of different types of non-conforming chips can be achieved. For example, for "soft failure" chips mainly caused by noise, they may be restored by adjusting the system environment or software parameters; while for "hard failure" chips, they can be directly scrapped or targeted for repair, thereby effectively reducing the misjudgment rate, improving resource utilization efficiency, and ultimately improving the overall production yield and product quality.

[0031] As an embodiment of the present invention, the step of quantitatively determining the failure component of the chip based on the residual deviation and the noise deviation includes: First, obtain the residual deviation and noise deviation data of the reference sample of the current batch of chips; The reference sample can be a random sample of chips from the same production batch, or data accumulated during the production process for chips with known quality status (e.g., qualified products, non-qualified products with specific failure modes). Residual deviation and noise deviation data are calculated using the above method to characterize the deviation of the chip's electrical parameters from the ideal design specifications and the degree to which they are affected by noise.

[0032] Secondly, the residual bias and noise bias data of the reference samples were statistically analyzed; This statistical analysis can include calculating statistical quantities such as the mean, standard deviation, median, and percentiles, as well as performing distribution fitting (e.g., normal distribution, Weibull distribution, etc.) or cluster analysis. Statistical analysis of a large amount of reference sample data can reveal the distribution characteristics and patterns of residual bias and noise bias in chips of varying quality, providing data support for subsequent quantitative judgments.

[0033] Furthermore, based on the statistical analysis results, a threshold value for quantitative judgment is determined; Thresholds are the limiting values ​​used to distinguish between different failure components or different quality levels. For example, thresholds can be set based on specific percentiles of a statistical distribution (such as the 95th or 99th percentile) or multiples of the standard deviation. These thresholds are designed to divide the chip's residual and noise variations into distinct regions, each corresponding to a quantitative assessment of one or more failure components.

[0034] Finally, the determined threshold is used to quantitatively judge the failure components of the chip based on the residual deviation and noise deviation.

[0035] Specifically, the residual deviation and noise deviation of the chip under test are compared with preset thresholds. Based on the region they fall into, it can be determined whether the chip's electrical parameter anomaly is primarily caused by a true physical defect (corresponding to a larger residual deviation), signal coupling noise (corresponding to a larger noise deviation), or both, and the failure component can be quantitatively assessed.

[0036] By incorporating statistical analysis of reference samples, this application's solution establishes an objective, data-driven set of quantitative judgment criteria. Through in-depth statistical analysis of residual deviation and noise deviation data, the inherent characteristics of different failure modes can be more accurately captured, thereby determining more representative and discriminatory judgment thresholds. This approach avoids subjective assumptions when quantitatively determining chip failure components, improving the accuracy and reliability of judgments.

[0037] The above technical solution enables refined, quantitative assessment of the failure components of integrated circuit chips. Compared to methods that rely solely on a single measurement value or simple threshold judgment, this solution, by combining the statistical characteristics of residual deviation and noise deviation, can more clearly identify whether chip anomalies are dominated by physical defects or noise interference, thereby providing a more accurate basis for subsequent refined classification and failure analysis. This helps optimize production processes, improve product yield, and effectively reduce resource waste caused by misjudgments.

[0038] As an embodiment of the present invention, the step of calculating the residual deviation and noise deviation of the chip according to the initial electrical parameter measurement value, the limit recovery value and the ideal design specification value of the chip includes: When the electrical parameter values ​​that deviate from the preset range involve multiple electrical parameter types or multiple chip pins at the same time, for the abnormalities of multiple electrical parameter types or multiple chip pins, the residual deviation and noise deviation of each abnormal electrical parameter are calculated based on the initial electrical parameter measurement value, the limit recovery value and the ideal design specification value of the chip; Specifically, when electrical parameter values ​​deviate from a preset range across multiple electrical parameter types or multiple chip pins simultaneously, this means that during the electrical parameter testing of an integrated circuit chip, the detected electrical parameter anomaly is not a single occurrence, but rather occurs simultaneously across multiple different electrical parameter types (e.g., voltage, current, frequency, timing, etc.) or across multiple different chip pins, with the measured values ​​all deviating from the preset acceptable range. For anomalies across multiple electrical parameter types or multiple chip pins, the residual deviation and noise deviation for each abnormal electrical parameter are calculated based on the initial electrical parameter measurement value, the extreme recovery value, and the chip's ideal design specification value. This means that for each detected abnormal electrical parameter, regardless of whether it belongs to a different electrical parameter type or is located on a different chip pin, the residual deviation and noise deviation are calculated independently. The initial electrical parameter measurement value refers to the measurement value when the electrical parameter anomaly is first detected; the extreme recovery value refers to the value obtained by measuring the electrical parameter again after adjusting the test conditions to the preset extreme margin state; and the ideal design specification value refers to the ideal or target value of the electrical parameter specified during chip design. These values ​​are used to calculate the residual deviation and noise deviation for each individual anomaly.

[0039] Furthermore, a weight is assigned to the residual deviation and noise deviation of each electrical parameter value that deviates from a preset range according to the type of each abnormal electrical parameter or the preset impact factor of its corresponding chip pin; In actual applications, the degree to which anomalies of different types of electrical parameters or different chip pins affect the overall function, performance, and reliability of the integrated circuit chip may vary significantly. For example, a voltage anomaly on a power pin may have a global impact on the function of the entire chip, while a small signal delay anomaly on a non-critical data pin may only affect local function. Therefore, an "impact factor" can be pre-set, which reflects the importance of a specific type of electrical parameter or chip pin, or the severity of its anomaly. These preset impact factors are used as weights and assigned to each individually calculated residual deviation and noise deviation to reflect its relative importance in the overall evaluation.

[0040] Therefore, the residual deviation and noise deviation of the assigned weights are weighted and aggregated to obtain the comprehensive residual deviation and comprehensive noise deviation of the chip.

[0041] After assigning a corresponding weight to each individual residual deviation and noise deviation, these discrete deviation values ​​with different importance weights are combined into a "comprehensive residual deviation" and "comprehensive noise deviation" that represent the overall chip status through weighted averaging or other appropriate weighted aggregation methods. This aggregation method can more comprehensively and accurately reflect the actual physical defect components and signal coupling noise components of the chip under multiple anomalies.

[0042] The solution of this application enables more accurate assessment of the failure components of integrated circuit chips by fine-tuning electrical parameters under multiple anomalies. Conventional methods, when faced with simultaneous anomalies in multiple electrical parameters or multiple pins, may fail to effectively distinguish the importance of different anomalies or simply treat all anomalies as equal, resulting in inaccurate assessments of actual physical defects and signal coupling noise. This solution ensures in-depth analysis of each specific anomaly by separately calculating the residual deviation and noise deviation for each anomaly electrical parameter. Furthermore, the step of assigning weights based on preset impact factors allows for differentiated treatment of anomalies of varying importance. For example, anomalies in critical parameters or pins with a greater impact on chip function are assigned higher weights, giving them a greater position in the final composite deviation. Finally, the step of weighted aggregation of weighted deviations integrates these discrete, weighted deviations into a comprehensive indicator that comprehensively reflects the overall quality of the chip. This enables quantitative assessment of the chip's failure components based on more representative and accurate data, avoiding misjudgments or inadequate assessments caused by multiple anomalies.

[0043] Through the above-mentioned technical solution, the present application can effectively solve the problem of inaccurate evaluation caused by traditional single or simple cumulative calculation methods when integrated circuit chips have multiple points or multiple types of electrical parameter anomalies. This solution independently calculates each anomaly and assigns weights according to its importance, ultimately aggregating it into a comprehensive deviation, making the quantitative judgment of the chip's residual deviation (real physical defects) and noise deviation (signal coupling noise) more accurate and comprehensive. As a result, the root cause of chip failure can be more accurately identified, improving the accuracy and efficiency of chip classification processing. Especially in complex failure modes, it can avoid misjudging occasional anomalies caused by noise as physical defects, or vice versa, thereby optimizing the quality control and yield management of integrated circuits and improving product reliability.

[0044] As an embodiment of the present invention, the step of determining a threshold value for quantitative judgment according to the statistical analysis results includes: During the production process, the chip's residual deviation and noise deviation data are continuously monitored. Specifically, throughout the entire production cycle of integrated circuit chips, after the residual deviation and noise deviation calculations are completed for each batch or each individual chip, the data is collected and stored in real time or near real time. This data can include residual deviation values, noise deviation values, test time, batch information, production line information, etc., to facilitate subsequent statistical analysis. Residual deviation refers to the inherent deviation between the actual electrical parameters of the chip and the ideal design specification values, while noise deviation reflects fluctuations in electrical parameters caused by non-physical defects such as signal coupling noise.

[0045] Statistical analysis of residual and noise deviation data is performed periodically or upon detection of changes in chip batch characteristics to generate updated statistical analysis results. Specifically, this involves statistically processing the collected residual and noise deviation data regularly (e.g., daily, weekly, or at the end of each batch) or upon specific event triggers (e.g., when a production line is adjusted, a raw material is replaced, or when quality control charts show abnormal trends). Statistical analysis can include calculating mean, median, standard deviation, percentiles, and distribution patterns to comprehensively understand the distribution characteristics of residual and noise deviation in chips under the current production status. This allows for the generation of up-to-date statistical analysis results reflecting the current production status.

[0046] Based on updated statistical analysis results, thresholds for quantitative judgment are determined. Specifically, this involves using the latest statistical analysis results to recalculate or adjust the judgment thresholds used to distinguish between chip failure components (for example, physical defects and noise effects). For example, new control limits can be set based on the updated mean and standard deviation, or the pass / fail threshold can be determined based on specific percentiles. This ensures that the quantitative judgment thresholds can dynamically adapt to actual changes in the production process, thereby improving the accuracy and robustness of judgments.

[0047] The solution of the present application effectively solves the problem that the threshold value in the traditional method is fixed and cannot adapt to changes in the production process by continuously monitoring the residual deviation and noise deviation data of the chip during the production process, and dynamically adjusting the threshold value of the quantitative judgment according to the updated statistical analysis results. When the production batch characteristics drift, for example due to equipment wear, process parameter fluctuations or raw material batch differences, the distribution of the residual deviation and noise deviation of the chip may change. Through periodic or event-driven statistical analysis, these changes can be captured in time, and the judgment threshold value can be updated accordingly, so that the threshold value can always accurately reflect the chip characteristics under the current production status. In this way, it is ensured that the quantitative judgment of the chip failure component is always based on the latest and most accurate data, thereby improving the accuracy of the judgment.

[0048] The above technical solution significantly improves the accuracy and reliability of quantitative determination of failure components in integrated circuit chip quality testing. Because the threshold can dynamically adapt to changes in batch characteristics during the production process, failures caused by real physical defects and anomalies caused by signal coupling noise can be more accurately identified, avoiding misjudgments or missed detections. This not only facilitates more efficient and refined chip classification, such as sending physically defective chips for failure analysis and noise-sensitive chips for specific optimization or downgrade, but also provides more accurate feedback for production process improvements, thereby improving overall production quality and efficiency.

[0049] As an embodiment of the present invention, the step of determining a threshold value for quantitative judgment according to the updated statistical analysis result includes: Based on the updated statistical analysis results, calculate the specific percentiles or standard deviation multiples of the statistical distribution of the residual deviation and noise deviation; specifically, after the statistical analysis of the residual deviation and noise deviation data, statistical methods can be used to quantify their distribution characteristics. Specifically, the specific percentiles can refer to, for example, the 95th percentile, the 99th percentile, etc. These percentiles can reflect the location of a specific proportion of data points in the data set. For example, the 99th percentile means that 99% of the data points are less than or equal to this value. The standard deviation multiple can refer to, for example, the mean plus or minus one, two or three standard deviations, etc. These multiples are often used for normally distributed data to define the degree to which the data points deviate from the mean. By calculating these statistics, data-driven boundaries can be provided for subsequent quantitative judgments.

[0050] A threshold for quantitative judgment is determined based on a specific percentile or standard deviation multiple. Specifically, the calculated specific percentile or standard deviation multiple is used directly or after appropriate adjustment as the judgment threshold for distinguishing chip failure components. For example, the 99th percentile of the residual deviation can be set as the threshold for judging the presence of a real physical defect in the chip, or the mean value of the noise deviation plus or minus two standard deviations can be set as the threshold for judging the presence of signal coupling noise in the chip. This threshold determination method based on statistical distribution characteristics can make the judgment threshold more objective and adaptable.

[0051] The solution of this application calculates specific percentiles or multiples of the standard deviation of the statistical distribution of residual deviation and noise deviation based on updated statistical analysis results, and uses this to determine the threshold for quantitative judgment. This allows the threshold to be set not as a fixed empirical value, but to be dynamically adjusted based on the characteristics of chip batches during actual production. This method can more accurately capture the actual distribution of residual deviation and noise deviation, thereby providing a more accurate basis for subsequent quantitative judgment of failure components.

[0052] The above technical solution ensures that the threshold used for quantitative judgment can reflect the actual quality distribution of the current batch of chips in real time, thereby improving the accuracy and reliability of the judgment of chip failure components. This helps to more effectively distinguish anomalies caused by signal coupling noise from those caused by actual physical defects in the chip, thereby achieving more refined chip classification processing, avoiding misjudgments, and improving overall testing efficiency and product quality.

[0053] As an embodiment of the present invention, the step of detecting a change in chip batch characteristics includes: Perform statistical process control analysis on residual deviation and noise deviation data; According to the statistical process control analysis results, when the residual deviation and noise deviation data exceed the preset statistical control limits or show a preset trend, it is judged that the chip batch characteristics have changed.

[0054] Statistical process control analysis refers to the use of statistical methods to monitor and analyze production processes to identify abnormal variations within the process. Its purpose is to ensure stable and consistent product quality. Statistical control limits are upper and lower limits determined based on historical data or theoretical models and used to determine whether a process is in a state of statistical control. Predicted trends can be understood as specific, non-random patterns of data points on a control chart, such as a continuous upward or downward trend or multiple points located on one side of the center line. These trends often indicate possible systemic problems or impending loss of control in the process.

[0055] The solution of the present application can monitor the quality characteristics of chip batches in real time or quasi-real time by performing statistical process control analysis on residual deviation and noise deviation data. When these key deviation data exceed the preset statistical control limits or show a specific preset trend, it indicates that non-random, systematic changes may have occurred in the production process of the chip batch, such as differences in raw material batches, wear of production equipment, drift of process parameters, etc. As a result, the statistical analysis of the residual deviation and noise deviation data can be triggered in a timely manner to ensure that the thresholds used for subsequent quantitative judgments can accurately reflect the true quality distribution of the current batch, avoiding misjudgment caused by the use of outdated or inaccurate thresholds.

[0056] The above technical solution enables sensitive and accurate detection of characteristic variations across batches of integrated circuit chips. This helps promptly detect anomalies in the production process and prevents products with potential defects or quality fluctuations from entering subsequent stages, thereby improving the timeliness and effectiveness of product quality control. Furthermore, by dynamically adjusting thresholds, it can better adapt to natural fluctuations in the production process and differences between batches, making the quantitative determination of failure components more precise, ultimately improving the overall reliability and efficiency of integrated circuit quality testing.

[0057] As an embodiment of the present invention, the step of performing statistical process control analysis on the residual deviation and noise deviation data includes: Use X-bar and R control charts or I-MR control charts to perform statistical process control analysis on residual deviation and noise deviation data.

[0058] Among them, the X-bar control chart and the R control chart are two commonly used control charts in statistical process control. The X-bar control chart is mainly used to monitor changes in the process mean, while the R control chart is used to monitor changes in the process variability. When the residual deviation and noise deviation data can be reasonably grouped, such as when a fixed number of chips are sampled for measurement in each test batch, these control charts can effectively reveal whether the process is in a state of statistical control. The I-MR control chart, that is, the individual value and moving range control chart, is suitable for situations where reasonable grouping cannot be performed or each sample has only one observation value, such as continuous monitoring of the residual deviation and noise deviation of a single chip. By drawing these control charts, one can intuitively observe the changing trend of the residual deviation and noise deviation data over time, and whether there are abnormal points that exceed the control limits or present a non-random pattern.

[0059] The solution in this application utilizes X-bar and R control charts or I-MR control charts to graphically display residual deviation and noise deviation data, and allows for real-time monitoring in conjunction with preset statistical control limits. Data points outside the control limits indicate possible process anomalies; data points exhibiting specific non-random patterns (such as continuous upward or downward trends or cyclical fluctuations) also indicate potential process changes. This allows for timely identification of chip batch characteristic deviations or anomalies, providing accurate judgment for subsequent refined classification processing.

[0060] As an embodiment of the present invention, the step of quantitatively determining the failure component of the chip based on the residual deviation and the noise deviation includes: comparing the residual deviation and the noise deviation with a plurality of preset judgment thresholds; Based on the comparison results, the failure components of the chip are quantitatively judged.

[0061] Multiple preset judgment thresholds can be determined based on historical test data, chip design specifications, known failure mode analysis results, or statistical process control (SPC) analysis results. These thresholds can be set to define boundaries for different failure levels or types. For example, a first set of thresholds can be set to distinguish minor electrical parameter deviations, a second set to distinguish moderate deviations, and a third set to distinguish severe electrical parameter deviations. Residual deviation and noise deviation can be compared against their respective threshold sets, or combined and compared against a multidimensional threshold space. This comparison yields a quantitative judgment result that indicates the degree of chip failure or the type of primary failure component. For example, if the residual deviation exceeds a specific threshold while the noise deviation does not, it may indicate a failure dominated by a physical defect; conversely, it may indicate a failure dominated by signal coupling noise. If both the residual deviation and the noise deviation exceed different thresholds, it may indicate a mixed failure involving both physical defects and signal coupling noise.

[0062] The solution of the present application can make a more precise and quantitative judgment on the failure components of the chip by comparing the residual deviation and noise deviation with multiple preset judgment thresholds. Traditional failure judgment may be limited to a binary classification of qualified and unqualified, or a rough distinction between physical defects and noise effects. However, by introducing multiple judgment thresholds, the failure components can be divided into different levels or categories according to the degree and type of deviation. For example, according to the numerical range of the residual deviation and the noise deviation, the failure components of the chip can be subdivided into various situations such as slight physical defects, severe physical defects, slight noise sensitivity, severe noise sensitivity, and physical defects and noise coupling. This multi-threshold comparison mechanism makes the judgment of the failure components no longer a simple "yes" or "no", but can provide richer failure information, thereby providing a more accurate basis for subsequent refined classification processing.

[0063] like Figure 2 An integrated circuit quality testing system is shown, the system comprising: The initial test module 201 is configured to execute a preset test instruction set to perform electrical parameter testing on the integrated circuit chip. When any electrical parameter value of the chip is detected to deviate from a preset range, the chip is not immediately judged as defective. Instead, the module records the initial electrical parameter measurement value when the electrical parameter deviates from the preset range, the identification of the test instruction sequence, and the chip pin number where the abnormality occurred. A repeat execution module 202, configured to repeatedly execute a test instruction sequence according to the recorded identification of the test instruction sequence and the chip pin number; A condition adjustment module 203, configured to adjust the test conditions to change the electrical margin of the chip when repeatedly executing the test instruction sequence; A secondary measurement module 204 is configured to measure the electrical parameters of the chip again under the adjusted test conditions to obtain secondary verified electrical parameter measurement values; The judgment module 205 is used to judge whether the electrical parameter anomaly is caused by signal coupling noise or a real physical defect of the chip based on the relationship between the initial electrical parameter measurement value and the secondary verification electrical parameter measurement value, so as to obtain a judgment result; The classification processing module 206 is used to classify the chips according to the judgment result.

[0064] The basic principles, main features, and advantages of the present invention are shown and described above. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions only describe the principles of the present invention. Various changes and improvements are possible without departing from the spirit and scope of the present invention, and such changes and improvements fall within the scope of the invention as claimed.

Claims

1. A method for testing the quality of an integrated circuit, characterized in that: The method comprises the following steps: Execute the preset test instruction set to perform electrical parameter tests on integrated circuit chips; When it is detected that any electrical parameter value of the chip deviates from a preset range, the initial electrical parameter measurement value when the electrical parameter deviates from the preset range, the identifier of the test instruction sequence, and the chip pin number where the abnormality occurs are recorded; Repeating the test instruction sequence according to the recorded identifier of the test instruction sequence and the chip pin number, and adjusting the test conditions to change the electrical margin of the chip when repeatedly executing the test instruction sequence, so as to measure and obtain a secondary verification electrical parameter measurement value; Determining, based on a relationship between the initial electrical parameter measurement value and the secondary verification electrical parameter measurement value, whether the electrical parameter anomaly is caused by signal coupling noise or a real physical defect of the chip, to obtain a determination result; The chips are classified according to the judgment result.

2. The integrated circuit quality testing method according to claim 1, wherein: When the chip is classified as a non-conforming product, the method further includes the following steps: Adjusting the test condition to a preset limit margin state to change the electrical margin of the chip; Under the adjusted test conditions, measuring the electrical parameters of the chip again to obtain a limit recovery value; Calculating the residual deviation and noise deviation of the chip according to the initial electrical parameter measurement value, the limit recovery value, and the ideal design specification value of the chip; quantifying the failure component of the chip according to the residual deviation and the noise deviation; According to the quantitative judgment result, the chip is subjected to refined classification processing.

3. The integrated circuit quality testing method according to claim 2, wherein: The step of quantitatively determining the failure component of the chip according to the residual deviation and the noise deviation includes: Obtain residual deviation and noise deviation data of reference samples of the current batch of chips; performing statistical analysis on the residual deviation and noise deviation data of the reference sample; Determining a threshold value for the quantitative judgment based on the statistical analysis results; A determined threshold is used to quantitatively determine the failure component of the chip according to the residual deviation and the noise deviation.

4. The integrated circuit quality testing method according to claim 2, wherein: The step of calculating the residual deviation and noise deviation of the chip according to the initial electrical parameter measurement value, the limit recovery value, and the ideal design specification value of the chip includes: When the electrical parameter values ​​that deviate from the preset range involve multiple electrical parameter types or multiple chip pins at the same time, for the abnormalities of the multiple electrical parameter types or multiple chip pins, respectively calculate the residual deviation and noise deviation of each abnormal electrical parameter based on the initial electrical parameter measurement value, the limit recovery value, and the ideal design specification value of the chip; Assigning weights to the residual deviation and noise deviation of each electrical parameter value that deviates from a preset range based on the type of each abnormal electrical parameter or the preset impact factor of its corresponding chip pin; The residual deviation and the noise deviation with assigned weights are weightedly aggregated to obtain a comprehensive residual deviation and a comprehensive noise deviation of the chip.

5. The integrated circuit quality testing method according to claim 3, characterized in that: The step of determining a threshold value for the quantitative judgment based on the statistical analysis result includes: During the production process, continuously monitoring the residual deviation and noise deviation data of the chip; Periodically or when a change in the chip batch characteristic is detected, statistically analyzing the residual deviation and noise deviation data to obtain updated statistical analysis results; A threshold value for the quantitative judgment is determined according to the updated statistical analysis result.

6. The integrated circuit quality testing method according to claim 5, characterized in that: The step of determining a threshold value for the quantitative judgment based on the updated statistical analysis result includes: Calculating specific percentiles or standard deviation multiples of the statistical distribution of the residual deviation and the noise deviation based on the updated statistical analysis results; A threshold value for the quantitative judgment is determined according to the specific percentile or standard deviation multiple.

7. The integrated circuit quality testing method according to claim 5, characterized in that: The step of detecting a change in the chip batch characteristic comprises: performing statistical process control analysis on the residual deviation and noise deviation data; According to the statistical process control analysis result, when the residual deviation and noise deviation data exceed preset statistical control limits or show a preset trend, it is determined that the chip batch characteristics have changed.

8. The integrated circuit quality testing method according to claim 7, characterized in that: The step of performing statistical process control analysis on the residual deviation and noise deviation data comprises: The residual deviation and noise deviation data are subjected to statistical process control analysis using X-bar and R control charts or I-MR control charts.

9. The integrated circuit quality testing method according to claim 2, characterized in that: The step of quantitatively determining the failure component of the chip according to the residual deviation and the noise deviation includes: comparing the residual deviation and the noise deviation with a plurality of preset judgment thresholds; According to the comparison result, a quantitative judgment is made on the failure component of the chip.

10. An integrated circuit quality testing system, characterized in that: The system comprises: An initial test module, configured to execute a preset test instruction set to perform electrical parameter testing on an integrated circuit chip. When any electrical parameter value of the chip is detected to deviate from a preset range, the module does not immediately determine the chip as a defective product, but instead records the initial electrical parameter measurement value when the electrical parameter deviates from the preset range, an identifier of the test instruction sequence, and the chip pin number where the abnormality occurred. A repeat execution module, configured to repeatedly execute the test instruction sequence according to the identifier of the recorded test instruction sequence and the chip pin number; a condition adjustment module, configured to adjust test conditions to change the electrical margin of the chip when repeatedly executing the test instruction sequence; A secondary measurement module, configured to measure the electrical parameters of the chip again under the adjusted test conditions to obtain secondary verified electrical parameter measurement values; a judgment module, configured to judge, based on a relationship between the initial electrical parameter measurement value and the secondary verification electrical parameter measurement value, whether the electrical parameter anomaly is caused by signal coupling noise or a real physical defect of the chip, so as to obtain a judgment result; The classification processing module is used to classify the chips according to the judgment result.

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