UVM verification method, electronic device and readable storage medium

Abstract

The application discloses a UVM verification method, an electronic device and a readable storage medium, and belongs to the computer field. The method comprises the following steps: obtaining a target excitation sequence for universal verification method (UVM) verification, wherein the target excitation sequence comprises a first excitation sequence, the first excitation sequence is an excitation sequence comprising a static bucket, the static bucket comprises a plurality of excitations stored in the form of a static queue, and there is a front-back correlation between at least two excitations in the plurality of excitations; and verifying a design under test by using the target excitation sequence.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of computers, and particularly relates to a UVM verification method, an electronic device and a readable storage medium. BACKGROUND

[0002] Before a to-be-tested design (for example, a chip) is formally applied, in order to ensure that the function of the to-be-tested design is normal, the to-be-tested design usually needs to be simulated and verified. At present, in the simulation and verification process of the to-be-tested design, a verification platform built by a universal verification methodology (UVM) is usually applied to apply an excitation signal to the to-be-tested design, so as to verify the to-be-tested design.

[0003] However, the excitation signal applied to the to-be-tested design in the related art is usually randomly generated, and such random excitation signal is difficult to perform directional verification on the to-be-tested design. SUMMARY

[0004] Embodiments of the present application provide a UVM verification method, an electronic device and a readable storage medium, and can solve the problem that the related art is difficult to perform directional verification on a to-be-tested design.

[0005] In a first aspect, embodiments of the present application provide a UVM verification method applied to a verification platform, comprising:

[0006] obtaining a target excitation sequence for UVM verification, the target excitation sequence containing a first excitation sequence, the first excitation sequence being an excitation sequence containing a static bucket, the static bucket containing a plurality of excitations stored in the form of a static queue, and there being a front-rear correlation between at least two excitations in the plurality of excitations;

[0007] verifying a to-be-tested design using the target excitation sequence.

[0008] In a second aspect, embodiments of the present application provide an electronic device comprising a processor and a memory, the memory storing a program or instructions, the program or instructions being executed by the processor to implement the method of the first aspect.

[0009] In a third aspect, embodiments of the present application provide a readable storage medium, the readable storage medium storing a program or instructions, the program or instructions being executed by a processor to implement the method of the first aspect.

[0010] In a fourth aspect, embodiments of the present application provide a computer program product comprising a computer program, the computer program being executed by a processor to implement the method of the first aspect.

[0011] In the embodiment of the present application, in the process of verifying the design under test, the target stimulus sequence used contains a static bucket, the static bucket contains a plurality of stimuli stored in the form of a static queue, and there is a correlation between at least two stimuli in the plurality of stimuli. Since the static bucket of the target stimulus sequence contains a plurality of stimuli stored in the form of a static queue, and there is a correlation between at least two stimuli in the plurality of stimuli, the static bucket in the target stimulus sequence can be used to perform directional verification on the design under test, thereby solving the problem that it is difficult to perform directional verification on the design under test in the related art. Moreover, compared with the single stimulus scenario using random stimuli in the related art, the embodiment of the present application introduces a directional stimulus scenario through the target stimulus sequence, thereby achieving a more abundant stimulus scenario. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a schematic diagram of a standard UVM verification platform;

[0013] Figure 2 is a schematic diagram of a verification platform based on the UVM library mechanism;

[0014] Figure 3 is a flowchart of a UVM verification method provided by the embodiment of the present application;

[0015] Figure 4 is an example schematic diagram of a static bucket provided by the embodiment of the present application;

[0016] Figure 5 is an example schematic diagram of a target library provided by the embodiment of the present application;

[0017] Figure 6 is an example schematic diagram of another target library provided by the embodiment of the present application;

[0018] Figure 7 is a flowchart of another UVM verification method provided by the embodiment of the present application;

[0019] Figure 8 is a schematic diagram of the overall flow of simulation verification provided by the embodiment of the present application;

[0020] Figure 9 is a schematic diagram of the specific flow of simulation verification provided by the embodiment of the present application;

[0021] Figure 10 is a specific flowchart of a UVM verification method provided by the embodiment of the present application;

[0022] Figure 11 is a structural block diagram of a UVM verification device provided by the embodiment of the present application;

[0023] Figure 12 is a structural block diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0025] The terms “first”, “second”, and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by “first”, “second”, and the like are generally of a kind and are not limited to the number of objects, for example, the first object can be one or more. In addition, “and / or” in the specification and claims indicates at least one of the connected objects, and the character “ / ” generally indicates that the front and rear associated objects are in an “or” relationship.

[0026] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application.

[0027] At present, the simulation verification process of the design to be tested is as follows: the verification platform applies a clock signal to the design to be tested, releases the reset end, waits for the design to be tested to complete its power-on / initialization process, and then applies different excitation signals to the input port of the design to be tested, and at the same time, the excitation signal is also applied to the reference model of the verification platform. The verification platform monitors the output of the design to be tested in real time, and verifies whether the function of the design to be tested is normal by comparing the output of the design to be tested with the output of the reference model.

[0028] To facilitate understanding of the UVM verification method provided in the embodiments of the present application, the UVM verification platform is introduced first. The UVM is a library and a set of methodology framework based on the System Verilog language for integrated circuit verification, which provides a standardized and reusable way to build a verification platform, thereby efficiently verifying the correctness of a digital circuit design. The UVM verification platform usually includes an input agent (in_agent), an output agent (out_agent), a reference model (reference model) and a scoreboard (scoreboard). Among them, the input agent includes a sequencer, a driver and a monitor; the output agent includes a monitor. During simulation verification, the stimulus content, which can be a transaction, is usually generated by a sequence generator (sequence) and sent to the sequencer. When the driver applies for data, the sequencer sends the stimulus content obtained from the sequence generator to the driver. After obtaining the stimulus content, the driver can drive the stimulus content to the input port of the design under test according to the interface protocol, thereby applying the stimulus signal to the design under test. The UVM verification platform in the embodiments of the present application can be in the form of software or a physical machine. The sequencer, driver, monitor and sequence generator in the UVM verification platform can be in the form of software or hardware that can realize their respective software functions.

[0029] Generally, the stimulus generated by the UVM verification platform is a single stimulus. Referring to Figure 1 , Figure 1 , it is a schematic diagram of a standard UVM verification platform. As shown in Figure 1 , there is only one stimulus sequence (stimulus sequence 1) in the figure, and the stimulus generated thereby is relatively single, so that the stimulus sent to the sequencer is relatively single. For example, if the current verification content is to access a block of memory, the three-dimensional data contained in the transaction are: [read or write], [read or write address], [if write, what is the value of write]. In this case, the generated stimulus is random, and if you want to specifically do [write address 1 first, then write address 8, then write address 6, then write address 9], or [read read read write write write read write read write] and the like, you can only rely on random to reach this scenario, which is like finding a needle in a haystack. Moreover, in this case, there is no necessary correlation between the stimuli, i.e., there is no relationship between the stimuli (i.e., stimulus 1, stimulus 2, stimulus 3... stimulus N in Figure 1 ) applied to the design under test by the driver.

[0030] To enrich the diversity of stimuli, the UVM verification methodology currently also proposes a way to generate diverse stimuli based on the UVM library mechanism. Referring to Figure 2 , Figure 2 is a schematic diagram of a verification platform based on the UVM library mechanism. This mechanism can call multiple stimulus sequences, i.e., stimulus sequence 1, stimulus sequence 2,..., and stimulus sequence N as shown in Figure 2 Although this way can generate more diverse stimuli, such as stimulus 1 of stimulus sequence 1, stimulus 1 of stimulus sequence 3, stimulus 2 of stimulus sequence 1,..., and stimulus 1 of stimulus sequence 2 as shown in Figure 2 , this way still cannot guarantee the correlation between stimuli, and cannot meet the verification requirements of the design under test requiring correlation between stimuli. The description of the verification platform and the components in the verification platform in Figure 1 and Figure 2 can be referred to above, and will not be specifically expanded here.

[0031] The UVM verification method provided by the embodiments of the present application is applied to the simulation verification technology of the design under test, and in particular, can be applied to the simulation verification scene where the design under test requires necessary correlation between stimuli and stimuli. In this scenario, through the UVM verification method provided by the embodiments of the present application, the design under test can be verified through the target stimulus sequence with the correlation between at least two stimuli, and the specific requirement of the correlation between the stimuli can be realized. directional verification, so as to enrich the verification scene and trigger more boundary scenarios. In addition, the target stimulus sequence in the embodiments of the present application can also include a first stimulus sequence and a second stimulus sequence, that is, the UVM verification method provided by the embodiments of the present application can have the specificity of directional verification and the randomness of the original stimulus sequence. Among them, the first stimulus sequence is a stimulus sequence containing a static bucket, which can be used to realize directional verification; the second stimulus sequence is a stimulus sequence containing randomly generated stimuli, which can be used to realize random verification.

[0032] The UVM verification method provided by the embodiments of the present application can be executed by a target device, which can be a verification platform, or the target device can be a device deployed with a simulation verification environment for the design under test.

[0033] The UVM verification method provided by the embodiments of the present application will be described in detail below in combination with the specific embodiments and their application scenarios.

[0034] Referring to Figure 3 , Figure 3 is a flowchart of a UVM verification method provided by the embodiments of the present application, which is applied to a verification platform. As shown in Figure 3 , the method comprises the following steps:

[0035] Step 310: obtaining a target stimulus sequence for UVM verification, the target stimulus sequence comprising a first stimulus sequence, the first stimulus sequence being a stimulus sequence comprising a static bucket, the static bucket comprising a plurality of stimuli stored in a static queue; there is a correlation between at least two stimuli in the plurality of stimuli.

[0036] In the embodiment of the present application, the first stimulus sequence is a stimulus sequence implemented by a static bucket. The target stimulus sequence can include one or more first stimulus sequences, the first stimulus sequence being a stimulus sequence for implementing a specific verification requirement (i.e., the to-be-tested design requires a correlation between stimuli), and the number of first stimulus sequences can be set according to specific requirements. The stimulus content of any one stimulus stored in the static bucket remains unchanged before and after being called, and the order of any two stimuli in the static bucket remains unchanged. In fact, the stimulus content and order of the plurality of stimuli stored in the static bucket remain unchanged before the stimuli in the static bucket are sent out.

[0037] Reference can be made to Figure 4 , Figure 4 is an example schematic diagram of a static bucket provided by the embodiment of the present application. As Figure 4 indicated, the first stimulus sequence can be, for example Figure 4 stimulus sequence A1, which comprises a static bucket, generates all stimuli at each time of scheduling, i.e. Figure 4 stimulus a1, stimulus a2, stimulus a3... stimulus an in

[0038] The plurality of stimuli can be a plurality of stimuli of the same stimulus type, or the plurality of stimuli can be a plurality of stimuli of different stimulus types, and the at least two stimuli can be stimuli of the same stimulus type in the plurality of stimuli. In fact, among the plurality of stimuli, there is a correlation between all stimuli of the same stimulus type. That is, the correlation here refers to the correlation between stimuli of the same stimulus type and the order of stimuli of the same stimulus type. The stimulus type here is the data type processed by the to-be-tested design, for example, the to-be-tested design can be an image processing chip, and the stimulus type can be an image type. However, it should be noted that the specific type of the to-be-tested design is not specifically limited in the embodiment of the present application, and is not limited to an image processing chip as an example, but can be a chip or circuit of other types. In particular, the embodiment of the present application can be applied to a to-be-tested design with a specific verification requirement (i.e., a correlation between stimuli).

[0039] In addition, it should be noted that the stimuli stored in the static bucket are transaction-level stimuli, and in fact, unless otherwise specified, the stimuli mentioned in the present application are transaction-level stimuli. Since the stimuli stored in the static bucket are transaction-level stimuli, in the process of sending the stimuli in the static bucket, no additional conversion is required compared to the case where the information in the bucket needs to be converted into transaction-level stimuli.

[0040] Step 320: verifying the design under test using the target stimulus sequence.

[0041] In the embodiments of the present application, in the process of verifying the design under test using the target stimulus sequence, the multiple stimuli stored in the static bucket in the first stimulus sequence can be sent in order and driven to the design under test, that is, the stimuli are sequentially sent according to the first-in-first-out order of the static queue, thereby verifying the design under test.

[0042] In the embodiments of the present application, since the static bucket in the target stimulus sequence contains multiple stimuli stored in the form of a static queue, and there is a front-back correlation between at least two of the multiple stimuli, the static bucket in the target stimulus sequence can be used to verify the design under test in a targeted manner, thereby solving the problem that related technologies are difficult to verify the design under test in a targeted manner. Moreover, compared to the single stimulus scenario using random stimuli in related technologies, the embodiments of the present application introduce a targeted stimulus scenario through the target stimulus sequence, thereby achieving a more diverse stimulus scenario.

[0043] In an embodiment of the present application, the number of the first stimulus sequences can be at least one, and each of the at least one first stimulus sequence contains a static bucket, and the at least two stimuli contained in the static bucket are stimuli for the same image. That is, the embodiments of the present application can be applied to verification scenarios such as image processing that require a front-back correlation between stimuli, and through the method provided by the embodiments of the present application, the front-back correlation between stimuli for the same image can be maintained through the static bucket, thereby facilitating the design under test to use this front-back correlation for image restoration.

[0044] In the embodiments of the present application, the design under test can be an image processing type chip or a digital circuit. The target stimulus sequence can include multiple first stimulus sequences, and each of the multiple first stimulus sequences can contain a static bucket. The multiple stimuli stored in the static bucket can be stimuli for the same image, or the multiple stimuli can include stimuli for multiple images. There is a front-back correlation between all the stimuli for the same image in the multiple stimuli, that is, if there is a front-back correlation between two stimuli, it can be considered that the two stimuli can be used to indicate the same image.

[0045] In an embodiment of the present application, the plurality of stimuli are stimuli for the same image, and each of the plurality of stimuli comprises information of a stimulus type, a total number of stimuli for the same image, and a number of a current stimulus. In this way, the sequence relationship between the stimuli is further indicated by the information, and after the stimuli are applied to the design under test, the design under test can obtain complete image data by the information contained in the stimuli.

[0046] In an embodiment of the present application, the static bucket contained in each first stimulus sequence is used to store a plurality of stimuli for the same image. Taking an image processing chip as an example, the stimulus type can be an image type, and the image processing chip can support processing images of multiple image specifications. For an image, image data of the image can be encapsulated in the format of an Ethernet frame, and the image processing chip can receive the image data through a network port (RJ45). According to the IEEE802.3 Ethernet standard, the maximum length of the data part (i.e., the Payload field) of an Ethernet frame is 1500 bytes. Taking an image processing chip processing an image of 1024*512*4 bytes as an example, the overall image data is much larger than 1500 bytes. Therefore, the image cannot be completely encapsulated in the same Ethernet frame, and the image data of the image needs to be divided to obtain multiple pieces of data, which are encapsulated in multiple Ethernet frames, and the multiple Ethernet frames correspond to the multiple stimuli one by one. After the image data is divided, the total number of Ethernet frames, i.e., the total number of stimuli, can be obtained.

[0047] In addition, the multiple Ethernet frames can be numbered. For each of the multiple Ethernet frames, an image type, a number (denoted as cur_cnt) of the Ethernet frame, and a total number (denoted as total_cnt) of Ethernet frames can be encapsulated in the Ethernet frame. Thus, after the multiple Ethernet frames are received, the design under test can obtain the three types of information by analyzing the Ethernet frames, and can determine which Ethernet frames can constitute a complete image data by the image type, cur_cnt, and total_cnt, so as to obtain complete image data. In this way, for the multiple Ethernet frames obtained by division, the sequence relationship between the Ethernet frames, i.e., cur_cnt, total_cnt, and the image type, can be maintained by encapsulating the three types of information in the Ethernet frames.

[0048] For any one of the plurality of stimuli, the stimulus corresponds to an Ethernet frame, and the Ethernet frame is used to encapsulate a piece of image data in an image. The stimulus type of the stimulus is an image type, and the number of the stimulus is the number of the Ethernet frame corresponding to the stimulus. For example, an image is totally divided into 5 Ethernet frames, i.e., the plurality of stimuli can be 5 stimuli, the first stimulus corresponds to the first Ethernet frame, the stimulus type of the first stimulus is an image type, the number of the stimulus (cur_cnt) is 1, and the total number of the stimuli is 5; the second stimulus corresponds to the second Ethernet frame, the stimulus type of the second stimulus is an image type, the number of the stimulus (cur_cnt) is 2, and the total number of the stimuli is 5; and the like, which will not be described herein again. The 5 stimuli are stored by the static bucket in the embodiment of the present application, so that the front-back relationship among the 5 stimuli can be further maintained.

[0049] In an embodiment of the present application, in addition to the first stimulus sequence, the target stimulus sequence can further include a second stimulus sequence, the second stimulus sequence is a stimulus sequence not containing a static bucket, and all the stimuli in the second stimulus sequence are randomly generated stimuli.

[0050] In the embodiment of the present application, the first stimulus sequence is a stimulus sequence used to implement directional verification, and the second stimulus sequence is a stimulus sequence used to implement random verification. The first stimulus sequence can be used to implement verification for a specific verification scenario (i.e., requiring correlation between front-back stimuli), and the second stimulus sequence can be used to implement verification for a random scenario (i.e., not requiring correlation between front-back stimuli). Since the target stimulus sequence contains both the first stimulus sequence and the second stimulus sequence, the target stimulus sequence can be used to verify the design under test, and the target stimulus sequence has both randomness of the original stimulus sequence and specificity of directional verification.

[0051] In an embodiment of the present application, the step 310 of obtaining the target stimulus sequence for UVM verification includes: obtaining the target stimulus sequence for UVM verification from a target library. The target library can be a stimulus sequence library containing a plurality of stimulus sequences, and the plurality of stimulus sequences contain the first stimulus sequence and the second stimulus sequence. Alternatively, the target library can contain a plurality of stimulus sequence libraries, and the plurality of stimulus sequence libraries contain at least one target stimulus sequence library, and the target stimulus sequence library contains the first stimulus sequence and the second stimulus sequence.

[0052] In the embodiments of the present application, the number of the excitation sequence libraries in the target library can be adjusted according to the verification scene and the verification requirement, and the target library can be stored in the verification platform in the form of a file. Taking the target library containing only one excitation sequence library as an example, the excitation sequence library can contain at least one first excitation sequence and at least one second excitation sequence, and the number of the first excitation sequences and the specific number of the second excitation sequences can be adjusted according to the verification scene and the verification requirement, and no specific limitation is made herein. For details, refer to Figure 5 , Figure 5 FIG. 1 is an example schematic diagram of a target library provided by the embodiments of the present application. Figure 5 As shown in FIG. 1, the target library can be, for example, an excitation sequence library 1 in Figure 5 which contains excitation sequence A1, excitation sequence A2, excitation sequence A3,..., and excitation sequence An. Among them, excitation sequence A1, excitation sequence A2, and excitation sequence An are all first excitation sequences, that is, excitation sequences containing static buckets. Before scheduling a static bucket each time, all excitations can be generated. For example, as shown in Figure 5 , before scheduling the static bucket in excitation sequence A1, excitations a1, a2, a3,..., and an can be generated first, and these excitations will be stored in the static bucket. Excitation sequence A3 is a second excitation sequence, that is, an excitation sequence containing randomly generated excitations. Such an excitation sequence is a common excitation sequence, similar to the excitation sequence in the standard UVM verification platform in Figure 1 , which is only used to generate a single excitation.

[0053] As shown in FIG. 1, the excitation sequence library can be created in multiple, that is, the target library can also contain multiple excitation sequence libraries, and at least one excitation sequence library in the multiple excitation sequence libraries contains both first excitation sequences and second excitation sequences, and other excitation sequence libraries can contain only first excitation sequences or only second excitation sequences, and no specific limitation is made herein. Figure 5 In fact, each excitation sequence library in the target library can contain both first excitation sequences and second excitation sequences. For details, refer to

[0054] , Figure 6 , Figure 6 FIG. 2 is another example schematic diagram of a target library provided by the embodiments of the present application. Figure 6 As shown in FIG. 2, the target library is a relatively complex example, and the multiple excitation sequence libraries can be, for example, excitation sequence library 1, excitation sequence library 2,..., and excitation sequence library N shown in Figure 6 . Among them, excitation sequence library 1, excitation sequence library 2, and excitation sequence library N can contain both first excitation sequences and second excitation sequences.

[0055] As shown in FIG. 2, the excitation sequence library can be created in multiple, that is, the target library can also contain multiple excitation sequence libraries, and at least one excitation sequence library in the multiple excitation sequence libraries contains both first excitation sequences and second excitation sequences, and other excitation sequence libraries can contain only first excitation sequences or only second excitation sequences, and no specific limitation is made herein. Figure 6As shown, the excitation sequence Al, the excitation sequence A2 and the excitation sequence An in the excitation sequence library 1 are all first excitation sequences (excitation sequences containing static buckets), and the excitation sequence A3 is a second excitation sequence (an excitation sequence containing randomly generated excitation). Similarly, the excitation sequence Bl, the excitation sequence B2 and the excitation sequence Bn in the excitation sequence library 2 are all first excitation sequences, and the excitation sequence B3 is a second excitation sequence. The excitation sequence Xl, the excitation sequence X2 and the excitation sequence Xn in the excitation sequence library N are all first excitation sequences, and the excitation sequence X3 is a second excitation sequence. In this way, in the entire verification platform, the set of all excitations is sum (excitation sequence library 1, excitation sequence library 2,..., excitation sequence library N), which can realize verification of specific verification scenarios in which there is correlation between the front and rear excitations (realized by the first excitation sequence containing static buckets), and also realize verification of random verification scenarios in which there is no correlation between the front and rear excitations (realized by the second excitation sequence not containing static buckets), and such a verification environment has both the randomness of original excitation sequences and the specificity of directional verification.

[0056] In fact, when the design under test does not require correlation between the front and rear excitations, the UVM verification method provided in the embodiments of the present application can also be used for directional testing. That is, the simulation verification is performed according to a specific excitation sequence to generate excitation signals and send them to the design under test to see whether the output of the design under test meets the expectation. In addition, the number of excitation sequence libraries, the number of excitation sequences in the excitation sequence library, and whether the excitation sequence contains a static bucket can all be adjusted according to the verification scenario and verification requirements, and are not limited to Figure 5 and Figure 6 two target library examples shown.

[0057] Please refer to Figure 7 , Figure 7 is a flowchart of another UVM verification method provided in the embodiments of the present application, which is applied to a verification platform, and the verification platform includes an excitation generator, a sequencer and a driver. As shown in Figure 7 , the method includes the following steps:

[0058] Step 710: The excitation generator obtains the first excitation sequence, and the first excitation sequence is used for transmission to the sequencer.

[0059] In the embodiments of the present application, as shown in Figure 1 and Figure 2As shown, the verification platform includes a stimulus generator (sequence module) and a sequencer. The stimulus generator can generate Transaction-level stimulus, and can notify the sequencer bound to it to get Transaction-level stimulus by calling the function start_item() and the function finish_item(). The multiple stimuli in the first stimulus sequence can be sent to the sequencer in sequence. The starting of the verification platform can be started by means of the mechanism of the sequence library of UVM.

[0060] It should be noted that, as described in the above embodiments, the target library in the embodiments of the present application can include multiple stimulus sequences (such as Figure 5 and Figure 6 As shown, after starting the verification platform, each stimulus sequence can be dispatched in sequence, and one stimulus sequence is dispatched at a time. After the dispatch of the stimulus sequence is completed, the next stimulus sequence is dispatched. The embodiments of the present application take the dispatch of the first stimulus sequence as an example for introduction.

[0061] Step 720: The driver sends a stimulus signal to the design under test to verify the design under test; wherein the stimulus signal is obtained based on the first stimulus sequence.

[0062] In the embodiments of the present application, the verification platform can further include a driver (driver). The driver has a pointer of a virtual interface (Virtual Interface) inside, and the pointer points to a physical interface (System Verilog Interface) that is actually connected to the design under test. The driver can obtain stimulus (Transaction) from the sequencer by pulling mode. Specifically, when the driver is ready to process new data, the next stimulus to be processed can be pulled from the sequencer by actively calling the function get_next_item(). After the driver obtains the stimulus, the abstract data (such as address and data, etc.) in the stimulus can be decomposed and converted into a series of specific stimulus signals according to the specific timing protocol of the interface of the design under test, and the stimulus signals are driven to the physical interface of the design under test through the virtual interface, so as to verify the design under test. The specific timing protocol can be, for example, a Gigabit Media Independent Interface (GMII) protocol.

[0063] In the embodiment of the present application, the first stimulus sequence is acquired by the stimulus generator, and the stimulus signal sent by the driver to the design under test is based on the first stimulus sequence, so that the first stimulus sequence containing the static bucket can be obtained from the source (the stimulus generator), without the need to modify the process after the stimulus generator, thereby ensuring convenient implementation of the whole scheme. Meanwhile, the first stimulus sequence contains the correlation between at least two stimuli, and the directional verification can be realized through the first stimulus sequence.

[0064] In one embodiment of the present application, after the stimulus generator acquires the first stimulus sequence in step 710, the UVM verification method comprises the following steps in addition to the above-mentioned steps 710-720: the stimulus generator judges whether the static bucket in the first stimulus sequence is empty; in the case that the static bucket is not empty, the stimulus generator judges whether all the stimuli in the static bucket need to be sent this time; in the case that the stimulus generator judges that all the stimuli in the static bucket do not need to be sent this time, the stimulus generator sends part of the stimuli in the static bucket to the sequencer; in the case that the stimulus generator judges that all the stimuli in the static bucket need to be sent this time, the stimulus generator sends the stimuli in the static bucket to the sequencer in sequence until the static bucket is empty.

[0065] Through the scheduling mode, when the first stimulus sequence is scheduled, all the stimuli in the static bucket of the first stimulus sequence can be sent to the sequencer in this scheduling process, or part of the stimuli in the static bucket can be sent to the sequencer, thereby realizing various different stimulus transmission modes.

[0066] For details, refer to Figure 8 and Figure 9 , Figure 8 is a general flowchart of simulation verification provided by the embodiment of the present application, Figure 9 is a specific flowchart of simulation verification provided by the embodiment of the present application. The specific implementation process will be described below in combination with Figure 8 and Figure 9 . As shown in Figure 8As shown, after the simulation of the verification platform starts, the initialization can be performed by calling the function env_cfg.randomize() first, and then the UVM stimulus sequence scheduling mechanism is started to schedule a certain stimulus sequence in the target library and execute the transactions of the stimulus sequence, and the scheduling of the stimulus sequence is completed. If all the stimulus sequences in the target library are scheduled after the completion of the scheduling of all the stimulus sequences, and there is still a static bucket in one of the stimulus sequences that is not empty, the UVM stimulus sequence scheduling mechanism can be continued to be executed until all the static buckets in the target library are empty, which indicates that the simulation verification process of the verification platform is completed. That is, whether the verification platform is completed can be determined according to whether the stimuli in the static buckets of all the stimulus sequences in the target library are all sent out.

[0067] The following is described by taking the scheduling to the first stimulus sequence as an example. As shown in Figure 9 First, the stimulus generator can determine whether the first stimulus sequence has completed all transactions, and if the first stimulus sequence has completed all transactions, the scheduling process of the current first stimulus sequence can be exited. If the first stimulus sequence has not completed all transactions, the stimulus generator can determine whether the static bucket in the first stimulus sequence is empty. In the case that the static bucket in the first stimulus sequence is not empty, the stimulus generator can send part of the stimuli in the static bucket to the sequencer. Here, the part of the stimuli in the static bucket may, for example, be one of the multiple stimuli stored in the static bucket.

[0068] Then, the stimulus generator can determine whether all the stimuli in the static bucket need to be sent this time. In the case that the stimulus generator determines that all the stimuli in the static bucket need to be sent this time, it can be determined whether the current static bucket is empty. In the case that the current static bucket is empty, it indicates that all the stimuli in the static bucket have been sent, and the scheduling process of the first stimulus sequence is exited. In the case that the current static bucket is not empty, the stimulus generator can continue to send the stimuli in the static bucket to the sequencer, which can be sent in the order of first-in-first-out of the static queue until the static bucket is empty, the scheduling process of the first stimulus sequence is exited, and the next scheduling is waited for.

[0069] In an embodiment of the present application, after the excitation generator determines whether the static bucket in the first excitation sequence is empty, the UVM verification method further comprises the following steps in addition to the above steps: if the static bucket is empty, generating the i th excitation. The i th excitation contains the following information: the total number of excitations N, the number of the i th excitation, and the type of the i th excitation; and writing the i th excitation into the static bucket. The value of i is increased by 1, and the above process is repeated until the N th excitation is written into the static bucket. Both i and N are positive integers, and i ≤ N. In this way, there is a correlation between the previous excitation and the next excitation among the N excitations generated, thereby ensuring that there is a correlation between the N excitations stored in the static bucket, so as to meet the verification requirements of a specific verification scenario.

[0070] may be combined Figure 9 It is understood that the above process of generating excitations is as follows: Figure 9 If the static bucket of the current first excitation sequence is empty, an excitation is generated and stored in the static bucket. For example, based on an image, the image data of the image is divided into N parts, and the N parts of image data are encapsulated in N Ethernet frames, each Ethernet frame corresponding to an excitation, and the N Ethernet frames corresponding to N excitations. The total number of excitations N is env_cfg.total_cnt in Figure 9 .

[0071] The variable i is initialized to 1, and it can be first determined whether i is equal to N+1. If i is equal to N+1, it means that N excitations have been generated, and the filling of the static bucket is complete. If i is not equal to N+1, it means that the generation of N excitations is not complete, and the i th excitation can be generated. Specifically, the excitation entity n(i) of the i th excitation is created, the number of the i th excitation (denoted as n(i).cur_cnt) is obtained, and the number of the i th excitation is determined as i, i.e. n(i).cur_cnt=i. At the same time, the total number of excitations corresponding to the i th excitation (denoted as n(i).total_cnt) is obtained, i.e. n(i).total_cnt=env_cfg.total_cnt=N, and the type of the i th excitation n(i).type=image is obtained, i.e. the type of the i th excitation is image type. At this time, all the information contained in the i th excitation has been generated, and the i th excitation can be written into the static bucket. The value of i is increased by 1, and it is determined whether the current i is equal to N+1, and the above process is repeated until i is equal to N+1, i.e. N excitations are written into the static bucket, and it is determined that the filling of the static bucket is complete. After the filling of the static bucket is complete, the excitation generator can be as follows: Figure 9The sending static bucket is filled with the excitation shown, and the sending process can refer to the above, which will not be expanded here.

[0072] Please refer to Figure 10 , Figure 10 is a specific flowchart of a UVM verification method provided by the embodiment of the application, the method is applied to a verification platform, and the verification platform includes an excitation generator, a sequencer and a driver. As shown in Figure 10 , the method includes the following steps:

[0073] Step 1010: obtaining a target excitation sequence for UVM verification from a target library, the target excitation sequence containing a first excitation sequence, the first excitation sequence being an excitation sequence containing a static bucket, the static bucket containing a plurality of excitations stored in the form of a static queue, and there being a front-back correlation between at least two excitations in the plurality of excitations.

[0074] In the embodiment of the application, each of the first excitation sequences contains a static bucket, the plurality of excitations are excitations for a same image, and each of the plurality of excitations contains information of an excitation type, a total number of excitations for the same image and a number of a current excitation. The target excitation sequence further includes a second excitation sequence, the second excitation sequence being an excitation sequence not containing a static bucket, and all excitations in the second excitation sequence being randomly generated excitations.

[0075] The target library can be an excitation sequence library containing a plurality of excitation sequences, the plurality of excitation sequences containing the first excitation sequence and the second excitation sequence; or the target library can contain a plurality of excitation sequence libraries, the plurality of excitation sequence libraries containing at least one target excitation sequence library, and the target excitation sequence library containing the first excitation sequence and the second excitation sequence.

[0076] Step 1020: verifying a design under test using the target excitation sequence.

[0077] Taking the first excitation sequence as an example, in the process of obtaining the target excitation sequence for UVM verification, the excitation generator obtains the first excitation sequence, and the first excitation sequence is transmitted to the sequencer. In the process of verifying the design under test using the target excitation sequence, the driver sends an excitation signal to the design under test to verify the design under test, and the excitation signal is obtained based on the first excitation sequence.

[0078] After the excitation generator acquires the first excitation sequence, the excitation generator judges whether the static bucket in the first excitation sequence is empty. In the case where the static bucket is not empty, the excitation generator judges whether all excitations in the static bucket need to be sent this time. In the case where the excitation generator judges that all excitations in the static bucket do not need to be sent this time, the excitation generator sends part of the excitations in the static bucket to the sequencer. In the case where the excitation generator judges that all excitations in the static bucket need to be sent this time, the excitation generator sends the excitations in the static bucket to the sequencer in turn until the static bucket is empty.

[0079] In the case where the static bucket is empty, the following process is performed: generating an i th excitation; wherein the i th excitation contains the following information: total number of excitations N, number of the i th excitation, type of the i th excitation; writing the i th excitation into the static bucket. The value of i is increased by 1, and the above process is repeatedly performed until the N th excitation is written into the static bucket. Wherein i and N are positive integers, and i≤N.

[0080] In the embodiments of the present application, the static bucket of the target excitation sequence contains a plurality of excitations stored in the form of a static queue, and there is a front-back correlation between at least two excitations in the plurality of excitations. Thus, the static bucket in the target excitation sequence can be used to perform directional verification on the design under test, solving the problem that the related art is difficult to perform directional verification on the design under test. Moreover, compared with the single excitation scenario using random excitation in the related art, the embodiments of the present application introduce a directional excitation scenario through the target excitation sequence, achieving a richer excitation scenario.

[0081] It should be noted that the descriptions of the same or corresponding steps in the above embodiments can be mutually referred to, for example Figure 3 the description of step 320 in Figure 10 step 1020 in, which will not be described here again.

[0082] Meanwhile, it should be understood that the UVM verification method provided in the embodiments of the present application can have the following beneficial effects: first, a management mechanism of an excitation sequence based on a static bucket is provided, there is a front-back correlation between a plurality of excitations for the same image stored in the static bucket, and a specific verification scenario requiring a front-back correlation between excitations can be achieved through the excitation sequence containing the static bucket, the excitation scenario can be enriched, and the coverage of the specific excitation sequence can be enhanced. Second, the verification platform in the embodiments of the present application can provide a simulation verification environment in which randomness and directionality coexist, and has the randomness of the original excitation sequence and the directional verification characteristics of the excitation sequence in the static bucket.

[0083] Please refer to Figure 11 ,Figure 11 is a structural block diagram of a UVM verification device provided by an embodiment of the present application. As shown in the figure, Figure 11 an embodiment of the present application provides a UVM verification device 1100, which comprises an acquisition module 1110 and a verification module 1120.

[0084] The acquisition module 1110 is configured to acquire a target excitation sequence for UVM verification, wherein the target excitation sequence comprises a first excitation sequence, the first excitation sequence is an excitation sequence comprising a static bucket, the static bucket comprises a plurality of excitations stored in the form of a static queue, and there is a correlation between at least two excitations in the plurality of excitations.

[0085] The verification module 1120 is configured to verify a design under test using the target excitation sequence.

[0086] In an embodiment of the present application, since the static bucket of the target excitation sequence comprises a plurality of excitations stored in the form of a static queue, and there is a correlation between at least two excitations in the plurality of excitations, the static bucket in the target excitation sequence can be used to perform directional verification on the design under test, thereby solving the problem that it is difficult to perform directional verification on the design under test in the related art. Moreover, compared with the single excitation scenario using random excitation in the related art, the target excitation sequence introduced by an embodiment of the present application introduces a directional excitation scenario, thereby achieving a more abundant excitation scenario.

[0087] The UVM verification device provided by an embodiment of the present application can implement each process achieved by the method embodiments, and thus details are not repeated here.

[0088] As shown in the figure, Figure 12As shown, the embodiments of the present application further provide an electronic device 1200. The electronic device 1200 comprises a processor 1210 and a memory 1220, and the memory 1220 stores programs or instructions, which are executed by the processor 1210 to implement the steps of any of the above-described methods. For example, the programs are executed by the processor 1210 to implement the following process: obtaining a target stimulus sequence for UVM verification, the target stimulus sequence comprising a first stimulus sequence, the first stimulus sequence being a stimulus sequence comprising a static bucket, the static bucket comprising a plurality of stimuli stored in a static queue, and there being a correlation between at least two of the plurality of stimuli; and verifying a design under test using the target stimulus sequence. Thus, since the static bucket of the target stimulus sequence comprises a plurality of stimuli stored in a static queue, and there is a correlation between at least two of the plurality of stimuli, the static bucket in the target stimulus sequence can be used to perform directional verification of the design under test, thereby solving the problem that it is difficult to perform directional verification of the design under test in the related art. Moreover, compared with the single stimulus scenario using random stimuli in the related art, the embodiments of the present application introduce a directional stimulus scenario through the target stimulus sequence, thereby achieving a richer stimulus scenario.

[0089] The embodiments of the present application further provide a readable storage medium, which stores programs or instructions, which are executed by a processor to implement the steps of the embodiments of the UVM verification method and achieve the same technical effects. To avoid repetition, details are not described herein.

[0090] The processor is the processor of the electronic device described in the above embodiments. The readable storage medium comprises a computer readable storage medium, such as a computer readable only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0091] The embodiments of the present application further provide a chip, which comprises a processor and a communication interface, the communication interface being coupled to the processor, and the processor being configured to run programs or instructions to implement the processes of the above-described method embodiments and achieve the same technical effects. To avoid repetition, details are not described herein.

[0092] The embodiments of the present application provide a computer program product, which is stored in a storage medium, and the program product is executed by at least one processor to implement the processes of the above-described method embodiments and achieve the same technical effects. To avoid repetition, details are not described herein.

[0093] It should be noted that, in the present document, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element. Furthermore, it is to be understood that the method and apparatus of the present application can be carried out by more than one process, method, article, or apparatus either simultaneously, concurrently, or with intervening action that are carried out at the same time, either in a simultaneous fashion or in a fashion that is interleaved in time. For example, the described methods can be performed in a different order from that described, and / or various steps can be combined or omitted, and / or additional steps can be added, without departing from the scope of the present application. Also, features described with respect to certain examples can be combined in other examples.

[0094] From the above description of the embodiments, it is apparent that the above-described method of the embodiments can be realized by means of software and general-purpose hardware platforms, and of course, can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such an understanding, the technical solutions of the present application can be embodied in the form of a computer software product, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disk), and includes a plurality of instructions for causing a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the method described in each embodiment of the present application.

[0095] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-described specific embodiments, and the above-described specific embodiments are merely illustrative, rather than limiting, and those of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims, which all belong to the protection of the present application.

Claims

1. A UVM verification method, characterized in that, Applications in verification platforms include: Obtain a target stimulus sequence for verification using the Universal Validation Method (UVM). The target stimulus sequence includes a first stimulus sequence, which is a stimulus sequence containing static buckets. Each static bucket contains multiple stimuli stored in the form of a static queue. At least two stimuli among the multiple stimuli are correlated. Each first stimulus sequence contains one static bucket, and the at least two stimuli in the static bucket are stimuli for the same image. Each of the multiple stimuli for the same image contains the following information: stimulus type, total number of stimuli for the same image, and the number of the current stimulus. The target stimulus sequence was used to verify the design under test; The target stimulus sequence further includes a second stimulus sequence, which is a stimulus sequence that does not contain a static bucket, and all stimuli in the second stimulus sequence are randomly generated.

2. The method according to claim 1, characterized in that, The process of obtaining the target stimulus sequence for verification using the Universal Validation Method (UVM) includes: Obtain the target stimulus sequence for UVM verification from the target library; Wherein, the target library is an incentive sequence library containing multiple incentive sequences, the multiple incentive sequences including the first incentive sequence and the second incentive sequence; or, the target library contains multiple incentive sequence libraries, the multiple incentive sequence libraries including at least one target incentive sequence library, the target incentive sequence library including the first incentive sequence and the second incentive sequence.

3. The method according to any one of claims 1-2, characterized in that, The verification platform includes an excitation generator, a sequencer, and a driver; The step of obtaining the target stimulus sequence for the Universal Validation Method (UVM) validation includes: the stimulus generator obtaining the first stimulus sequence, which is used to transmit the first stimulus sequence to the sequencer; The verification of the design under test using the target stimulus sequence includes: the driver sending a stimulus signal to the design under test to verify the design under test; wherein the stimulus signal is obtained based on the first stimulus sequence.

4. The method according to claim 3, characterized in that, After the stimulus generator obtains the first stimulus sequence, the method further includes: The incentive generator determines whether the static bucket in the first incentive sequence is empty; If the static bucket is not empty, the stimulus generator determines whether it is necessary to send all stimuli in the static bucket this time; If the stimulus generator determines that it does not need to send all the stimuli in the static bucket this time, the stimulus generator sends a portion of the stimuli in the static bucket to the sequencer; If the stimulus generator determines that all stimuli in the static bucket need to be sent this time, the stimulus generator sends the stimuli in the static bucket to the sequencer in sequence until the static bucket is empty.

5. The method according to claim 4, characterized in that, The method further includes: If the static bucket is empty, the following process is performed: generate the i-th stimulus; wherein, the i-th stimulus contains the following information: the total number of stimuli N, the number of the i-th stimulus, and the type of the i-th stimulus; and write the i-th stimulus into the static bucket. Increment the value of i by 1 and repeat the above process until the Nth stimulus is written into the static bucket; Where i and N are both positive integers, and i ≤ N.

6. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that, when executed by the processor, implement the method as described in any one of claims 1 to 5.

7. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the method as described in any one of claims 1 to 5.

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