Verification method and device, electronic equipment, storage medium and program product

Abstract

The invention relates to a verification method and device, electronic equipment, a storage medium and a program product, and relates to the field of chip verification, the method comprises the following steps: using a to-be-verified model to carry out arbitration operation, and outputting a first result; calling a target reference model, and simulating an arbitration behavior of the to-be-verified model through queue polling by taking an arrangement sequence of request channel numbers in a first queue of the target reference model as a polling sequence to obtain a second result; and comparing the first result with the second result, and determining a verification result. According to the embodiment of the invention, complex time sequence level modeling is avoided, the target reference model takes the arrangement sequence of the request channel numbers in the first queue as a polling sequence, and the arbitration behavior of the to-be-verified model is simulated through queue polling, so that the to-be-verified model is fully verified, and the verification complexity and investment cost are greatly reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of chip verification, and in particular to a verification method and device, electronic equipment, storage medium, and program product. Background Art

[0002] During the chip design process, chip design verification is required to ensure its correctness and to ensure that the subsequently produced chips meet the design objectives and expected functions. During chip verification, reference models of hardware modules can be established as required to fully verify the chip design.

[0003] For chip designs integrating a polling arbiter, achieving a polling arbiter model consistent with the hardware circuit requires timing-level modeling. Without a timing model for the polling arbiter, only fuzzy comparisons based on the final interface output make it difficult to guarantee the accuracy of the arbitration results, increasing the risk of chip development later. While timing-level modeling fully simulates the timing characteristics and logical relationships of the hardware circuit, it requires significant manpower and time for verification and development. Summary of the Invention

[0004] The present disclosure provides a verification method and device, an electronic device, a storage medium, and a program product.

[0005] According to one aspect of the present disclosure, a verification method is provided, comprising: performing an arbitration operation on at least one request signal using a model to be verified, and outputting a first result; calling a target reference model, taking the arrangement order of the request channel numbers in the first queue of the target reference model as the polling order, simulating the arbitration behavior of the model to be verified on the at least one request signal through queue polling, and obtaining a second result; and comparing the first result with the second result to determine a verification result.

[0006] In one possible implementation, the method for constructing the target reference model includes: describing the behavior of the polling arbitrator in software using a hardware description language to obtain an initial reference model; setting the first queue and the second queue for the initial reference model to obtain the target reference model, wherein the second queue is used to store the interface sampling data of the model to be verified, and the first queue is used to store the request channel number of the model to be verified.

[0007] In one possible implementation, the method further includes: obtaining specification information of the model to be verified, the specification information being used to indicate the maximum number of request signals that can be arbitrated by the model to be verified each time; and constructing a sampling interface for the model to be verified in a chip verification system based on the specification information, wherein the sampling interface is used to sample the model to be verified, and the sampled interface sampling data of the model to be verified is stored in the second queue of the target reference model.

[0008] In one possible implementation, the interface sampling data includes N-bit data, a first identifier, and a second identifier, the N-bit data is used to indicate the validity of the request signals of the N request channels of the model to be verified, the first identifier is used to indicate whether there is a valid request signal of at least one request channel, and the second identifier is used to indicate whether the arbitration of the model to be verified is successful, and N is an integer greater than 1.

[0009] In one possible implementation, the target reference model is called, and the arrangement order of the request channel numbers in the first queue of the target reference model is used as the polling order. The arbitration behavior of the model to be verified on the at least one request signal is simulated through queue polling to obtain a second result, including: outputting the first result in response to the model to be verified completing the arbitration operation, and obtaining the second result according to the first queue and the second queue of the target reference model when the first identifier in the second queue is the first identifier value and the second identifier is the second identifier value, wherein the first identifier value indicates that the request signal of at least one request channel is valid, and the second identifier value indicates that the arbitration of the model to be verified is successful.

[0010] In one possible implementation, the second result is obtained based on the first queue and the second queue of the target reference model, including: judging whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the first queue; if the request signal corresponding to the request channel number in the second queue is not empty, taking the request signal corresponding to the request channel number as the second result, and arranging the request channel number stored at the head of the first queue to the end of the first queue as the first queue corresponding to the next round of arbitration operation of the target reference model.

[0011] In one possible implementation, the method further includes: when the request signal corresponding to the request channel number in the second queue is empty, arranging the request channel number stored at the head of the first queue to the end of the first queue to obtain an updated first queue; continuing to judge whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the updated first queue, until a second result of the target reference model is obtained.

[0012] In one possible implementation, the first queue and the second queue are set for the initial reference model to obtain the target reference model, including: obtaining specification information of the model to be verified, the specification information being used to indicate the maximum number of request signals that can be arbitrated by the model to be verified each time; and according to the specification information, setting the first queue and the second queue for the initial reference model to obtain the target reference model, the depth of the first queue and the second queue being determined by the specification information.

[0013] According to one aspect of the present disclosure, a verification device is provided, including: a first module, used to use a model to be verified to perform an arbitration operation on at least one request signal and output a first result; a second module, used to call a target reference model, take the arrangement order of the request channel numbers in the first queue of the target reference model as the polling order, simulate the arbitration behavior of the model to be verified on the at least one request signal through queue polling, and obtain a second result; a comparison module, used to compare the first result with the second result to determine a verification result.

[0014] In one possible implementation, the verification device also includes a construction module for constructing the target reference model, including: describing the behavior of the polling arbitrator in software through a hardware description language to obtain an initial reference model; setting the first queue and the second queue for the initial reference model to obtain the target reference model, wherein the second queue is used to store the interface sampling data of the model to be verified, and the first queue is used to store the request channel number of the model to be verified.

[0015] In one possible implementation, the device also includes a sampling interface construction module, which is used to: obtain specification information of the model to be verified, where the specification information is used to indicate the maximum number of request signals that can be arbitrated by the model to be verified each time; and construct a sampling interface for the model to be verified in a chip verification system based on the specification information, wherein the sampling interface is used to sample the model to be verified, and store the sampled interface sampling data of the model to be verified into the second queue of the target reference model.

[0016] In one possible implementation, the interface sampling data includes N-bit data, a first identifier, and a second identifier, the N-bit data is used to indicate the validity of the request signals of the N request channels of the model to be verified, the first identifier is used to indicate whether there is a valid request signal of at least one request channel, and the second identifier is used to indicate whether the arbitration of the model to be verified is successful, and N is an integer greater than 1.

[0017] In one possible implementation, the second module is used to: output the first result in response to the model to be verified completing the arbitration operation, and when the first identifier in the second queue is a first identifier value and the second identifier is a second identifier value, obtain the second result according to the first queue and the second queue of the target reference model, wherein the first identifier value indicates that there is a valid request signal of at least one request channel, and the second identifier value indicates that the arbitration of the model to be verified is successful.

[0018] In one possible implementation, a second result is obtained based on the first queue and the second queue of the target reference model, including: judging whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the first queue; if the request signal corresponding to the request channel number in the second queue is not empty, taking the request signal corresponding to the request channel number as the second result, and arranging the request channel number stored at the head of the first queue to the end of the first queue as the first queue corresponding to the next round of arbitration operation of the target reference model.

[0019] In one possible implementation, the second module is also used to: when the request signal corresponding to the request channel number in the second queue is empty, arrange the request channel number stored at the head of the first queue to the end of the first queue to obtain an updated first queue; continue to judge whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the updated first queue, until the second result of the target reference model is obtained.

[0020] In one possible implementation, a first queue and a second queue are set for the initial reference model to obtain a target reference model, including: obtaining specification information of the model to be verified, the specification information being used to indicate the maximum number of request signals that can be arbitrated by the model to be verified each time; and according to the specification information, setting the first queue and the second queue for the initial reference model to obtain the target reference model, wherein the depth of the first queue and the second queue is determined by the specification information.

[0021] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0022] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above method is implemented.

[0023] According to one aspect of the present disclosure, a computer program product is provided, comprising computer program instructions, which implement the above method when executed by a processor.

[0024] In an embodiment of the present disclosure, an arbitration operation is performed on at least one request signal using a model to be verified, and a first result is output; the target reference model is called, and the arrangement order of the request channel numbers in the first queue of the target reference model is used as the polling order, and the arbitration behavior of the model to be verified on at least one request signal is simulated through queue polling to obtain a second result; the first result is compared with the second result to determine the verification result.

[0025] Compared to related technologies, chip verification involves creating reference models (e.g., software simulation models) for hardware modules (e.g., polling arbiters) as needed. Modeling polling arbiters is particularly challenging. To achieve a reference model consistent with the hardware circuit, timing-level modeling is required to fully simulate the hardware circuit's timing and logic, ensuring that the reference model's multiple inputs are strictly consistent with the actual inputs of the model to be verified, and achieving timing alignment. This places significant demands on verification development manpower and time. Without a timing model, fuzzy comparisons based solely on the final interface outputs can make it difficult to guarantee the accuracy of the arbitration results, increasing the risk of chip failure later.

[0026] The verification method of the disclosed embodiment, by setting a first queue in the target reference model, can use the order of the request channel numbers in the first queue as the polling order, and simulate the arbitration behavior of the model to be verified through queue polling, avoiding complex timing level modeling. Because by setting the first queue, it is convenient to store the request channel numbers in the first queue according to the preset rules, the originally complex timing relationship is abstracted into a simple queue order relationship, which greatly simplifies the timing processing. For example, an initial polling order can be set for the first queue, and then each time the model to be verified performs an arbitration operation, the target reference model can be called once, so that the target reference model updates the first queue according to the preset rules each time it simulates arbitration behavior, so as to obtain the polling order of the next round of simulated arbitration behavior of the target reference model (that is, the polling order used for the next call to the target reference model), aligning the timing of the target reference model and the model to be verified, which is conducive to the full verification of the model to be verified and greatly reduces the complexity and investment cost of verification.

[0027] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0029] Figure 1 A flowchart of a verification method according to an embodiment of the present disclosure is shown.

[0030] Figure 2 A schematic diagram showing a model to be verified according to an embodiment of the present disclosure.

[0031] Figure 3 A block diagram of a verification device according to an embodiment of the present disclosure is shown.

[0032] Figure 4 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0033] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0034] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0035] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of three situations: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0036] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0037] Figure 1 A flow chart of a verification method according to an embodiment of the present disclosure is shown as follows: Figure 1 As shown, the verification method may include:

[0038] In step S11, an arbitration operation is performed on at least one request signal using the model to be verified, and a first result is output;

[0039] In step S12, the target reference model is called, and the order of the request channel numbers in the first queue of the target reference model is used as the polling order. The arbitration behavior of the model to be verified on at least one request signal is simulated through queue polling to obtain a second result.

[0040] In step S13, the first result is compared with the second result to determine a verification result.

[0041] In one possible implementation, the verification method of the embodiment of the present disclosure can be executed by an electronic device such as a terminal device or a server. The terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. The verification method can be implemented by a processor calling computer-readable instructions stored in a memory. Alternatively, the verification method can be executed by a server. Among them, a chip verification system can be deployed on the electronic device, such as a Universal Verification Methodology (UVM) verification platform. This application does not limit the type of chip verification system.

[0042] In a possible implementation, in step S11, the model to be verified is a register transfer level model used to simulate a polling arbiter in a chip verification system. The model to be verified in the chip verification system can be used to perform arbitration operations on at least one request signal and output a first result.

[0043] Arbiters manage competing access to shared resources (such as buses and memory) from multiple requesters (such as devices and interrupt sources), ensuring that resources are used by only one requester at a time and avoiding conflicts. A round-robin arbiter, a relatively common arbiter, primarily receives request signals from multiple requesters and allocates resources in a sequential, round-robin manner, ensuring that each requester receives fair access. In hardware, round-robin arbiters can be used to manage shared resources and ensure efficient system operation. This round-robin, fair arbitration strategy effectively improves system performance and fairness.

[0044] The request signal for the model to be verified can come from a driver of the chip verification system. The driver is used to continuously apply different excitation signals to the model to be verified as request signals for the model to be verified, thereby providing the model to be verified with a simulated real-world input scenario. The driver can set different request signals at different cycles based on user input instructions. Alternatively, the driver can randomly generate different request signals at different cycles. The embodiments of this disclosure do not limit the specific manner in which the driver generates the request signal.

[0045] It should be understood that in the chip verification system, since the driver can generate request signals that comply with various interface protocols, the driver can generate request signals with different functions according to different scenarios.

[0046] For example, in a scenario where multiple devices simultaneously initiate access requests to a memory device, this is equivalent to the multiple devices being upstream of the model to be verified and the memory device being downstream. In this case, the request signal applied by the driver to the model to be verified is an access request signal, and the model to be verified can be used to perform arbitration on at least one access request signal and output a first result.

[0047] For another example, if multiple peripherals (such as a keyboard, mouse, and timer) simultaneously initiate interrupt requests to the processor, this means the model to be verified has multiple peripherals upstream and the processor downstream. In this case, the request signal applied by the driver to the model to be verified is an interrupt request signal, and the model to be verified can be used to arbitrate at least one interrupt request signal and output a first result.

[0048] Among them, the request signal may include signals of various functions such as access request, read request, write request, calculation request, interrupt request, etc. The embodiments of the present disclosure do not specifically limit the functional category of the request signal.

[0049] In one possible implementation, in step S12, whenever it is detected that the model to be verified completes the arbitration operation on at least one request signal input in the current round and outputs a first result, the target reference model can be called to arbitrate the same at least one request signal in accordance with the order of the request channel numbers recorded in the first queue to obtain a second result.

[0050] The arbitration rule for the target reference model is to poll from the head of the first queue in each round. If the request channel corresponding to a request channel number does not have a request signal in the current round, the request channel number is skipped and the next request channel number is polled until a request channel with a request signal is found or the first queue is exhausted. After each round of arbitration, the selected request channel number is moved to the end of the first queue. This update maintains the order of the request channel numbers recorded in the first queue and serves as the polling order for the next round of arbitration under the target reference model.

[0051] In one possible implementation, in step S13, the first result of the arbitration output of the model to be verified and the second result of the arbitration output of the target reference model can be compared round by round to determine the verification result. If the first and second results of a round differ, an error message is output and verification is restarted. If the first result of each round of arbitration output of the model to be verified and the second result of the arbitration output of the target reference model are identical, the verification result indicates that the model to be verified has passed verification.

[0052] In related technologies, modeling polling arbiters is particularly challenging, as reference models are built for hardware modules as needed during chip verification. To achieve a reference model consistent with the hardware circuit, timing-level modeling is required to fully simulate the hardware circuit's timing and logic, ensuring that the reference model's multiple inputs are strictly consistent with the actual inputs of the model to be verified, and achieving timing alignment. This places a significant demand on verification and development personnel and time. Without a timing model, fuzzy comparisons based solely on the final interface outputs can make it difficult to guarantee the accuracy of the arbitration results, increasing the risk of later chip development.

[0053] The verification method of the disclosed embodiment avoids complex timing-level modeling. Instead, a first queue is set up in the target reference model to store the request channel numbers of the model to be verified. The order of the request channel numbers in the first queue of the target reference model is used as the polling order, and the arbitration behavior of the model to be verified is simulated through queue polling. By setting up the first queue, the request channel numbers are easily stored in the first queue according to preset rules, abstracting the originally complex timing relationship into a simple queue order relationship, greatly simplifying the timing processing. For example, an initial polling order can be set for the first queue. Then, each time the model to be verified performs an arbitration operation, the target reference model can be called once. Each time the target reference model simulates arbitration behavior, the first queue is updated according to the preset rules. The polling order for the next round of simulated arbitration behavior of the target reference model (i.e., the polling order used for the next call to the target reference model) is obtained. This aligns the timing of the target reference model and the model to be verified, facilitates the full verification of the model to be verified, and greatly reduces the complexity and investment cost of verification.

[0054] In one possible implementation, a method for constructing a target reference model includes: describing the behavior of a polling arbitrator in software using a hardware description language to obtain an initial reference model; setting a second queue and a first queue for the initial reference model to obtain a target reference model, wherein the second queue is used to store interface sampling data of the model to be verified, and the first queue is used to store the request channel number of the model to be verified.

[0055] For example, the initial reference model is derived from the logic modeling of the polling arbiter's arbitration behavior using a hardware description language. It should be understood that this initial reference model is not derived from timing-level modeling; it is a non-timing-level reference model, significantly less difficult to develop than a timing-level reference model. In actual applications, while this initial reference model cannot simulate the timing logic of the polling arbiter and cannot directly synchronize with the polling arbiter's timing, it can be used to simulate the polling arbiter's arbitration logic.

[0056] Because hardware description languages ​​are cross-platform, the same initial reference model code can run on different simulation environments or hardware platforms. This provides developers with greater flexibility to fully leverage the advantages of various resources. Examples of hardware description languages ​​include SV (System Verilog), a high-level hardware description and verification language widely used in digital chip design and verification. For example, a reference model for a polling arbitrator can be established using SV software. The disclosed embodiments do not limit the specific type of hardware description language.

[0057] After the initial reference model is obtained, a first queue and a second queue may be set for the initial reference model to obtain a target reference model.

[0058] By setting up the first and second queues for the initial reference model, the resulting target reference model can monitor each arbitration action of the model under verification to align timing and synchronize that timing with the target reference model. The model under verification is a register transfer level (RTL) model used to simulate a polling arbiter in a chip verification system. This is an abstract model of synchronous digital circuits, determined by the flow of digital signals between logic units such as hardware registers, memories, combinational logic devices, and buses, and their logical algebraic operation.

[0059] In the chip verification system's verification environment, the interface sampling data of the model to be verified can be transferred to the target reference model, and each sampled interface sampling data is stored in the target reference model's second queue. Furthermore, a first queue with the same dimensions as the number of request channels of the model to be verified is created in the target reference model. The polling order is based on the order of the request channel numbers in the target reference model's first queue, simulating a polling arbiter using queue polling.

[0060] For example, the input of the polling arbiter simulated by the model to be verified includes N (N is an integer greater than 1) request channels, namely: request channel 1 to request channel N. The first queue can be initialized to 1, 2, 3, ..., N. The request channel 1 indicated by the request channel number 1 stored at the head of the first queue has the highest priority, and the request channel N indicated by the request channel number N stored at the end of the first queue has the lowest priority.

[0061] The interface sampling data of the model to be verified can be monitored in real time. Assume that in the first cycle (corresponding to the first arbitration operation), an excitation signal is applied to the request channel 2 and the request channel 3 of the model to be verified. By monitoring the interface sampling data of the model to be verified, the interface sampling data of the first cycle can be stored in the second queue. The second and third bits of the N-bit data included in the interface sampling data are set to 1, and the other N-2 bits are set to 0, indicating that only the request channel 2 and the request channel 3 have received the request signal, and the other N-2 request channels have not received the request signal. The model to be verified can query whether the second bit of the N-bit data in the second queue (that is, the position indicated by the request channel number 2 stored at the current head of the first queue) is 1. Since the second bit of the N-bit data included in the interface sampling data is 1, it means that the excitation signal is applied to request channel 2. The request signal from request channel 2 can be used as the arbitration result, and the request channel number 2 stored at the head of the first queue is arranged at the end of the first queue. The first queue is updated to 3, 4, ..., N, 1, 2, indicating the next arbitration order, among which request channel 3 has the highest priority and request channel 2 has the lowest priority.

[0062] Assume that in the second cycle (corresponding to the first arbitration operation), request channels 1 and 3 of the model to be verified apply an excitation signal. By monitoring the interface sampling data of the model to be verified, the interface sampling data of the second cycle can be stored in a second queue. The first and third bits of the N-bit data included in this interface sampling data are set to 1, and the other N-2 bits are set to 0, indicating that only request channels 1 and 3 have received the request signal, while the other N-2 request channels have not received the request signal. The model to be verified can query whether the third bit of the N-bit data in the second queue (i.e., the position indicated by request channel number 3 stored at the head of the first queue) is 1. Since the third bit of the N-bit data included in the interface sampling data is 1, it indicates that request channel 3 has applied an excitation signal. The request signal from request channel 3 can be used as the arbitration result, and request channel number 3 stored at the head of the first queue is moved to the end of the first queue. The first queue is updated to 4, ..., N, 1, 2, 3, indicating the next arbitration order, where request channel 4 has the highest priority and request channel 3 has the lowest priority.

[0063] For another example, assuming that in the second cycle (corresponding to the first arbitration operation), excitation signals are applied to request channel 1 and request channel 4 of the model to be verified. By monitoring the interface sampling data of the model to be verified, the interface sampling data of the second cycle can be stored in the second queue, and the 1st and 4th bits of the N-bit data included in the interface sampling data are set to 1, and the other N-2 bits are set to 0, indicating that only request channel 1 and request channel 4 have received the request signal, and the other N-2 request channels have not received the request signal. The model to be verified can query whether the third bit of the N-bit data in the second queue (that is, the position indicated by the request channel number 3 stored at the current head of the first queue) is 1. Since the third bit of the N-bit data included in the interface sampling data is not 1, it means that the request channel 3 has not applied the excitation signal. The first queue is updated to 4, ..., N, 1, 2, 3, and the query continues to check whether the fourth bit of the N-bit data in the second queue (that is, the position indicated by the request channel number 4 stored at the current head of the first queue) is 1. Since the fourth bit of the N-bit data included in the interface sampling data is 1, it means that the request channel 4 has applied the excitation signal. The request signal from request channel 4 can be used as the arbitration result, and the first queue is updated to 5, ..., N, 1, 2, 3, 4, indicating the next arbitration order, where request channel 5 has the highest priority and request channel 4 has the lowest priority.

[0064] The process continues in this way until the driver stops applying the excitation signal to the model to be verified. The embodiment of the present disclosure does not impose any specific restrictions on the number of request channels and arbitration times of the simulated polling arbitrator, and they can be set according to actual application scenarios.

[0065] After obtaining a target reference model with a second queue and a first queue in step S12, the model to be verified can be verified against the target reference model in step S13 to obtain a verification result. For example, interface sampling data of the model to be verified can be periodically sampled and stored in the second queue of the target reference model. Based on the interface sampling data stored in the second queue and the arbitration order stored in the first queue, a determination is made as to whether the behavior of the target reference model is consistent with that of the model to be verified, thereby obtaining a verification result.

[0066] As can be seen, due to the high complexity and high investment cost of timing-level modeling for the polling arbiter in hardware, there is a risk of inadequate verification. In view of this, the verification method of the disclosed embodiments avoids complex timing-level modeling and provides a first queue and a second queue in the target reference model. The second queue is used to store the interface sampling data of the model to be verified, and the first queue stores the request channel numbers of the model to be verified. The polling order is based on the order of the request channel numbers in the first queue of the target reference model, simulating the polling arbiter. Because the second queue can store the interface sampling data of each cycle of the model to be verified in real time, each time the second queue is updated (i.e., corresponding to an arbitration operation of the model to be verified), the first queue can be updated based on the second queue (for example, the number of request channel numbers at the head of the first queue to be inserted into the tail of the queue can be determined based on the N-bit data included in the interface sampling data in the second queue), thereby obtaining the polling order for the next cycle of the target reference model. This aligns the timing of the target reference model and the model to be verified (each time the model to be verified arbitrates, the arbitration order of the target reference model can be synchronously updated using the first and second queues). This facilitates the full verification of the model to be verified and significantly reduces the complexity and investment cost of verification.

[0067] The verification method of the embodiment of the present disclosure is described below.

[0068] In actual applications, we first need to clarify the implementation specifications of the register transfer level model (i.e., the model to be verified) used to simulate the polling arbiter in the chip verification system, and understand the specific multiple request objects of the model to be verified.

[0069] In a possible implementation, specification information of the model to be verified may be obtained, where the specification information indicates the maximum number of request signals that can be arbitrated each time by the model to be verified, that is, the number of request channels of the polling arbitrator hardware simulated by the model to be verified.

[0070] Figure 2 Schematic diagram of a model to be verified according to an embodiment of the present disclosure is shown. Figure 2 As shown, the model to be verified is a register-transfer-level model used to simulate a polling arbiter in a chip verification system. The inputs simulated by this model include a control terminal arb_en that receives an enable signal and four (N=4) request channels: pipe0, pipe1, pipe2, and pipe3. The outputs of this model simulation include two output interfaces: arb_out, which provides the arbitration result of the model to be verified, such as the selected request channel number; and arb_out_valid, which provides the output validity flag of the model to be verified.

[0071] According to the specification information of the model to be verified, the behavior of the polling arbitrator is described in software through the hardware description language to obtain an initial reference model. According to the specification information, the first queue and the second queue can be set for the initial reference model to obtain the target reference model. The depth of the first queue and the second queue is determined by the specification information.

[0072] By setting the depth of the first and second queues using the specification information, you can build a target reference model that fully matches the behavior of the model to be verified, improving verification efficiency and accuracy. For example, if the specification information is N, indicating that the model to be verified has N request channels, you can set the depth of the second queue to N+2 and the depth of the first queue to N.

[0073] In one possible implementation, a sampling interface is constructed for the model to be verified in the chip verification system based on the specification information. The sampling interface is used to sample the model to be verified and store the sampled interface data of the model to be verified in a second queue of the target reference model. For example, in the verification environment, the sampling interface can be used to perform real-time sampling of multiple request channels of the model to be verified, and the collected interface sample data can be stored in the second queue.

[0074] Since the second queue can store the interface sampling data of each round of arbitration operation of the model to be verified in real time, every time the second queue is updated (that is, each time an arbitration operation of the model to be verified occurs), the first queue can be updated based on the second queue to obtain the next round of polling order of the target reference model. This aligns the timing of the target reference model and the model to be verified, facilitates the full verification of the model to be verified, and greatly reduces the complexity and investment cost of verification.

[0075] In one possible implementation, the interface sampling data may include N-bit data data[0:N-1], a first identifier valid and a second identifier enable, the N-bit data data[0:N-1] is used to indicate the validity of the request signals of the N request channels of the model to be verified, the N-bit data data[0:N-1] is data composed of bit-wise splicing of the validity information of the request signals of multiple request channels of the model to be verified, the first identifier valid is used to indicate whether there is a valid request signal of at least one request channel, the second identifier enable is used to indicate whether the arbitration of the model to be verified is successful, and N is an integer greater than 1.

[0076] like Figure 2 As shown, the 4-bit data data[0:3] included in the interface sampling data can be obtained by splicing from low to high according to the validity of each request signal in the request channel pipe0, request channel pipe1, request channel pipe2, and request channel pipe3.

[0077] For example, assuming that the request signals of the three request channels pipe0, pipe1, and pipe2 are valid, and the request channel pipe3 has not received the request signal, data[0:3]=0111; among them, data[0]=1 indicates that the request channel pipe0 has received the request signal, data[1]=1 indicates that the request channel pipe1 has received the request signal, data[2]=1 indicates that the request channel pipe2 has received the request signal, and data[3]=0 indicates that the request channel pipe3 has not received the request signal.

[0078] By adjusting the N value, the target reference model can be easily adapted to models to be verified of different sizes and complexities, thus enhancing the scalability of the verification method.

[0079] The first flag is a flag indicating that any request channel is valid, which can be expressed as valid, such as Figure 2 As shown, if the request signal of any of the four request channels is valid, the first identifier valid is valid, which is recorded as the first identifier valid=1; if none of the four request channels receives a valid request signal, the first identifier valid is invalid, which is recorded as the first identifier valid=0.

[0080] The second flag, enable, is a flag indicating that the model to be verified has successfully arbitrated. Figure 2 As shown, if the control terminal arb_en is enabled, the second flag enable is valid, enable=arb_en=1; if the control terminal arb_en input is empty or low level, the second flag enable is invalid, enable=arb_en=0.

[0081] Through the first identifier valid, it is possible to quickly determine whether there is a valid request signal from at least one request channel in the current round of the model to be verified. Through the second identifier enable, it is possible to quickly determine whether the arbitration operation of the current round of the model to be verified is successful. Through the first identifier valid and the second identifier enable, the accuracy and effectiveness of the verification method can be improved. When the first identifier valid and the second identifier enable are both true, for example, the first identifier valid & the second identifier enable = 1, the interface sampling data is valid data; otherwise, when the first identifier valid or the second identifier enable is not true, for example, the first identifier valid & the second identifier enable = 0, the interface sampling data is invalid data, which will mislead the verification results.

[0082] It should be understood that the embodiments of the present disclosure are only Figure 2 As an example, in actual applications, there is no limit on the number of request channels in the verification model.

[0083] In one possible implementation, a model to be verified can be verified based on a target reference model comprising a first queue and a second queue to obtain a verification result. For example, the model to be verified can be sampled via a sampling interface, and the interface sampling data of the model to be verified can be stored in the second queue. In response to the model to be verified completing an arbitration operation and outputting a first result, a second result can be generated based on the first queue and the second queue of the target reference model. The first result can then be compared with the second result to obtain a verification result.

[0084] For example, the sampling interface can be a software interface pre-written in program code, used to sample the model to be verified and store the interface sampling data of the model to be verified in the second queue. The sampling interface can use the valid_enable handshake protocol and simultaneously create an N-bit data field corresponding to the N-bit data data[0:N-1]. The first flag, Valid, is generated by the logic that the first flag, Valid, is valid if the request signal of any of the N request channels is valid. The second flag, Enable, is generated by the logic that the control terminal, arb_en, is enabled, and the second flag, Enable, is valid.

[0085] In response to the model to be verified completing the arbitration operation, a first result is output, for example Figure 2 The output interface arb_out of the model to be verified outputs the selected request channel number. Since the second queue of the target reference model stores the interface sampling data of the model to be verified and the first queue stores the arbitration order indicating the priority, the second result can be generated according to the first queue and the second queue of the target reference model.

[0086] In a possible implementation, in step S12, in response to the model to be verified completing the arbitration operation and outputting the first result, the target reference model may be called to generate a second result according to the first queue and the second queue of the target reference model.

[0087] For example, in response to the model to be verified completing the arbitration operation and outputting the first result, the target reference model can be called, and when the first identifier in the second queue is the first identifier value and the second identifier is the second identifier value, the second result is obtained according to the first queue and the second queue of the target reference model, wherein the first identifier value indicates that the request signal of at least one request channel is valid, and the second identifier value indicates that the arbitration of the model to be verified is successful.

[0088] In the example, the first identifier valid is an identifier that any request channel is valid. If the first identifier valid=1, that is, the first identifier valid is true, it means that among the request signals of the N request channels of the model to be verified, at least one request channel has received the request signal; if the first identifier valid=0, that is, the first identifier valid is false, it means that all the request channels of the model to be verified have not received the request signal.

[0089] The second flag enable is an identifier indicating that the arbitration of the model to be verified is successful. If the second flag enable=1, that is, the second flag enable is true, it means that the model to be verified will perform the arbitration operation; if the second flag enable=0, that is, the second flag enable is false, it means that the model to be verified will not perform the arbitration operation.

[0090] If either the first identifier valid or the second identifier enable is false, it means that the interface sampling data of the model to be verified stored in the second queue is invalid, and the chip verification system can output an error and restart the verification process; if the first identifier valid is true and the second identifier enable is also true, it means that the interface sampling data of the model to be verified stored in the second queue is valid, and a second result can be generated based on the first queue and the second queue of the target reference model.

[0091] Setting the first identifier and the second identifier is helpful to improve the accuracy and effectiveness of the verification method.

[0092] In one possible implementation, a second result is obtained based on the first and second queues of the target reference model, including: determining whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the first queue; if the request signal corresponding to the request channel number in the second queue is not empty, taking the request signal corresponding to the request channel number as the second result, and arranging the request channel number stored at the head of the first queue to the end of the first queue as the first queue corresponding to the next round of arbitration operations of the target reference model. If the request signal corresponding to the request channel number in the second queue is empty, arranging the request channel number stored at the head of the first queue to the end of the first queue to obtain an updated first queue; and continuing to determine whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the updated first queue, until the second result of the target reference model is obtained.

[0093] In this way, the target reference model can wait for the arbitration behavior of the model to be verified in real time. Whenever the model to be verified completes an arbitration operation, it obtains the interface sampling data corresponding to the current arbitration operation and stores it in the second queue of the target reference model.

[0094] For each round of arbitration operation of the target reference model, the request channel number stored in the head of the first queue of the target reference model may be first obtained to determine whether the request channel indicated by the request channel number has a request signal.

[0095] If the request channel is not empty, it means that the request channel has received a request signal in the current round. The request signal received at the request channel can be used as the request signal after this round of arbitration. At the same time, the request channel number at the head of the first queue is dequeued, and the request channel numbers originally ranked second and later are moved forward in turn, and the request channel number corresponding to the request channel is placed at the end of the first queue to obtain the updated first queue. The updated first queue is used as the first queue corresponding to the next round of arbitration operation of the target reference model.

[0096] If the request channel is empty, it means that the request channel has not received a request signal in the current round and is invalid. Then the request channel number at the head of the first queue is dequeued, and the request channel numbers originally ranked second and later are moved forward in turn, and the request channel number corresponding to the request channel is placed at the end of the first queue to obtain the updated first queue.

[0097] Then, the request channel number stored in the head of the updated first queue can be checked in the same way to determine whether there is a request signal in the request channel indicated by the request channel number, until it is determined that the request signal corresponding to the request channel number in the second queue is not empty based on the request channel number stored at the head of the updated first queue. The request signal received at the request channel can be used as the request signal after this round of arbitration to obtain the second result of the target reference model of this round.

[0098] For example, suppose the model to be verified is Figure 2 The register transfer level model shown has four request channels and can simulate the behavior of the polling arbiter in terms of timing through the first queue arb_4master_rr_q[0:3] with a depth of 4 in the target reference model. Among them, arb_4master_rr_q[0] represents the head of the first queue arb_4master_rr_q[0:3], and arb_4master_rr_q[3] represents the tail of the first queue arb_4master_rr_q[0:3].

[0099] At the beginning of the simulation of the target reference model, a total of four request channel numbers 0 to 3 can be sent to the first queue arb_4master_rr_q[0:3]= [3,2,1,0] in sequence, where request channel number 0 is used to indicate request channel pipe0, and arb_4master_rr_q[0]=0 indicates that request channel pipe0 has the highest priority; request channel number 1 is used to indicate request channel pipe1, and arb_4master_rr_q[1]=1 indicates that request channel pipe1 has the second highest priority; request channel number 2 is used to indicate request channel pipe2, and arb_4master_rr_q[2]=2 indicates that request channel pipe2 has the third priority; request channel number 3 is used to indicate request channel pipe3, and arb_4master_rr_q[3]=3 indicates that request channel pipe3 has the lowest priority.

[0100] For the first round of arbitration operation of the target reference model, the request channel number 0 stored in the first queue arb_4master_rr_q[0] of the target reference model can be obtained to determine whether the request channel pipe0 indicated by the request channel number 0 has a request signal.

[0101] For example, if the request channel pipe0 is not empty, it means that the request channel pipe0 has received a request signal. The request signal received at the request channel pipe0 can be used as the request signal after this round of arbitration. At the same time, the request channel number 0 corresponding to the request channel pipe0 is placed at the end of the first queue arb_4master_rr_q[0:3] to obtain the updated first queue arb_4master_rr_q[0:3], and the updated first queue arb_4master_rr_q[0:3] is used as the first queue corresponding to the second round of arbitration operation of the target reference model, that is: the first queue arb_4master_rr_q[0:3]= [0,3,2,1].

[0102] For another example, if the request channel pipe0 is empty, it means that the request channel pipe0 has not received the request signal and is invalid. Then the request channel number 0 corresponding to the request channel pipe0 is placed at the end of the first queue arb_4master_rr_q[0:3], and the updated first queue arb_4master_rr_q[0:3]= [0,3,2,1] is obtained. Then, the same method can be used to check the request channel number 1 stored in the first queue arb_4master_rr_q[0] in the updated first queue arb_4master_rr_q[0:3]= [0,3,2,1] to determine whether the request channel pipe1 indicated by the request channel number 1 has a request signal. If the request channel pipe1 is not empty, it means that the request channel pipe1 has received the request signal. The request signal received at the request channel pipe1 can be used as the request signal after the first round of arbitration. At the same time, the request channel number 1 corresponding to the request channel pipe1 is placed at the end of the first queue arb_4master_rr_q[0:3] to obtain the updated first queue arb_4master_rr_q[0:3], and the updated first queue arb_4master_rr_q[0:3] is used as the first queue corresponding to the second round of arbitration operation of the target reference model, that is: the first queue arb_4master_rr_q[0:3]= [1,0,3,2].

[0103] Similarly, in each round of arbitration, the first queue arb_4master_rr_q[0:3] can be checked according to the above method until the request signal at the request channel corresponding to the request channel number stored at the first arb_4master_rr_q[0] in the updated first queue arb_4master_rr_q[0:3] is not empty. The request signal received at this request channel can be used as the request signal after arbitration for this round, thereby obtaining the second result of the target reference model for this round. Because arbitration has occurred in the model to be verified, a request channel number can be found in the first queue arb_4master_rr_q[0:3].

[0104] A verification result is obtained by performing a real-time comparison at the transmission level between the first result output by the arbitration of the model to be verified and the second result output by the arbitration of the target reference model. For example, the first result output by the arbitration of the model to be verified and the second result output by the arbitration of the target reference model can be compared round by round to determine if they are identical. If they are not identical, an error message is output and verification is restarted. If the first result output by the arbitration of the model to be verified and the second result output by the arbitration of the target reference model are identical in each round, the verification result indicates that verification has passed. It should be understood that the specific comparison method is diverse and is not specifically limited in the embodiments of the present disclosure.

[0105] By setting the first queue and the second queue, a complex timing model can be avoided, and a target reference model of the polling arbiter can be developed through indirect timing synchronization, thereby fully verifying the model to be verified in the chip verification system.

[0106] In summary, the verification method of the embodiment of the present disclosure sets a first queue and a second queue in the target reference model, the second queue is used to store the interface sampling data of the model to be verified, and the first queue is used to simulate the arbitration order of the polling arbitrator. According to the first queue and the second queue, it can be combined with the timing of the model to be verified to achieve full verification of the model to be verified, avoiding complex timing-level modeling (the development difficulty of the target reference model is much lower than that of the timing-level model). The target reference model does not need to be time-aligned with the model to be verified, but only relies on the behavior of the model to be verified. The arbitration function can be fully verified with the target reference model, which greatly reduces the complexity and investment cost of verification.

[0107] It is understood that the above-mentioned various method embodiments mentioned in this disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, this disclosure will not go into details. It is understood by those skilled in the art that in the above-mentioned methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0108] In addition, the present disclosure also provides a verification device, an electronic device, a computer-readable storage medium, and a program, all of which can be used to implement any verification method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method section and will not be repeated here.

[0109] Figure 3 A block diagram of a verification device according to an embodiment of the present disclosure is shown as follows: Figure 3 As shown, the verification device may include:

[0110] The first module 31 is configured to perform an arbitration operation on at least one request signal using the model to be verified, and output a first result;

[0111] The second module 32 is configured to call the target reference model, use the order of the request channel numbers in the first queue of the target reference model as the polling order, simulate the arbitration behavior of the model to be verified on at least one request signal through queue polling, and obtain a second result;

[0112] The comparison module 33 is used to compare the first result with the second result to determine a verification result.

[0113] In one possible implementation, the verification device also includes a construction module for constructing a target reference model, including: describing the behavior of the polling arbitrator in software through a hardware description language to obtain an initial reference model; setting a first queue and a second queue for the initial reference model to obtain a target reference model, wherein the second queue is used to store interface sampling data of the model to be verified, and the first queue is used to store the request channel number of the model to be verified.

[0114] In one possible implementation, the device also includes a sampling interface construction module, which is used to: obtain specification information of the model to be verified, the specification information is used to indicate the maximum number of request signals that can be arbitrated by the model to be verified each time; based on the specification information, construct a sampling interface for the model to be verified in the chip verification system, wherein the sampling interface is used to sample the model to be verified, and the sampled interface sampling data of the model to be verified is stored in the second queue of the target reference model.

[0115] In one possible implementation, the interface sampling data includes N-bit data, a first identifier, and a second identifier. The N-bit data is used to indicate the validity of the request signals of the N request channels of the model to be verified. The first identifier is used to indicate whether there is a valid request signal of at least one request channel. The second identifier is used to indicate whether the arbitration of the model to be verified is successful. N is an integer greater than 1.

[0116] In one possible implementation, the second module 32 is used to: output a first result in response to the model to be verified completing the arbitration operation, and obtain a second result according to the first queue and the second queue of the target reference model when the first identifier in the second queue is the first identifier value and the second identifier is the second identifier value, wherein the first identifier value indicates that the request signal of at least one request channel is valid, and the second identifier value indicates that the arbitration of the model to be verified is successful.

[0117] In one possible implementation, a second result is obtained based on the first queue and the second queue of the target reference model, including: judging whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the first queue; if the request signal corresponding to the request channel number in the second queue is not empty, taking the request signal corresponding to the request channel number as the second result, and arranging the request channel number stored at the head of the first queue to the end of the first queue as the first queue corresponding to the next round of arbitration operation of the target reference model.

[0118] In one possible implementation, the second module 32 is also used to: when the request signal corresponding to the request channel number in the second queue is empty, arrange the request channel number stored at the head of the first queue to the end of the first queue to obtain an updated first queue; continue to judge whether the request signal corresponding to the request channel number in the second queue is empty based on the request channel number stored at the head of the updated first queue, until the second result of the target reference model is obtained.

[0119] In one possible implementation, a first queue and a second queue are set for an initial reference model to obtain a target reference model, including: obtaining specification information of the model to be verified, the specification information being used to indicate the maximum number of request signals that can be arbitrated by the model to be verified each time; and according to the specification information, setting a first queue and a second queue for the initial reference model to obtain a target reference model, wherein the depth of the first queue and the second queue is determined by the specification information.

[0120] This method has a specific technical connection with the internal structure of the computer system, and can solve the technical problem of how to improve the hardware computing efficiency or execution effect (including reducing the amount of data storage, reducing the amount of data transmission, increasing the hardware processing speed, etc.), thereby obtaining the technical effect of improving the internal performance of the computer system in accordance with the laws of nature.

[0121] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0122] The present disclosure also provides a computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0123] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0124] An embodiment of the present disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0125] The electronic device may be provided as a terminal, a server, or other forms of devices.

[0126] Figure 4FIG1 shows a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 can be provided as a server or a terminal device. Figure 4 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above-described method.

[0127] The electronic device 1900 may further include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), Apple's graphical user interface operating system (Mac OS X TM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open-source Unix-like operating system (FreeBSD TM ) or similar.

[0128] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0129] The present disclosure may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0130] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, (but not limited to) an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure within a groove on which instructions are stored, and any suitable combination thereof. As used herein, a computer-readable storage medium is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse passing through a fiber optic cable), or an electrical signal transmitted through an electrical wire.

[0131] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0132] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, the state information of the computer-readable program instructions is used to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), so that the electronic circuit can execute the computer-readable program instructions, thereby implementing various aspects of the present disclosure.

[0133] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0134] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0135] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0136] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0137] The computer program product may be implemented in hardware, software, or a combination thereof. In one embodiment, the computer program product is implemented as a computer storage medium. In another embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0138] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0139] Those skilled in the art will understand that in the above-mentioned method of the specific implementation method, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0140] If the technical solution of this application involves personal information, the product that applies the technical solution of this application has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing personal information. If the technical solution of this application involves sensitive personal information, the product that applies the technical solution of this application has obtained the individual's separate consent before processing sensitive personal information, and at the same time meets the "explicit consent" requirement. For example, on personal information collection devices such as cameras, a clear and prominent sign is set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that they agree to the collection of their personal information; or on the personal information processing device, when the personal information processing rules are notified by obvious signs / information, the individual's authorization is obtained through pop-up information or by asking the individual to upload their personal information; among which, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0141] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A verification method, characterized in that: The method comprises: Performing an arbitration operation on at least one request signal using the model to be verified, and outputting a first result; Calling the target reference model, using the arrangement order of the request channel numbers in the first queue of the target reference model as the polling order, simulating the arbitration behavior of the model to be verified on the at least one request signal through queue polling, and obtaining a second result; Compare the first result with the second result to determine a verification result.

2. The method according to claim 1, characterized in that The method for constructing the target reference model includes: Describe the behavior of the polling arbiter in software using a hardware description language to obtain an initial reference model; The first queue and the second queue are set for the initial reference model to obtain the target reference model, wherein the second queue is used to store the interface sampling data of the model to be verified, and the first queue is used to store the request channel number of the model to be verified.

3. The method according to claim 2, characterized in that The method further comprises: Acquiring specification information of the model to be verified, where the specification information is used to indicate a maximum number of request signals that can be arbitrated by the model to be verified each time; According to the specification information, a sampling interface is constructed for the model to be verified in a chip verification system, wherein the sampling interface is used to sample the model to be verified, and the interface sampling data of the model to be verified is stored in the second queue of the target reference model.

4. The method according to claim 2 or 3, characterized in that The interface sampling data includes N-bit data, a first identifier and a second identifier, the N-bit data is used to indicate the validity of the request signals of the N request channels of the model to be verified, the first identifier is used to indicate whether the request signal of at least one request channel is valid, and the second identifier is used to indicate whether the arbitration of the model to be verified is successful, and N is an integer greater than 1.

5. The method according to claim 2, characterized in that The calling of the target reference model, taking the arrangement order of the request channel numbers in the first queue of the target reference model as the polling order, simulating the arbitration behavior of the model to be verified on the at least one request signal through queue polling, and obtaining a second result, including: In response to the model to be verified completing the arbitration operation and outputting the first result, when the first identifier in the second queue is the first identifier value and the second identifier is the second identifier value, the second result is obtained according to the first queue and the second queue of the target reference model, wherein the first identifier value indicates that the request signal of at least one request channel is valid, and the second identifier value indicates that the arbitration of the model to be verified is successful.

6. The method according to claim 5, characterized in that Obtaining the second result according to the first queue and the second queue of the target reference model includes: According to the request channel number stored at the head of the first queue, determining whether the request signal corresponding to the request channel number in the second queue is empty; When the request signal corresponding to the request channel number in the second queue is not empty, the request signal corresponding to the request channel number is taken as the second result, and the request channel number stored at the head of the first queue is arranged to the end of the first queue as the first queue corresponding to the next round of arbitration operation of the target reference model.

7. The method according to claim 6, characterized in that The method further comprises: When the request signal corresponding to the request channel number in the second queue is empty, arranging the request channel number stored at the head of the first queue to the tail of the first queue to obtain an updated first queue; Continue to determine whether the request signal corresponding to the request channel number in the second queue is empty based on the updated request channel number stored at the head of the first queue, until the second result of the target reference model is obtained.

8. The method according to claim 2, characterized in that Setting the first queue and the second queue for the initial reference model to obtain the target reference model includes: Acquiring specification information of the model to be verified, where the specification information is used to indicate a maximum number of request signals that can be arbitrated by the model to be verified each time; According to the specification information, the first queue and the second queue are set for the initial reference model to obtain the target reference model, and the depths of the first queue and the second queue are determined by the specification information.

9. A verification device, characterized in that: include: A first module is configured to perform an arbitration operation on at least one request signal using a model to be verified, and output a first result; A second module is configured to call a target reference model, use the order of the request channel numbers in the first queue of the target reference model as a polling order, simulate the arbitration behavior of the model to be verified on the at least one request signal through queue polling, and obtain a second result; A comparison module is used to compare the first result with the second result to determine a verification result.

10. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 8 is implemented.

12. A computer program product comprising computer program instructions, characterized in that When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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