FPGA-based multi-grayscale jitter image display device and method for cholesteric LCD displays

Abstract

This invention discloses an FPGA-based cholesteric LCD display device and method for multi-grayscale dithering image display, comprising: an image update module for receiving RGB image data and outputting the RGB image data to an image dithering processing module; an image dithering processing module for performing dithering processing on the received RGB image data to generate image dithering data, and generating a write address to store the image dithering data in a BRAM; an image grayscale processing module for generating a read address based on a field synchronization signal and a line synchronization signal, reading the image dithering data from the BRAM, dividing and encoding the image dithering data into grayscale levels based on a target grayscale number n, generating n-level grayscale data, and outputting it to an image display module; and an image display module for generating control signals for the cholesteric LCD display based on the received n-level grayscale data. The device and method of this application effectively reduce image refresh time and lower the hardware implementation difficulty while ensuring delicate image display.

Description

Technical Field

[0001] This invention relates to the field of cholesteric LCD display technology, and more particularly to a cholesteric LCD display multi-grayscale dithering image display device and method based on FPGA. Background Technology

[0002] Cholesteric liquid crystals (ChLCs) are widely used in electronic paper display technology due to their bistable properties. Common states include: H-state (vertically aligned state), where liquid crystal molecules are aligned perpendicular to the substrate and exhibit transparency; P-state (planar state), where liquid crystal molecules are aligned parallel to the substrate, forming a helical structure and exhibiting selective reflectivity; and FC-state (focal conic state), a transitional state between the H and P states.

[0003] Cholesteric LCD displays achieve different grayscale levels by adjusting the arrangement of liquid crystal molecules through voltage changes, thereby altering the brightness of transmitted light. In other words, different applied voltages result in different transmittances in the LCD display, thus achieving grayscale display. In existing technologies, due to limitations in the refresh architecture, the next grayscale voltage output cannot begin until the grayscale data corresponding to the previous voltage level has been scanned. When displaying more detailed images requiring multi-grayscale driving, such as 16 or more grayscale levels, the refresh time for a single image increases, and the hardware requirements become more stringent, necessitating finer voltage divisions within a certain voltage range. Summary of the Invention

[0004] To address the technical problems existing in the background art, the present invention proposes a cholesteric phase LCD display multi-grayscale dithering image display device and method based on FPGA.

[0005] The present invention proposes an FPGA-based cholesteric phase LCD display device for multi-grayscale dithering image display, comprising:

[0006] The image update module is used to receive RGB image data and output the RGB image data to the image jitter processing module.

[0007] The image jitter processing module is used to jitter the received RGB image data, generate image jitter data, and generate a write address to store the image jitter data into BRAM.

[0008] The image grayscale processing module is used to generate a read address based on the field synchronization signal and the line synchronization signal, read the image jitter data from the BRAM, perform grayscale division and encoding on the image jitter data based on the target grayscale number n, generate n-level grayscale data and output it to the image display module;

[0009] The image display module is used to generate control signals for the cholesteric phase LCD display screen based on the received n-level grayscale data.

[0010] Preferably, in the image jitter processing module, the step of jitter processing the received RGB image data to generate image jitter data specifically includes:

[0011] Select the corresponding grayscale level set for the RGB image data;

[0012] Iterate through each pixel of the RGB image data, quantize the original pixel value of each pixel to the closest gray value in the gray level set, and obtain the corresponding quantized pixel value.

[0013] The error between the original pixel value and the quantized pixel value is calculated, and the error is distributed among the neighboring pixels of the current pixel.

[0014] Repeat the above steps until all pixels have been traversed to obtain the image jitter data corresponding to the RGB image data.

[0015] Preferably, in the image jitter processing module, distributing the error to the neighboring pixels of the current pixel specifically includes: using the current pixel as a reference, distributing the error to the buffer registers of the right neighbor, lower left, lower right, and lower right pixels of the current pixel according to a preset weight.

[0016] Preferably, it further includes: a timing control module, used to generate image display timing control signals to control the coordinated operation of each module, wherein the timing control signals include field synchronization signals and line synchronization signals; the timing control module is also used to generate screen initialization refresh control signals and screen image refresh control signals;

[0017] The PWM signal generation module is used to generate a PWM signal based on the field synchronization signal to control the power supply circuit of the cholesteric LCD display to output the voltage corresponding to each gray level.

[0018] Preferably, the screen image refresh control signal generated by the timing control module is used to control the image grayscale processing module to read the image jitter data and process it into grayscale data corresponding to grayscale 1 to grayscale n-1 in sequence, and transmit the grayscale data to the image display module to generate the corresponding screen output control signal. At the same time, the screen image refresh control signal controls the PWM signal generation module to generate voltage control signals corresponding to grayscale 1 to grayscale n-1 in sequence, where n is the target grayscale number.

[0019] Preferably, when the target gray level number n is specifically 8, the gray level set is [0,36,73,109,146,182,219,255].

[0020] The present invention proposes a method for displaying multi-grayscale jitter images on a cholesteric phase LCD display screen based on FPGA, applicable to any of the aforementioned FPGA-based cholesteric phase LCD display screen multi-grayscale jitter image display devices. The method includes the following steps:

[0021] S1. The timing control module generates screen image refresh control signals, field synchronization signals and line synchronization signals. The image grayscale processing module generates a read address based on the field synchronization signal and the line synchronization signal, reads the image jitter data from the BRAM, divides and encodes it based on the target grayscale number n, generates grayscale data corresponding to grayscale 1 to grayscale n-1 and transmits it to the image display module.

[0022] S2. The image display module generates a control signal for the cholesteric phase LCD display screen based on the received grayscale data. When the control signal is high, the corresponding pixel is given the current grayscale voltage. When the control signal is low, the corresponding pixel remains in a total reflection state.

[0023] S3, the PWM signal generation module generates a PWM signal based on the field synchronization signal. Simultaneously with the image display module outputting a control signal, it sequentially generates voltage control signals corresponding to grayscale levels 1 to n-1 to control the power supply circuit to output the corresponding voltage. This allows the cholesteric phase LCD display screen, now in the P-state, to form the corresponding reflectivity through the voltage control signals from grayscale levels 1 to n-1, thus achieving n-level grayscale display.

[0024] Preferably, the method further includes the following steps before step S1:

[0025] S01. Generate screen initialization refresh control signal through timing control module;

[0026] S02. The screen initialization refresh control signal controls the image display module to sequentially generate a screen output positive voltage control signal, a screen output negative voltage control signal, and a screen output ground control signal. At the same time, the screen initialization refresh control signal controls the PWM signal generation module to sequentially generate a maximum positive voltage control signal and a maximum negative voltage control signal, so that the cholesteric LCD display screen is first in the H state and then outputs the ground control signal. At this time, the cholesteric LCD display screen changes from the H state to the P state.

[0027] Preferably, the method further includes the following steps before step S02:

[0028] The image update module receives externally transmitted RGB image data through its SPI interface and transmits the RGB image data to the image jitter processing module.

[0029] The RGB image data is jittered by the image jitter processing module to generate jittered image data, which is then stored in BRAM.

[0030] Preferably, in step S02, the process of the cholesteric LCD display screen changing from the H state to the P state is as follows: after the PWM signal generation module outputs the maximum positive driving voltage and the minimum negative driving voltage in sequence to drive the cholesteric LCD display screen into the H state, the driving voltage is then reduced to 0 so that all pixels in the cholesteric LCD enter the P state.

[0031] This invention presents an FPGA-based multi-grayscale dithering image display device and method for a cholesteric LCD display. Using an FPGA as the control platform, the image update module receives RGB image data via an SPI interface and transmits it to the image dithering processing module. The image dithering processing module employs an error diffusion algorithm to dither the data, generating image dithering data and storing it in the BRAM. A timing control module generates synchronization and control signals to coordinate the image grayscale processing module to read data from the BRAM and encode it into grayscale data. The image display module then generates display control signals, while a PWM signal generation module controls the corresponding grayscale voltage output. The display process utilizes the liquid crystal's transitions between H, P, and FC states to achieve multi-grayscale display. This invention ensures detailed image display while effectively reducing refresh time and lowering hardware implementation difficulty, making it suitable for multi-grayscale image display scenarios on cholesteric LCD displays. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the device architecture of the FPGA-based cholesteric LCD multi-grayscale dithering image display device proposed in this invention;

[0033] Figure 2 This is a schematic diagram of the grayscale voltage output waveform of the PWM signal generation module of the cholesteric phase LCD multi-grayscale dithering image display device based on FPGA proposed in this invention;

[0034] Figure 3 This is a driving timing diagram of one embodiment of the cholesteric phase LCD multi-grayscale dithering image display device based on FPGA proposed in this invention;

[0035] Figure 4 This is a comparison of the display effects of one embodiment of the cholesteric phase LCD multi-grayscale dithering image display device based on FPGA proposed in this invention;

[0036] Figure 5 This is a flowchart illustrating the process of the FPGA-based cholesteric LCD display method for displaying multi-grayscale dithered images. Detailed Implementation

[0037] Reference Figure 1-4The present invention proposes an FPGA-based cholesteric LCD display device for multi-grayscale dithering images, comprising:

[0038] The image update module is used to receive RGB image data and output the RGB image data to the image jitter processing module.

[0039] The image jitter processing module is used to jitter the received RGB image data, generate image jitter data, and generate a write address to store the image jitter data into BRAM.

[0040] The image grayscale processing module is used to generate a read address based on the field synchronization signal and the line synchronization signal, read the image jitter data from the BRAM, divide and encode the image jitter data into grayscale based on the target grayscale number n, generate n-level grayscale data and output it to the image display module.

[0041] The image display module is used to generate control signals for the cholesteric phase LCD display screen based on the received n-level grayscale data.

[0042] In this embodiment, the image jitter processing module performs jitter processing on the received RGB image data to generate image jitter data, specifically including:

[0043] Select the corresponding grayscale level set for the RGB image data;

[0044] Iterate through each pixel of the RGB image data, quantize the original pixel value of each pixel to the closest gray value in the gray level set, and obtain the corresponding quantized pixel value.

[0045] Calculate the error between the original pixel value and the quantized pixel value, and distribute the error among the neighboring pixels of the current pixel;

[0046] Repeat the above steps until all pixels have been traversed to obtain the image jitter data corresponding to the RGB image data.

[0047] In this embodiment, the image jitter processing module distributes the error to the neighboring pixels of the current pixel. Specifically, it includes distributing the error to the buffer registers of the right neighbor, lower left, lower right and right pixels of the current pixel according to a preset weight, based on the current pixel.

[0048] Specifically, image dithering involves introducing noise into an image to distribute color errors to nearby pixels, thus enabling the visual simulation of more colors. Image dithering can produce effects with different grayscale levels. Similarly, in cholesteric LCD displays, the transmittance varies depending on the voltage applied after the liquid crystal enters the P-state, resulting in multi-grayscale display. We can combine the grayscale levels of the cholesteric LCD display to perform multi-grayscale dithering, thereby displaying more detailed images on the cholesteric LCD screen.

[0049] In this embodiment, it further includes: a timing control module, used to generate image display timing control signals to control the coordinated operation of each module, wherein the timing control signals include field synchronization signals and line synchronization signals; the timing control module is also used to generate screen initialization refresh control signals and screen image refresh control signals;

[0050] The PWM signal generation module is used to generate PWM signals based on the field synchronization signal to control the power supply circuit of the cholesteric LCD display to output the voltage corresponding to each gray level.

[0051] Specifically, the screen image refresh control signal generated by the timing control module is used to control the image grayscale processing module to read the image jitter data and process it into grayscale data corresponding to grayscale 1 to grayscale n-1 in sequence, and transmit the grayscale data to the image display module to generate the corresponding screen output control signal. At the same time, the screen image refresh control signal controls the PWM signal generation module to generate the voltage control signal corresponding to grayscale 1 to grayscale n-1 in sequence, where n is the target grayscale number.

[0052] Specifically, during the image update process, the image update module receives RGB image data through the SPI interface, parses it according to the SPI protocol, and outputs it to the image jitter processing module. The image jitter processing module performs image jitter processing on the RGB image data according to the image jitter principle, generates image jitter data, and generates a write address to store the image jitter data in BRAM for subsequent image display.

[0053] Specifically, during image display, the timing control module first generates a screen initialization refresh control signal, which controls the image display module to sequentially generate a positive screen output voltage control signal, a negative screen output voltage control signal, and a screen output ground control signal; simultaneously, it controls the PWM signal generation module to sequentially generate a maximum positive voltage control signal and a maximum negative voltage control signal. Then, the timing control module generates a screen image refresh control signal, which controls the image grayscale processing module to read the jittery image data and sequentially process it into grayscale 1, grayscale 2, ..., grayscale n-1, transmitting the grayscale data to the image display module to generate the corresponding screen output control signal; simultaneously, it controls the PWM signal generation module to sequentially generate grayscale 1 voltage, grayscale 2 voltage, and grayscale n-1 voltage control signals. The image display timing is as follows: first, the maximum voltage is output, putting the liquid crystal in the H state; then, the voltage is rapidly reduced, and the H-state liquid crystal enters the P state. After entering the P state, different voltages are output to obtain different reflectivities; that is, different voltages are output after entering the P state to complete multi-grayscale display. Because the liquid crystal is totally reflective after entering the P state, it can be considered as one grayscale, so n-1 grayscale voltages are needed to display n grayscale levels.

[0054] Example 1:

[0055] In this embodiment, when the target grayscale number n is specifically 8, the grayscale level set is [0,36,73,109,146,182,219,255]. That is, the values ​​in the grayscale set output by the image dithering module. The driving timing of the output result of an image through the image dithering module is as follows: Figure 3 As shown, for a cholesteric LCD display, if the control signal is high, the pixel applies the current grayscale voltage; if the control signal is low, the pixel does not apply the current grayscale voltage and continues to maintain total reflection. Figure 4 As shown, it can be seen that 8-grayscale image dithering display is more delicate than 8-grayscale display. What might have previously required 16 grayscale levels to display the effect of 8-grayscale image dithering: that is, instead of scanning 15 times and outputting 15 grayscale voltages to complete one image refresh, it can now be done in 7 scans and outputting 8 grayscale voltages, saving almost half the refresh time; that is, instead of needing the hardware to divide the effective voltage into 15 grayscale voltage levels, now only 7 levels are needed, also reducing the hardware implementation difficulty.

[0056] Reference Figure 1-5 The present invention proposes a method for displaying multi-grayscale jitter images on a cholesteric phase LCD display screen based on FPGA, applicable to any of the above-mentioned cholesteric phase LCD display screen multi-grayscale jitter image display devices. The method includes the following steps:

[0057] S1. The timing control module generates screen image refresh control signals, field synchronization signals and line synchronization signals. The image grayscale processing module generates a read address based on the field synchronization signal and the line synchronization signal, reads the image jitter data from the BRAM, divides and encodes it based on the target grayscale number n, generates grayscale data corresponding to grayscale 1 to grayscale n-1 and transmits it to the image display module.

[0058] S2. The image display module generates a control signal for the cholesteric phase LCD display screen based on the received grayscale data. When the control signal is high, the corresponding pixel is given the current grayscale voltage. When the control signal is low, the corresponding pixel remains in a total reflection state.

[0059] S3, the PWM signal generation module generates a PWM signal based on the field synchronization signal. While the image display module outputs the control signal, it sequentially generates voltage control signals corresponding to grayscale 1 to grayscale n-1 to control the power supply circuit to output the corresponding voltage. This allows the cholesteric phase LCD display screen, which has entered the P state, to form the corresponding reflectivity through the voltage control signals corresponding to grayscale 1 to grayscale n-1, thereby achieving n-level grayscale display.

[0060] In this embodiment, the method further includes the following step before step S1:

[0061] S01. Generate screen initialization refresh control signal through timing control module;

[0062] S02. The screen initialization refresh control signal controls the image display module to sequentially generate a screen output positive voltage control signal, a screen output negative voltage control signal, and a screen output ground control signal. At the same time, the screen initialization refresh control signal controls the PWM signal generation module to sequentially generate a maximum positive voltage control signal and a maximum negative voltage control signal, so that the cholesteric LCD display screen is first in the H state and then outputs the ground control signal. At this time, the cholesteric LCD display screen changes from the H state to the P state.

[0063] Specifically, the procedure before step S02 also includes:

[0064] The image update module receives externally sent RGB image data through its SPI interface and transmits the RGB image data to the image jitter processing module.

[0065] The RGB image data is jittered by the image jitter processing module to generate jittered image data, which is then stored in BRAM.

[0066] Specifically, in step S02, the process of the cholesteric LCD display screen changing from the H state to the P state is as follows: the maximum positive driving voltage and the minimum negative driving voltage are output sequentially by the PWM signal generation module to drive the cholesteric LCD display screen into the H state, and then the driving voltage is reduced to 0 so that all pixels in the cholesteric LCD enter the P state.

[0067] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A cholesteric LCD display device for multi-grayscale dithering image display based on FPGA, characterized in that, include: The image update module is used to receive RGB image data and output the RGB image data to the image jitter processing module. The image jitter processing module is used to jitter the received RGB image data, generate image jitter data, and generate a write address to store the image jitter data into BRAM. The image grayscale processing module is used to generate a read address based on the field synchronization signal and the line synchronization signal, read the image jitter data from the BRAM, perform grayscale division and encoding on the image jitter data based on the target grayscale number n, generate n-level grayscale data and output it to the image display module; The image display module is used to generate control signals for the cholesteric phase LCD display screen based on the received n-level grayscale data; The timing control module is used to generate image display timing control signals to control the coordinated operation of each module. The timing control signals include field synchronization signals and line synchronization signals. The timing control module is also used to generate screen initialization refresh control signals and screen image refresh control signals. The PWM signal generation module is used to generate a PWM signal based on the field synchronization signal to control the power supply circuit of the cholesteric LCD display to output the voltage corresponding to each gray level. The screen image refresh control signal generated by the timing control module is used to control the image grayscale processing module to read the image jitter data and process it into grayscale data corresponding to grayscale 1 to grayscale n-1 in sequence, and transmit the grayscale data to the image display module to generate the corresponding screen output control signal. At the same time, the screen image refresh control signal controls the PWM signal generation module to generate the voltage control signal corresponding to grayscale 1 to grayscale n-1 in sequence, where n is the target grayscale number.

2. The FPGA-based cholesteric LCD display multi-grayscale dithering image display device according to claim 1, characterized in that, In the image jitter processing module, the step of jitter processing the received RGB image data to generate image jitter data specifically includes: Select the corresponding grayscale level set for the RGB image data; Iterate through each pixel of the RGB image data, quantize the original pixel value of each pixel to the closest gray value in the gray level set, and obtain the corresponding quantized pixel value. The error between the original pixel value and the quantized pixel value is calculated, and the error is distributed among the neighboring pixels of the current pixel. Repeat the above steps until all pixels have been traversed to obtain the image jitter data corresponding to the RGB image data.

3. The FPGA-based cholesteric LCD multi-grayscale dithering image display device according to claim 2, characterized in that, In the image jitter processing module, distributing the error to the neighboring pixels of the current pixel specifically includes: using the current pixel as a reference, distributing the error to the buffer registers of the right neighbor, lower left, lower right, and lower right pixels of the current pixel according to a preset weight.

4. The FPGA-based cholesteric LCD multi-grayscale dithering image display device according to claim 2, characterized in that, When the target gray level number n is specifically 8, the gray level set is [0,36,73,109,146,182,219,255].

5. A method for displaying multi-grayscale dithered images on a cholesteric LCD display screen based on FPGA, characterized in that, The method, applied to the FPGA-based cholesteric LCD display multi-grayscale dithering image display device as described in any one of claims 1-4, comprises the following steps: S1. The timing control module generates screen image refresh control signals, field synchronization signals and line synchronization signals. The image grayscale processing module generates a read address based on the field synchronization signal and the line synchronization signal, reads the image jitter data from the BRAM, divides and encodes it based on the target grayscale number n, generates grayscale data corresponding to grayscale 1 to grayscale n-1 and transmits it to the image display module. S2. The image display module generates a control signal for the cholesteric phase LCD display screen based on the received grayscale data. When the control signal is high, the corresponding pixel is given the current grayscale voltage. When the control signal is low, the corresponding pixel remains in a total reflection state. S3, the PWM signal generation module generates a PWM signal based on the field synchronization signal. While the image display module outputs the control signal, it sequentially generates voltage control signals corresponding to grayscale 1 to grayscale n-1 to control the power supply circuit to output the corresponding voltage. This allows the cholesteric phase LCD display screen, which has entered the P state, to form the corresponding reflectivity through the voltage control signals corresponding to grayscale 1 to grayscale n-1, thereby achieving n-level grayscale display.

6. The method for displaying multi-grayscale dithered images on a cholesteric phase LCD display screen based on FPGA according to claim 5, characterized in that, The steps preceding step S1 also include: S01. Generate screen initialization refresh control signal through timing control module; S02. The screen initialization refresh control signal controls the image display module to sequentially generate a screen output positive voltage control signal, a screen output negative voltage control signal, and a screen output ground control signal. At the same time, the screen initialization refresh control signal controls the PWM signal generation module to sequentially generate a maximum positive voltage control signal and a maximum negative voltage control signal, so that the cholesteric LCD display screen is first in the H state and then outputs the ground control signal. At this time, the cholesteric LCD display screen changes from the H state to the P state.

7. The method for displaying multi-grayscale dithered images on a cholesteric phase LCD display screen based on FPGA according to claim 6, characterized in that, The steps preceding step S02 also include: The image update module receives externally transmitted RGB image data through its SPI interface and transmits the RGB image data to the image jitter processing module. The RGB image data is jittered by the image jitter processing module to generate jittered image data, which is then stored in BRAM.

8. The method for displaying multi-grayscale dithered images on a cholesteric phase LCD display screen based on FPGA according to claim 6, characterized in that, In step S02, the process of the cholesteric LCD display screen changing from H state to P state is as follows: the maximum positive driving voltage and the minimum negative driving voltage are output sequentially by the PWM signal generation module to drive the cholesteric LCD display screen into H state, and then the driving voltage is reduced to 0 so that all pixels in the cholesteric LCD enter P state.

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