Refresh control circuit and method thereof, display panel, and display device

Abstract

The application discloses a refresh control circuit and method thereof, a display panel and a display device, and relates to the technical field of display. The circuit comprises pixel units arranged in an array. A refresh control module comprises refresh control units corresponding to the pixel units. Each refresh control unit is electrically connected to a corresponding pixel unit. The refresh control module is configured to determine a pixel unit identification group to be refreshed according to current frame pixel refresh information of a to-be-displayed picture, and enable the refresh control units corresponding to the pixel units in the pixel unit identification group to perform pixel refresh operations. The application aims to realize free refresh control of a display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a refresh control circuit and method thereof, a display panel and a display device. BACKGROUND

[0002] With the continuous development of display technology, users have higher requirements for visual smooth experience and device power consumption control of display panels. Although high refresh rate display panels can significantly improve the smoothness of dynamic pictures, they inevitably bring higher power consumption burden.

[0003] The prior art adopts a free frame rate (FFR) scheme based on GOA (Gate Driver on Array) timing adjustment, which implements local low refresh rate in the static area of a picture to reduce power consumption. However, this scheme has great technical defects. On the one hand, due to the driving architecture of GOA, the control granularity can only reach the row level, and it is impossible to independently and finely control the refresh rate of different pixel regions in the same row (for example, the left side needs low refresh rate for static content, and the right side needs high refresh rate for dynamic content); on the other hand, due to the inherent characteristics of the GOA row-by-row scanning mechanism, the refresh rate adjustment must follow the row scanning direction, that is, the refresh rate of the previous row must be higher than that of the next row, which severely limits the flexibility of application scenarios.

[0004] Therefore, how to realize free refresh control of a display panel is a technical problem to be solved at present. SUMMARY

[0005] The main purpose of the present application is to provide a refresh control circuit and method thereof, a display panel and a display device, aiming to realize free refresh control of a display panel.

[0006] To achieve the above purpose, the present application provides a refresh control circuit, which comprises:

[0007] pixel units arranged in an array;

[0008] a refresh control module, the refresh control module comprising refresh control units corresponding to each of the pixel units, each of the refresh control units being electrically connected to the corresponding pixel unit, and the refresh control module being configured to determine a pixel unit identification group to be refreshed according to current frame pixel refresh information of a to-be-displayed picture, and enable the refresh control units corresponding to each of the pixel units in the pixel unit identification group to perform a pixel refresh operation.

[0009] In an embodiment, the refresh control unit comprises a refresh enabling subunit, a first data writing channel and a second data writing channel.

[0010] The control end of the refresh enabling subunit is electrically connected with the row scanning line, the data input end of the refresh enabling subunit is electrically connected with the data line, the data output end of the refresh enabling subunit is electrically connected with the data input end of the first data write channel and the data input end of the second data write channel respectively, and the data output end of the first data write channel and the data output end of the second data write channel are electrically connected with the corresponding pixel unit respectively, and the control end of the first data write channel and the control end of the second data write channel are electrically connected with the pixel polarity line respectively.

[0011] In an embodiment, when the target pixel unit is any one of the pixel units in the pixel unit identification group, the refresh control unit corresponding to the target pixel unit is configured to enable the refresh enabling subunit to charge the pixel data voltage provided by the data line to the target pixel unit through the first data write channel when the polarity potential of the pixel polarity line is the first potential and / or enable the refresh enabling subunit to charge the pixel data voltage provided by the data line to the target pixel unit through the second data write channel when the polarity potential of the pixel polarity line is the second potential in response to the valid scanning signal provided by the row scanning line.

[0012] When the target pixel unit is any one of the pixel units other than the pixel unit identification group, the refresh control unit corresponding to the target pixel unit is configured to trigger the first data write channel and the second data write channel to synchronously disconnect the communication of the refresh enabling subunit to the target pixel unit when the refresh enabling subunit accesses the pixel data voltage with the same polarity potential under the driving of the valid scanning signal, so that the target pixel unit maintains the historical data voltage written in the last frame of the current frame.

[0013] In an embodiment, the refresh enabling subunit comprises a first switch tube.

[0014] The gate end of the first switch tube constitutes the control end of the refresh enabling subunit and is electrically connected with the row scanning line, and the first passage end of the first switch tube constitutes the data input end of the refresh enabling subunit and is electrically connected with the data line.

[0015] The second passage end of the first switch tube constitutes the data output end of the refresh enabling subunit and is electrically connected with the data input end of the first data write channel and the data input end of the second data write channel respectively.

[0016] In an embodiment, the first data write channel comprises a second switch tube and a third switch tube.

[0017] The gate terminal of the second switch tube is electrically connected with the control terminal of the first data write channel and the pixel polarity line, and the first pass terminal of the second switch tube is electrically connected with the data input terminal of the first data write channel and the data output terminal of the refresh enable subunit.

[0018] The second pass terminal of the second switch tube is electrically connected with the first pass terminal of the third switch tube, the gate terminal of the third switch tube is electrically connected with the data line, and the second pass terminal of the third switch tube is electrically connected with the data output terminal of the first data write channel and the corresponding pixel unit.

[0019] In an embodiment, the second data write channel comprises a fourth switch tube and a fifth switch tube.

[0020] The gate terminal of the fourth switch tube is electrically connected with the control terminal of the second data write channel and the pixel polarity line, and the first pass terminal of the fourth switch tube is electrically connected with the data input terminal of the second data write channel and the data output terminal of the refresh enable subunit.

[0021] The second pass terminal of the fourth switch tube is electrically connected with the first pass terminal of the fifth switch tube, the gate terminal of the fifth switch tube is electrically connected with the data line, and the second pass terminal of the fifth switch tube is electrically connected with the data output terminal of the second data write channel and the corresponding pixel unit.

[0022] In an embodiment, the refresh control circuit further comprises a plurality of pull-down modules, the first terminal of each of the pull-down modules is electrically connected with the corresponding data line, and the second terminal of each of the pull-down modules is connected with a reference potential line.

[0023] In addition, to achieve the above-mentioned purpose, the present application also provides a refresh control method, which is applied to the refresh control circuit as described above, and the refresh control method comprises:

[0024] According to the current frame pixel refresh information of the to-be-displayed picture, the pixel unit identification group to be refreshed is determined, and the refresh control unit corresponding to each pixel unit in the pixel unit identification group is enabled to perform the pixel refresh operation.

[0025] In addition, to achieve the above-mentioned purpose, the present application also provides a display panel, which comprises a color film substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color film substrate, and the array substrate comprises the refresh control circuit as described above.

[0026] In addition, to achieve the above-mentioned purpose, the present application also provides a display device, which comprises the display panel as described above.

[0027] Or the memory, the processor and the charge driver stored on the memory and running on the processor, the processor executes the charge driver to realize the steps of the refresh control method as described above.

[0028] The present application realizes free refresh control at the pixel level by integrating the array-distributed pixel units and the refresh control module in the refresh control circuit of the display panel, and configuring each pixel unit with an independent refresh control unit in the refresh control module. Specifically, the refresh control module detects the current frame pixel refresh information of the to-be-displayed picture in real time, so as to directly locate the pixel unit identification group to be refreshed; then, the refresh control units corresponding to each pixel unit in the pixel unit identification group are enabled to independently execute the pixel refresh operation, thereby breaking through the limitation of the traditional GOA row-level control, allowing different pixel units in the same row to independently set the differentiated refresh rate according to the display content requirement, and completely eliminating the limitation of the traditional line-by-line scanning on the refresh rate adjustment direction, so that the display panel can realize accurate on-demand refresh with any pixel as the minimum unit, and realize the truly free and flexible refresh control of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0029] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the application.

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, those skilled in the art can obtain other drawings according to these drawings without any creative effort.

[0031] Figure 1 is a refresh direction diagram of the existing FFR scheme based on GOA timing adjustment;

[0032] Figure 2 is a structural block diagram of the first embodiment of the refresh control circuit of the present application;

[0033] Figure 3 is an embodiment diagram of the pixel unit identification group involved in the embodiment scheme of the present application;

[0034] Figure 4 is another embodiment diagram of the pixel unit identification group involved in the embodiment scheme of the present application;

[0035] Figure 5 is a circuit diagram of the refresh control circuit involved in the embodiment scheme of the present application;

[0036] Figure 6is a circuit and a signal waveform schematic diagram related to a positive polarity pixel unit in a high brush state according to an embodiment of the present application;

[0037] Figure 7 is a circuit and a signal waveform schematic diagram related to a positive polarity pixel unit in a high brush state according to an embodiment of the present application;

[0038] Figure 8 is a circuit and a signal waveform schematic diagram related to a positive polarity pixel unit in a high brush state according to an embodiment of the present application;

[0039] Figure 9 is a circuit and a signal waveform schematic diagram related to a positive polarity pixel unit in a high brush state according to an embodiment of the present application;

[0040] Figure 10 is a circuit and a signal waveform schematic diagram related to a positive polarity pixel unit in a high brush state according to an embodiment of the present application;

[0041] Figure 11 is a circuit and a signal waveform schematic diagram related to a positive polarity pixel unit in a high brush state according to an embodiment of the present application;

[0042] Figure 12 is a circuit and a signal waveform schematic diagram related to a positive polarity pixel unit in a high brush state according to an embodiment of the present application;

[0043] Figure 13 is a circuit and a signal waveform schematic diagram related to a positive polarity pixel unit in a high brush state according to an embodiment of the present application;

[0044] Figure 14 is a circuit schematic diagram of a pull-down module according to an embodiment of the present application;

[0045] Figure 15 is a timing diagram of the Nth pixel row in a low brush state according to an embodiment of the present application;

[0046] Figure 16 is a structure schematic diagram of a display device according to an embodiment of the present application.

[0047] Explanation of reference numerals:

[0048] 100, refresh control unit; 10, refresh enable subunit; 20, first data writing channel; 30, second data writing channel; 200, pixel unit; Gi, row scanning line; Si, data line; XGi, pixel polarity line; T1, first switch tube; T2, second switch tube; T3, third switch tube; T4, fourth switch tube; T5, fifth switch tube; Cst, storage capacitor.

[0049] The objectives, functional features and advantages of the present application will be further described with reference to the embodiments in combination with the accompanying drawings. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be clearly and completely described in combination with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work are within the protection scope of the present application.

[0051] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, motion condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly.

[0052] In addition, if the embodiments of the present application involve descriptions of “first”, “second”, etc., the descriptions of “first”, “second”, etc. are only for description purposes, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by “first”, “second” can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can realize it, and when the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist, and is also not within the protection scope claimed by the present application.

[0053] The exemplary embodiments will be described in detail hereinbelow with reference to the accompanying drawings. The following description relates to the drawings, unless otherwise indicated, in which like numerals refer to like elements throughout. The implementations described in the following exemplary embodiments are not meant to represent all implementations in which the present application can be practiced.

[0054] In recent years, with the rapid development of display technology, high refresh rate displays gradually become the mainstream demand of the market due to their smoother visual experience in dynamic pictures, faster response speed, and reduced visual fatigue. However, high refresh rate also brings higher power consumption problems, especially in mobile devices, notebook computers and other application scenarios with high requirements for endurance, high power consumption has become one of the key factors restricting the popularization of high refresh rate.

[0055] To balance the contradiction between visual experience and power consumption, some screen providers propose a FFR (free framerate) scheme, the basic principle of which is: when displaying a static picture, by analyzing the picture characteristics of the subsequent frame, it is determined whether the picture local area changes. If the content of a certain area does not change, the refresh rate of the area is reduced to reduce power consumption; if the content changes, the high refresh rate is maintained to ensure smoothness.

[0056] At present, the implementation of FFR technology mainly depends on GOA (Gate Driver on Array, array substrate row driving) timing adjustment, which controls the refresh of pixels through line-by-line scanning. However, the GOA-based FFR technology has significant limitations. On the one hand, GOA performs refresh control in units of rows, while actual picture changes may be pixel-level or local area, for example, some pixels in the same row need high refresh rate, while the other part needs low refresh rate. At this time, the GOA-based FFR technology cannot realize fine refresh rate adjustment, resulting in limited power consumption optimization effect. On the other hand, as shown in Figure 1 Figure 1 Due to the line-by-line scanning characteristics of GOA, the GOA-based FFR technology requires the refresh rate of the previous row to be higher than or equal to the next row, that is, region 1 of the middle region ≥…≥ region n of the refresh rate, otherwise it will cause timing conflict or picture abnormality, so that the FFR technology cannot flexibly adapt to complex and changeable picture refresh requirements, for example, some scenes may need local high refresh rate and low refresh rate areas to be staggered, and the existing technology is difficult to support.

[0057] In summary, although the existing GOA-based FFR technology realizes local refresh rate differentiation control to a certain extent, due to the problems of large refresh adjustment granularity and strong refresh direction dependence, the application of the technology in wider scenarios is limited.

[0058] Therefore, in order to realize the free refresh control of the display panel, the present application provides a refresh control circuit and method thereof, a display panel and a display device.

[0059] The embodiment of the present application provides a refresh control circuit, as shown in Figure 2 Figure 2 ​​is a structural block diagram of a first embodiment of a refresh control circuit of the present application. The refresh control circuit comprises: pixel units 200 arranged in an array; a refresh control module, the refresh control module comprising refresh control units 100 corresponding to each of the pixel units 200, each of the refresh control units 100 being electrically connected to the corresponding pixel unit 200, the refresh control module being configured to determine a pixel unit identification group to be refreshed according to current frame pixel refresh information of a to-be-displayed picture, and enable each of the refresh control units 100 corresponding to the pixel units 200 in the pixel unit identification group to perform a pixel refresh operation.

[0060] In the present embodiment, the refresh control module first acquires the current frame pixel refresh information of the to-be-displayed picture. If the current frame pixel refresh information indicates that each of the pixel units 200 in the Nth pixel row is in a pixel low refresh state as shown in FIG. 1B, it is determined that the pixel unit identification group to be refreshed comprises all the pixel units 200 except the pixel units 200 in the Nth pixel row. Next, the refresh control units 100 corresponding to each of the pixel units 200 in the pixel unit identification group are enabled to independently perform the pixel refresh operation, thereby realizing free refresh control at the pixel level. Figure 3

[0061] It should be noted that the pixel unit identification group to be refreshed comprises all the pixel units 200 in the array distribution except the pixel units 200 in the pixel low refresh state. For example, if the current frame pixel refresh information indicates that the first pixel unit 200 in the first pixel row identified as Pixel1-1 is in a pixel low refresh state as shown in FIG. 1C, it is determined that the pixel unit identification group to be refreshed comprises all the pixel units 200 except the pixel unit 200 corresponding to Pixel1-1, i.e., the pixel unit identification group to be refreshed comprises the pixel units 200 corresponding to Pixel1-2, Pixel1-3, Pixel2-1, Pixel2-2, Pixel2-3, Pixel3-1, Pixel3-2 and Pixel3-3. Figure 4

[0062] ​​The application realizes free refresh control at the pixel level by integrating the array-distributed pixel units 200 and the refresh control module in the refresh control circuit of the display panel, and configuring each pixel unit 200 with an independent refresh control unit 100 in the refresh control module. Specifically, the refresh control module detects the current frame pixel refresh information of the to-be-displayed picture in real time, so as to directly locate the pixel unit identification group to be refreshed; then, the refresh control units 100 corresponding to each pixel unit 200 in the pixel unit identification group are enabled to independently perform pixel refresh operations, thereby breaking through the limitation of the traditional GOA row-level control, allowing different pixel units 200 in the same row to independently set a differentiated refresh rate according to the display content requirement, completely eliminating the limitation of the traditional line-by-line scanning on the adjustment direction of the refresh rate, and enabling the display panel to realize accurate on-demand refresh with any pixel as the minimum unit, thereby realizing truly free and flexible refresh control of the display panel.

[0063] Further, in some possible embodiments, referring to Figure 5 , the refresh control unit 100 includes a refresh enabling subunit 10, a first data writing channel 20, and a second data writing channel 30; the control end of the refresh enabling subunit 10 is electrically connected with the row scanning line Gi, the data input end of the refresh enabling subunit 10 is electrically connected with the data line, the data output end of the refresh enabling subunit 10 is respectively electrically connected with the data input end of the first data writing channel 20 and the data input end of the second data writing channel 30, the data output end of the first data writing channel 20 and the data output end of the second data writing channel 30 are respectively electrically connected with the corresponding pixel unit 200, and the control end of the first data writing channel 20 and the control end of the second data writing channel 30 are respectively electrically connected with the pixel polarity line XGi.

[0064] In the embodiment, referring to Figure 5The application sets the refresh control unit 100 of the integrated refresh enabling subunit 10, the first data writing channel 20 and the second data writing channel 30 to realize more flexible local refresh rate adjustment. Specifically, since each pixel unit 200 in the pixel unit identification group is in a high refresh state, when the row scanning line Gi is scanned to the pixel row where the pixel unit 200 in the pixel high refresh state, the refresh enabling subunit 10 enables the pixel data voltage provided by the data line to be selected to be charged to the corresponding pixel unit 200 through the second data writing channel 30 or the second data writing channel 30 based on the polarity potential of the pixel polarity line XGi in response to the valid scanning signal provided by the row scanning line Gi, thereby realizing accurate data writing in the high refresh state while being compatible with the polarity inversion type display panel. When the pixel row electrically connected with the row scanning line Gi further includes at least one pixel unit 200 in a pixel low refresh state in addition to the pixel unit identification group, that is, in the scanning period of the pixel unit 200 in the pixel low refresh state without refresh, the refresh enabling subunit 10 can access the pixel data voltage provided by the data line under the driving of the valid scanning signal provided by the row scanning line Gi, but the communication path of the data line to the pixel unit 200 is automatically blocked through the first data writing channel 20 and the second data writing channel 30, so that the storage capacitor Cst in the pixel unit 200 in the low refresh state continuously maintains the historical voltage written in the last frame of the current frame without data updating, thereby realizing low refresh rate, reducing invalid refresh operation, further reducing power consumption, and not affecting the normal work of other pixel units 200 in the same pixel row in the high refresh state, fully reflecting the flexibility of local refresh rate adjustment.

[0065] It should be noted that the valid scanning signal can be understood as a high potential pulse signal with a normal low potential.

[0066] Further, in some other possible embodiments, referring to (a) and (b) in the description, Figure 6 When the target pixel unit is any one of the pixel units 200 in the pixel unit identification group, the refresh control unit 100 corresponding to the target pixel unit is set to enable the refresh enabling subunit 10 to charge the pixel data voltage provided by the data line to the target pixel unit through the first data writing channel 20 when the polarity potential of the pixel polarity line XGi is the first potential in response to the valid scanning signal provided by the row scanning line Gi.

[0067] In the embodiment, referring to Figure 6 When the target pixel unit is any one of the pixel units 200 in the pixel unit identification group, the pixel row where the target pixel unit is located is scanned row by row, and if the row scanning line Gi outputs Figure 6The effective scan signal that jumps from a low potential to a high potential is shown in (b) above, and the polarity potential of the pixel polarity line XGi is... Figure 6 As shown in (b), when the target pixel unit transitions from a high potential to a low potential, it is determined to be a positive polarity pixel unit. And when the target pixel unit is a positive polarity pixel unit, it is... Figure 6 The refresh enable subunit 10 shown in (a) charges the high-potential pixel data voltage Datan output from the data line into the storage capacitor Cst in the target pixel unit via the first data write channel 20, thereby realizing the directional data update of the pixel unit 200 to be refreshed in the current pixel row, which is a positive polarity pixel unit.

[0068] It should be noted that, Figure 6 The bold solid line shown in (a) indicates the flow of high potential through the link. Figure 6 The bold dashed line shown in (a) indicates a low-potential flow through the link, and... Figure 6 In diagram (a), solid lines represent the on-state of each switch, and dashed lines represent the off-state. A high potential can be understood as a high level, and a low potential as a low level.

[0069] In another embodiment, when the target pixel unit is any one of the pixel units 200 in the pixel unit identifier group, when scanning line by line to the next pixel line where the target pixel unit is a positive polarity pixel unit, since Figure 7 (a) and Figure 8 As shown in (a), the row scan line Gi outputs to the pixel row where the target pixel unit is located. Figure 7 (b) and Figure 8 The invalid scan signal, shown in (b), transitions from a high to a low potential, causing the refresh enable subunit 10 to switch from an on state to an off state, thereby triggering the first data write channel 20 to automatically disconnect the connection path from the data line to the storage capacitor Cst of the target pixel unit. At this time, regardless of the data line providing... Figure 7 In (b), the pixel data voltage Datan+1 at a high potential is still... Figure 8 As shown in (b), the pixel data voltage is at a low potential. The pixel data voltage charged into the storage capacitor Cst of the target pixel unit is no longer affected by the change in data line potential. It is always maintained at the high potential pixel data voltage Datan written during the effective scanning of the pixel row where the target pixel unit is a positive polarity pixel unit, thereby achieving stable maintenance of the pixel data of the target pixel unit.

[0070] It should be noted that, Figure 7 (a) and Figure 8 The bold solid line shown in (a) indicates the flow of high potential through the link.Figure 7 (a) and Figure 8 The bold dashed line shown in (a) indicates a low-potential flow through the link, and... Figure 7 (a) and Figure 8 In diagram (a), solid lines represent the on-state of each switch, and dashed lines represent the off-state. A high potential can be understood as a high level, and a low potential as a low level.

[0071] When the refresh enable subunit 10 is enabled, the pixel data voltage provided by the data line is charged into the target pixel unit via the second data write channel 30 when the polarity potential of the pixel polarity line XGi is the second potential.

[0072] In this embodiment, refer to Figure 9 When the target pixel unit is any one of the pixel units 200 in the pixel unit identifier group, scan line by line to the pixel row where the target pixel unit is located. If the row scan line Gi outputs... Figure 9 The effective scan signal that jumps from a low potential to a high potential is shown in (b) above, and the polarity potential of the pixel polarity line XGi is... Figure 9 When the second potential, as shown in (b), transitions from a low potential to a high potential, the target pixel unit is determined to be a negative polarity pixel unit, and when the target pixel unit is a negative polarity pixel unit, it is determined by... Figure 9 The refresh enable subunit 10 shown in (a) charges the low-potential pixel data voltage Datan output from the data line into the storage capacitor Cst in the target pixel unit through the second data write channel 30, thereby realizing the directional data update of the negative polarity pixel unit 200 of the pixel unit to be refreshed in the current pixel row.

[0073] It should be noted that, Figure 9 The bold solid line shown in (a) indicates the flow of high potential through the link. Figure 9 The bold dashed line shown in (a) indicates a low-potential flow through the link, and... Figure 9 In diagram (a), solid lines represent the on-state of each switch, and dashed lines represent the off-state. A high potential can be understood as a high level, and a low potential as a low level.

[0074] In another embodiment, when the target pixel unit is any one of the pixel units 200 in the pixel unit identifier group, when scanning line by line to the next pixel line where the target pixel unit is a negative polarity pixel unit, since Figure 10 (a) and Figure 11 As shown in (a), the row scan line Gi outputs to the pixel row where the target pixel unit is located. Figure 10 (b) and Figure 11invalid scan signal shown in (b) of FIG. 1 jumps from high potential to low potential, so that the refresh enable subunit 10 switches from the on state to the off state, thereby triggering the second data write channel 30 to automatically disconnect the communication path of the data line to the storage capacitor Cst of the target pixel unit. At this time, whether the pixel data voltage Datan+1 shown in (b) of FIG. 1 is at low potential or Figure 10 Figure 11 the pixel data voltage shown in (b) of FIG. 1 is at high potential, the pixel data voltage charged in the storage capacitor Cst of the target pixel unit is no longer affected by the change of the potential of the data line, and always remains as the low potential pixel data voltage Datan written in the effective scan period of the pixel row in which the target pixel unit is a negative polarity pixel unit, thereby realizing stable retention of the pixel data of the target pixel unit.

[0075] It should be noted that, Figure 10 the bold solid line shown in (a) of FIG. 1 represents a link flowing through the chain at high potential, Figure 11 the bold solid line shown in (a) of FIG. 1 represents a link flowing through the chain at high potential, Figure 10 the bold dashed line shown in (a) of FIG. 1 represents a link flowing through the chain at low potential, and in Figure 11 the bold dashed line shown in (a) of FIG. 1 represents a link flowing through the chain at low potential, and in Figure 10 the bold dashed line shown in (a) of FIG. 1 represents a link flowing through the chain at low potential, and in Figure 11 the bold dashed line shown in (a) of FIG. 1 represents a link flowing through the chain at low potential, and in

[0076] When the target pixel unit is any one of the pixel units 200 except the pixel unit identification group, the refresh control unit 100 corresponding to the target pixel unit is set to trigger the first data write channel 20 and the second data write channel 30 to synchronously disconnect the communication of the refresh enable subunit 10 to the target pixel unit when the refresh enable subunit 10 accesses the pixel data voltage of the same polarity as the polarity potential under the driving of the effective scan signal, so that the target pixel unit maintains the historical data voltage written in the last frame of the current frame.

[0077] In the present embodiment, with reference to Figure 12 When the target pixel unit is any one of the pixel units 200 except the pixel unit identification group, the pixel row in which the target pixel unit is located is scanned row by row, Figure 12 the row scan line Gi shown in (a) of FIG. 1 outputs Figure 12 the effective scan signal shown in (b) of FIG. 1 jumps from low potential to high potential. Since the data line has no pixel data voltage output at low potential when the target pixel unit is a positive polarity pixel unit, and the polarity potential of the pixel polarity line XGi is low when the target pixel unit is a positive polarity pixel unit, at this time, although the refresh enable subunit 10 is connected to the data line through the on state​Figure 12 but the first data write channel 20 and the second data write channel 30 always maintain the off state, so that the low pixel data voltage output by the data line in (b) cannot be charged into the target pixel cell through any data write channel, thereby maintaining the data stability of the positive polarity pixel cell in the low brush state.

[0078] In another embodiment, referring to Figure 13 When the target pixel cell is any one pixel cell 200 other than the pixel cell identification group, the target pixel cell is scanned row by row, Figure 13 the row scanning line Gi in (a) outputs Figure 13 the active scanning signal in (b) jumps from low to high, and since the pixel data voltage output by the data line is high when the target pixel cell is a negative polarity pixel cell, and the polarity potential of the pixel polarity line XGi is high when the target pixel cell is a negative polarity pixel cell, at this time, although the high pixel data voltage output by the data line in (b) is accessed through the turned-on refresh enable subunit 10, the first data write channel 20 and the second data write channel 30 always maintain the off state, so that the high pixel data voltage cannot be charged into the target pixel cell through any data write channel, thereby maintaining the data stability of the negative polarity pixel cell in the low brush state. Figure 13 but the first data write channel 20 and the second data write channel 30 always maintain the off state, so that the low pixel data voltage output by the data line in (b) cannot be charged into the target pixel cell through any data write channel, thereby maintaining the data stability of the positive polarity pixel cell in the low brush state.

[0079] Further, in some feasible embodiments, referring to Figure 5 The refresh enable subunit 10 includes a first switch tube T1; the gate end of the first switch tube T1 constitutes the control end of the refresh enable subunit 10 and is electrically connected with the row scanning line Gi, the first pass end of the first switch tube T1 constitutes the data input end of the refresh enable subunit 10 and is electrically connected with the data line; and the second pass end of the first switch tube T1 constitutes the data output end of the refresh enable subunit 10 and is respectively electrically connected with the data input end of the first data write channel 20 and the data input end of the second data write channel 30.

[0080] In the embodiment, since the first switch tube T1 provided by the application is an N-type MOS tube, the first switch tube T1 switches from the off state to the on state when the active scanning signal representing the high potential is provided on the row scanning line Gi, so as to ensure that a low impedance path is formed between the data line and the data writing channel (i.e. the first data writing channel 20 and the second data writing channel 30), so that the pixel data voltage can be efficiently and losslessly transmitted to the subsequent data writing channel, and the timeliness and accuracy of the pixel data voltage writing are improved; on the contrary, the first switch tube T1 always maintains the off state when the invalid scanning signal representing the low potential is provided on the row scanning line Gi, so as to completely cut off the electrical connection between the data line and the first data writing channel 20 and the second data writing channel 30, effectively avoid the potential fluctuation of the data line in the invalid scanning stage from causing interference to the data of the pixel unit 200 which has been written, ensure that the pixel data voltage on the storage capacitor Cst remains stable, and improve the consistency of the display picture.

[0081] It should be noted that the switching characteristics of the N-type MOS tube are that the high potential is on and the low potential is off; the switching characteristics of the P-type MOS tube are that the high potential is off and the low potential is on.

[0082] Further, in some other possible embodiments, referring to Figure 5 , the first data writing channel 20 comprises a second switch tube T2 and a third switch tube T3; the gate end of the second switch tube T2 is electrically connected with the control end of the first data writing channel 20 and the pixel polarity line XGi; the first path end of the second switch tube T2 is electrically connected with the data input end of the first data writing channel 20 and the data output end of the refresh enable sub-unit 10; the second path end of the second switch tube T2 is electrically connected with the first path end of the third switch tube T3; the gate end of the third switch tube T3 is electrically connected with the data line; and the second path end of the third switch tube T3 constitutes the data output end of the first data writing channel 20 and is electrically connected with the corresponding pixel unit 200.

[0083] In the embodiment, the second switch tube T2 and the third switch tube T3 provided by the application are a P-type MOS tube and an N-type MOS tube respectively. When the target pixel unit is any one of the pixel units 200 in the pixel unit identification group, the pixel row where the target pixel unit is located is scanned line by line, if the active scanning signal represented by the row scanning line Gi jumps from the low potential to the high potential as shown in (b) in the table, and the polarity potential of the pixel polarity line XGi is Figure 6 , the second switch tube T2 is turned on, and the third switch tube T3 is turned off, so as to form a low impedance path between the data line and the first data writing channel 20, and the pixel data voltage can be efficiently and losslessly transmitted to the first data writing channel 20; on the contrary, if the row scanning line Gi outputs the invalid scanning signal represented by the column scanning line Gi as shown in (a) in the table, and the polarity potential of the pixel polarity line XGi is Figure 6When the target pixel unit is a positive polarity pixel unit, as shown in (b) above, the high-potential pixel data voltage Datan output from the data line is written into the storage capacitor Cst in the target pixel unit through the first switch T1, the second switch T2 and the third switch T3 in sequence. Meanwhile, the fourth switch T4 and the fifth switch T5 in the second data writing channel 30 are always kept in the off state, thereby realizing the directional data update of the pixel unit 200 to be refreshed in the current pixel row that is a positive polarity pixel unit.

[0084] Furthermore, in some feasible embodiments, reference is made to Figure 5 The second data writing channel 30 includes a fourth switch T4 and a fifth switch T5; the gate terminal of the fourth switch T4 is electrically connected to the control terminal of the second data writing channel 30 and the pixel polarity line XGi; the first path terminal of the fourth switch T4 constitutes the data input terminal of the second data writing channel 30 and is electrically connected to the data output terminal of the refresh enable subunit 10; the second path terminal of the fourth switch T4 is electrically connected to the first path terminal of the fifth switch T5; the gate terminal of the fifth switch T5 is electrically connected to the data line; the second path terminal of the fifth switch T5 constitutes the data output terminal of the second data writing channel 30 and is electrically connected to the corresponding pixel unit 200.

[0085] In this embodiment, the fourth switch T4 is set to an N-type MOSFET and the fifth switch T5 is set to a P-type MOSFET. When the target pixel unit is any one of the pixel units 200 in the pixel unit identifier group, the system scans line by line to the pixel row where the target pixel unit is located. If the row scan line Gi outputs... Figure 9 The effective scan signal that transitions from a low potential to a high potential is shown in (b) above, and the polarity potential of the pixel polarity line XGi is... Figure 9 When the second potential, shown in (b), changes from low to high, i.e., the target pixel unit is a negative polarity pixel unit, the low-potential pixel data voltage Datan output from the data line is written into the storage capacitor Cst in the target pixel unit through the first switch T1, the fourth switch T4, and the fifth switch T5, which are turned on in sequence. Meanwhile, the second switch T2 and the third switch T3 in the first data writing channel 20 are always kept in the off state, thereby realizing the directional data update of the pixel unit 200 to be refreshed in the current pixel row, which is a negative polarity pixel unit.

[0086] Furthermore, in some other feasible embodiments, reference is made to... Figure 14 The refresh control circuit further includes multiple pull-down modules, the first end of each pull-down module is electrically connected to the corresponding data line Si, and the second end of each pull-down module is connected to a reference potential line.

[0087] In the embodiment, the application adds a corresponding pull-down module for each data line Si (i = 1, 2, 3, …, n), and sets the reference potential line as Figure 14 a low potential represented by VGL when the pixel unit 200 is a positive polarity pixel unit; and sets the reference potential line as Figure 14 a high potential represented by VGH when the pixel unit 200 is a negative polarity pixel unit, thereby significantly improving the reliability and response speed of the refresh control. Specifically, when the pixel unit 200 is a positive polarity pixel unit, the data line Si has no pixel voltage output, and the corresponding pull-down module quickly pulls the data signal provided by the data line Si connected thereto to a low potential VGL, so that the potential state of the data signal can quickly reach a low potential state; and when the pixel unit 200 is a negative polarity pixel unit, the data line Si has no pixel voltage output, and the corresponding pull-down module quickly pulls the data signal provided by the data line Si connected thereto to a high potential VGL, so that the potential state of the data signal can quickly reach a high potential state, effectively eliminating the error refresh problem that may be caused by the floating state of the data line Si when there is no data signal output. At the same time, the pull-down module set by the application has minimal modification to the existing display panel driving circuit, and can be implemented by simply integrating a pull-down switch in the source driving circuit, thereby having excellent process compatibility and mass production feasibility.

[0088] It should be noted that when there are multiple data lines Si, the multiple data lines Si can be the data line S1, the data line S2, the data line S3, …, the data line Sn as shown in the figure. Figure 14 The pull-down module can be a pull-down resistor.

[0089] In summary, the application integrates the array-distributed pixel unit 200 and the refresh control module in the refresh control circuit of the display panel, and configures each pixel unit 200 with an independent refresh control unit 100 in the refresh control module, thereby achieving free refresh control at the pixel level. Specifically, the refresh control module detects the current frame pixel refresh information of the to-be-displayed picture in real time, so as to directly locate the pixel unit identification group to be refreshed; then, the refresh control units 100 corresponding to the pixel units 200 in the pixel unit identification group are enabled to independently perform pixel refresh operations, thereby breaking through the limitation of the traditional GOA row-level control, allowing different pixel units 200 in the same row to independently set different refresh rates according to the display content requirements, and completely eliminating the limitation of the traditional line-by-line scanning on the adjustment direction of the refresh rate, so that the display panel can achieve accurate on-demand refresh with any pixel as the minimum unit, thereby realizing truly free and flexible refresh control of the display panel.

[0090] Further, based on the first embodiment of the refresh control circuit, the second embodiment of the refresh control method is proposed.

[0091] The refresh control method is applied to any of the above refresh control circuits, and is executed by a display device to which the refresh control circuit is applied. The refresh control method includes the following implementation step S10.

[0092] Step S10: Determine the pixel unit identification group to be refreshed according to the current frame pixel refresh information of the to-be-displayed picture, and enable the refresh control unit 100 corresponding to each pixel unit 200 in the pixel unit identification group to perform pixel refresh operation.

[0093] In this embodiment, by the refresh control module according to the current frame pixel refresh information of the to-be-displayed picture, the pixel unit identification group to be refreshed can be accurately positioned to include all pixel units 200 except the pixel units 200 in the Nth pixel row; then, the refresh control unit 100 corresponding to each pixel unit 200 in the pixel unit identification group is enabled to independently perform pixel refresh operation, thereby realizing free refresh control at the pixel level.

[0094] In specific embodiments, referring to Figure 3 and Figure 15 , if the current frame pixel refresh information of the to-be-displayed picture is that the N-1th pixel row connected by the scanning line Gn-1 and the N+1th pixel row connected by the scanning line Gn+1 are high refresh, and the Nth pixel row connected by the scanning line Gn is low refresh, only the timing control of the pixel freezing mode (i.e. the pixel low refresh state) shown in Figure 15 is needed for each pixel unit 200 in the Nth pixel row connected by the scanning line Gn, i.e. the storage capacitor Cst of each pixel unit 200 in the Nth pixel row always maintains the pixel data voltage Data2-1 charged in the first frame when the scanning line Gn provides an effective scanning signal, wherein Figure 15 the reference sign Cst_n-1 in represents the storage capacitor Cst in each pixel unit 200 in the N-1th pixel row connected by the scanning line Gn-1; Figure 15 the reference sign Cst_n in represents the storage capacitor Cst in each pixel unit 200 in the Nth pixel row connected by the scanning line Gn; Figure 15 the reference sign Cst_n+1 in represents the storage capacitor Cst in each pixel unit 200 in the N+1th pixel row connected by the scanning line Gn+1.

[0095] In summary, the application realizes free refresh control at the pixel level by integrating the array-distributed pixel units 200 and the refresh control module in the refresh control circuit of the display panel, and configuring each pixel unit 200 with an independent refresh control unit 100 in the refresh control module. Specifically, the refresh control module detects the current frame pixel refresh information of the to-be-displayed picture in real time, so as to directly locate the pixel unit identification group to be refreshed; then, the refresh control units 100 corresponding to the pixel units 200 in the pixel unit identification group are enabled to independently perform pixel refresh operations, thereby breaking through the limitation of the traditional GOA row-level control, allowing different pixel units 200 in the same row to independently set different refresh rates according to the display content requirements, and completely eliminating the limitation of the traditional line-by-line scanning on the refresh rate adjustment direction, so that the display panel can realize accurate on-demand refresh with any pixel as the minimum unit, and realize truly free and flexible refresh control of the display panel.

[0096] In addition, the application further provides a display panel, which comprises a color film substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color film substrate, and the array substrate comprises the refresh control circuit of any one of the above.

[0097] In addition, the application further provides a display device. Please refer to Figure 16 , Figure 16 is a structural schematic diagram of a display device related to the embodiment scheme of the application. The display device of the embodiment of the application can be a device running the refresh control method locally.

[0098] As shown in Figure 16 , the display device of the embodiment of the application can comprise a display panel, or a processor 1001 such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004 and a memory 1005. The communication bus 1002 is used to realize the connection and communication among these components. The user interface 1003 can comprise a display screen (Display) and an input unit such as a keyboard (Keyboard), and the optional user interface 1003 can further comprise a standard wired interface and a wireless interface. The network interface 1004 can optionally comprise a standard wired interface and a wireless interface (such as a Wi-Fi interface).

[0099] The memory 1005 is arranged on the main body of the display device, and the memory 1005 stores a program, which realizes corresponding operations when executed by the processor 1001. The memory 1005 is also used to store parameters for use by the display device. The memory 1005 can be a high-speed RAM memory or a stable memory (non-volatile memory) such as a magnetic disk memory. The memory 1005 can optionally be a storage device independent of the aforementioned processor 1001.

[0100] Those skilled in the art can understand that Figure 16 The display device structure shown in the figures does not constitute a limitation on the display device, and can include more or fewer components than shown, or combine certain components, or different component arrangements.

[0101] As Figure 16 As shown, the memory 1005 as a storage medium can include an operating system, a network communication module, a user interface module, and a charging driver.

[0102] In Figure 16 In the display device shown, the processor 1001 can be configured to invoke the charging driver stored in the memory 1005 and execute the steps of the refresh control method as described above.

[0103] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles, or systems that include a series of elements not only include those elements, but also include other elements not explicitly listed, or inherent to such processes, methods, articles, or systems. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or system that includes the element.

[0104] The above-mentioned sequence numbers of the embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0105] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be realized by software and necessary general hardware platform, of course, also can be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium such as a ROM / RAM, a magnetic disk, or an optical disk, and includes a plurality of instructions for causing a display device (which can be a mobile phone, a computer, a server, or a network device) to execute the methods described in the various embodiments of the present application.

[0106] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation made by using the contents of the specification and drawings, or directly or indirectly applied to other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A refresh control circuit, characterized by comprising: The refresh control circuit comprises: pixel units arranged in an array; a refresh control module, each of the refresh control units is electrically connected with the corresponding pixel unit, and the refresh control module is configured to determine a pixel unit identification group to be refreshed according to current frame pixel refresh information of a to-be-displayed picture, and enable the refresh control unit corresponding to each pixel unit in the pixel unit identification group to perform a pixel refresh operation; The refresh control unit comprises a refresh enable subunit, a first data write channel and a second data write channel; the control end of the refresh enable subunit is electrically connected with the row scanning line, the data input end of the refresh enable subunit is electrically connected with the data line, the data output end of the refresh enable subunit is electrically connected with the data input end of the first data write channel and the data input end of the second data write channel respectively, and the data output end of the first data write channel and the data output end of the second data write channel are electrically connected with the corresponding pixel unit respectively, and the control end of the first data write channel and the control end of the second data write channel are electrically connected with the pixel polarity line respectively; When the target pixel unit is any one of the pixel units in the pixel unit identification group, the refresh control unit corresponding to the target pixel unit is configured to enable the refresh enable subunit to charge the pixel data voltage provided by the data line to the target pixel unit through the first data write channel when the polarity potential of the pixel polarity line is the first potential in response to the valid scanning signal provided by the row scanning line, and / or enable the refresh enable subunit to charge the pixel data voltage provided by the data line to the target pixel unit through the second data write channel when the polarity potential of the pixel polarity line is the second potential; When the target pixel unit is any one of the pixel units other than the pixel unit identification group, the refresh control unit corresponding to the target pixel unit is configured to trigger the first data write channel and the second data write channel to synchronously disconnect the communication of the refresh enable subunit to the target pixel unit when the refresh enable subunit accesses the pixel data voltage with the same polarity under the driving of the valid scanning signal, so that the target pixel unit maintains the historical data voltage written in the last frame of the current frame.

2. The refresh control circuit of claim 1, wherein, The refresh enable subunit comprises a first switch tube; The gate end of the first switch tube constitutes the control end of the refresh enable subunit and is electrically connected with the row scanning line, and the first passage end of the first switch tube constitutes the data input end of the refresh enable subunit and is electrically connected with the data line; The second passage end of the first switch tube constitutes the data output end of the refresh enable subunit and is electrically connected with the data input end of the first data write channel and the data input end of the second data write channel respectively.

3. The refresh control circuit of claim 1, wherein, The first data write channel comprises a second switch tube and a third switch tube; The gate terminal of the second switch tube is electrically connected with the control terminal of the first data write channel and the pixel polarity line, and the first pass terminal of the second switch tube is electrically connected with the data input terminal of the first data write channel and the data output terminal of the refresh enable subunit. The second pass terminal of the second switch tube is electrically connected with the first pass terminal of the third switch tube, the gate terminal of the third switch tube is electrically connected with the data line, and the second pass terminal of the third switch tube is electrically connected with the data output terminal of the first data write channel and the corresponding pixel unit.

4. The refresh control circuit of claim 1, wherein, The second data write channel comprises a fourth switch tube and a fifth switch tube. The gate terminal of the fourth switch tube is electrically connected with the control terminal of the second data write channel and the pixel polarity line, and the first pass terminal of the fourth switch tube is electrically connected with the data input terminal of the second data write channel and the data output terminal of the refresh enable subunit. The second pass terminal of the fourth switch tube is electrically connected with the first pass terminal of the fifth switch tube, the gate terminal of the fifth switch tube is electrically connected with the data line, and the second pass terminal of the fifth switch tube is electrically connected with the data output terminal of the second data write channel and the corresponding pixel unit.

5. The refresh control circuit of claim 1, wherein, The refresh control circuit further comprises a plurality of pull-down modules, the first terminal of each of the pull-down modules is electrically connected with the corresponding data line, and the second terminal of each of the pull-down modules is connected with a reference potential line.

6. A refresh control method, characterized by, The refresh control method is applied to the refresh control circuit according to any one of claims 1 to 5, and the refresh control method comprises: According to the current frame pixel refresh information of a to-be-displayed picture, a pixel unit identification group to be refreshed is determined, and the refresh control units corresponding to each pixel unit in the pixel unit identification group are enabled to perform pixel refresh operations.

7. A display panel, characterized by, The display panel comprises a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate comprises the refresh control circuit according to any one of claims 1 to 5.

8. A display device, characterized by comprising: The display device comprises the display panel according to claim 7. Alternatively, The memory, the processor and a charging driver stored in the memory and executable on the processor, when the processor executes the charging driver, the steps of the refresh control method according to claim 6 are implemented.

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