An asymmetric bias doherty power amplifier with load mismatch immunity

Abstract

The application relates to the technical field of wireless communication, in particular to an asymmetric bias Doherty power amplifier with load mismatch resistance, which comprises a 90-degree input coupler, a carrier power amplifier, a peak power amplifier, a 90-degree output coupler, an impedance element and a switch; wherein: the 90-degree input coupler is used for acquiring an input signal, the isolation end is grounded through the impedance element, the through end is connected with the input end of the carrier power amplifier, and the coupling end is connected with the input end of the peak power amplifier; the carrier power amplifier is connected with the through end of the 90-degree output coupler; the peak power amplifier is connected with the coupling end of the 90-degree output coupler; and the 90-degree output coupler is grounded through the switch at the isolation end and is used for outputting an amplified signal. Through the design of the asymmetric drain supply voltage, the load mismatch resistance of the Doherty device is improved.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and more specifically to an asymmetric biased Doherty power amplifier with load mismatch resistance. Background Technology

[0002] The Doherty Power Amplifier is a power amplifier architecture designed for processing complex broadband modulated signals and is used in 5G communication equipment.

[0003] Doherty power amplifiers are often used in load-modulated power amplifier circuit topology and theoretical analysis. However, existing theoretical analyses are all based on standard load impedance. When faced with load impedance mismatch caused by the diversification and arraying of communication systems, the power amplifier efficiency and power characteristics deteriorate severely, and the equipment reliability is seriously affected.

[0004] Therefore, there is an urgent need for an asymmetric biased Doherty power amplifier with load mismatch resistance. Summary of the Invention

[0005] In view of this, the present invention discloses an asymmetric biased Doherty power amplifier with load mismatch resistance to solve the above problems; comprising: a 90° input coupler, a carrier power amplifier, a peak power amplifier, a 90° output coupler, an impedance element, and a switch; wherein:

[0006] 90° Input Coupler: The input terminal is used to acquire the input signal, the isolation terminal is grounded through an impedance element, the through terminal is connected to the input terminal of the carrier power amplifier, and the coupling terminal is connected to the input terminal of the peak power amplifier;

[0007] Carrier power amplifier: The output terminal is connected to the straight-through terminal of the 90° output coupler;

[0008] Peak power amplifier: The output terminal is connected to the coupling terminal of the 90° output coupler;

[0009] 90° output coupler: The isolation terminal is grounded via a switch, and the output terminal is used to output amplified signals;

[0010] Furthermore, the characteristic impedance parameters of the impedance element, the 90° input coupler, and the 90° output coupler are the same;

[0011] Furthermore, the carrier power amplifier and the peak power amplifier adopt a power supply scheme with asymmetrical drain supply voltage.

[0012] During signal transmission, there are two situations: impedance matching and impedance mismatch. The asymmetrical biased Doherty power amplifier includes parallel mode and series mode. The operating mode is determined by the closed state of the switch at the isolation terminal of the 90° output coupler.

[0013] This invention solves the problems of decreased power transfer efficiency and deteriorated circuit performance caused by load mismatch in Doherty power amplifiers by adopting an asymmetrical drain supply voltage design, thereby further improving circuit stability. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the asymmetric biased Doherty power amplifier with load mismatch resistance capability in this invention.

[0015] Figure 2 This is a simplified structural diagram of the parallel mode of the asymmetric biased Doherty power amplifier in matched state in an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram showing the voltage, current, and efficiency changes of an asymmetric biased Doherty power amplifier in an embodiment of the present invention.

[0017] Figure 4 In this embodiment of the invention, the OBO range of the asymmetric biased Doherty power amplifier varies with γ. V A schematic diagram illustrating the changes;

[0018] Figure 5 This is a schematic diagram illustrating how the performance of an asymmetric biased Doherty power amplifier changes by switching modes in an embodiment of the present invention.

[0019] Figure 6 This is a schematic diagram of the structure used in the simulation of the asymmetric bias Doherty power amplifier in the embodiments of the present invention;

[0020] Figure 7 The simulation results of the asymmetric biased Doherty power amplifier under impedance matching state in the embodiments of the present invention are shown.

[0021] Figure 8 This is the simulation result of the drain efficiency of the asymmetric biased Doherty power amplifier in parallel mode under impedance mismatch in the embodiment of the present invention.

[0022] Figure 9 This is the simulation result of the drain efficiency of the asymmetric biased Doherty power amplifier in series mode under impedance mismatch in an embodiment of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, features, and advantages of the present invention clearer, the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0024] This embodiment includes an asymmetric biased Doherty power amplifier with load mismatch resistance to address the aforementioned problems. It includes: a 90° input coupler, a carrier power amplifier, a peak power amplifier, a 90° output coupler, impedance elements, and switches.

[0025] 90° Input Coupler: The input terminal is used to acquire the input signal, the isolation terminal is grounded through an impedance element, the through terminal is connected to the input terminal of the carrier power amplifier, and the coupling terminal is connected to the input terminal of the peak power amplifier. In this embodiment, a 50Ω 3dB 90° input coupler is used.

[0026] Carrier power amplifier: The output terminal is connected to the straight-through terminal of the 90° output coupler.

[0027] Peak power amplifier: The output terminal is connected to the coupling terminal of the 90° output coupler.

[0028] 90° output coupler: The isolation terminal is grounded through a switch, and the output terminal is used to output an amplified signal; the amplified signal is input to the load circuit of the subsequent stage. In this embodiment, a 3dB 90° output coupler is used.

[0029] Furthermore, the characteristic impedance parameters of the impedance element, the 90° input coupler, and the 90° output coupler are the same.

[0030] Furthermore, the drain supply voltage of the carrier power amplifier is different from that of the peak power amplifier; the drain supply voltage of the carrier PA is always lower than that of the peak PA.

[0031] During signal transmission, there are two scenarios: impedance matching and impedance mismatch. The operating states of an asymmetrically biased Doherty power amplifier include parallel mode and series mode, determined by the switch states. Switch states include open circuit and short circuit. When the switch is short-circuited, the asymmetrically biased Doherty power amplifier operates in parallel mode; when the switch is open-circuited, it operates in series mode. Figure 1 In this diagram, Input represents the input signal of the power amplifier; the two 3dB 90° output couplers indicate the 90° input coupler and 90° output coupler used in this invention; Mode-1 indicates parallel mode; Mode-2 indicates series mode; PA (Power Amplifier) ​​1 represents the carrier PA; PA2 represents the peak PA; and V... D1 V represents the drain supply voltage of the carrier PA. D2I1 represents the peak drain supply voltage of the PA, I2 represents the peak output current of the PA, and Z0 represents the impedance element. L Indicates load.

[0032] When an asymmetric biased Doherty power amplifier is under impedance matching conditions, its parallel and series modes exhibit the same performance. This embodiment uses the parallel mode as an example for analysis. The simplified circuit for the parallel mode under matching conditions is as follows: Figure 2 As shown in the figure, Coupler represents the coupler, V1 represents the output voltage of the carrier PA, V2 represents the output voltage of the peak PA, and Z... L Z represents the load impedance. L =Z0 indicates that the load impedance is the same as the coupler impedance under the matching condition.

[0033] Specifically, such as Figure 3 The diagram shows the voltage, current, and efficiency variations of an asymmetric biased Doherty power amplifier. This invention designs an asymmetric drain supply voltage scheme where the drain supply voltages of the carrier PA and the peak PA are different. The ratio of the drain supply voltages of the carrier PA and the peak PA is denoted as γ. V :

[0034] γ V =V D1 / V D2

[0035] The traditional Doherty Power Amplifier (DPA) model assumes that the carrier and peak transistors have the same current amplitude at the saturation power level. In reality, the current amplitudes of the carrier PA and peak PA at the saturation power level are not the same. Therefore, the maximum fundamental current ratio γ between the carrier PA and peak PA is introduced. C :

[0036] γ C =I 1_max / I 2_max

[0037] Among them, I 1_max I represents the maximum fundamental current of the carrier PA. 2_max This represents the maximum fundamental current of the peak PA. Through calculation, we can obtain:

[0038]

[0039] As can be seen from the formula, the ratio of the maximum fundamental current between the carrier PA and the peak PA is determined by the ratio of the asymmetric drain bias voltage γ. V Decide.

[0040] Furthermore, compared to traditional symmetrical DPAs, the asymmetrical biased Doherty power amplifier designed in this invention has an extended OBO (Output Back-Off) range, i.e. Figure 3 OBO Range. Assuming the peak PA is on, and the normalized input of the circuit is β, the peak PA output current is 0. The output power at the back-off point of the asymmetric bias Doherty amplifier, i.e., the back-off power, corresponds to... Figure 3 At the point of back-off, the value of the output current I1 of the carrier PA is I. 1_bo The calculation formula is:

[0041]

[0042] Furthermore, through derivation, we obtain:

[0043]

[0044] As can be seen from the formula, the asymmetric drain bias voltage γ V This also affects the turn-on point of the peak PA. The peak PA is in the on state and the normalized input of the circuit is γ. V When the current is 2 / 2, the peak power amplifier output current is 0.

[0045] Calculate the saturation power P of the asymmetric biased Doherty power amplifier. sat To assess the OBO range. sat correspond Figure 3 Saturation point, P sat The formula is:

[0046] P sat =0.5(V) D1 I 1_max +V D2 I 2_max )

[0047] Output power P of an asymmetric biased Doherty power amplifier at the OBO power level bo The calculation formula is:

[0048] P bo =0.5V D1 I 1bo

[0049] Furthermore, the formula for the OBO range Δ of the asymmetric biased Doherty power amplifier is:

[0050] Δ = 10log(P) sat / P bo ) = 20log(2 / γ V)

[0051] As can be seen from the formula, the OBO range of the asymmetric bias Doherty power amplifier designed in this invention is determined only by the ratio of the supply voltage of the carrier PA to the peak PA.

[0052] Figure 4 The OBO range and γ were demonstrated. V The relationship is shown in the figure. When γ V When the value is 0.8, the asymmetric bias Doherty power amplifier designed in this invention achieves an OBO range of approximately 8dB. The 8dB OBO range allows the power amplifier to flexibly adjust the output power within a certain range according to the changes in the input signal power. Furthermore, at this time, the input-output characteristics of the amplifier are closer to linear, which can effectively reduce signal distortion when processing signals with peak-to-average power ratio (PAPR) and improve indicators such as adjacent channel leakage ratio.

[0053] When the load impedance of an asymmetric biased Doherty power amplifier is mismatched, there are differences between the parallel mode and the series mode.

[0054] Specifically, the efficiency responses of parallel and series connections are complementary. For example... Figure 5 As shown, in parallel mode, the asymmetric bias Doherty power amplifier designed in this invention exhibits high saturation efficiency on the left side of the Smith circle and high back-off efficiency on the right side. In series mode, the asymmetric bias Doherty power amplifier designed in this invention exhibits high back-off power efficiency on the left side of the Smith circle and high saturation power efficiency on the right side. The right side of the Smith circle represents a high-impedance state where the normalized resistance is greater than 1. By switching the switching state to change the operating mode, the power amplifier performance of the asymmetric bias Doherty power amplifier is altered.

[0055] This embodiment uses a 20mil thick Rogers 4350B substrate and a CG2H40010F power amplifier for testing, with the operating frequency set to 2.0GHz; in order to obtain an 8dB OBO range (i.e., γ V (Approximately 0.8), the drain bias voltages of the carrier PA and the peak PA are set to 22V and 28V respectively, and the corresponding gate voltages of the carrier PA and the peak PA are -2.95V and -4.8V respectively.

[0056] The structure of the 90° input coupler and the 90° output coupler is as follows: Figure 6 As shown in the Coupler diagram, IMN represents the input matching network, OMN represents the output matching network, and the numbers in the diagram represent the ratio of the width to the length of the transmission line.

[0057] Furthermore, the carrier PA and peak PA have the same structure, both consisting of an input matching network (IMN), a transistor, and an output matching network (OMN), as shown in the specific structure below. Figure 6 As shown.

[0058] Under matched conditions, the analog drain efficiency (DE) of the asymmetric biased Doherty power amplifier designed in this invention in parallel and series modes is as follows: Figure 7 As shown, the saturated drain efficiency and the back-off drain efficiency at 8dB are both greater than 70% and 65% in each mode. Meanwhile, the simulated gain of the asymmetric biased Doherty power amplifier is greater than 15dB in each mode.

[0059] When an asymmetric biased Doherty power amplifier is under impedance mismatch conditions, the performance of its parallel and series modes is complementary.

[0060] Specifically, under mismatch conditions, the load impedance was tested by varying it in 45° phase steps along a 2:1 voltage standing wave ratio circle. The test results are as follows: Figure 8 , Figure 9 As shown.

[0061] like Figure 8 The figure shows the simulation results of the drain efficiency of the asymmetric biased Doherty power amplifier designed in this invention in parallel mode under impedance mismatch. The curves of different colors represent different load impedances in the voltage standing wave ratio (OSR) circle. It can be seen that when the load impedance is on the left side of the Smith chart, the amplifier has higher efficiency in saturation, but the output backoff range will be reduced; while when the load impedance is on the right side of the Smith chart, both the OBO range and the backoff efficiency can be maintained.

[0062] like Figure 9 The figure shows the simulation results of the drain efficiency of the asymmetric biased Doherty power amplifier designed in this invention in series mode under impedance mismatch. When the load impedance is located to the left of the Smith chart, it can maintain the expected OBO range and backoff drain efficiency.

[0063] Finally, it should be noted that the above description only depicts some embodiments of the present invention. For those skilled in the art, various changes, modifications, substitutions, and variations can be conceived of these embodiments without departing from the principles and spirit of the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents, and all the above-mentioned behaviors should be covered within the scope of protection of the present invention.

Claims

1. An asymmetric biased Doherty power amplifier with load mismatch resistance, characterized in that, include: 90° input coupler, carrier power amplifier, peak power amplifier, 90° output coupler, impedance element, switch; wherein: 90° Input Coupler: The input terminal is used to acquire the input signal, the isolation terminal is grounded through an impedance element, the through terminal is connected to the input terminal of the carrier power amplifier, and the coupling terminal is connected to the input terminal of the peak power amplifier; Carrier power amplifier: The output terminal is connected to the straight-through terminal of the 90° output coupler; Peak power amplifier: The output terminal is connected to the coupling terminal of the 90° output coupler; 90° output coupler: The isolation terminal is grounded via a switch, and the output terminal is used to output amplified signals; The asymmetric Doherty power amplifier with load mismatch resistance has two operating modes: parallel mode and series mode. The different modes are determined by the state of the switch. The switch states include open circuit and short circuit. When the switch is short circuit, the asymmetric Doherty power amplifier is in parallel mode. When the switch is open circuit, the asymmetric Doherty power amplifier is in series mode. When an asymmetric biased Doherty power amplifier is under impedance matching conditions, its parallel and series modes have the same performance, and the circuit exhibits the following relationship: in, This represents the ratio of the maximum fundamental current of the carrier power amplifier to that of the peak power amplifier. This represents the ratio of the drain supply voltage of the carrier power amplifier to that of the peak power amplifier; When an asymmetric biased Doherty power amplifier is under impedance mismatch conditions, the performance of its parallel and series modes is complementary.

2. The asymmetric biased Doherty power amplifier with load mismatch resistance according to claim 1, characterized in that, The characteristic impedance parameters of the impedance element, the 90° input coupler, and the 90° output coupler are the same.

3. The asymmetric biased Doherty power amplifier with load mismatch resistance according to claim 1, characterized in that, The drain supply voltage of the carrier power amplifier is lower than that of the peak power amplifier.

4. The asymmetric biased Doherty power amplifier with load mismatch resistance according to claim 1, characterized in that, The peak power amplifier is in the ON state and the normalized input of the circuit is At that time, the peak power amplifier output current is 0.

5. The asymmetric biased Doherty power amplifier with load mismatch resistance according to claim 1, characterized in that, The output power back-off range of the asymmetric bias Doherty power amplifier and The decision is made using the following formula: in, This indicates the output power back-off range.

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