Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof. The semiconductor device includes a substrate, a word line structure, a gate conductive layer, a contact and a lining layer. The word line structure is disposed in the substrate. The gate conductive layer is disposed on the word line structure. The contact is disposed on the word line structure. The lining layer is disposed between the gate conductive layer and the contact and covers a side surface of the gate conductive layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device including a liner and a method for forming the same. Background Art

[0002] Dynamic random access memory (DRAM) has attracted widespread attention due to its fast access speeds. However, as semiconductor devices continue to shrink, memory size continues to decrease to increase density and improve performance. However, this continued size reduction can lead to seams in the contacts formed, degrading the memory's electrical performance.

[0003] Although existing semiconductor devices and their formation methods have gradually met their intended uses, they still do not fully meet the requirements in all aspects. Therefore, there are still some problems to be overcome regarding semiconductor devices and their formation methods. Summary of the Invention

[0004] According to some embodiments of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, a wordline structure, a gate conductive layer, a contact, and a liner. The wordline structure is disposed in the substrate. The gate conductive layer is disposed on the wordline structure. The contact is disposed on the wordline structure. The liner is disposed between the gate conductive layer and the contact and covers the side surfaces of the gate conductive layer.

[0005] According to some embodiments of the present invention, a method for forming a semiconductor device is provided. The method includes providing a substrate; forming a wordline structure in the substrate; forming a gate conductive layer on the wordline structure; forming a trench in the gate conductive layer, the wordline structure, and the substrate; forming a liner in the trench so that the liner covers a side surface of the gate conductive layer; and forming a contact in the trench.

[0006] The semiconductor device and the method for forming the same according to the embodiments of the present invention can improve the electrical performance and reliability of the semiconductor device.

[0007] The semiconductor device and its formation method disclosed in the present invention can be applied to various types of electronic devices. To make the components and advantages disclosed in the present invention more clearly understood, various embodiments are given below with accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 19 The figures are cross-sectional schematic diagrams of semiconductor devices at different stages of a fabrication method according to some embodiments disclosed in the present invention.

[0009] Description of Figure Numbers:

[0010] 1,2,3:Semiconductor devices

[0011] 100:Substrate

[0012] 101,102,103,108: Dielectric layer

[0013] 104: first word line liner

[0014] 105: first word line conductive layer

[0015] 106: second word line liner

[0016] 107: second word line conductive layer

[0017] 109,110,210:Mask

[0018] 200: Gate conductive layer

[0019] 200S, 210S: side surface

[0020] 220: Groove

[0021] 220a, 220b, 300a, 300b, 410a, 410b: Width

[0022] 300: Lining

[0023] 310: upper part

[0024] 320: bottom

[0025] 400: Contact material

[0026] 410: Contact

[0027] IP: Ion Implantation Process

[0028] PP: Planarization process

[0029] STI: Isolation Structure

[0030] WLS: Word Line Structure DETAILED DESCRIPTION

[0031] like Figure 1 As shown, a substrate 100 may be provided. In some embodiments, substrate 100 may be, for example, a wafer, a semiconductor-on-insulator (SOI) substrate, or a bulk semiconductor substrate. In some embodiments, substrate 100 may be a multilayer substrate or a graded substrate. Substrate 100 may be an elemental semiconductor including silicon or germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or a combination thereof, but the present disclosure is not limited thereto. Substrate 100 may be a doped or undoped semiconductor substrate.

[0032] like Figure 1 As shown, an isolation structure STI can be formed in the substrate 100, and the active region of the semiconductor device is defined by the isolation structure STI. In some embodiments, the isolation structure STI may be a shallow trench isolation structure or other isolation structure. The isolation structure STI may include multiple dielectric layers. For example, the multiple dielectric layers may include a dielectric layer 101 and a dielectric layer 102 disposed on the dielectric layer 101. The dielectric layer may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, the like, or a combination thereof, but the present disclosure is not limited thereto. For example, the dielectric layer 101 may include silicon oxide, and the dielectric layer 102 may include silicon nitride. The dielectric layer 101 and / or the dielectric layer 102 may be formed in the substrate 100 by a removal process such as an etching process, a deposition process such as a chemical vapor deposition process, the like, or a combination thereof.

[0033] like Figure 1 As shown, a wordline structure (WLS) may be formed in substrate 100 and interposed between adjacent isolation structures (STI). In some embodiments, wordline structure WLS may be a buried wordline structure. Wordline structure WLS may serve as a wordline (or portion thereof) of a dynamic random access memory (DRAM). Wordline structure WLS may include a first dielectric layer 103 disposed in substrate 100, a wordline conductive structure disposed on first dielectric layer 103, and a second dielectric layer 108 disposed on the wordline conductive structure. First dielectric layer 103 may serve as a gate dielectric layer for the wordline. First dielectric layer 103 and second dielectric layer 108 may surround the wordline conductive structure. The materials and formation methods of first dielectric layer 103 and / or second dielectric layer 108 may be the same as or different from those of dielectric layer 101 and / or dielectric layer 102. First dielectric layer 103 may include silicon oxide, and second dielectric layer 108 may include silicon nitride.

[0034] The wordline conductive structure may include a first wordline liner 104, a first wordline conductive layer 105, a second wordline liner 106, and a second wordline conductive layer 107. In some embodiments, the first wordline liner 104 and the second wordline liner 106 may improve interfacial compatibility. The first wordline liner 104 may be disposed on the first dielectric layer 103. The first wordline conductive layer 105 may be disposed on the first wordline liner 104. The second wordline liner 106 may be disposed on the first wordline liner 104 and the first wordline conductive layer 105. The second wordline conductive layer 107 may be disposed on the second wordline liner 106. The second dielectric layer 108 may be disposed on the second wordline conductive layer 107.

[0035] The first wordline liner 104 and the second wordline liner 106 may comprise TiN, WSi, the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the first wordline conductive layer 105 and the second wordline conductive layer 107 may comprise a conductive material. For example, the conductive material may include polysilicon; amorphous silicon; a metal such as tungsten, copper, silver, gold, or cobalt; a metal nitride such as tungsten nitride or titanium nitride; a conductive metal oxide; or other suitable materials or combinations thereof. The first wordline conductive layer 105 may comprise tungsten, and the second wordline conductive layer 107 may comprise polysilicon. The first wordline liner 104, the first wordline conductive layer 105, the second wordline liner 106, and the second wordline conductive layer 107 may be formed by a deposition process such as a chemical vapor deposition process, a sputtering process, the like, or a combination thereof.

[0036] like Figure 1 As shown, a mask 109 and a mask 110 may be formed on the word line structure WLS and the isolation structure STI. In some embodiments, the mask 109 may include silicon nitride, and the mask 110 may include silicon oxide. The mask 109 and the mask 110 may be omitted.

[0037] like Figure 1 As shown, a gate conductive layer 200 can be formed on the wordline structure WLS and the isolation structure STI. In some embodiments, the gate conductive layer 200 can be disposed on the mask 110. If the mask 109 and the mask 110 are omitted, the gate conductive layer 200 can be disposed on the second dielectric layer 108 of the wordline structure WLS. The material and formation method of the gate conductive layer 200 can be the same as or different from the materials and formation methods of the first wordline conductive layer 105 and the second wordline conductive layer 107. The gate conductive layer 200 can include polysilicon.

[0038] like Figure 1 As shown, a patterned mask 210 may be formed on the gate conductive layer 200. Next, a removal process, such as an etching process, is performed on the gate conductive layer 200. For example, the patterned mask 210 is used as an etching mask, and the gate conductive layer 200 is etched by a dry etching process to pattern the gate conductive layer 200, thereby forming a trench 220 in the gate conductive layer 200, the mask 110, the mask 109, the word line structure WLS, and the substrate 100. In some embodiments, the trench 220 may penetrate the gate conductive layer 200 but not penetrate the word line structure WLS and the substrate 100, so as to expose the side surface 200S of the gate conductive layer 200, the top surface of the word line structure WLS, and the top surface of the substrate 100. The shape of the trench 220 can be controlled by adjusting the parameters of the etching process. For example, when viewed in a cross-sectional view, the trench 220 may have a rectangular outline, but the present disclosure is not limited thereto. The width 220a of the upper portion of the trench 220 away from the substrate 100 and the width 220b of the bottom portion of the trench 220 adjacent to the substrate 100 may be substantially the same (eg, Figure 1For example, when viewed in cross-section, the groove 220 may have a pentagonal profile. The upper width 220a of the groove 220 may be greater than the bottom width 220b of the groove 220 (as described later). Figure 8 and Figure 15 shown).

[0039] like Figure 2 As shown, a liner 300 is conformally formed in the trench 220. In some embodiments, the liner 300 may be disposed on the top and side surfaces of the mask 210, the side surfaces of the gate conductive layer 200, the top surface of the wordline structure WLS, and the top surface of the substrate 100. In some embodiments, the liner 300 may contact the first dielectric layer 103 and the second dielectric layer 108 of the wordline structure WLS. The material and formation method of the liner 300 may be the same as or different from the material and formation method of the dielectric layer 101 and / or the dielectric layer 102. The liner 300 may include silicon oxide or silicon nitride. In the normal direction of the substrate 100, the liner 300 may have a thickness greater than or equal to 1 nm and less than or equal to 30 nm. For example, the thickness of the liner 300 may be 1 nm, 3 nm, 5 nm, 10 nm, 20 nm, 30 nm, or any value therebetween or a range of values ​​consisting of any of the foregoing values, but the present disclosure is not limited thereto.

[0040] like Figure 3 As shown, a portion of the liner 300 is removed to expose the top surface of the substrate 100. In some embodiments, a horizontal portion of the liner 300 is removed to expose the top surface of the mask 210 and the top surface of the substrate 100. The portion of the liner 300 can be removed by an etching process such as dry etching.

[0041] like Figure 4 As shown, the liner 300 is etched back to remove the vertical portion of the liner 300. In the normal direction of the substrate 100, the top surface of the liner 300 may be higher than or flush with the top surface of the gate conductive layer 200. For example, the liner 300 may cover at least the side surface of the gate conductive layer 200. The liner 300 may further cover a portion of the side surface of the mask 210 to improve the process adjustability (for example, fault tolerance) of the etch-back process. The liner 300 may expose the side surface of the mask 210 to improve the process adjustability of performing subsequent planarization processes. In some embodiments, the liner 300 may be etched back by an etching process such as dry etching. As Figure 4As shown, the etch-back process of the liner 300 can further remove a portion of the wordline structure WLS and a portion of the substrate 100, causing the trench 220 to extend toward the substrate 100. Accordingly, after removing the horizontal portion of the liner 300, the etch-back process is performed to extend the depth of the trench 220, facilitating the removal of the horizontal portion of the liner 300. For example, before the etch-back process is performed, because the trench 220 may have a rectangular profile, the horizontal portion of the liner 300 may be more easily removed by the dry etching process.

[0042] like Figure 5 As shown, the filling contact material 400 is formed in the trench 220 (refer to Figure 4 ). In some embodiments, a contact material 400 is deposited in the trench 220. The material and formation method of the contact material 400 may be the same as or different from the material and formation method of the gate conductive layer 200. The contact material 400 may include polysilicon. Accordingly, since the liner 300 may cover the side surface 200S of the gate conductive layer 200, a seam in a subsequently formed contact may be avoided. For example, when the gate conductive layer 200 and the contact material 400 are of the same or similar material type (for example, the gate conductive layer 200 and the contact material 400 may include a silicon-based material such as polysilicon), the contact material 400 is more likely to be formed (for example, deposited or epitaxially grown) on the side surface 200S of the gate conductive layer 200 than on the second dielectric layer 108, the mask 109 or the mask 110. In other words, the formation rate of the contact material 400 on the side surface 200S of the gate conductive layer 200 is greater than the formation rate of the contact material 400 on the second dielectric layer 108, the mask 109, or the mask 110. As a result, the contact material 400 overhangs on the side surface 200S of the gate conductive layer 200. As a result, the contact material 400 is likely to seal prematurely at the side surface 200S of the gate conductive layer 200, and form a seam in the contact material 400 located in the trench 220.

[0043] In other words, the factor that affects the formation rate of the contact material 400 is the gate conductive layer 200, which is made of a material similar to the contact material 400. Therefore, the gate conductive layer 200 can be covered by the liner 300, thereby preventing the gate conductive layer 200 from affecting the formation rate of the contact material 400. Therefore, the present disclosure uses the liner 300 to reduce the seams in the contact, thereby improving the electrical performance (for example, reducing the resistance of the contact to increase the current) and reliability of the semiconductor device.

[0044] like Figure 6As shown, the contact material 400 is etched back so that the top surface of the contact material 400 is flush with the top surface of the liner 300. This improves the process adjustability of the subsequent planarization process. For example, it makes the planarization process easier to perform and / or increases the flatness of the surface after the planarization process.

[0045] like Figure 7 As shown, a planarization process PP is performed to make the top surface of the gate conductive layer 200 and the contact material 400 (see Figure 6 ) is flush with the top surface of the liner 300 to form a contact 410 in the groove 220 (refer to Figure 4 ) to obtain the semiconductor device 1. In some embodiments, the planarization process PP may include a chemical mechanical polishing (CMP) process or a wet removal process. For example, the wet removal process may use tetrahydrofuran (THF). The contact 410 may be disposed on the word line structure WLS, and the contact 410 may be in contact with the substrate 100. The contact 410 is in contact with the first dielectric layer 103 and the second dielectric layer 108 of the word line structure WLS. The top surface of the gate conductive layer 200, the top surface of the contact 410, and the top surface of the liner 300 may be flush. The upper width 410a of the contact 410 away from the substrate 100 may be greater than the bottom width 410b of the contact 410 adjacent to the substrate 100 to improve the process adjustability of the subsequent formation of the bit line structure on the contact 410.

[0046] Accordingly, since the liner 300 can be disposed between the gate conductive layer 200 and the contact 410 and can cover the side surface 200S of the gate conductive layer 200, the seam in the contact 410 can be reduced as described above. Furthermore, the capacitance of the semiconductor device 1 can be reduced. For example, the semiconductor device 1 can be further processed to form a dynamic random access memory.

[0047] In some embodiments, a bitline stack including a bitline conductive structure can be formed on a contact 410 in a semiconductor device 1. The bitline stack and contact 410 are then patterned to obtain a bitline structure. The bitline structure can serve as a bitline (or a portion thereof) of a dynamic random access memory (DRAM). Bitline spacers are then formed on the sidewalls of the bitline structure. Because the liner 300 is disposed between the gate conductive layer 200 and the contact 410, the liner 300 occupies the space previously used to form the bitline spacer. Therefore, by adjusting the material type of the liner 300, the capacitance of the semiconductor device 1 can be adjusted accordingly. For example, when the bitline spacer comprises silicon oxide and the liner 300 comprises silicon nitride, the liner 300 occupies a portion of the space previously used to form the bitline spacer, thereby reducing the amount of silicon oxide occupying the sidewalls of the bitline structure (and increasing the amount of silicon nitride occupying the sidewalls), thereby reducing the capacitance of the semiconductor device 1.

[0048] like Figure 8 As shown, the upper width 220a of the trench 220 may be greater than the bottom width 220b of the trench 220 to facilitate conformal formation of the liner 300 in the trench 220. For example, the trench 220 may have a pentagonal profile, a bullet-shaped profile, or other similar profiles to reduce the drop at the corners when conformally forming the liner 300, thereby improving the reliability of the liner 300.

[0049] like Figure 9 As shown, a liner 300 is formed in the trench 220. Figure 10 As shown, a portion of the liner 300 is removed to expose the top surface of the substrate 100. Figure 11 As shown, the liner 300 is etched back to remove the vertical portion of the liner 300. In some embodiments, the liner 300 is etched back without substantially removing the word line structure WLS and the substrate 100. Figure 12 As shown, the contact material 400 is deposited in the trench 220 (refer to Figure 11 ). Figure 13 As shown, the contact material 400 is etched back so that the top surface of the contact material 400 is flush with the top surface of the liner 300. Figure 14 As shown, a planarization process PP is performed to make the top surface of the gate conductive layer 200 and the contact material 400 (see Figure 13 ) is flush with the top surface of the liner 300 to form a contact 410 in the groove 220 (refer to Figure 11 ) to obtain a semiconductor device 2.

[0050] like Figure 15 As shown, continue Figure 10An ion implantation process IP is performed on the liner 300 to remove a portion of the upper portion 310 of the liner 300. In some embodiments, the ion implantation process IP is performed using helium (He) ions, neon (Ne) ions, argon (Ar) ions, krypton (Kr) ions, xenon (Xe) ions, or a combination thereof to avoid using radioactive radon (Rn) ions. For example, the ion implantation process IP can be performed using xenon (Xe) ions, which have a relatively large atomic weight, to effectively remove a portion of the liner 300 and shape the liner 300.

[0051] After performing the ion implantation process IP on the liner 300, the upper portion 310 of the liner 300 may have a curved profile when viewed in a cross-sectional view. In some embodiments, the curved profile of the upper portion 310 of the liner 300 on a sidewall of the trench 220 protrudes outward toward the opposite sidewall of the trench 220. In some embodiments, the bottom 320 of the liner 300 may have a curved profile. After performing the ion implantation process IP, the upper width 220a of the trench 220 may be widened. For example, the upper width 220a of the trench 220 may be larger than the bottom width 220b of the trench 220 to facilitate reducing the aspect ratio of the trench 220 that is subsequently filled with contact material. Therefore, performing the ion implantation process IP can avoid the formation of seams in the subsequently formed contacts. The step of etching back the liner 300 can be omitted, and a portion of the wordline structure WLS and a portion of the substrate 100 are not substantially removed.

[0052] Performing the ion implantation process IP can remove the remaining portion of the liner 300 that may be present on the bottom surface of the trench 220. Therefore, performing the ion implantation process IP can improve the process adjustability of the horizontal portion removal process of the liner 300. In other words, since the ion implantation process IP can remove the remaining portion of the liner 300 that may be present on the bottom surface of the trench 220, even if the remaining portion of the liner 300 may be present on the bottom surface of the trench 220, it can be removed by the ion implantation process IP.

[0053] like Figure 16 As shown, the contact material 400 is deposited in the trench 220 (refer to Figure 15 ). Figure 17 As shown, the contact material 400 is etched back so that the top surface of the contact material 400 is flush with the top surface of the liner 300. Figure 18As shown, a wet cleaning process is performed to remove the liner 300 covering the mask 210, so that the top surface of the liner 300 is flush with the top surface of the gate conductive layer 200. In some embodiments, the wet cleaning process may use a cleaning solution such as phosphoric acid. This can improve the process tunability of the subsequent planarization process. For example, it can make the planarization process easier to perform and / or increase the flatness of the surface after the planarization process.

[0054] like Figure 19 As shown, a planarization process PP is performed to make the top surface of the gate conductive layer 200 and the contact material 400 (see Figure 18 ) is flush with the top surface of the liner 300 to form a contact 410 in the groove 220 (refer to Figure 15 ), and obtain the semiconductor device 3. Figure 19 As shown, the upper width 300a of the liner 300 may be greater than the bottom width 300b of the liner 300. Since the liner 300 is thicker near the gate conductive layer 200, the liner 300 can effectively separate the contact 410 from the gate conductive layer 200.

[0055] Accordingly, the semiconductor device and its formation method disclosed herein can set a liner 300 between the gate conductive layer 200 and the contact 410, and make the liner 300 cover the side surface 200S of the gate conductive layer 200 to reduce the seam formed in the contact 410 and / or reduce the capacitance in the semiconductor device, so as to improve the electrical performance and reliability of the semiconductor device.

[0056] The above summarizes several embodiments. Those skilled in the art can better understand the concepts of the embodiments of the present disclosure and can design or modify other processes and structures based on these embodiments to achieve the same purposes and / or advantages. At the same time, it is understood that such equivalent processes and structures do not depart from the spirit and scope of the present disclosure and that various changes, substitutions and replacements can be made within the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a substrate; a word line structure, disposed in the substrate; a gate conductive layer disposed on the word line structure; a contact disposed on the word line structure; as well as A liner is disposed between the gate conductive layer and the contact and covers a side surface of the gate conductive layer.

2. The semiconductor device according to claim 1, wherein The top surface of the gate conductive layer, the top surface of the contact and the top surface of the liner are flush.

3. The semiconductor device according to claim 1, wherein An upper width of the lining layer is greater than a bottom width of the lining layer.

4. The semiconductor device according to claim 1, wherein The word line structure includes: a first dielectric layer disposed in the substrate; a word line conductive structure, disposed on the first dielectric layer; and a second dielectric layer disposed on the word line conductive layer, and the first dielectric layer and the second dielectric layer surround the word line conductive layer; The liner is in contact with the second dielectric layer.

5. A method for forming a semiconductor device, characterized in that: include: providing a substrate; forming a word line structure in the substrate; forming a gate conductive layer on the word line structure; forming a trench in the gate conductive layer, the word line structure and the substrate; forming a liner in the trench so that the liner covers a side surface of the gate conductive layer; as well as A contact is formed in the trench.

6. The forming method according to claim 5, wherein: Forming the liner in the trench includes: conformally forming the liner in the trench; and A portion of the liner is removed to expose the top surface of the substrate.

7. The method for forming a semiconductor device according to claim 6, wherein: Forming the liner in the trench further includes: The liner layer is etched back so that a top surface of the liner layer is higher than or flush with a top surface of the gate conductive layer.

8. The method for forming a semiconductor device according to claim 7, wherein: The liner is etched back to remove a portion of the word line structure and a portion of the substrate, so that the trench extends toward the substrate.

9. The method for forming a semiconductor device according to claim 6, wherein: Forming the liner in the trench further includes: An ion implantation process is performed on the liner to remove a portion of the liner so that an upper width of the trench is greater than a bottom width of the trench.

10. The method for forming a semiconductor device according to claim 9, wherein: After the ion implantation process is performed on the liner, an upper portion of the liner has a curved profile.

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