Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and the semiconductor device comprises a trench which is formed in a substrate; a first gate filled in the bottom of the trench; and a second gate disposed over the first gate, where each of the first gate and the second gate includes an oxygen material, and an oxygen content of the first gate is greater than an oxygen content of the second gate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0049280, filed on April 12, 2024, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a buried gate and a method of manufacturing the same. Background Art

[0004] Metal gate electrodes are used to ensure high performance of transistors. Specifically, buried-gate transistors require controlled threshold voltages to achieve high-performance operation. Gate-induced drain leakage (GIDL) can significantly affect the performance of buried-gate transistors. Summary of the Invention

[0005] Embodiments of the present invention are directed to a semiconductor device having improved electrical characteristics.

[0006] According to one embodiment of the present invention, a semiconductor device includes: a trench formed in a substrate; a first gate filled in a lower portion of the trench; and a second gate above the first gate, wherein each of the first gate and the second gate contains an oxygen material, and the oxygen content of the first gate is greater than the oxygen content of the second gate.

[0007] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a trench in a substrate; forming a first gate filling a lower portion of the trench; forming a second gate above the first gate; forming a sacrificial layer above the second gate; replacing a surface of the second gate with silicon oxide by performing heat treatment; and removing the sacrificial layer and the silicon oxide, wherein each of the first gate and the second gate contains an oxygen material, and the oxygen content of the first gate is greater than the oxygen content of the second gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.

[0009] Figure 2A According to the first embodiment of the present invention Figure 1 The cross-sectional view of the semiconductor device is taken along line AA'.

[0010] Figure 2B According to the first embodiment of the present invention Figure 1FIG. 1 is a cross-sectional view of the semiconductor device taken along line BB′.

[0011] Figures 3 to 13 are cross-sectional views showing semiconductor devices according to second to twelfth embodiments of the present invention, respectively.

[0012] Figure 14 is a plan view showing a semiconductor device according to a thirteenth embodiment of the present invention.

[0013] Figure 15 According to the thirteenth embodiment of the present invention Figure 14 FIG. 1 is a cross-sectional view of the semiconductor device taken along line II′.

[0014] 16A to 16D 1 and 2 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

[0015] 17A to 17E 4 is a cross-sectional view showing a process of manufacturing a semiconductor device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0016] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be embodied in different forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to make this disclosure thorough and complete and to fully convey the scope of the present invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in the various figures and embodiments of the present invention.

[0017] The drawings are not necessarily drawn to scale, and in some cases, the proportions may be exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or on a substrate, it may refer not only to a case where the first layer is directly formed on the second layer or substrate, but also to a case where a third layer exists between the first and second layers or between the substrates.

[0018] In the following embodiments of the present invention, the threshold voltage Vt may depend on the flatband voltage VFB. The flatband voltage VFB may depend on the work function. The work function can be designed using a variety of methods. For example, the work function can be adjusted by the material of the gate electrode and the material between the gate electrode and the channel. The flatband voltage can be shifted by increasing or decreasing the work function. A high work function can shift the flatband voltage in a positive direction, while a low work function can shift the flatband voltage in a negative direction. As described above, the threshold voltage can be adjusted by shifting the flatband voltage. According to embodiments of the present invention, the threshold voltage can be adjusted by shifting the flatband voltage even if the channel concentration is reduced or the channel doping process is skipped.

[0019] In the following embodiments of the present invention, a buried gate structure may be arranged in a trench. The buried gate structure may include a gate dielectric layer and a gate electrode. The gate dielectric layer may cover the surface of the trench, and the gate electrode may fill a portion of the trench above the gate dielectric layer. Therefore, the gate electrode may be referred to as a "buried gate electrode". The gate electrode may include a lower buried gate LBG and an upper buried gate UBG. The lower buried gate may fill the lower portion of the trench, and the upper buried gate may fill the upper portion of the trench above the lower buried gate. As described above, the gate electrode may be a dual-gate electrode, wherein the upper buried gate is arranged above the lower buried gate. The lower buried gate may overlap with the channel, and the upper buried gate may overlap with the first doped region and the second doped region (i.e., the source / drain region).

[0020] Figure 1 is a plan view showing a semiconductor device 100 according to an embodiment of the present invention. Figure 2A According to the first embodiment of the present invention Figure 1 The cross-sectional view of the semiconductor device 100 is taken along line AA′. Figure 2B According to the first embodiment of the present invention Figure 1 The cross-sectional view of the semiconductor device 100 is taken along line BB′.

[0021] See also Figure 1 、 Figure 2A and Figure 2B The semiconductor device 100 may include a substrate 101, and a buried gate structure 100G, a first doping region 110, and a second doping region 111 embedded in the substrate 101. The buried gate structure 100G and the first doping region 110 and the second doping region 111 may form a cell transistor. Due to the buried gate structure, the cell transistor may improve short channel effects.

[0022] The semiconductor device 100 may be part of a memory cell. For example, the semiconductor device 100 may be part of a memory cell of a dynamic random access memory (DRAM). The semiconductor device 100 may include a bit line BL and a memory storage element CAP electrically connected to the substrate 101. The bit line BL may be coupled to the first doped region 110, and the memory storage element CAP may be coupled to the second doped region 111. The bit line BL and the memory storage element CAP may be arranged at a higher level than the buried gate structure 100G. The bit line BL and the memory storage element CAP may be arranged at different levels. The memory storage element CAP may be arranged at a higher level than the bit line BL. The memory storage element CAP may include a capacitor.

[0023] The substrate 101 may comprise a material suitable for semiconductor processing. The substrate 101 may comprise a semiconductor substrate. The substrate 101 may comprise a material comprising silicon. The substrate 101 may comprise silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. The substrate 101 may also comprise other semiconductor materials, such as germanium. The substrate 101 may comprise a III-V semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). The substrate 101 may comprise a silicon-on-insulator (SOI) substrate.

[0024] An isolation layer 102 and an active region 103 may be formed over the substrate 101. The active region 103 may be defined by the isolation layer 102. The active region 103 may have a major axis and a minor axis. The active region 103 may be tilted diagonally. A pair of buried gate structures 100G spaced apart from each other may be formed in one active region 103. A first doped region 110 may be formed in the active region 103 between the pair of buried gate structures 100G. A second doped region 111 may be formed in the active region 103 outside each buried gate structure 100G. This embodiment may present a "6F2" structure including a pair of buried gate structures 100G, one first doped region 110, and two second doped regions 111 in one active region.

[0025] The isolation layer 102 may be a shallow trench isolation (STI) region formed by a trench etching process. The isolation layer 102 may be formed by filling the isolation trench 102T with a dielectric material. The isolation layer 102 may include silicon oxide, silicon nitride, or a combination thereof.

[0026] Two trenches 105 may be formed in the substrate 101. Each trench 105 may be formed by using the hard mask layer 104 as an etch barrier and etching the substrate 101. Figure 1 From the perspective of the top view of FIG, each trench 105 may have a linear shape extending along the first direction D1. Each trench 105 may have a shape of a line intersecting the active area 103 and the isolation layer 102. The trenches 105 may be spaced apart from each other in the second direction D2. The first direction D1 may be perpendicular to the second direction D2. The trenches 105 may have a depth shallower than that of the isolation trenches 102T. According to another embodiment of the present invention, the lower portion of the trench 105 may have an arc line. The trench 105 may be a space for forming the buried gate structure 100G. Therefore, the trench 105 may be referred to as a "gate trench 105."

[0027] The first doping region 110 and the second doping region 111 may be formed in the active region 103. The first doping region 110 and the second doping region 111 may be regions doped with conductive dopants. For example, the conductive dopants may include phosphorus (P), arsenic (As), antimony (Sb), or boron (B). The first doping region 110 and the second doping region 111 may be doped with dopants of the same conductivity type. The first doping region 110 and the second doping region 111 may be disposed in the active region 103 on both sides of the trench 105. The first doping region 110 and the second doping region 111 may be spaced apart from each other by the trench 105. The bottom surfaces of the first doping region 110 and the second doping region 111 may be disposed at a predetermined depth from the top surface of the active region 103. The bottom surfaces of the first doping region 110 and the second doping region 111 may be higher than the bottom surface of the trench 105. The first doping region 110 may be referred to as a "first source / drain region 110," and each second doping region 111 may be referred to as a "second source / drain region 111." A channel may be defined between the first doping region 110 and each of the second doping regions 111 by the buried gate structure 100G. The channel may be defined along the outline of the trench 105.

[0028] The trench 105 may include a first trench T1 and a second trench T2. The first trench T1 may be formed in the active area 103. The second trench T2 may be formed in the isolation layer 102. The trench 105 may extend continuously from the first trench T1 to the second trench T2. In the trench 105, the bottom surface of the first trench T1 may be set at a higher level than the bottom surface of the second trench T2. The height difference between the first trench T1 and the second trench T2 may be formed as the isolation layer 102 is recessed. Therefore, the second trench T2 may include a recessed region R having a lower bottom surface than the first trench T1. Due to the height difference between the first trench T1 and the second trench T2, a fin 103F may be formed in the active area 103. Therefore, the active area 103 may include the fin 103F.

[0029] As described above, the fin 103F may be formed under the first trench T1, and the sidewall of the fin 103F may be exposed by the recessed isolation layer 102F. The fin 103F may form a portion of a channel (not shown). The fin 103F may increase the channel width and improve electrical characteristics.

[0030] According to another embodiment of the present invention, the fin 103F may be omitted.

[0031] The buried gate structure 100G may be embedded in the trench 105. The buried gate structure 100G may be disposed in the active region 103 between the first doping region 110 and the second doping region 111 and extend into the isolation layer 102. In the buried gate structure 100G, the bottom surface of the portion disposed in the active region 103 and the bottom surface of the portion disposed in the isolation layer 102 may be disposed at different levels. When the fin 103F is omitted, the bottom surface of the portion disposed in the active region 103 and the bottom surface of the portion disposed in the isolation layer 102 may be disposed at the same level in the buried gate structure 100G.

[0032] The buried gate structure 100G may include: a gate dielectric layer 106 covering the bottom surface and sidewalls of the trench 105, and a lower buried gate LBG, an upper buried gate UBG, and a capping layer 109 sequentially stacked on the gate dielectric layer 106 to fill the trench 105. The lower buried gate LBG may be referred to as a "first gate LBG" or a "first buried conductive layer LBG." The upper buried gate UBG may be referred to as a "second gate UBG" or a "second buried conductive layer UBG."

[0033] The gate dielectric layer 106 may be conformally formed on the bottom and inner surface of the trench 105. The gate dielectric layer 106 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. A high-k material may include a material having a dielectric constant greater than that of silicon oxide. For example, a high-k material may include a material having a dielectric constant greater than approximately 3.9. As another example, a high-k material may include a material having a dielectric constant greater than approximately 10. As another example, a high-k material may include a material having a dielectric constant between approximately 10 and 30. The high-k material may include at least one metal element. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to another embodiment of the present invention, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. Other known high-k materials may be used as the high-k material. The gate dielectric layer 106 may include a metal oxide.

[0034] The top surface of the lower buried gate LBG may be disposed at a lower level than the bottom surfaces of the first doping region 110 and the second doping region 111. The lower buried gate LBG may include a stacked structure of a first barrier layer 107 and a first gate electrode 108. The top surfaces of the first barrier layer 107 and the first gate electrode 108 may be at the same level. The first gate electrode 108 may be formed on the first barrier layer 107. The first barrier layer 107 may have a liner shape, and the first gate electrode 108 may have a block shape. The bottom surface and outer surface of the first gate electrode 108 may be surrounded by the first barrier layer 107.

[0035] The first barrier layer 107 may be used to supply oxygen to the first gate electrode 108. The first barrier layer 107 may include a metal-based oxygen material (i.e., an oxygen-containing material). The first barrier layer 107 may be referred to as an "oxygen supply layer 107." The first barrier layer 107 may include a plurality of layers. The first barrier layer 107 may be a multilayer including a metal nitride oxygen-containing material. The first barrier layer 107 may be a three-layer including a metal nitride oxygen-containing material. The first barrier layer 107 may include a stacked structure of a first metal oxynitride 107A, a metal nitride 107B, and a second metal oxynitride 107C. For example, the first barrier layer 107 may include a stacked structure of a first titanium oxynitride 107A (TiON), a first titanium nitride 107B (TiN), and a second titanium oxynitride 107C (TiON).

[0036] According to another embodiment of the present invention, the first barrier layer 107 may include a stack structure of a first metal nitride 107A, a metal oxynitride 107B, and a second metal nitride 107C. For example, the first barrier layer 107 may include a stack structure of a first titanium nitride 107A (TiN), a titanium oxynitride 107B (TiON), and a second titanium nitride 107C (TiN).

[0037] According to another embodiment of the present invention, the first barrier layer 107 may be a triple layer including a metal nitride and a metal oxide. The first barrier layer 107 may include a stacked structure of a first metal nitride 107A, a metal oxide 107B, and a second metal nitride 107C. For example, the first barrier layer 107 may include a stacked structure of a first titanium nitride 107A (TiN), a titanium oxide 107B (TiO), and a second titanium nitride 107C (TiN).

[0038] According to another embodiment of the present invention, the first barrier layer 107 may include a stack structure of metal nitride and metal oxide. For example, the first barrier layer 107 may include a stack structure of titanium nitride (TiN) and titanium oxide (TiO).

[0039] The first gate electrode 108 may have a high work function. Here, a high work function may refer to a work function greater than the mid-gap work function of silicon. A low work function may refer to a work function less than the mid-gap work function of silicon. Specifically, a high work function may have a work function greater than approximately 4.5 eV, and a low work function may have a work function less than approximately 4.5 eV.

[0040] According to another embodiment of the present invention, the first gate electrode 108 may have an increased high work function. The first gate electrode 108 may include a metal nitride. The first gate electrode 108 may be referred to as a "first conductive layer." The first gate electrode 108 may include a metal nitride oxygen-containing material. The first gate electrode 108 may include a metal nitride with a controlled oxygen content. For example, the first gate electrode 108 may include high-oxygen titanium nitride (high-oxygen TiN). Titanium nitride may have a high work function, and the titanium nitride may contain oxygen to further increase the work function of the titanium nitride. The oxygen content of high-oxygen titanium nitride (high-oxygen TiN) may be greater than the oxygen content of titanium nitride (TiN). When oxygen in the first barrier layer 107 diffuses into the first gate electrode 108 during the heat treatment, high-oxygen titanium nitride (high-oxygen TiN) may be formed. The oxygen content of high-oxygen titanium nitride (high-oxygen TiN) can be adjusted within a range in which the work function can be increased while maintaining the resistance of the first gate electrode 108.

[0041] An upper buried gate UBG may be formed above the lower buried gate LBG. The top surface of the upper buried gate UBG may be set at a level lower than the top surface of the active area 103 including the first doped region 110 and the second doped region 111. The upper buried gate UBG may be formed of a low-resistance material to reduce the gate sheet resistance. The upper buried gate UBG may have a low work function. The upper buried gate UBG may include a metal nitride. The upper buried gate UBG may include a metal nitride with a controlled oxygen content. The upper buried gate UBG may include a metal nitride having a lower oxygen content in the film than the first gate electrode 108. For example, the upper buried gate 108 may include low-oxygen titanium nitride (low-oxygen TiN). Here, low-oxygen titanium nitride (low-oxygen TiN) may refer to titanium nitride having no oxygen or a minimal oxygen content in the film. The oxygen content of low-oxygen titanium nitride (low-oxygen TiN) may be less than the oxygen content of titanium nitride (TiN).

[0042] According to this embodiment of the present invention, titanium nitride (TiN) may have a titanium to nitrogen ratio of about 1:1 compared to high-oxygen titanium nitride or low-oxygen titanium nitride, that is, titanium nitride (TiN) may have a stoichiometric composition. Stoichiometric composition may refer to a state in which a compound has an ideal chemical composition ratio. According to this embodiment of the present invention, titanium nitride (TiN) having a stoichiometric composition may refer to titanium nitride in which oxygen influx is minimized during the manufacturing process.

[0043] The capping layer 109 may be used to protect the upper buried gate UBG. The capping layer 109 may fill the upper portion of the trench 105 above the upper buried gate UBG. The top surface of the capping layer 109 may be set at the same level as the top surface of the hard mask 104. The top surface of the capping layer 109 may be set at a level higher than the top surface of the substrate 101. According to another embodiment of the present invention, the top surface of the capping layer 109 may be set at the same level as the top surface of the substrate 101.

[0044] The capping layer 109 may include a dielectric material. The capping layer 109 may include silicon nitride, silicon oxynitride, or a combination thereof. According to another embodiment of the present invention, the capping layer 109 may include a combination of silicon nitride and silicon oxide. The capping layer 109 may include a silicon nitride liner and a spin-on dielectric (SOD) material.

[0045] As described above, according to this embodiment of the present invention, by adjusting the oxygen content of the lower buried gate LBG and the upper buried gate UBG, respectively, the lower buried gate LBG and the upper buried gate UBG can have a high work function and a low work function. In addition, compared to a dual-gate structure in which metal and silicon materials are stacked, this embodiment can reduce device resistance and improve refresh performance by forming the lower buried gate LBG and the upper buried gate UBG from metal materials.

[0046] Figures 3 to 13 1 are cross-sectional views showing semiconductor devices 200 to 1200 according to the second to twelfth embodiments of the present invention. In addition to the buried gate structure, Figures 3 to 13 Can include Figure 2A Same structure. Figures 3 to 13 The substrate 101, isolation layer 102, active region 103, hard mask layer 104, gate dielectric layer 106, capping layer 109, first doping region 110 and second doping region 111 shown may have the same Figure 2A The same materials and structures are used and will not be described again.

[0047] See also Figure 3 , the semiconductor device 200 according to the second embodiment of the present invention may include a substrate 101 and a buried gate structure 200G embedded in the substrate 101 .

[0048] The buried gate structure 200G may include a gate dielectric layer 106 covering a bottom surface and sidewalls of the trench 105 , and a lower buried gate LBG and an upper buried gate UBG sequentially stacked on the gate dielectric layer 106 to fill the trench 105 .

[0049] The top surface of the lower buried gate LBG may be disposed at a lower level than the bottom surfaces of the first doping region 110 and the second doping region 111. The lower buried gate LBG may include a stacked structure of a first barrier layer 201 and a first gate electrode 108. The top surfaces of the first barrier layer 201 and the first gate electrode 108 may be at the same level. The first gate electrode 108 may be formed on the first barrier layer 201. The first barrier layer 201 may have a liner shape, and the first gate electrode 108 may have a block shape. The bottom surface and outer surface of the first gate electrode 108 may be surrounded by the first barrier layer 201.

[0050] The first barrier layer 201 may be used to supply oxygen to the first gate electrode 108. The first barrier layer 201 may include a metal-based oxygen material. The first barrier layer 201 may be referred to as an "oxygen supply layer 201." The first barrier layer 201 may be a metal nitride oxygen-containing material. The first barrier layer 201 may include a metal oxynitride. For example, the first barrier layer 201 may be titanium oxynitride (TiON).

[0051] The first gate electrode 108 may have a high work function. Here, a high work function may refer to a work function greater than the mid-gap work function of silicon. A low work function may refer to a work function less than the mid-gap work function of silicon. Specifically, a high work function may have a work function greater than approximately 4.5 eV, and a low work function may have a work function less than approximately 4.5 eV.

[0052] According to another embodiment of the present invention, the first gate electrode 108 may have an increased high work function. The first gate electrode 108 may include a metal nitride. The first gate electrode 108 may include a metal nitride oxygen-containing material. The first gate electrode 108 may include a metal nitride with a controlled oxygen content. The first gate electrode 108 may include high-oxygen titanium nitride (high-oxygen TiN). Titanium nitride may have a high work function, and oxygen may be included in the titanium nitride to further increase the work function of the titanium nitride. The oxygen content of high-oxygen titanium nitride (high-oxygen TiN) may be greater than the oxygen content of titanium nitride (TiN). When oxygen in the first barrier layer 201 diffuses into the first gate electrode 108 during the heat treatment, high-oxygen titanium nitride (high-oxygen TiN) may be formed. The oxygen content of high-oxygen titanium nitride (high-oxygen TiN) can be adjusted within a range in which the work function can be increased while maintaining the resistance of the first gate electrode 108.

[0053] An upper buried gate UBG may be formed above the lower buried gate LBG. The top surface of the upper buried gate UBG may be set at a level lower than the top surface of the active area 103 including the first doped region 110 and the second doped region 111. The upper buried gate UBG may be formed of a low-resistance material to reduce the gate sheet resistance. The upper buried gate UBG may have a low work function. The upper buried gate UBG may include a metal nitride. The upper buried gate UBG may include a metal nitride with a controlled oxygen content. The upper buried gate UBG may include a metal nitride having a lower oxygen content in the film than the first gate electrode 108. For example, the upper buried gate 108 may include low-oxygen titanium nitride (low-oxygen TiN). Here, low-oxygen titanium nitride (low-oxygen TiN) may refer to titanium nitride having no oxygen or a minimal oxygen content in the film. The oxygen content of low-oxygen titanium nitride (low-oxygen TiN) may be less than the oxygen content of titanium nitride (TiN).

[0054] See also Figure 4 , the semiconductor device 300 according to the third embodiment of the present invention may include a substrate 101 and a buried gate structure 300G embedded in the substrate 101 .

[0055] The buried gate structure 300G may include a gate dielectric layer 106 covering the bottom surface and sidewalls of the trench 105 , and a lower buried gate LBG and an upper buried gate UBG sequentially stacked on the gate dielectric layer 106 to fill the trench 105 .

[0056] The top surface of the lower buried gate LBG may be disposed at a lower level than the bottom surfaces of the first doping region 110 and the second doping region 111. The lower buried gate LBG may include a stacked structure of a first barrier layer 107 and a first gate electrode 108. The top surfaces of the first barrier layer 107 and the first gate electrode 108 may be at the same level. The first gate electrode 108 may be formed on the first barrier layer 107. The first barrier layer 107 may have a liner shape, and the first gate electrode 108 may have a block shape. The bottom surface and outer surface of the first gate electrode 108 may be surrounded by the first barrier layer 107.

[0057] The first barrier layer 107 may be used to supply oxygen to the first gate electrode 108. The first barrier layer 107 may include a metal-based oxygen material. The first barrier layer 107 may be referred to as an "oxygen supply layer 107." The first barrier layer 107 may include a plurality of layers. The first barrier layer 107 may be a multilayer including a metal nitride oxygen-containing material. The first barrier layer 107 may be a three-layer including a metal nitride oxygen-containing material. Figure 2A As shown, the first barrier layer 107 may include a stack structure of a first metal oxynitride 107A, a metal nitride 107B, and a second metal oxynitride 107C. For example, the first barrier layer 107 may include a stack structure of a first titanium oxynitride 107A (TiON), a first titanium nitride 107B (TiN), and a second titanium oxynitride 107C (TiON).

[0058] According to another embodiment of the present invention, the first barrier layer 107 may include a stacked structure of a first metal nitride 107A, a metal oxynitride 107B, and a second metal nitride 107C. Figure 2A For example, the first barrier layer 107 may include a stack structure of a first titanium nitride 107A (TiN), a titanium oxynitride 107B (TiON), and a second titanium nitride 107C (TiN).

[0059] According to another embodiment of the present invention, the first barrier layer 107 may be a triple layer including metal nitride and metal oxide. Figure 2A As shown, the first barrier layer 107 may include a stack structure of a first metal nitride 107A, a metal oxide 107B, and a second metal nitride 107C. For example, the first barrier layer 107 may include a stack structure of a first titanium nitride 107A (TiN), a titanium oxide 107B (TiO), and a second titanium nitride 107C (TiN).

[0060] According to another embodiment of the present invention, the first barrier layer 107 may include a stack structure of metal nitride and metal oxide. For example, the first barrier layer 107 may include a stack structure of titanium nitride (TiN) and titanium oxide (TiO).

[0061] According to another embodiment of the present invention, Figure 3 As shown, the first barrier layer 107 may be a single layer of metal nitride oxygen-containing material. For example, the first barrier layer 107 may be a single layer of titanium oxynitride (TiON).

[0062] The first gate electrode 108 may have a high work function. Here, a high work function may refer to a work function greater than the mid-gap work function of silicon. A low work function may refer to a work function less than the mid-gap work function of silicon. Specifically, a high work function may have a work function greater than approximately 4.5 eV, and a low work function may have a work function less than approximately 4.5 eV.

[0063] According to another embodiment of the present invention, the first gate electrode 108 may have an increased high work function. The first gate electrode 108 may include a metal nitride. The first gate electrode 108 may include a metal nitride oxygen-containing material. The first gate electrode 108 may include a metal nitride with a controlled oxygen content. For example, the first gate electrode 108 may include high-oxygen titanium nitride (high-oxygen TiN). Titanium nitride may have a high work function, and oxygen may be included in the titanium nitride to further increase the work function of the titanium nitride. The oxygen content of high-oxygen titanium nitride (high-oxygen TiN) may be greater than the oxygen content of titanium nitride (TiN). When the oxygen in the first barrier layer 201 diffuses into the first gate electrode 108 during the heat treatment, high-oxygen titanium nitride (high-oxygen TiN) may be formed. The oxygen content of high-oxygen titanium nitride can be adjusted within a range that can increase the work function while maintaining the resistance of the first gate electrode 108.

[0064] An upper buried gate UBG may be formed above the lower buried gate LBG. The top surface of the upper buried gate UBG may be disposed at a lower level than the top surface of the active region 103 including the first doped region 110 and the second doped region 111. The upper buried gate UBG may have a stacked structure of a second barrier layer 301 and a second gate electrode 302. The top surfaces of the second barrier layer 301 and the second gate electrode 302 may be at the same level. The second gate electrode 302 may be formed above the second barrier layer 301. The second barrier layer 301 may have a liner shape, and the second gate electrode 302 may have a block shape. The bottom surface and outer surface of the second gate electrode 302 may be surrounded by the second barrier layer 301.

[0065] The second barrier layer 301 can be disposed between the first gate electrode 108 and the second gate electrode 302, and between the second gate electrode 302 and the gate dielectric layer 106. The second barrier layer 301 can serve as a barrier to separate the first gate electrode 108 and the second gate electrode 302 and prevent the migration of oxygen or metal ions therebetween. Furthermore, the second barrier layer 301 can be used to capture oxygen on the surface of the first gate electrode 108. The second barrier layer 301 can be referred to as an "oxygen capture layer 301." The second barrier layer 301 can capture oxygen on the surface of the first gate electrode 108 and prevent oxygen from diffusing into the second gate electrode 302. The second barrier layer 301 can also be referred to as an "oxygen diffusion prevention layer 301." The second barrier layer 301 can be formed in-situ or ex-situ with the second gate electrode 302. The second barrier layer 301 can comprise a silicon-based material. For example, the second barrier layer 301 can comprise polysilicon. The second barrier layer 301 can be adjusted to have a minimum thickness that allows it to capture oxygen without increasing device resistance. For example, the second barrier layer 301 may be formed to have a thickness of about 2 nm or less.

[0066] The second gate electrode 302 may be formed of a low-resistance material to reduce the gate sheet resistance. The second gate electrode 302 may have a low work function. The second gate electrode 302 may include a metal nitride. The second gate electrode may be referred to as a "second conductive layer". The second gate electrode 302 may include a metal nitride with a controlled oxygen content. The second gate electrode 302 may include a metal nitride having a lower oxygen content in the film than the first gate electrode 108. For example, the second gate electrode 302 may include low-oxygen titanium nitride (low-oxygen TiN). Here, low-oxygen titanium nitride may refer to titanium nitride that does not contain oxygen or has a minimal oxygen content in the film. The oxygen content of low-oxygen titanium nitride (low-oxygen TiN) may be less than the oxygen content of titanium nitride (TiN).

[0067] See also Figure 5 , the semiconductor device 400 according to the fourth embodiment of the present invention may include a substrate 101 and a buried gate structure 400G embedded in the substrate 101 .

[0068] The buried gate structure 400G may include a gate dielectric layer 106 covering the bottom surface and sidewalls of the trench 105 , and a lower buried gate LBG and an upper buried gate UBG sequentially stacked on the gate dielectric layer 106 to fill the trench 105 .

[0069] The top surface of the lower buried gate LBG may be disposed at a lower level than the bottom surfaces of the first doping region 110 and the second doping region 111. The lower buried gate LBG may include a stacked structure of a first barrier layer 107 and a first gate electrode 108. The top surfaces of the first barrier layer 107 and the first gate electrode 108 may be at the same level. The first gate electrode 108 may be formed on the first barrier layer 107. The first barrier layer 107 may have a liner shape, and the first gate electrode 108 may have a block shape. The bottom surface and outer surface of the first gate electrode 108 may be surrounded by the first barrier layer 107.

[0070] The first barrier layer 107 may be used to supply oxygen to the first gate electrode 108. The first barrier layer 107 may include a metal-based oxygen material. The first barrier layer 107 may be referred to as an "oxygen supply layer 107." The first barrier layer 107 may include a plurality of layers. The first barrier layer 107 may be a multilayer including a metal nitride oxygen-containing material. The first barrier layer 107 may be a three-layer including a metal nitride oxygen-containing material. Figure 2A As shown, the first barrier layer 107 may include a stack structure of a first metal oxynitride 107A, a metal nitride 107B, and a second metal oxynitride 107C. For example, the first barrier layer 107 may include a stack structure of a first titanium oxynitride 107A (TiON), a first titanium nitride 107B (TiN), and a second titanium oxynitride 107C (TiON).

[0071] According to another embodiment of the present invention, the first barrier layer 107 may include a stacked structure of a first metal nitride 107A, a metal oxynitride 107B, and a second metal nitride 107C. Figure 2A For example, the first barrier layer 107 may include a stack structure of a first titanium nitride 107A (TiN), a titanium oxynitride 107B (TiON), and a second titanium nitride 107C (TiN).

[0072] According to another embodiment of the present invention, the first barrier layer 107 may be a triple layer including metal nitride and metal oxide. Figure 2A As shown, the first barrier layer 107 may include a stack structure of a first metal nitride 107A, a metal oxide 107B, and a second metal nitride 107C. For example, the first barrier layer 107 may include a stack structure of a first titanium nitride 107A (TiN), a titanium oxide 107B (TiO), and a second titanium nitride 107C (TiN).

[0073] According to another embodiment of the present invention, the first barrier layer 107 may include a stack structure of metal nitride and metal oxide. For example, the first barrier layer 107 may include a stack structure of titanium nitride (TiN) and titanium oxide (TiO).

[0074] According to another embodiment of the present invention, the first barrier layer 107 may be a single layer of metal nitride oxygen-containing material, such as Figure 3 For example, the first barrier layer 107 may be a single layer of titanium oxynitride (TiON).

[0075] The first gate electrode 108 may have a high work function. Here, a high work function may refer to a work function greater than the mid-gap work function of silicon. A low work function may refer to a work function less than the mid-gap work function of silicon. Specifically, a high work function may have a work function greater than approximately 4.5 eV, and a low work function may have a work function less than approximately 4.5 eV.

[0076] According to another embodiment of the present invention, the first gate electrode 108 may have an increased high work function. The first gate electrode 108 may include a metal nitride. The first gate electrode 108 may include a metal nitride oxygen-containing material. The first gate electrode 108 may include a metal nitride with a controlled oxygen content. For example, the first gate electrode 108 may include high-oxygen titanium nitride (high-oxygen TiN). Titanium nitride may have a high work function, and oxygen may be included in the titanium nitride to further increase the work function of the titanium nitride. The oxygen content of high-oxygen titanium nitride (high-oxygen TiN) may be greater than the oxygen content of titanium nitride (TiN). When oxygen in the first barrier layer 201 diffuses into the first gate electrode 108 during the heat treatment, high-oxygen titanium nitride (high-oxygen TiN) may be formed. The oxygen content of high-oxygen titanium nitride (high-oxygen TiN) can be adjusted within a range in which the work function can be increased while maintaining the resistance of the first gate electrode 108.

[0077] The upper buried gate UBG may be formed above the lower buried gate LBG. The top surface of the upper buried gate UBG may be set at a level lower than the top surface of the active region 103 including the first doping region 110 and the second doping region 111. The upper buried gate UBG may have a stacked structure of a second barrier layer 401 and a second gate electrode 402. The second gate electrode 402 may be formed on the second barrier layer 401.

[0078] A second barrier layer 401 may be disposed between the first gate electrode 108 and the second gate electrode 402. The second barrier layer 401 may serve as a barrier to separate the first gate electrode 108 and the second gate electrode 402 and prevent oxygen or metal ions from migrating between them. Furthermore, the second barrier layer 401 may capture oxygen on the surface of the first gate electrode 108. The second barrier layer 401 may be referred to as an "oxygen capture layer 401." The second barrier layer 401 may capture oxygen on the surface of the first gate electrode 108 and prevent oxygen on the surface of the first gate electrode 104 from diffusing into the second gate electrode 402. The second barrier layer 401 may also be referred to as an "oxygen diffusion prevention layer 401." The second barrier layer 401 may be formed in-situ or ex-situ with the second gate electrode 402. The second barrier layer 401 may comprise a silicon-based material. For example, the second barrier layer 401 may comprise polycrystalline silicon. The second barrier layer 401 may be adjusted to have a minimum thickness sufficient to capture oxygen without increasing device resistance. For example, the second barrier layer 401 may be formed to a thickness of approximately 2 nm or less.

[0079] The second gate electrode 402 may be formed of a low-resistance material to reduce the gate sheet resistance. The second gate electrode 402 may have a low work function. The second gate electrode 402 may include a metal nitride. The second gate electrode 402 may include a metal nitride with a controlled oxygen content. The second gate electrode 402 may include a metal nitride having a lower oxygen content in the film than the first gate electrode 108. For example, the second gate electrode 402 may include low-oxygen titanium nitride (low-oxygen TiN). Here, low-oxygen titanium nitride may refer to titanium nitride that does not contain oxygen or has a minimal oxygen content in the film. The oxygen content of low-oxygen titanium nitride (low-oxygen TiN) may be less than the oxygen content of titanium nitride (TiN).

[0080] See also Figure 6 , a semiconductor device 500 according to the fifth embodiment of the present invention may include a substrate 101 and a buried gate structure 500G embedded in the substrate 101 .

[0081] The buried gate structure 500G may include a gate dielectric layer 106 covering the bottom surface and sidewalls of the trench 105 , and a lower buried gate LBG and an upper buried gate UBG sequentially stacked on the gate dielectric layer 106 to fill the trench 105 .

[0082] The top surface of the lower buried gate LBG may be disposed at a lower level than the bottom surfaces of the first doping region 110 and the second doping region 111. The lower buried gate LBG may include a stacked structure of a first barrier layer 107 and a first gate electrode 108. The top surfaces of the first barrier layer 107 and the first gate electrode 108 may be at the same level. The first gate electrode 108 may be formed on the first barrier layer 107. The first barrier layer 107 may have a liner shape, and the first gate electrode 108 may have a block shape. The bottom surface and outer surface of the first gate electrode 108 may be surrounded by the first barrier layer 107.

[0083] The first barrier layer 107 may be used to supply oxygen to the first gate electrode 108. The first barrier layer 107 may include a metal-based oxygen material. The first barrier layer 107 may be referred to as an "oxygen supply layer 107." The first barrier layer 107 may include a plurality of layers. The first barrier layer 107 may be a multilayer including a metal nitride oxygen-containing material. The first barrier layer 107 may be a three-layer including a metal nitride oxygen-containing material. Figure 2A As shown, the first barrier layer 107 may include a stack structure of a first metal oxynitride 107A, a metal nitride 107B, and a second metal oxynitride 107C. For example, the first barrier layer 107 may include a stack structure of a first titanium oxynitride 107A (TiON), a first titanium nitride 107B (TiN), and a second titanium oxynitride 107C (TiON).

[0084] According to another embodiment of the present invention, the first barrier layer 107 may include a stacked structure of a first metal nitride 107A, a metal oxynitride 107B, and a second metal nitride 107C. Figure 2A For example, the first barrier layer 107 may include a stack structure of a first titanium nitride 107A (TiN), a titanium oxynitride 107B (TiON), and a second titanium nitride 107C (TiN).

[0085] According to another embodiment of the present invention, the first barrier layer 107 may be a triple layer comprising metal nitride and metal oxide. Figure 2A As shown, the first barrier layer 107 may include a stack structure of a first metal nitride 107A, a metal oxide 107B, and a second metal nitride 107C. For example, the first barrier layer 107 may include a stack structure of a first titanium nitride 107A (TiN), a titanium oxide 107B (TiO), and a second titanium nitride 107C (TiN).

[0086] According to another embodiment of the present invention, the first barrier layer 107 may include a stack structure of metal nitride and metal oxide. For example, the first barrier layer 107 may include a stack structure of titanium nitride (TiN) or titanium oxide (TiO).

[0087] According to another embodiment of the present invention, the first barrier layer 107 may be a single layer of metal nitride oxygen-containing material, such as Figure 3 For example, the first barrier layer 107 may be a single layer of titanium oxynitride (TiON).

[0088] The first gate electrode 108 may have a high work function. Here, a high work function may refer to a work function greater than the mid-gap work function of silicon. A low work function may refer to a work function less than the mid-gap work function of silicon. Specifically, a high work function may have a work function greater than approximately 4.5 eV, and a low work function may have a work function less than approximately 4.5 eV.

[0089] According to another embodiment of the present invention, the first gate electrode 108 may have an increased high work function. The first gate electrode 108 may include a metal nitride. The first gate electrode 108 may include a metal nitride oxygen-containing material. The first gate electrode 108 may include a metal nitride with a controlled oxygen content. For example, the first gate electrode 108 may include high-oxygen titanium nitride (high-oxygen TiN). Titanium nitride may have a high work function, and oxygen may be included in the titanium nitride to further increase the work function of the titanium nitride. The oxygen content of high-oxygen titanium nitride (high-oxygen TiN) may be greater than the oxygen content of titanium nitride (TiN). When oxygen in the first barrier layer 201 diffuses into the first gate electrode 108 during the heat treatment, high-oxygen titanium nitride (high-oxygen TiN) may be formed. The oxygen content of high-oxygen titanium nitride (high-oxygen TiN) can be adjusted within a range in which the work function can be increased while maintaining the resistance of the first gate electrode 108.

[0090] The upper buried gate UBG may be formed above the lower buried gate LBG. The top surface of the upper buried gate UBG may be set at a level lower than the top surface of the active area 103 including the first doping region 110 and the second doping region 111. The upper buried gate UBG may have a stacked structure of a second barrier layer 401, a second gate electrode 501, a first oxygen capture layer 502, a third gate electrode 503, and a second oxygen capture layer 504.

[0091] A second barrier layer 401 may be disposed between the first gate electrode 108 and the second gate electrode 501. The second barrier layer 401 may serve as a barrier separating the first gate electrode 108 and the second gate electrode 501 from each other and may prevent oxygen or metal ions from migrating between them. Furthermore, the second barrier layer 401 may capture oxygen on the surface of the first gate electrode 108. The second barrier layer 401 may be referred to as an "oxygen capture layer 401." The second barrier layer 401 may capture oxygen on the surface of the first gate electrode 108 and prevent oxygen from diffusing into the second gate electrode 501 and the third gate electrode 503. The second barrier layer 401 may also be referred to as an "oxygen diffusion prevention layer 401." The second barrier layer 401 may be formed in situ or ex situ with the second gate electrode 501. The second barrier layer 401 may comprise a silicon-based material. For example, the second barrier layer 401 may comprise polysilicon. The second barrier layer 401 may be adjusted to have a minimum thickness sufficient to capture oxygen without increasing device resistance. For example, the second barrier layer 401 may be formed to have a thickness of about 2 nm or less.

[0092] The second gate electrode 501, the first oxygen capture layer 502, and the third gate electrode 503 may have a cylindrical shape. The second gate electrode 501 may cover the outer surface of the first oxygen capture layer 502. The first oxygen capture layer 502 may cover the outer surface of the third gate electrode 503. The third gate electrode 503 may cover the outer surface of the second oxygen capture layer 504. The top surfaces of the second gate electrode 501, the first oxygen capture layer 502, the third gate electrode 503, and the second oxygen capture layer 504 may be arranged at the same level.

[0093] The first oxygen capture layer 502 and the second oxygen capture layer 504 can capture oxygen in the second gate electrode 501 and the third gate electrode 503. Each of the first oxygen capture layer 502 and the second oxygen capture layer 504 can include a silicon material. Each of the first oxygen capture layer 502 and the second oxygen capture layer 504 can include polycrystalline silicon. The first oxygen capture layer 502 and the second oxygen capture layer 504 can be adjusted to have a thickness that does not increase the resistance of the device. Each of the first oxygen capture layer 502 and the second oxygen capture layer 504 can be adjusted to have a thickness of no more than about That is, each of the first oxygen capture layer 502 and the second oxygen capture layer 504 may be formed to have a thickness of approximately or smaller thickness.

[0094] The second gate electrode 501 and the third gate electrode 503 can be formed of a low resistance material to reduce the gate sheet resistance. Each of the second gate electrode 501 and the third gate electrode 503 can have a low work function. The second gate electrode 501 and the third gate electrode 503 can be referred to as a "second conductive layer and a third conductive layer". Each of the second gate electrode 501 and the third gate electrode 503 can include a metal nitride. Each of the second gate electrode 501 and the third gate electrode 503 can include a metal nitride with a controlled oxygen content. Each of the second gate electrode 501 and the third gate electrode 503 can include a metal nitride having an oxygen content in the film lower than that of the first gate electrode 108. For example, each of the second gate electrode 501 and the third gate electrode 503 can include low-oxygen titanium nitride (low-oxygen TiN). Here, low-oxygen titanium nitride can refer to titanium nitride that does not contain oxygen or has a minimal oxygen content in the film. The oxygen content of low-oxygen titanium nitride (low-oxygen TiN) can be less than the oxygen content of titanium nitride (TiN). The second gate electrode 501 can be formed to be approximately According to another embodiment of the present invention, the third gate electrode 503 may include a low-resistance metal material, such as tungsten (W) or molybdenum (Mo).

[0095] See also Figure 7 , the semiconductor device 600 according to the sixth embodiment of the present invention may include a substrate 101 and a buried gate structure 501G embedded in the substrate 101 .

[0096] The buried gate structure 501G may include Figure 2A According to another embodiment of the present invention, the buried gate structure 501G may include the same lower buried gate LBG as the buried gate structure 100G shown in FIG. Figure 3 The buried gate structure 200G shown has the same lower buried gate LBG.

[0097] The upper buried gate UBG of the buried gate structure 501G may include a stacked structure of a second gate electrode 501, a first oxygen capture layer 502, a third gate electrode 503, and a second oxygen capture layer 504. Figure 6 In addition to the buried gate structure 500G and the second barrier layer 401 shown, the second gate electrode 501 , the first oxygen capture layer 502 , the third gate electrode 503 and the second oxygen capture layer 504 may have the same structure.

[0098] See also Figure 8 , the semiconductor device 700 according to the seventh embodiment of the present invention may include a substrate 101 and a buried gate structure 510G embedded in the substrate 101 .

[0099] The buried gate structure 510G may include Figure 2AAccording to another embodiment of the present invention, the buried gate structure 510G may include the same lower buried gate LBG as the buried gate structure 100G shown in FIG. Figure 3 The buried gate structure 200G shown has the same lower buried gate LBG.

[0100] The upper buried gate UBG of the buried gate structure 510G may include a stack structure of a second barrier layer 401 , a second gate electrode 501 , a first oxygen capture layer 502 , and a third gate electrode 503 .

[0101] A second barrier layer 401 may be disposed between the first gate electrode 108 and the second gate electrode 501. The second barrier layer 401 may serve as a barrier to separate the first gate electrode 108 and the second gate electrode 501 and prevent oxygen or metal ions from migrating between them. Furthermore, the second barrier layer 401 may capture oxygen on the surface of the first gate electrode 108. The second barrier layer 401 may be referred to as an "oxygen capture layer 401." The second barrier layer 401 may capture oxygen on the surface of the first gate electrode 108 and prevent oxygen from diffusing into the second gate electrode 501 and the third gate electrode 503. The second barrier layer 401 may also be referred to as an "oxygen diffusion prevention layer 401." The second barrier layer 401 may be formed in situ or ex situ with the second gate electrode 501. The second barrier layer 401 may comprise a silicon-based material. For example, the second barrier layer 401 may comprise polysilicon. The second barrier layer 401 may be adjusted to have a minimum thickness sufficient to capture oxygen without increasing device resistance. For example, the second barrier layer 401 may be formed to have a thickness of about 2 nm or less.

[0102] The second gate electrode 501 and the first oxygen capture layer 502 may have a cylindrical shape. The second gate electrode 501 may cover the outer surface of the first oxygen capture layer 502. The first oxygen capture layer 502 may cover the outer surface of the third gate electrode 503. The top surfaces of the second gate electrode 501, the first oxygen capture layer 502, and the third gate electrode 503 may be arranged at the same level.

[0103] The first oxygen capture layer 502 can capture oxygen in the second gate electrode 501 and the third gate electrode 503. The first oxygen capture layer 502 can include a silicon material. The first oxygen capture layer 502 can include polysilicon. The first oxygen capture layer 502 can be adjusted to have a thickness that does not increase the resistance of the device. The first oxygen capture layer 502 can be adjusted to have a thickness of no more than about That is, the first oxygen capture layer 502 may be formed to have a thickness of approximately or smaller thickness.

[0104] The second gate electrode 501 and the third gate electrode 503 may be formed of a low resistance material to reduce the gate sheet resistance. Each of the second gate electrode 501 and the third gate electrode 503 may have a low work function. Each of the second gate electrode 501 and the third gate electrode 503 may include a metal nitride. Each of the second gate electrode 501 and the third gate electrode 503 may include a metal nitride with a controlled oxygen content. Each of the second gate electrode 501 and the third gate electrode 503 may include a metal nitride having an oxygen content in the film lower than that of the first gate electrode 108. For example, each of the second gate electrode 501 and the third gate electrode 503 may include low-oxygen titanium nitride (low-oxygen TiN). Here, low-oxygen titanium nitride may refer to titanium nitride that does not contain oxygen or has a minimal oxygen content in the film. The oxygen content of low-oxygen titanium nitride (low-oxygen TiN) may be less than the oxygen content of titanium nitride (TiN). The second gate electrode 501 may be formed to have approximately or smaller thickness.

[0105] According to another embodiment of the present invention, the third gate electrode 503 may include a metal material. For example, the third gate electrode 503 may include a low-resistance metal material, such as tungsten (W) or molybdenum (Mo).

[0106] See also Figure 9 , the semiconductor device 800 according to the eighth embodiment of the present invention may include a substrate 101 and a buried gate structure 511G embedded in the substrate 101 .

[0107] The buried gate structure 511G may include Figure 2A According to another embodiment of the present invention, the buried gate structure 511G may include the same lower buried gate LBG as the buried gate structure 100G shown in FIG. Figure 3 The buried gate structure 200G shown has the same lower buried gate LBG.

[0108] The upper buried gate UBG of the buried gate structure 511G may include a stacked structure of a second gate electrode 501, a first oxygen capture layer 502, and a third gate electrode 503. Figure 8 Except for the buried gate structure 510G and the second barrier layer 401 shown, the second gate electrode 501 , the first oxygen capture layer 502 , and the third gate electrode 503 may have the same structure.

[0109] See also Figure 10 , the semiconductor device 900 according to the ninth embodiment of the present invention may include a substrate 101 and a buried gate structure 520G embedded in the substrate 101 .

[0110] The buried gate structure 520G may include Figure 2AAccording to another embodiment of the present invention, the buried gate structure 520G may include the same lower buried gate LBG as the buried gate structure 100G shown in FIG. Figure 3 The buried gate structure 200G shown has the same lower buried gate LBG.

[0111] The upper buried gate UBG of the buried gate structure 520G may include a stack structure of a second barrier layer 401 , a second gate electrode 501 , and a first oxygen capture layer 504 .

[0112] A second barrier layer 401 may be disposed between the first gate electrode 108 and the second gate electrode 501. The second barrier layer 401 may serve as a barrier, separating the first gate electrode 108 and the second gate electrode 501 from each other and preventing oxygen or metal ions from migrating between them. Furthermore, the second barrier layer 401 may capture oxygen on the surface of the first gate electrode 108. The second barrier layer 401 may be referred to as an "oxygen capture layer 401." The second barrier layer 401 may capture oxygen on the surface of the first gate electrode 108 and prevent oxygen from diffusing into the second gate electrode 501 and the third gate electrode 503. The second barrier layer 401 may also be referred to as an "oxygen diffusion prevention layer 401." The second barrier layer 401 may be formed in-situ or ex-situ with the second gate electrode 501. The second barrier layer 401 may comprise a silicon-based material. For example, the second barrier layer 401 may comprise polycrystalline silicon. The second barrier layer 401 may be adjusted to have a minimum thickness sufficient to capture oxygen without increasing device resistance. For example, the second barrier layer 401 may be formed to a thickness of approximately 2 nm or less.

[0113] An outer surface of the first oxygen capture layer 504 may be covered by the second gate electrode 501. Top surfaces of the second gate electrode 501 and the first oxygen capture layer 504 may be disposed at the same level.

[0114] The first oxygen capture layer 504 can capture oxygen in the second gate electrode 501. The first oxygen capture layer 504 can include a silicon material. The first oxygen capture layer 504 can include polysilicon. The first oxygen capture layer 504 can be adjusted to have a thickness that does not increase the device resistance. The first oxygen capture layer 504 can be adjusted to have a thickness of no more than about That is, the first oxygen capture layer 504 may be formed to have a thickness of approximately or smaller thickness.

[0115] The second gate electrode 501 may be formed of a low-resistance material to reduce the gate sheet resistance. The second gate electrode 501 may have a low work function. The second gate electrode 501 may include a metal nitride. The second gate electrode 501 may include a metal nitride with a controlled oxygen content. The second gate electrode 501 may include a metal nitride having a lower oxygen content in the film than the first gate electrode 108. For example, the second gate electrode 501 may include low-oxygen titanium nitride (low-oxygen TiN). Here, low-oxygen titanium nitride may refer to titanium nitride that does not contain oxygen or has a minimal oxygen content in the film. The oxygen content of low-oxygen titanium nitride (low-oxygen TiN) may be lower than the oxygen content of titanium nitride (TiN).

[0116] See also Figure 11 , the semiconductor device 1000 according to the tenth embodiment of the present invention may include a substrate 101 and a buried gate structure 521G embedded in the substrate 101 .

[0117] The buried gate structure 521G may include Figure 2A According to another embodiment of the present invention, the buried gate structure 521G may include the same lower buried gate LBG as the buried gate structure 100G shown in FIG. Figure 3 The buried gate structure 200G shown has the same lower buried gate LBG.

[0118] The upper buried gate UBG of the buried gate structure 521G may include a stacked structure of a second gate electrode 501 and a first oxygen capture layer 504. Figure 10 In addition to the buried gate structure 520G and the second barrier layer 401 shown, the second gate electrode 501 and the first oxygen capture layer 504 may include the same structure.

[0119] See also Figure 12 , the semiconductor device 1100 according to the eleventh embodiment of the present invention may include a substrate 101 and a buried gate structure 600G embedded in the substrate 101 .

[0120] The buried gate structure 600G may include Figure 2A According to another embodiment of the present invention, the buried gate structure 600G may include the same lower buried gate LBG as the buried gate structure 100G shown in FIG. Figure 3 The buried gate structure 200G shown has the same lower buried gate LBG.

[0121] The upper buried gate UBG of the buried gate structure 600G may be formed above the lower buried gate LBG. The top surface of the upper buried gate UBG may be set at a level lower than the top surface of the active region 103 including the first doping region 110 and the second doping region 111. The upper buried gate UBG may include a stacked structure of a second barrier layer 401, a second gate dielectric layer 601, a second gate electrode 501, a first oxygen capture layer 502, a third gate electrode 503, and a second oxygen capture layer 504.

[0122] In addition to the second gate dielectric layer 601, the buried gate structure 600G may be Figure 6 The buried gate structure 500G shown is identical.

[0123] A second barrier layer 401 may be disposed between the first gate electrode 108 and the second gate electrode 501. The second barrier layer 401 may serve as a barrier to separate the first gate electrode 108 and the second gate electrode 501 and prevent oxygen or metal ions from migrating between them. Furthermore, the second barrier layer 401 may capture oxygen on the surface of the first gate electrode 108. The second barrier layer 401 may be referred to as an "oxygen capture layer 401." The second barrier layer 401 may capture oxygen on the surface of the first gate electrode 108 and prevent oxygen from diffusing into the second gate electrode 501 and the third gate electrode 503. The second barrier layer 401 may also be referred to as an "oxygen diffusion prevention layer 401." The second barrier layer 401 may comprise a silicon-based material. For example, the second barrier layer 401 may comprise polycrystalline silicon. The second barrier layer 401 may be adjusted to have a minimum thickness sufficient to capture oxygen without increasing device resistance. For example, the second barrier layer 401 may be formed to a thickness of approximately 2 nm or less.

[0124] The second gate dielectric layer 601 may be disposed between the second barrier layer 401 and the second gate electrode 501, and between the second gate electrode 501 and the gate dielectric layer 106. The second gate dielectric layer 601 may include silicon oxide. The second gate dielectric layer 601 may increase the total thickness of the gate dielectric layer overlapping the first doping region 110 and the second doping region 111, thereby reducing the leakage current and GIDL of the sidewall. The thickness of the second gate dielectric layer 601 may be adjusted to have a thickness of at least about or smaller thickness.

[0125] The second gate electrode 501, the first oxygen capture layer 502, and the third gate electrode 503 may have a cylindrical shape. The second gate electrode 501 may cover the outer surface of the first oxygen capture layer 502. The first oxygen capture layer 502 may cover the outer surface of the third gate electrode 503. The third gate electrode 503 may cover the outer surface of the second oxygen capture layer 504. The top surfaces of the second gate electrode 501, the first oxygen capture layer 502, the third gate electrode 503, and the second oxygen capture layer 504 may be arranged at the same level.

[0126] The first oxygen capture layer 502 and the second oxygen capture layer 504 can capture oxygen in the second gate electrode 501 and the third gate electrode 503. Each of the first oxygen capture layer 502 and the second oxygen capture layer 504 can include a silicon material. Each of the first oxygen capture layer 502 and the second oxygen capture layer 504 can include polycrystalline silicon. The first oxygen capture layer 502 and the second oxygen capture layer 504 can be adjusted to have a thickness that does not increase the resistance of the device. Each of the first oxygen capture layer 502 and the second oxygen capture layer 504 can be adjusted to have a thickness of no more than about That is, each of the first oxygen capture layer 502 and the second oxygen capture layer 504 may be formed to have a thickness of approximately or smaller thickness.

[0127] The second gate electrode 501 and the third gate electrode 503 may be formed of a low resistance material to reduce the gate sheet resistance. Each of the second gate electrode 501 and the third gate electrode 503 may have a low work function. Each of the second gate electrode 501 and the third gate electrode 503 may include a metal nitride. Each of the second gate electrode 501 and the third gate electrode 503 may include a metal nitride with a controlled oxygen content. Each of the second gate electrode 501 and the third gate electrode 503 may include a metal nitride having an oxygen content in the film lower than that of the first gate electrode 108. For example, each of the second gate electrode 501 and the third gate electrode 503 may include low-oxygen titanium nitride (low-oxygen TiN). Here, low-oxygen titanium nitride may refer to titanium nitride that does not contain oxygen or has a minimal oxygen content in the film. The oxygen content of low-oxygen titanium nitride (low-oxygen TiN) may be less than the oxygen content of titanium nitride (TiN). The second gate electrode 501 may be formed to be approximately According to another embodiment of the present invention, the third gate electrode 503 may include a low-resistance metal material, such as tungsten (W) or molybdenum (Mo).

[0128] See also Figure 13 , the semiconductor device 1200 according to the twelfth embodiment of the present invention may include a substrate 101 and a buried gate structure 601G embedded in the substrate 101 .

[0129] The buried gate structure 601G may include Figure 2A According to another embodiment of the present invention, the buried gate structure 601G may include the same lower buried gate LBG as the buried gate structure 100G shown in FIG. Figure 3 The buried gate structure 200G shown has the same lower buried gate LBG.

[0130] The upper buried gate UBG of the buried gate structure 601G may include a stacked structure of a second gate dielectric layer 601, a second gate electrode 501, a first oxygen capture layer 502, a third gate electrode 503, and a second oxygen capture layer 504. Figure 12In addition to the buried gate structure 600G and the second barrier layer 401 shown in FIG, the second gate dielectric layer 601, the second gate electrode 501, the first oxygen capture layer 502, the third gate electrode 503 and the second oxygen capture layer 504 may include the same structure.

[0131] Figure 14 is a plan view showing a semiconductor device according to a thirteenth embodiment of the present invention. Figure 15 According to the thirteenth embodiment of the present invention Figure 14 FIG. 1 is a cross-sectional view of the semiconductor device taken along line II′.

[0132] See also Figure 14 and Figure 15 The semiconductor device 1300 according to the thirteenth embodiment of the present invention may include a substrate 101 and a buried gate structure 100G, a first doping region 110, and a second doping region 111 embedded in the substrate 101. The buried gate structure 100G and the first doping region 110 and the second doping region 111 may form a cell transistor. Due to the buried gate structure, the cell transistor may improve short channel effects.

[0133] The semiconductor device 1300 may be part of a memory cell. For example, the semiconductor device 1300 may be part of a DRAM memory cell. The semiconductor device 1300 may include a bit line BL and a memory storage element CAP electrically connected to the substrate 101. The bit line BL may be coupled to the first doped region 110, and the memory storage element CAP may be coupled to the second doped region 111. The bit line BL and the memory storage element CAP may be arranged at a higher level than the buried gate structure 100G. The bit line BL and the memory storage element CAP may be arranged at different levels. The memory storage element CAP may be arranged at a higher level than the bit line BL. The memory storage element CAP may include a capacitor.

[0134] An isolation layer 102 and an active region 103 may be formed over the substrate 101. The active region 103 may be defined by the isolation layer 102. The active region 103 may have a major axis and a minor axis. The active region 103 may be tilted diagonally. One buried gate structure 100G may be formed in one active region 103. A first doped region 110 or a second doped region 111 may be formed in each active region 103 on both sides of the buried gate structure 100G. This embodiment may include one buried gate structure 100G, one first doped region 110, and one second doped region 111 in one active region.

[0135] The buried gate structure 100G may be embedded in the trench 105. The buried gate structure 100G may include the same structure as the buried gate structure 100 shown in FIG.

[0136] According to another embodiment of the present invention, the buried gate structure 100G may include Figures 3 to 13 The buried gate structures shown in FIG. 1 are the same as those in the second to twelfth embodiments.

[0137] 16A to 16D 1 and 2 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 16A to 16D Shown for forming Figure 2A An example of a method of manufacturing a semiconductor device 100 is shown.

[0138] See also Figure 16A , an isolation layer 12 may be formed on the substrate 11. The active area 13 may be defined by the isolation layer 12. The isolation layer 12 may be formed by a shallow trench isolation (STI) process. For example, the substrate 11 may be etched to form an isolation trench 12T. The isolation trench 12T may be filled with a dielectric material to form the isolation layer 12. The isolation layer 12 may include silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or another deposition process may be performed to fill the isolation trench 12T with a dielectric material. A planarization process such as chemical mechanical polishing (CMP) may be additionally used.

[0139] A trench 15 may be formed in the substrate 11. The trench 15 may be formed in the shape of a line intersecting the active area 13 and the isolation layer 12. The trench 15 may be formed by performing an etching process on the substrate 11 using the hard mask layer 14 as an etching mask. The hard mask layer 14 may be formed on the substrate 11 and may have a linear opening. The hard mask layer 14 may be formed of a material having an etching selectivity relative to the substrate 11. The hard mask layer 14 may be silicon oxide, such as tetraethyl orthosilicate (TEOS). The trench 15 may be formed shallower than the isolation trench 12T. The depth of the trench 15 may be sufficient to increase the average cross-sectional area of ​​the subsequent gate electrode. Therefore, the resistance of the gate electrode may be reduced. The lower edge of the trench 15 may have an arc shape.

[0140] Subsequently, the fin 13F may be formed. To form the fin 13F, the isolation layer 12 below the trench 15 may be selectively recessed. For the structure of the fin 13F, see Figure 2B Fin 103F is shown.

[0141] Subsequently, a first gate dielectric layer 16 may be formed on the surface of the trench 15. Before forming the first gate dielectric layer 16, etching damage on the surface of the trench 15 may be restored. For example, after forming a sacrificial oxide by a thermal oxidation process, the sacrificial oxide may be removed.

[0142] The first gate dielectric layer 16 may be formed by a thermal oxidation process and may include silicon oxide.

[0143] According to another embodiment of the present invention, the first gate dielectric layer 16 can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The first gate dielectric layer 16 formed by the deposition process may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to another embodiment of the present invention, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, and aluminum oxide, or a combination thereof. Regarding the high-k material, other known high-k materials may be selectively used. The first gate dielectric layer 16 may include a material having a high planar density of oxygen atoms.

[0144] See also Figure 16B A lower buried gate LBG may be formed on the first gate dielectric layer 16 to gap-fill the lower portion of the trench 15. The lower buried gate LBG may include a stacked structure of a first barrier layer 17 and a first gate electrode 18. The lower buried gate LBG may be formed through a series of processes, namely, conformally forming a barrier material on the first gate dielectric layer 16, forming a conductive material on the barrier material to fill the trench 15, and then performing a recess process on the barrier material and the conductive material. The recess process may be performed through a dry etching process (e.g., an etch-back process).

[0145] The top surfaces of the first barrier layer 17 and the first gate electrode 18 may be at the same level. The first gate electrode 18 may be formed on the first barrier layer 17. The first barrier layer 17 may have a liner shape, and the first gate electrode 18 may have a block shape. The bottom surface and outer surface of the first gate electrode 18 may be surrounded by the first barrier layer 17.

[0146] The first barrier layer 17 can be used to supply oxygen to the first gate electrode 18. The first barrier layer 17 may include a metal-based oxygen material. The first barrier layer 17 may be referred to as an "oxygen supply layer 17." The first barrier layer 17 may include multiple layers. The first barrier layer 17 may be a multilayer of an oxygen-containing material including a metal nitride. The first barrier layer 17 may be a trilayer of an oxygen-containing material including a metal nitride. The first barrier layer 17 may include a stacked structure of a first metal oxynitride 17A, a metal nitride 17B, and a second metal oxynitride 17C. For example, the first barrier layer 17 may include a stacked structure of a first titanium oxynitride 17A (TiON), a first titanium nitride 17B (TiN), and a second titanium oxynitride 17C (TiON). Here, the first metal oxynitride 17A, the metal nitride 17B, and the second metal oxynitride 17C may be formed through a deposition process. According to another embodiment of the present invention, the second metal oxynitride 17C may be formed by forming the metal nitride 17B and then oxidizing a predetermined thickness of the metal nitride 17B by exposing it to air.

[0147] According to another embodiment of the present invention, the first barrier layer 17 may include a stacked structure of a first metal nitride 17A, a metal oxynitride 17B, and a second metal nitride 17C. For example, the first barrier layer 17 may include a stacked structure of a first titanium nitride 17A, a titanium oxynitride 17B (TiON), and a second titanium nitride 17C. Here, the first metal nitride 17A, the metal oxynitride 17B, and the second metal nitride 17C may be formed by a deposition process. According to another embodiment of the present invention, the metal oxynitride 17B may be formed by forming the first metal nitride 17A and then oxidizing a predetermined thickness of the first metal nitride 17A by exposing it to air.

[0148] According to another embodiment of the present invention, the first barrier layer 17 may be a triple layer including a metal nitride and a metal oxide. The first barrier layer 17 may include a stacked structure of a first metal nitride 17A, a metal oxide 17B, and a second metal nitride 17C. For example, the first barrier layer 17 may include a stacked structure of a first titanium nitride 17A (TiN), a titanium oxide 17B (TiO), and a second titanium nitride 17C (TiN). Here, the first metal nitride 17A, the metal oxide 17B, and the second metal nitride 17C may be formed by a deposition process.

[0149] According to another embodiment of the present invention, the first barrier layer 17 may include a stacked structure of metal nitride and metal oxide. For example, the first barrier layer 17 may include a stacked structure of titanium nitride (TiN) and titanium oxide (TiO). Here, the metal nitride and metal oxide may be formed by a deposition process.

[0150] The first gate electrode 18 may have a high work function. Here, a high work function may refer to a work function greater than the mid-gap work function of silicon. A low work function may refer to a work function less than the mid-gap work function of silicon. Specifically, a high work function may have a work function greater than approximately 4.5 eV, and a low work function may have a work function less than approximately 4.5 eV.

[0151] According to another embodiment of the present invention, the first gate electrode 18 may have an increased high work function. The first gate electrode 18 may include a metal nitride. The first gate electrode 18 may include a metal nitride oxygen-containing material. The first gate electrode 18 may include a metal nitride with a controlled oxygen content. For example, the first gate electrode 18 may include high-oxygen titanium nitride (high-oxygen TiN). Titanium nitride may have a high work function, and oxygen may be included in the titanium nitride to further increase the work function of the titanium nitride. The oxygen content of high-oxygen titanium nitride (high-oxygen TiN) may be greater than the oxygen content of titanium nitride (TiN). During the heat treatment, when oxygen in the first barrier layer 17 diffuses into the first gate electrode 18, high-oxygen titanium nitride (high-oxygen TiN) may be formed. The oxygen content of high-oxygen titanium nitride (high-oxygen TiN) can be adjusted within a range in which the work function can be increased while maintaining the resistance of the first gate electrode 18.

[0152] See also Figure 16C The upper buried gate UBG may be formed above the lower buried gate LBG. The upper buried gate UBG may be formed through a series of processes, namely, forming a conductive material to fill the trench 15 above the lower buried gate LBG, and then performing a recess process on the conductive material. The recess process may be performed through a dry etching process (e.g., an etch-back process).

[0153] The upper buried gate UBG may be formed above the lower buried gate LBG. The top surface of the upper buried gate UBG may be set at a level lower than the top surface of the active region 13. The upper buried gate UBG may be formed of a low-resistance material to reduce the gate sheet resistance. The upper buried gate UBG may have a low work function. The upper buried gate UBG may include a metal nitride. The upper buried gate UBG may include a metal nitride with a controlled oxygen content. The upper buried gate UBG may include a metal nitride having a lower oxygen content in the film than the first gate electrode 18. For example, the upper buried gate 18 may include low-oxygen titanium nitride (low-oxygen TiN). Here, low-oxygen titanium nitride may refer to titanium nitride that does not contain oxygen or has a minimal oxygen content in the film. The oxygen content of low-oxygen titanium nitride (low-oxygen TiN) may be lower than the oxygen content of titanium nitride (TiN).

[0154] Subsequently, a sacrificial layer 19 may be formed over the upper buried gate UBG. The sacrificial layer 19 may prevent the work function of the upper buried gate UBG from increasing by trapping oxygen on the surface of the upper buried gate UBG. The sacrificial layer 19 may include a silicon material. For example, the sacrificial layer 19 may include polysilicon.

[0155] Subsequently, heat treatment may be performed. When the heat treatment is performed, titanium oxide (TiO x ) can be replaced by silicon oxide (SiO2). x ) is replaced by silicon oxide, the oxygen on the surface of the upper buried gate UBG no longer penetrates or diffuses into the upper buried gate UBG.

[0156] Subsequently, the sacrificial layer 19 may be removed. The sacrificial layer 19 may be removed by a wet etching process. When the sacrificial layer 19 is removed, the substituted silicon oxide (SiO 2 ) may be removed together.

[0157] See also Figure 16D A capping layer 20 may be formed over the upper buried gate UBG to gap-fill the remaining portion of the trench 15. The capping layer 20 may include a dielectric material. The capping layer 20 may include silicon nitride. Subsequently, the capping layer 20 may be planarized to expose the top surface of the hard mask layer 14. The capping layer 20 may have an oxide-nitride-oxide (ONO) structure.

[0158] Subsequently, a first doping region 21 and a second doping region 22 may be formed in the substrate 11. The first doping region 21 and the second doping region 22 may be formed by doping impurities into the substrate 11 through an implantation process or another doping process.

[0159] Through the above series of processes, the buried gate structure 100G can be formed.

[0160] 17A to 17E 4 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. 17A to 17E Shown for forming Figure 5 An example of a method of manufacturing a semiconductor device 400 is shown.

[0161] See also Figure 17A , an isolation layer 12 may be formed over the substrate 11. The active area 13 may be defined by the isolation layer 12. The isolation layer 12 may be formed by a shallow trench isolation (STI) process. For example, the substrate 11 may be etched to form an isolation trench 12T. The isolation trench 12T may be filled with a dielectric material to form the isolation layer 12. The isolation layer 12 may include silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or another deposition process may be performed to fill the isolation trench 12T with a dielectric material. A planarization process, such as chemical mechanical polishing (CMP), may be additionally performed.

[0162] A trench 15 may be formed in the substrate 11. The trench 15 may be formed in the shape of a line intersecting the active area 13 and the isolation layer 12. The trench 15 may be formed by using a hard mask layer 14 as an etching mask and performing an etching process on the substrate 11. The hard mask layer 14 may be formed on the substrate 11 and may have a linear opening. The hard mask layer 14 may be formed of a material having an etching selectivity relative to the substrate 11. The hard mask layer 14 may be silicon oxide, such as tetraethyl orthosilicate (TEOS). The trench 15 may be formed to be shallower than the isolation trench 12T. The depth of the trench 15 may be sufficient to increase the average cross-sectional area of ​​the subsequent gate electrode. Therefore, the resistance of the gate electrode may be reduced. The lower edge of the trench 15 may have an arc shape.

[0163] Subsequently, the fin 13F may be formed. To form the fin 13F, the isolation layer 12 below the trench 15 may be selectively recessed. For the structure of the fin 13F, reference may be made to Figure 5 Fin 103F.

[0164] Subsequently, a first gate dielectric layer 16 may be formed on the surface of the trench 15. Before forming the first gate dielectric layer 16, etching damage on the surface of the trench 15 may be restored. For example, after forming a sacrificial oxide by a thermal oxidation process, the sacrificial oxide may be removed.

[0165] The first gate dielectric layer 16 may be formed by a thermal oxidation process and may include silicon oxide.

[0166] According to another embodiment of the present invention, the first gate dielectric layer 16 can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The first gate dielectric layer 16 formed by the deposition method may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to other embodiments of the present invention, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. Regarding the high-k material, other known high-k materials may be selectively used. The first gate dielectric layer 16 may include a material having a high planar density of oxygen atoms.

[0167] See also Figure 17BA lower buried gate LBG may be formed on the first gate dielectric layer 16 to gap-fill the lower portion of the trench 15. The lower buried gate LBG may include a stacked structure of a first barrier layer 17 and a first gate electrode 18. The lower buried gate LBG may be formed through a series of processes, namely, conformally forming a barrier material on the first gate dielectric layer 16, forming a conductive material on the barrier material to fill the trench 15, and then performing a recess process on the barrier material and the conductive material. The recess process may be performed through a dry etching process (e.g., an etch-back process).

[0168] The top surfaces of the first barrier layer 17 and the first gate electrode 18 may be at the same level. The first gate electrode 18 may be formed on the first barrier layer 17. The first barrier layer 17 may have a liner shape, and the first gate electrode 18 may have a block shape. The bottom surface and outer surface of the first gate electrode 18 may be surrounded by the first barrier layer 17.

[0169] The first barrier layer 17 can be used to supply oxygen to the first gate electrode 18. The first barrier layer 17 can include a metal-based oxygen material. The first barrier layer 17 can be referred to as an "oxygen supply layer." The first barrier layer 17 can include multiple layers. The first barrier layer 17 can be a multilayer structure including a metal nitride oxygen-containing material. The first barrier layer 17 can be a trilayer structure including a metal nitride oxygen-containing material. The first barrier layer 17 can include a stacked structure of a first metal oxynitride 17A, a metal nitride 17B, and a second metal oxynitride 17C. For example, the first barrier layer 17 can include a stacked structure of a first titanium oxynitride 17A (TiON), a first titanium nitride 17B (TiN), and a second titanium oxynitride 17C (TiON). Here, the first metal oxynitride 17A, the metal nitride 17B, and the second metal oxynitride 17C can be formed through a deposition process. According to another embodiment of the present invention, the second metal oxynitride 17C can be formed by forming the metal nitride 17B and then oxidizing the metal nitride 17B to a predetermined thickness by exposing it to air.

[0170] According to another embodiment of the present invention, the first barrier layer 17 may include a stacked structure of a first metal nitride 17A, a metal oxynitride 17B, and a second metal nitride 17C. For example, the first barrier layer 17 may include a stacked structure of a first titanium nitride 17A, a titanium oxynitride 17B (TiON), and a second titanium nitride 17C. Here, the first metal nitride 17A, the metal oxynitride 17B, and the second metal nitride 17C may be formed by a deposition process. According to another embodiment of the present invention, the metal oxynitride 17B may be formed by forming the first metal nitride 17A and then oxidizing a predetermined thickness of the first metal nitride 17A by exposing it to air.

[0171] According to another embodiment of the present invention, the first barrier layer 17 may be a triple layer including a metal nitride and a metal oxide. The first barrier layer 17 may include a stacked structure of a first metal nitride 17A, a metal oxide 17B, and a second metal nitride 17C. For example, the first barrier layer 17 may include a stacked structure of a first titanium nitride 17A (TiN), a titanium oxide 17B (TiO), and a second titanium nitride 17C (TiN). Here, the first metal nitride 17A, the metal oxide 17B, and the second metal nitride 17C may be formed by a deposition process.

[0172] According to another embodiment of the present invention, the first barrier layer 17 may include a stacked structure of metal nitride and metal oxide. For example, the first barrier layer 17 may include a stacked structure of titanium nitride (TiN) and titanium oxide (TiO). Here, the metal nitride and metal oxide may be formed by a deposition process.

[0173] The first gate electrode 18 may have a high work function. Here, a high work function may refer to a work function greater than the mid-gap work function of silicon. A low work function may refer to a work function less than the mid-gap work function of silicon. Specifically, a high work function may have a work function greater than approximately 4.5 eV, and a low work function may have a work function less than approximately 4.5 eV.

[0174] According to another embodiment of the present invention, the first gate electrode 18 may have an increased high work function. The first gate electrode 18 may include a metal nitride. The first gate electrode 18 may include a metal nitride oxygen-containing material. The first gate electrode 18 may include a metal nitride with a controlled oxygen content. For example, the first gate electrode 18 may include high-oxygen titanium nitride (high-oxygen TiN). Titanium nitride may have a high work function, and oxygen may be included in the titanium nitride to further increase the work function of the titanium nitride. The oxygen content of high-oxygen titanium nitride (high-oxygen TiN) may be greater than the oxygen content of titanium nitride (TiN). During the heat treatment, when oxygen in the first barrier layer 17 diffuses into the first gate electrode 18, high-oxygen titanium nitride (high-oxygen TiN) may be formed. The oxygen content of high-oxygen titanium nitride (high-oxygen TiN) can be adjusted within a range in which the work function can be increased while maintaining the resistance of the first gate electrode 18.

[0175] See also Figure 17C , a second barrier layer 30 may be formed on the lower buried gate LBG.

[0176] The second barrier layer 30 can be formed by a deposition process or a treatment process. The second barrier layer 30 can be formed by performing an ex-situ deposition process on the subsequent second gate electrode. According to another embodiment of the present invention, the second barrier layer 30 can be formed in situ with the subsequent second gate by treating monosilane (SiH4) present in the processing equipment for forming the second gate electrode. The second barrier layer 30 may include a silicon-based material. For example, the second barrier layer 30 may include polysilicon. The second barrier layer 30 can be adjusted to have a minimum thickness that can capture oxygen without increasing the resistance of the device. The second barrier layer 30 can be adjusted to have a thickness of no more than at least about 2nm. That is, the second barrier layer 30 can be formed to have a thickness of about 2nm or less.

[0177] The second barrier layer 30 can capture oxygen on the surface of the first gate electrode 18. Furthermore, the second barrier layer 30 can function as a barrier layer that separates the first gate electrode 18 and the subsequent second gate electrode from each other and prevents oxygen or metal ions from migrating therebetween. The second barrier layer 30 can be referred to as an "oxygen capture layer 30." The second barrier layer 30 can capture oxygen on the surface of the first gate electrode 18 and prevent the oxygen on the surface of the first gate electrode 18 from diffusing into the subsequent second gate electrode. The second barrier layer 30 can also be referred to as an "oxygen diffusion prevention layer 30."

[0178] See also Figure 17D , an upper buried gate UBG can be formed by stacking a second gate electrode 31 on the second barrier layer 30. The second gate electrode 31 can be formed by a series of processes, namely, forming a conductive material on the second barrier layer 30 to fill the trench 15, and then performing a recess process on the conductive material. The recess process can be performed by a dry etching process (e.g., an etch-back process).

[0179] The second gate electrode 31 may be formed of a low-resistance material to reduce the gate sheet resistance. The second gate electrode 31 may have a low work function. The second gate electrode 31 may include a metal nitride. The second gate electrode 31 may include a metal nitride with a controlled oxygen content. The second gate electrode 31 may include a metal nitride having a lower oxygen content in the film than the first gate electrode 18. For example, the second gate electrode 31 may include low-oxygen titanium nitride (low-oxygen TiN). Here, low-oxygen titanium nitride may refer to titanium nitride that does not contain oxygen or has a minimal oxygen content in the film. The oxygen content of low-oxygen titanium nitride (low-oxygen TiN) may be less than the oxygen content of titanium nitride (TiN).

[0180] Subsequently, a sacrificial layer 19 may be formed over the second gate electrode 31. The sacrificial layer 19 may prevent the work function of the second gate electrode 31 from increasing by trapping oxygen on the surface of the second gate electrode 31. The sacrificial layer 19 may include a silicon material. For example, the sacrificial layer 19 may include polysilicon.

[0181] Subsequently, heat treatment may be performed. When heat treatment is performed, titanium oxide (TiO 2 ) generated by oxidizing the surface of the second gate electrode 31 may be replaced with silicon oxide (SiO 2 ). x ), and in the use of silicon oxide instead of titanium oxide (TiO x ) after which the oxygen on the surface of the second gate electrode 31 no longer penetrates or diffuses into the second gate electrode 31.

[0182] Subsequently, the sacrificial layer 19 may be removed. The sacrificial layer 19 may be removed by a wet etching process. When the sacrificial layer 19 is removed, the substituted silicon oxide (SiO 2 ) may be removed together.

[0183] See also Figure 17E A capping layer 20 may be formed over the upper buried gate UBG to gap-fill the remaining portion of the trench 15. The capping layer 20 may include a dielectric material. The capping layer 20 may include silicon nitride. Subsequently, the capping layer 20 may be planarized to expose the top surface of the hard mask layer 14. The capping layer 20 may have an oxide-nitride-oxide (ONO) structure.

[0184] Subsequently, a first doping region 21 and a second doping region 22 may be formed in the substrate 11. The first doping region 21 and the second doping region 22 may be formed by doping impurities into the substrate 11 using an implantation process or another doping process.

[0185] Through the above series of processes, a buried gate structure 400G can be formed.

[0186] According to an embodiment of the present invention, gate induced drain leakage (GIDL) may be improved by adjusting the work functions of the upper gate electrode and the lower gate electrode.

[0187] According to an embodiment of the present invention, the resistance of a word line may be reduced by applying a gate electrode including a metal material.

[0188] Although the embodiments of the present invention have been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. Furthermore, these embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device comprising: a trench formed in the substrate; a first gate filling the lower portion of the trench; as well as a second gate, which is disposed above the first gate, Each of the first gate and the second gate includes an oxygen material, and the oxygen content of the first gate is greater than the oxygen content of the second gate.

2. The semiconductor device according to claim 1, wherein The first gate includes a stack structure of an oxygen supply layer and a first conductive layer, and the oxygen supply layer supplies oxygen to the first conductive layer.

3. The semiconductor device according to claim 2, wherein The oxygen supply layer includes a metal-based oxygen material.

4. The semiconductor device according to claim 2, wherein The oxygen supply layer includes titanium oxynitride.

5. The semiconductor device according to claim 2, wherein The oxygen supply layer and the first conductive layer include the same metal material. The semiconductor device according to claim 2 , wherein: The oxygen supply layer includes a plurality of oxygen supply layers.

7. The semiconductor device according to claim 1, wherein The second gate includes: Low-oxygen titanium nitride (low-oxygen TiN) has an oxygen content lower than that of titanium nitride (TiN).

8. The semiconductor device according to claim 1, wherein The second gate includes one selected from the following: a stacked structure of a second conductive layer, a first oxygen capture layer, a third conductive layer, and a second oxygen capture layer, a stacked structure of a second conductive layer, a first oxygen capture layer, and a third conductive layer, and A stacked structure of the second conductive layer and the first oxygen capture layer.

9. The semiconductor device according to claim 8, wherein The second conductive layer covers an outer surface of the first oxygen capture layer.

10. The semiconductor device according to claim 8, wherein The thickness of the first oxygen capture layer is smaller than the thickness of the second conductive layer.

11. The semiconductor device according to claim 8, wherein Each of the second conductive layer and the third conductive layer includes: Low-oxygen titanium nitride (low-oxygen TiN) has an oxygen content lower than that of titanium nitride (TiN).

12. The semiconductor device according to claim 8, wherein Each of the first and second oxygen capture layers includes polysilicon.

13. The semiconductor device according to claim 1, further comprising: a first gate dielectric layer between the first gate and the second gate structures and the inner surface of the trench, and a second gate dielectric layer extending from a space between the first gate and the second gate to a space between the second gate and the first gate dielectric layer.

14. The semiconductor device according to claim 1, further comprising: A barrier layer is between the first gate and the second gate.

15. The semiconductor device according to claim 14, wherein The barrier layer includes polysilicon.

16. The semiconductor device according to claim 14, further comprising: a first gate dielectric layer between the first gate structure and the second gate structure and an inner surface of the trench; The blocking layer extends to a space between the second gate and the first gate dielectric layer.

17. The semiconductor device according to claim 13, further comprising: A barrier layer is between the first gate and the second gate dielectric layer.

18. A method for manufacturing a semiconductor device, the method comprising: forming a trench in a substrate; forming a first gate filling a lower portion of the trench; forming a second gate on the first gate; forming a sacrificial layer on the second gate; replacing a surface of the second gate with silicon oxide by performing a heat treatment; as well as removing the sacrificial layer and the silicon oxide, Each of the first gate and the second gate includes an oxygen material, and the oxygen content of the first gate is greater than the oxygen content of the second gate.

19. The method according to claim 18, further comprising: Before forming the first gate, A gate dielectric layer is formed covering the bottom and inner surface of the trench.

20. The method according to claim 18, wherein Forming the first gate includes: forming an oxygen supply layer; and A first conductive layer is formed over the oxygen supply layer, the oxygen supply layer supplying oxygen to the first conductive layer.

21. The method according to claim 20, wherein The oxygen supply layer includes titanium oxynitride, and The first conductive layer includes high-oxygen titanium nitride (high-oxygen TiN), the oxygen content of which is greater than that of titanium nitride (TiN).

22. The method of claim 18, further comprising: Before forming the second gate, A barrier layer is formed on the first gate.

23. The method according to claim 22, wherein The barrier layer extends to an outer surface of the second gate.

24. The method according to claim 22, wherein Forming the barrier layer comprises: A polysilicon deposition process is performed.

25. The method according to claim 22, wherein Forming the barrier layer comprises: A treatment process using monosilane (SiH 4 ) is performed in a chamber for the second gate before forming the second gate.

26. The method of claim 18, further comprising: Before forming the first gate, forming a first gate dielectric layer covering the bottom and inner surface of the trench, and Before forming the second gate, a second gate dielectric layer is formed on the first gate and on the first gate dielectric layer exposed by the first gate.

27. The method according to claim 18, wherein The second gate includes: Low-oxygen titanium nitride (low-oxygen TiN) has an oxygen content lower than that of titanium nitride (TiN).

28. The method according to claim 18, wherein The second gate includes one selected from the following: a stacked structure of a first low-oxygen titanium nitride, a first oxygen capture layer, a second low-oxygen titanium nitride, and a second oxygen capture layer; a stacked structure of a first low-oxygen titanium nitride, a first oxygen capture layer, and a second low-oxygen titanium nitride; and a stacked structure of a first low-oxygen titanium nitride and a first oxygen capture layer.

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