Semiconductor device and manufacturing method thereof

Abstract

Disclosed herein are a semiconductor device and a method of manufacturing the same. The present disclosure relates to methods, devices, systems, and techniques for managing channel holes and gate lines incorporated in semiconductor devices. An exemplary semiconductor device includes a first memory block, a second memory block, and at least a first gate line structure between the first memory block and the second memory block. Each of the first memory block and the second memory block includes a stack of conductive layers and insulating layers alternating with each other in a first direction. The first gate line structure insulates the conductive layer of the first memory block from the conductive layer of the second memory block. The first gate line structure includes: gate line insulating layers spaced apart in a first direction; and pillars spaced apart in a second direction perpendicular to the first direction and extending through the gate line insulating layer in the first direction.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive because they can stack more layers within a similar footprint, thereby increasing array density. 3D memory devices typically include a storage array of memory cells and peripheral circuitry for facilitating the operation of the storage array. Summary of the Invention

[0003] The present disclosure describes methods, devices, systems, and techniques for managing channel holes and gate lines incorporated into semiconductor devices.

[0004] One aspect of the present disclosure is characterized by a semiconductor device. The semiconductor device includes memory blocks and at least a first gate line structure. The memory blocks include at least a first memory block and a second memory block, wherein each of the first memory block and the second memory block includes a stack of conductive layers and insulating layers alternating with each other along a first direction. The first gate line structure is located between the first memory block and the second memory block. The first gate line structure insulates the conductive layer of the first memory block from the conductive layer of the second memory block. The first gate line structure includes a gate line insulating layer and a pillar. The gate line insulating layer is spaced apart along a first direction. The pillar is spaced apart along a second direction perpendicular to the first direction and extends through the gate line insulating layer along the first direction.

[0005] In some embodiments, the first gate line structure contacts a sidewall of the first memory block and a sidewall of the second memory block.

[0006] In some embodiments, the gate line insulating layer in the gate line insulating layer is located between the corresponding conductive layer of the first memory block and the corresponding conductive layer of the second memory block.

[0007] In some embodiments, one of the pillars includes an outer layer and an inner structure surrounded by the outer layer, the outer layer includes a dielectric material, and the inner structure includes at least one of a polysilicon material, a dielectric material, or a metal.

[0008] In some embodiments, one of the gate line insulation layers includes a dielectric material.

[0009] In some embodiments, the semiconductor device further includes a third memory block and a second gate line structure located between the second memory block and the third memory block.

[0010] In some embodiments, the semiconductor device further includes one or more other gate line structures, wherein the first memory block includes a plurality of memory fingers separated by the one or more other gate line structures.

[0011] In some embodiments, the stack of conductive and insulating layers includes a plurality of stacks stacked along a first direction, and each stack of the plurality of stacks includes a subset of the stack of conductive and insulating layers.

[0012] Another aspect of the present disclosure is characterized by a method comprising: providing a semiconductor structure. The semiconductor structure comprises: a stack of conductive layers and insulating layers alternating with each other along a first direction; a channel structure extending through the stack along the first direction, wherein the channel structure comprises at least a first array of channel structures and a second array of channel structures; and at least a first group of gate line holes extending through the stack along the first direction. The first group of gate line holes is located between the first array of channel structures and the second array of channel structures. The first group of gate line holes is spaced apart along a second direction perpendicular to the first direction. The conductive layers are connected through conductive inner surfaces of the first group of gate line holes. The method further comprises: forming a first gate line space by etching away the conductive inner surfaces of the first group of gate line holes to expose the conductive layer and recessing the conductive layer. The first gate line space comprises: a tunnel located between the insulating layers and extending along the second direction; and a first group of gate line holes extending through the tunnel along the first direction. The method further comprises: forming a first gate line structure in the first gate line space.

[0013] In some embodiments, the first gate line space divides the conductive layer into a first group of conductive layers through which the first array of channel structures extends, and a second group of conductive layers through which the second array of channel structures extends.

[0014] In some embodiments, the first gate line structure includes: a gate line insulating layer located in the tunnel; and pillars located in the first set of gate line holes. Each of the pillars includes an outer layer connected to the gate line insulating layer and an inner structure surrounded by the outer layer.

[0015] In some embodiments, forming the first gate line structure includes forming a gate line insulation layer and an outer layer of each of the pillars by depositing a dielectric material through a first set of gate line holes in the first gate line spaces. Forming the first gate line structure also includes forming an inner structure of each of the pillars by filling the first set of gate line holes with at least one of a polysilicon material, a dielectric material, or a metal.

[0016] In some embodiments, providing a semiconductor structure includes: forming a stack of sacrificial layers and insulating layers alternating with each other along a first direction; forming gate line holes and channel holes by a same etching process; and forming a channel structure in the channel holes. The gate line holes and the channel holes extend through the stack of sacrificial layers and insulating layers along the first direction, and the gate line holes include a first group of gate line holes.

[0017] In some embodiments, providing the semiconductor structure further includes removing the sacrificial layer, and forming a conductive layer and conductive inner surfaces of the first set of gate line holes by depositing at least one conductive material into the first set of gate line holes.

[0018] In some embodiments, the channel structures further include a third array of channel structures, and the gate line holes further include a second group of gate line holes located between the second array of channel structures and the third array of channel structures.

[0019] In some embodiments, forming a channel structure in the channel hole includes: filling the gate line hole and the channel hole with a sacrificial material; covering the gate line hole; removing the sacrificial material in the channel hole; and depositing a high-k material, a storage film, and a channel layer into each of the channel holes.

[0020] Another aspect of the present disclosure is characterized by a memory system comprising a memory device and a memory controller coupled to the memory device and configured to control the memory device. The memory device comprises: a memory block comprising: at least a first memory block and a second memory block, wherein each of the first memory block and the second memory block comprises a stack of conductive layers and insulating layers alternating with each other along a first direction; and at least a first gate line structure, the first gate line structure being located between the first memory block and the second memory block, wherein the first gate line structure insulates the conductive layer of the first memory block from the conductive layer of the second memory block. The first gate line structure comprises: a gate line insulating layer spaced apart along a first direction; and a pillar spaced apart along a second direction perpendicular to the first direction and extending through the gate line insulating layer along the first direction.

[0021] In some embodiments, the gate line insulating layer in the gate line insulating layer is located between the corresponding conductive layer of the first memory block and the corresponding conductive layer of the second memory block.

[0022] In some embodiments, one of the pillars includes an outer layer and an inner structure surrounded by the outer layer, the outer layer includes a dielectric material, and the inner structure includes at least one of a polysilicon material, a dielectric material, or a metal.

[0023] In some embodiments, the memory device further includes a third memory block and a second gate line structure located between the second memory block and the third memory block.

[0024] The details of one or more implementations of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated herein and form a part of this disclosure, illustrate various aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and enable one of ordinary skill in the art to make and use the disclosure.

[0026] Figure 1A-1B An exemplary semiconductor device is shown.

[0027] Figure 2A-2G An exemplary process for fabricating a semiconductor device is shown.

[0028] Figure 3 A flow chart illustrating an exemplary process for fabricating a semiconductor device is shown.

[0029] Figure 4 A block diagram of an exemplary system is shown.

[0030] Like reference numbers and designations in the various drawings indicate like elements.It should also be understood that the various exemplary embodiments shown in the drawings are merely illustrative representations and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0031] Due to the demand for lower-cost memory devices with higher density, memory devices (e.g., 3D NAND flash memory) can be formed with multiple stacks, and each stack can have a larger number of layers. The high aspect ratio of such memory devices can pose challenges to the manufacturing process. For example, the channel hole and the gate line hole can be formed in the same etching process using the same etching mask, which can be referred to as channel hole and gate line merging.

[0032] Embodiments of the present disclosure provide exemplary techniques for managing channel holes and gate line merging in a semiconductor device (e.g., by forming a gate line structure between two memory blocks of the semiconductor device). The gate line structure can insulate the conductive layer of one memory block from the conductive layer of another memory block. The gate line structure can include a gate line insulating layer and a pillar. In some cases, the gate line insulating layer can be spaced apart in a vertical direction. The pillars can be spaced apart in a horizontal direction perpendicular to the vertical direction and extend through the gate line insulating layer in the vertical direction.

[0033] Embodiments of the present disclosure may provide one or more of the following technical advantages and / or benefits. Channel holes and gate line holes may be formed in the same etching process using the same etching mask, thereby improving the manufacturing process flow and reducing manufacturing costs. In addition, the overlay (OVL) offset problem may be resolved and the process window may be expanded. In addition, a gate line structure may be formed between two memory blocks of a memory device to prevent a memory block (e.g., one with a high aspect ratio) from tilting or collapsing, which may improve the quality of the memory device and increase production yield. For example, the gate line structure may have a layered oxide connected to the sidewalls of the memory block, thereby improving the stability of the memory block. This technology may result in better structural uniformity of the channel structure and improvements to the input / output (I / O) load of the external holes in the gate line gaps of the memory device. Therefore, the manufacturing cost of the memory device may be reduced, and the storage capacity per unit area of ​​the memory device may be increased.

[0034] This technology can be applied to various types of semiconductor devices, including volatile memory devices (e.g., DRAM memory devices) or non-volatile memory (NVM) devices (e.g., NAND flash memory, NOR flash memory), resistive random access memory (RRAM), phase change memory (PCM) (e.g., PCRAM), spin-transfer torque (STT) magnetoresistive random access memory (MRAM), and others. This technology can also be applied to charge trapping-based memory devices (e.g., silicon-oxide-nitride-oxide-silicon (SONOS) memory devices) and floating gate-based memory devices. This technology can be applied to three-dimensional (3D) memory devices. This technology can be applied to various memory types, such as single-layer (SLC) devices, multi-layer (MLC) devices (e.g., dual-layer (2-layer)) devices, triple-layer (TLC) devices, quadruple-layer (QLC) devices, or five-layer (PLC) devices. Additionally or alternatively, the technology may be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, and others.

[0035] Figure 1A A top view of an exemplary semiconductor device 100 is shown. The semiconductor device 100 may be a memory device, such as a three-dimensional (3D) NAND memory device. The semiconductor device 100 may include one or more array regions and one or more connection regions configured to provide conductive connections to the one or more array regions. In some embodiments, as Figure 1AAs shown, the semiconductor device 100 includes two array regions 111 and a connection region 109 located between the two array regions along a first horizontal direction (e.g., X direction). Each array region 111 may include an array of channel structures 112. Each channel structure 112 may be used to form a string of memory cells coupled in series along a vertical direction (e.g., Z direction) perpendicular to the first horizontal direction. In some embodiments, the connection region 109 may include a stepped structure (not shown) and an array of contact structures 114 formed on the stepped structure. In some other embodiments, the conductive layer in the connection region 109 (e.g., as described below) may be connected to a plurality of memory cells connected to the ... Figure 1B The conductive layer 104A in (a)-(c) of FIG. 1 may form a structure different from a staircase structure. For example, the contact structures in the array of contact structures 114 may be connected to corresponding conductive layers and may extend through other conductive layers, and spacers for insulation may be formed between the contact structures and other conductive layers. In some embodiments, the gate line structures 116 extending in the X direction may divide the array area into a plurality of memory blocks (e.g., Figure 1A 1 and 118-2 shown in FIG. 1 ). In some embodiments, two adjacent portions 118-1 and 118-2 can be considered a single memory block, and each of portions 118-1 and 118-2 can be referred to as a memory finger. In some embodiments, at least some of the gate line structures 116 can serve as a common source contact for the channel structures 112 in the array region 111. For example, a top select gate (TSG) cut 120 can be provided in each of the memory blocks 118-1 and 118-2 to divide the memory block into a plurality of portions. In some instances, each TSG cut 120 can extend (e.g., in a vertical direction) through a stack of alternating conductive and insulating layers (e.g., as described below) in the semiconductor device 100. Figure 1B In some embodiments, the array region 111 and the connection region 109 may include dummy channel structures or dummy memory strings (not shown) for process variation control during manufacturing and / or for additional mechanical support.

[0036] It should be noted that the X-axis, Y-axis, and Z-axis (also referred to as the X-direction, Y-direction, and Z-direction) are included in Figure 1A, to further illustrate the spatial relationship of various components in the semiconductor device. The substrate of the semiconductor device 100 includes two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the substrate on which components of the semiconductor device can be formed, and a bottom surface on the back side of the substrate opposite to the front side. The Z direction is perpendicular to both the X direction and the Y direction. As used herein, when the substrate is located in the lowest plane of the semiconductor device in the Z direction, whether a component (e.g., a layer or device) is "on", "above" or "below" another component (e.g., a layer or device) of the semiconductor device is determined relative to the substrate of the semiconductor device in the Z direction (a vertical direction perpendicular to the XY plane, e.g., the thickness direction of the substrate). The same concept for describing spatial relationships is applied throughout this disclosure.

[0037] Figure 1B (a)-(c) show the semiconductor device 100 along the Figure 1A In some embodiments, as shown in FIG. Figure 1B As shown in (a) and (c) of FIG. 1 , the semiconductor device 100 includes a substrate 102 and a stack 104 of alternating conductive layers 104A and insulating layers 104B provided on the substrate 102. The stack 104 can extend across two memory blocks 118-1 and 118-2. The substrate 102 can be any suitable semiconductor substrate having any suitable semiconductor material (e.g., a single crystal, polycrystalline, or single crystal semiconductor). For example, the substrate 102 can include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon on insulator (SOI), germanium on insulator (GOI), gallium nitride, silicon carbide, a III-V compound, or any combination thereof. The semiconductor device 100 can include a top layer 106 made of an isolation material (e.g., an oxide).

[0038] The stack 104 may extend in a second horizontal direction (e.g., the Y direction) that is parallel to the top surface of the substrate 102 and perpendicular to the first horizontal direction. The conductive layers 104A and the insulating layers 104B may alternate in a vertical direction (e.g., the Z direction) that is perpendicular to the second horizontal direction. The conductive layers 104A may be the same or different in thickness from one another, for example, in the range of 10-500 nm, for example, about 35 nm. The insulating layers 104B may also be the same or different in thickness from one another, for example, in the range of 10-500 nm, for example, about 25 nm. It should be noted that Figure 1BThe number of conductive layers 104A and insulating layers 104B shown in (a) or (c) is for illustration only, and any suitable number of conductive layers 104A and insulating layers 104B may be included in stack 104. In some embodiments, stack 104 may include multiple stacks stacked along a vertical direction (e.g., the Z direction). Each of the multiple stacks may include a subset of the conductive layers 104A and insulating layers 104B in stack 104. Conductive layer 104A may include any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polysilicon, doped silicon, silicide, or any combination thereof. Insulating layer 104B may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, insulating layer 104B may also include a high-K dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof.

[0039] In some embodiments, as Figure 1B As shown in (a) or (c) of FIG. 1 , the stack 104 includes a liner 104C. The liner 104C may cover part or all of the side surfaces of the corresponding conductive layer 104A and be located between the conductive layer 104A and two insulating layers 104B adjacent to the corresponding conductive layer 104A. The liner 104C may include a high-K dielectric material (e.g., Al2O3). In some examples, the conductive layer 104A includes a metal material (e.g., W) and an adhesive material (e.g., TiN), and the adhesive material may be deposited between the metal material and the high-K dielectric material. In some examples, the conductive layer 104A includes a metal material (e.g., W), and the liner 104C includes an adhesive material (e.g., TiN) and a high-K dielectric material.

[0040] like Figure 1BAs shown in (a) or (c) of FIG. 1 , each memory block (e.g., memory block 118-1 or 118-2) of the semiconductor device 100 includes a channel structure 112 extending vertically through the stack 104 and into the substrate 102. Each channel structure 112 may be pillar-shaped or cylindrical, and may include: a high-K layer, a barrier layer surrounded by the high-K layer, a charge trapping layer (or storage layer) surrounded by the barrier layer, a tunneling layer surrounded by the charge trapping layer, a channel layer surrounded by the tunneling layer, and a core-filling layer surrounded by the channel layer, wherein the high-K layer, barrier layer, charge trapping layer, tunneling layer, channel layer, and core-filling layer extend through the conductive layer 104A and the insulating layer 104B of the stack 104; and a channel contact formed above the core-filling layer and in contact with the channel layer. In some embodiments, the channel layer may include silicon, such as amorphous silicon, polycrystalline silicon, or single crystal silicon, the tunneling layer may include silicon oxide, silicon nitride, or any combination thereof, the blocking layer may include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof, and the charge trapping layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the tunneling layer, the charge trapping layer, and the blocking layer (collectively referred to as a storage film) may include an ONO dielectric (silicon oxide-silicon nitride-silicon oxide).

[0041] like Figure 1A As shown, one or more gate line structures 116 may be formed in the array region 111 in a first horizontal direction (eg, X direction) to divide the semiconductor device 100 into a plurality of memory blocks (eg, memory blocks 118-1 and 118-2). Figure 1B (a)-(c) of FIG. 1 show cross-sectional views of one of the gate line structures 116. Figure 1A As shown, the gate line structure 116 extends along a first horizontal direction (eg, X direction) and is located between the memory block 118-1 and the memory block 118-2. Figure 1B As shown in (a)-(c) of FIG. 1 , the gate line structure 116 extends through the stack 104 and into the substrate 102 in a vertical direction (e.g., Z direction) perpendicular to the first horizontal direction and the second horizontal direction. The gate line structure 116 can insulate the conductive layer 104A of the memory block 118-1 from the conductive layer 104A of the memory block 118-2. Figure 1B As shown in (a), the gate line structure may contact the sidewalls of the memory block 118 - 1 and the sidewalls of the memory block 118 - 2 along the Y direction.

[0042] In some embodiments, the gate line structure 116 includes gate line insulation layers 108 spaced apart in a vertical direction (e.g., the Z direction) and pillars 110 extending through the gate line insulation layer 108 in the vertical direction. Each gate line insulation layer 108 can be located between the corresponding conductive layer 104A of the memory block 118-1 and the corresponding conductive layer 104A of the memory block 118-2 along the Y direction. In some embodiments, each gate line insulation layer 108 can include a dielectric material (e.g., silicon oxide). The pillars 110 are spaced apart along a first horizontal direction (e.g., the X direction). Figure 1B As shown in (a) and (b) of FIG. 1 , each of the pillars 110 may include an outer layer 110A and an inner structure 110B surrounded by the outer layer 110A. In some embodiments, the outer layer 110A may include a dielectric material (e.g., silicon oxide). The inner structure 110B may include at least one of a polysilicon material, a dielectric material, or a metal.

[0043] In some embodiments, the cross-section of the pillar 110 may be larger than the cross-section of the channel structure 112. The cross-section of the pillar 110 and the cross-section of the channel structure 112 are perpendicular to the Z direction. The cross-section of the pillar 110 and the cross-section of the channel structure 112 may be located at the same position along the Z direction. In some other embodiments, the cross-section of the pillar 110 may be equal to the cross-section of the channel structure 112. In some embodiments, the cross-section of the pillar 110 may be smaller than the cross-section of the channel structure 112.

[0044] Figure 2A-2G The manufacturing process of a semiconductor device (e.g., Figure 1A-1B An exemplary process of the semiconductor device 100 shown in FIG. Figure 2A-2G 1 shows a cross-sectional view of an exemplary semiconductor structure at various stages of the manufacturing process. Specifically, Figure 2A (a) to Figure 2G (a) shows an exemplary semiconductor structure along Figure 1A The cross-sectional view of the cutting line AA' in Figure 2A (b) to Figure 2G (b) shows an exemplary semiconductor structure along Figure 1A The cross-sectional view of the cutting line BB' in Figure 2A (c) to Figure 2G (c) shows an exemplary semiconductor structure along Figure 1A Cross-sectional view of cutting line CC' in.

[0045] like Figure 2AAs shown in (a)-(c) of FIG. 1 , a semiconductor structure 200a is provided. The semiconductor structure 200a includes a first portion 218-1 and a second portion 218-2 arranged along the Y direction. The semiconductor structure 200a includes a substrate 202 and a stack 204 of alternating sacrificial layers 204D and insulating layers 204B provided on the substrate 102. The stack 204 may extend across the first portion 218-1 and the second portion 218-2. The sacrificial layers 204D and the insulating layers 204B may alternate in a vertical direction (e.g., a Z direction). The insulating layer 204B may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the sacrificial layer 204D may include a dielectric material different from the dielectric material of the insulating layer 204B. For example, the insulating layer 204B may include silicon oxide, and the sacrificial layer 204D may include silicon nitride.

[0046] The semiconductor structure 200a may include a first array of channel holes 213-1 located in the first portion 218-1 and a second array of channel holes 213-2 located in the second portion 218-2. The semiconductor structure 200a may also include gate line holes 215, which are arranged between the first portion 218-1 and the second portion 218-2 along a line extending in the X direction and are spaced apart. The first array of channel holes 213-1, the second array of channel holes 213-2, and the gate line holes 215 may extend through the stack 204 and into the substrate 202 along the Z direction. In some embodiments, the first array of channel holes 213-1, the second array of channel holes 213-2, and the gate line holes 215 may be formed by the same etching process. For example, the first array of channel holes 213-1, the second array of channel holes 213-2, and the gate line holes 215 may be formed using an etching mask ( Figure 2A The holes are formed by etching (not shown). The etching mask may have a pattern designed for these holes. The holes are formed by etching to extend through the sacrificial layer 204D and the insulating layer 204B of the stack 204 and down into the substrate 202.

[0047] like Figure 2BAs shown in (a)-(c) of FIG. 2 , a semiconductor structure 200b can be formed by filling a filler material (e.g., polysilicon) into the first array of channel holes 213-1, the second array of channel holes 213-2, and the gate line holes 215 of the semiconductor structure 200a. In some embodiments, before filling the filler material, a protective structure 217 can be formed on the bottom of the channel holes 213-1 and 213-2 and the gate line holes 215 (which is in contact with the substrate 202) to protect the substrate 202. For example, the protective structure 217 can be formed using polysilicon oxidation. A sacrificial film 219 can be deposited on top of the semiconductor structure 200a to cover the first array of channel holes 213-1, the second array of channel holes 213-2, and the gate line holes 215.

[0048] like Figure 2C As shown in (a)-(c) of FIG. 1 , a semiconductor structure 200 c may be formed, the semiconductor structure 200 c including channel structures in channel holes 213-1 and 213-2. The channel structure may include a first array of channel structures 212-1 formed in a first array of channel holes 213-1 and a second array of channel structures 212-2 formed in a second array of channel holes 213-2. The channel structures 212-1 and 212-2 may be formed as follows: a channel opening 214 is formed in a sacrificial film 219 to expose the channel holes 213-1 and 213-2; a filler material in the channel holes 213-1 and 213-2 is removed; and components of the channel structure (e.g., a high-K layer, a barrier layer, a charge trapping layer, a tunneling layer, a channel layer, a core filler layer, and a channel contact) may be subsequently filled into each of the channel holes 213-1 and 213-2.

[0049] like Figure 2D As shown in the semiconductor structure 200d in (a)-(c) of FIG. 1 , a new sacrificial film 219-2 may be formed on top of the semiconductor structure 200c to cover the first array of channel structures 212-1 and the second array of channel structures 212-2. Gate line openings 221 are formed in the sacrificial film 219-2 to expose the gate line holes 215. The filler material in the gate line holes 215 may be removed. The sacrificial layer 204D of the stack 204 may be removed by an etching process. For example, the etching process may be performed by filling the gate line holes 215 with an etchant.

[0050] like Figure 2EAs shown in (a)-(c) of FIG. 2 , a semiconductor structure 200e is formed. The stack 204 of the semiconductor structure 200e includes a conductive layer 204A located between insulating layers 204B. The conductive layers 204A and the insulating layers 204B alternate with each other along the vertical direction (e.g., the Z direction). In other words, the sacrificial layer 204D of the stack 204 in the semiconductor structure 200c is now replaced by the conductive layer 204A. The semiconductor structure 200e includes a conductive inner surface 222 (also referred to as a conductive inner layer) formed in the gate line hole 215. Each conductive inner layer 222 contacts the interior of the corresponding gate line hole 215. The conductive layer 204A is connected through the conductive inner layer 222. The conductive layer 204A and the conductive inner layer 222 can be formed by depositing at least one conductive material (e.g., W) into the gate line hole 215. In some embodiments, before forming the conductive layer 204A, a high-K dielectric material (e.g., Al2O3) may be deposited on the surface of the insulating layer 204B and the inner surface of the gate line hole 215 to form a liner 204C. The conductive layer 204A may be in contact with the liner 204C. In some embodiments, the liner 204C may include an adhesive material (e.g., TiN) and a high-K dielectric material. For example, Figure 2E As shown in Figures (a)-(c), liner 204C includes layer 204C-1 and layer 204C-2. Layer 204C-1 is made of a high-K material and contacts the surface of insulating layer 204B and the inner surface of gate line hole 215. Layer 204C-2 is made of an adhesive material. Layer 204C-1 can provide increased protection for conductive layer 204A and increase the breakdown voltage of conductive layer 204A. Layer 204C-2 can also strengthen the connection between liner 204C and conductive layer 204A.

[0051] like Figure 2F As shown in (a)-(c) of FIG. 2 , the semiconductor structure 200 f is formed by performing an etching process to etch away the conductive inner layer 222. For example, the etching process can be performed by filling an etchant into the gate line hole 215. The etching process can further expose the conductive layer 204A and recess the conductive layer 204A, and form tunnels 224. Each of the tunnels 224 extends in the XY plane and is located between two adjacent insulating layers 204B. The gate line hole 215 extends through the tunnel 224 in a vertical direction (e.g., the Z direction). The space formed by the tunnel 224 and the gate line hole 215 can be referred to as Figure 2F The gate line space 226 shown in (a)-(c) of FIG. Figure 2FAs shown in (a) and (b) of FIG. 2 , gate line space 226 can divide conductive layer 204A into a first group of conductive layers and a second group of conductive layers. The first group of conductive layers is located in portion 218-1 of semiconductor structure 200f. A first array of channel structures 212-1 extends through the first group of conductive layers along the Z direction. The second group of conductive layers is located in portion 218-2 of semiconductor structure 200f. A second array of channel structures 212-2 extends through the second group of conductive layers along the Z direction. The first group of conductive layers in portion 218-1 and the second group of conductive layers in portion 218-2 are electrically isolated by gate line space 226.

[0052] In some embodiments, depending on the choice of etchant, a portion of the liner 204C may also be removed by an etching process. Figure 2F As shown in (a)-(c), a portion of the adhesive material of the liner 204C (e.g., layer 204C-2) can be removed. In some other examples (in Figure 2F (not shown in (a)-(c)), a portion of the high-K material of the liner 204C (eg, layer 204C-1) may also be removed.

[0053] like Figure 2G As shown in (a)-(c), a semiconductor structure 200g is formed. The semiconductor structure 200g can be formed as shown in FIG. Figure 1A-1B The semiconductor structure 200g may be similar or identical to the semiconductor device 100 shown in FIG. The portion 218-1 and the portion 218-2 of the semiconductor structure 200g may be similar or identical to the memory block 118-1 and the memory block 118-2 of the semiconductor device 100, respectively. The semiconductor structure 200g includes a gate line structure 216 located in the gate line space 226. The gate line structure 216 may be similar to the gate line space 226. Figure 1A-1B 2. The gate line structure 216 may be similar to or identical to the gate line structure 116 of the semiconductor device 100. For example, the gate line structure 216 includes a gate line insulating layer 208 formed in the tunnel 224 and a pillar 210 formed in the gate line hole 215. The pillar 210 extends through the gate line insulating layer 208 in a vertical direction. Each gate line insulating layer 208 may be located between a corresponding conductive layer 204A in the portion 218-1 and a corresponding conductive layer 204A in the portion 218-2 along the Y direction. Each pillar 210 may include an outer layer 210A connected to the gate line insulating layer 208 and an inner structure 210B surrounded by the outer layer 210A. The gate line structure 216 may be similar to or identical to the gate line structure 116 of the semiconductor device 100. The pillar 210 may be similar to or identical to the pillar 110 of the semiconductor device 100.

[0054] In some embodiments, the gate line insulation layer 208 and the outer layer 210A of each of the pillars 210 can be formed by depositing a dielectric material through the gate line hole 215 in the gate line space 226. The inner structure 210B of each of the pillars 210 can be formed by filling the remaining space of the gate line hole 215 with a filler material. The filler material can include at least one of a polysilicon material, a dielectric material, or a metal. It should be understood that although Figure 2G The semiconductor structure 200g is shown to include two memory blocks 218-1 and 218-2 and one gate line structure 216, but in practice, the semiconductor device may include any appropriate number of memory blocks and any appropriate number of gate line structures.

[0055] Figure 3 3. A flow chart of an exemplary process 300 is shown. The process 300 may be performed to form a semiconductor device. The semiconductor device may be Figure 1A-1B The semiconductor device 100 is similar or identical to the semiconductor device 100 in FIG. Figure 2A-2G To describe process 300. Process 300 may include Figure 2A-2G It should be understood that the operations shown in process 300 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of these operations may be performed simultaneously or in parallel. Figure 3 The different orders shown in .

[0056] At operation 302, a semiconductor structure (eg, Figure 2E The semiconductor structure 200e in FIG. 2 may include conductive layers (eg, conductive layers 200b) alternating with each other along a first direction (eg, Z direction). Figure 2E The conductive layer 204A in the embodiment and the insulating layer (e.g., Figure 2E The insulating layer 204B in the stack (eg, Figure 2E The stack 204 in the embodiment of the present invention includes a channel structure extending through the stack along a first direction, and at least a first group of gate line holes (eg, a gate line hole extending through the stack along the first direction) extending through the stack. Figure 2E The gate line hole 215 in the channel structure includes at least a first array of channel structures (eg, Figure 2E ) and a second array of channel structures (e.g., Figure 2E The first group of gate line holes is located between the first array of channel structures and the second array of channel structures. The first group of gate line holes is spaced apart along a second direction (e.g., X direction) perpendicular to the first direction. The conductive layer is formed through the conductive inner surface (e.g., Figure 2EThe conductive inner surface 222 in the body is connected.

[0057] In some embodiments, providing a semiconductor structure includes forming sacrificial layers (eg, Figure 2A sacrificial layer 204D) and an insulating layer (eg, Figure 2A The insulating layer 204B in the stack (eg, Figure 2A Providing a semiconductor structure further includes: forming a gate line hole (eg, Figure 2A The gate line hole 215 in the embodiment of the present invention) and the channel hole (eg, Figure 2A The gate line holes and the channel holes extend through the stack of the sacrificial layer and the insulating layer along a first direction. The gate line holes include a first group of gate line holes. Providing a semiconductor structure further includes: forming a channel structure (e.g., Figure 2C channel structures 212-1 and 212-2 in FIG.

[0058] In some embodiments, providing a semiconductor structure further comprises: removing the sacrificial layer (e.g., as described in reference Figure 2D ) and forming a conductive layer and a conductive inner surface of the first set of gate line holes by depositing at least one conductive material into the first set of gate line holes (e.g., as described in reference Figure 2E described).

[0059] At operation 304, a first gate line space (eg, a first gate line hole) is formed by etching away the conductive inner surface of the first set of gate line holes to expose the conductive layer and recessing the conductive layer. Figure 2F The first gate line space includes: a tunnel (eg, Figure 2F The tunnel 224 in the insulating layer (eg Figure 2F and a first group of gate line holes (eg, Figure 2F The first set of gate line holes 215 in the tunnel extends through the tunnel along a first direction.

[0060] At operation 306, a first gate line structure (eg, Figure 2G 216 in the gate line structure).

[0061] In some embodiments, the first gate line space divides the conductive layer into a first array of channel structures (eg, Figure 2F The array of channel structures 212-1 in FIG) extends through a first set of conductive layers (eg, Figure 2F The conductive layer 204A in the portion 218-1 in the conductive layer 204A) and the second array of channel structures (eg, Figure 2FThe array of channel structures 212-2 in the second set of conductive layers (eg, Figure 2F conductive layer 204A in portion 218-2).

[0062] In some embodiments, the first gate line structure includes a gate line insulating layer (eg, Figure 2G 208 in the gate line insulation layer) and the pillars in the first set of gate line holes (eg, Figure 2G Each of the pillars includes an outer layer (eg, Figure 2G The outer layer 210A in the embodiment and the inner structure surrounded by the outer layer (e.g., Figure 2G Internal structure 210B).

[0063] In some embodiments, forming the first gate line structure includes forming a gate line insulation layer and an outer layer of each of the pillars by depositing a dielectric material through a first set of gate line holes in the first gate line spaces. Forming the first gate line structure also includes forming an inner structure of each of the pillars by filling the first set of gate line holes with at least one of a polysilicon material, a dielectric material, or a metal.

[0064] In some embodiments, forming a channel structure in the channel hole includes filling the gate line hole with a sacrificial material (eg, Figure 2A The gate line hole 215 in the embodiment of the present invention) and the channel hole (eg, Figure 2A channel holes 213-1 and 213-2 in the , covering the gate line holes (eg, using Figure 2C sacrificial film 219 in the channel hole), removing the sacrificial material in the channel hole (for example, as shown in reference Figure 2C ), and depositing a high-k material, a memory film, and a channel layer into each of the channel holes (e.g., as described in reference Figure 2C described).

[0065] In some embodiments, the channel structures further include a third array of channel structures, and the gate line holes further include a second group of gate line holes located between the second array of channel structures and the third array of channel structures.

[0066] Figure 4 1 shows a block diagram of an exemplary system 400. The system 400 may have one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure. The system 400 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 4 As shown, system 400 may include a host device 408 and a memory system 402 having one or more memory devices 404 and a memory controller 406. Host device 408 may include a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host device 408 may be configured to send data to or receive data from one or more memory devices 404.

[0067] The memory device 404 may be any memory device disclosed herein, such as Figure 1A-1B 4. The memory device (e.g., NAND flash memory) shown in FIG. A memory controller 406 (also referred to as a controller circuit) is coupled to the memory device 404 and the host device 408. Consistent with embodiments of the present disclosure, the memory device 404 may include a plurality of conductive interconnects that pass through the cover layer and contact the conductive pads in the conductive pad layer, and the memory controller 406 may be coupled to the memory device 404 via at least one of the plurality of conductive interconnects. The memory controller 406 is configured to control the memory device 404. For example, the memory controller 406 may be configured to operate a plurality of channel structures via word lines. The memory controller 406 may manage data stored in the memory device 404 and communicate with the host device 408.

[0068] In some embodiments, the memory controller 406 is designed / configured to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 406 is designed / configured to operate in a high duty cycle environment, such as an SSD or an embedded MultiMediaCard (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 406 can be configured to control the operations of the memory device 404 (e.g., read operations, erase operations, and program (or write) operations). The memory controller 406 can also be configured to manage various functions related to data stored or to be stored in the memory device 404, including but not limited to: bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 406 is also configured to process error correction code (ECC) on data read from or written to the memory device 404. Memory controller 406 may also perform any other suitable functions, such as formatting memory device 404 .

[0069] The memory controller 406 may communicate with an external device (e.g., the host device 408) according to a specific communication protocol. For example, the memory controller 406 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini-interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, and the like.

[0070] The memory controller 406 and the one or more memory devices 404 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage device (UFS) package or an eMMC package). That is, the memory system 402 can be implemented and packaged into different types of terminal electronic products. Figure 4 In one example shown, the memory controller 406 and the single memory device 404 may be integrated into a memory card 402. The memory card 402 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc.

[0071] The embodiments of the subject matter described in this disclosure and the actions and operations may be implemented in digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware (including the structures disclosed in this disclosure and their structural equivalents), or a combination of one or more thereof. The embodiments of the subject matter described in this disclosure may be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by a data processing device or for controlling the operation of the data processing device. The carrier may be a tangible, non-transitory computer storage medium. Alternatively or in addition, the carrier may be an artificially generated propagated signal, for example, a machine-generated electrical, optical, or electromagnetic signal, which is generated to encode information for transmission to an appropriate receiver device for execution by the data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more thereof, or a portion thereof. A computer storage medium is not a propagated signal.

[0072] It should be noted that references in this disclosure to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment must include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0073] Generally, a term can be understood, at least in part, from its usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a" or "the" can also be understood to convey singular usage or to convey plural usage. Additionally, also depending at least in part on the context, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but rather can allow for the presence of additional factors that are not necessarily explicitly described.

[0074] It should be readily understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween. Furthermore, “over” or “over” not only means “over something” or “on something,” but also includes the meaning of “over something” or “over something” with no intervening features or layers therebetween (i.e., directly on something).

[0075] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or process steps in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0076] As used herein, the term "substrate" refers to a material onto which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of a substrate is typically where semiconductor devices are formed, and therefore, unless otherwise specified, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite the top surface, and therefore, the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0077] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far away from the substrate. A layer can extend over the entire underlying or overlying structure, or can have a range that is smaller than the range of the underlying or overlying structure. In addition, a layer can be an area of ​​a uniform or non-uniform continuous structure having a thickness that is smaller than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers on, above and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductive and contact layers (wherein contacts, interconnect lines and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0078] As used herein, the term "nominal / nominally" refers to an expected or target value for a characteristic or parameter set for a component or process step during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. As used herein, a range of values ​​can be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates a value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" can indicate a value of a given quantity that varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0079] In this disclosure, the term “horizontal / horizontally / laterally” means nominally parallel to a lateral surface of a substrate, and the term “vertical / vertically” means nominally perpendicular to a lateral surface of a substrate.

[0080] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having a string of vertically oriented memory cell transistors (referred to herein as a "memory string," such as a NAND string) on ​​a laterally oriented substrate, such that the memory string extends in a vertical direction relative to the substrate.

[0081] The present disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be restrictive. For example, in the description below, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature may be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0082] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, based on the teaching and guidance provided herein, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments.

[0083] Although this disclosure contains many specific implementation details, these should not be interpreted as limitations on the scope of the claims defined by the claims themselves, but rather as descriptions of features that may be directed to specific embodiments of specific inventions. Certain features described in this disclosure may also be implemented in combination in a single embodiment in the context of separate embodiments. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any appropriate sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed as such, one or more features from the claimed combination may in some cases be deleted from the combination, and claims may be directed to sub-combinations or variations of sub-combinations.

[0084] Similarly, although operations are depicted in the drawings and recited in the claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order or sequence shown, or that all illustrated operations be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0085] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the particular order or sequence shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

[0086] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device comprising: memory blocks, the memory blocks including at least a first memory block and a second memory block, wherein each of the first memory block and the second memory block includes a stack of conductive layers and insulating layers alternating with each other along a first direction; and At least a first gate line structure, the first gate line structure being located between the first storage block and the second storage block, wherein the first gate line structure insulates the conductive layer of the first storage block from the conductive layer of the second storage block, and the first gate line structure comprises: a gate line insulating layer, the gate line insulating layer being spaced apart along the first direction; and Pillars are spaced apart along a second direction perpendicular to the first direction and extend through the gate line insulating layer along the first direction.

2. The semiconductor device according to claim 1, wherein The first gate line structure contacts a sidewall of the first memory block and a sidewall of the second memory block.

3. The semiconductor device according to claim 1 or claim 2, wherein: The gate line insulating layer in the gate line insulating layer is located between the corresponding conductive layer of the first memory block and the corresponding conductive layer of the second memory block.

4. The semiconductor device according to claim 1 or claim 2, wherein: One of the pillars includes an outer layer and an inner structure surrounded by the outer layer, the outer layer includes a dielectric material, and the inner structure includes at least one of a polysilicon material, a dielectric material, or a metal.

5. The semiconductor device according to claim 1 or claim 2, wherein One of the gate line insulating layers includes a dielectric material. 6 . The semiconductor device according to claim 1 , further comprising a third memory block and a second gate line structure located between the second memory block and the third memory block.

7. The semiconductor device according to claim 1 or claim 2, further comprising one or more other gate line structures, wherein: The first memory block includes a plurality of memory fingers separated by the one or more other gate line structures.

8. The semiconductor device according to claim 1 or claim 2, wherein: The stack of conductive and insulating layers includes a plurality of stacks stacked along the first direction, and each stack of the plurality of stacks includes a subset of the stack of conductive and insulating layers.

9. A method for manufacturing a semiconductor device, comprising: A semiconductor structure is provided, comprising: a stack of conductive layers and insulating layers alternating with each other along a first direction; a channel structure extending through the stack along the first direction, wherein the channel structure comprises at least a first array of channel structures and a second array of channel structures; and At least a first set of gate line holes extending through the stack along the first direction, wherein: The first group of gate line holes is located between the first array of channel structures and the second array of channel structures; The first set of gate line holes are spaced apart along a second direction perpendicular to the first direction; and The conductive layer is connected through the conductive inner surfaces of the first group of gate line holes; forming a first gate line space by etching away the conductive inner surfaces of the first group of gate line holes to expose the conductive layer and recessing the conductive layer, wherein the first gate line space comprises: a tunnel located between the insulating layers and extending along the second direction; and the first group of gate line holes extending through the tunnel along the first direction; and A first gate line structure is formed in the first gate line space.

10. The method according to claim 9, wherein: The first gate line spaces divide the conductive layers into a first group of conductive layers through which the first array of channel structures extends, and a second group of conductive layers through which the second array of channel structures extends.

11. The method according to claim 9 or claim 10, wherein: The first gate line structure includes: a gate line insulating layer located in the tunnel; and Pillars are positioned in the first group of gate line holes, wherein each of the pillars includes an outer layer connected to the gate line insulating layer and an inner structure surrounded by the outer layer.

12. The method according to claim 11, wherein Forming the first gate line structure includes: forming the gate line insulating layer and the outer layer of each of the pillars by depositing a dielectric material in the first gate line space through the first set of gate line holes; and The inner structure of each of the pillars is formed by filling at least one of a polysilicon material, a dielectric material, or a metal into the first set of gate line holes.

13. The method according to claim 9 or claim 10, wherein: Providing the semiconductor structure includes: forming a stack of sacrificial layers and insulating layers alternating with each other along the first direction; forming gate line holes and channel holes by a same etching process, wherein the gate line holes and the channel holes extend through the stack of the sacrificial layer and the insulating layer along the first direction, and the gate line holes include the first group of gate line holes; and The channel structure is formed in the channel hole.

14. The method according to claim 13, wherein: Providing the semiconductor structure further includes: removing the sacrificial layer; and The conductive layer and the conductive inner surfaces of the first set of gate line holes are formed by depositing at least one conductive material into the first set of gate line holes.

15. The method according to claim 13, wherein The channel structures further include a third array of channel structures, and the gate line apertures further include a second group of gate line apertures located between the second array of channel structures and the third array of channel structures.

16. The method according to claim 13, wherein: Forming the channel structure in the channel hole includes: filling the gate line hole and the channel hole with a sacrificial material; covering the gate line hole; removing the sacrificial material in the trench hole; and A high-k material, a memory film, and a channel layer are deposited into each of the channel holes.

17. A memory system comprising: memory device; as well as a memory controller coupled to the memory device and configured to control the memory device, Wherein, the memory device comprises: memory blocks, the memory blocks including at least a first memory block and a second memory block, wherein each of the first memory block and the second memory block includes a stack of conductive layers and insulating layers alternating with each other along a first direction; and At least a first gate line structure, the first gate line structure being located between the first storage block and the second storage block, wherein the first gate line structure insulates the conductive layer of the first storage block from the conductive layer of the second storage block, and the first gate line structure comprises: a gate line insulating layer, the gate line insulating layer being spaced apart along the first direction; and Pillars are spaced apart along a second direction perpendicular to the first direction and extend through the gate line insulating layer along the first direction.

18. The memory system according to claim 17, wherein: The gate line insulating layer in the gate line insulating layer is located between the corresponding conductive layer of the first memory block and the corresponding conductive layer of the second memory block.

19. The memory system of claim 17 or claim 18, wherein: One of the pillars includes an outer layer and an inner structure surrounded by the outer layer, the outer layer includes a dielectric material, and the inner structure includes at least one of a polysilicon material, a dielectric material, or a metal.

20. The memory system of claim 17 or claim 18, wherein: The memory device further includes a third memory block and a second gate line structure located between the second memory block and the third memory block.

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