Semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device. According to one embodiment, a semiconductor device includes: a semiconductor layer including a plurality of first trenches and a plurality of second trenches extending in a first direction; a first gate electrode in the first trench; a second gate electrode in the second trench; a first gate wiring including a first upper metal layer and a first lower metal layer and electrically connected to the first gate electrode; and a second gate wiring including a second upper metal layer and a second lower metal layer and electrically connected to the second gate electrode, the first lower metal layer and the second upper metal layer are not present or the first upper metal layer and the second lower metal layer are not present at a first crossing portion where the first gate wiring and the second gate wiring intersect.

Description

[0001] Related applications

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2024-061319 (filing date: April 5, 2024), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Art

[0004] An example of a semiconductor device for power is an insulated gate bipolar transistor (IGBT). For example, an IGBT has a p-type collector region, an n-type drift region, and a p-type base region disposed on a collector electrode. Furthermore, a gate electrode is disposed within a trench that penetrates the p-type base region and reaches the n-type drift region, with a gate insulating film sandwiched between them. Furthermore, an n-type emitter region connected to the emitter electrode is disposed in an area adjacent to the trench on the surface of the p-type base region.

[0005] In an IGBT, a positive voltage greater than the threshold voltage is applied to the gate electrode, forming a channel in the p-type base region. Electrons are then injected from the n-type emitter region into the n-type drift region, while holes are injected from the collector region into the n-type drift region. This causes a current, with electrons and holes as carriers, to flow between the collector and emitter electrodes.

[0006] In IGBTs, it's desirable to balance reducing on-resistance with reducing switching losses. To achieve this balance, IGBTs that independently drive multiple gates have been proposed. By varying the drive timing of these multiple gates, the IGBT's switching time can be shortened, reducing switching losses.

[0007] In an IGBT that drives multiple gates independently, multiple gate wirings are provided, connected to multiple gate electrode pads. Each of these gate wirings is connected to the gate electrodes of different gates. If the resistance of the gate wiring increases, signal wiring delays occur, making it difficult to increase the speed of the IGBT operation, for example. Therefore, it is desirable to reduce the resistance of the gate wiring. Summary of the Invention

[0008] A semiconductor device according to an embodiment comprises: a semiconductor layer having a first surface and a second surface opposite to the first surface, comprising a plurality of first trenches provided on one side of the first surface and extending in a first direction parallel to the first surface, and a plurality of second trenches provided on one side of the first surface and extending in the first direction; a first electrode provided on one side of the first surface of the semiconductor layer; a second electrode provided on one side of the second surface of the semiconductor layer; a first gate electrode provided in the first trench; a second gate electrode provided in the second trench; a first gate wiring provided on one side of the first surface of the semiconductor layer, comprising a first upper metal layer and a first lower metal layer provided between the first upper metal layer and the first surface, and comprising a first portion extending in a second direction parallel to the first surface and perpendicular to the first direction, and a second portion extending in the second direction and having the first electrode provided between the first portion, the first gate wiring being electrically connected to the first gate electrode; and the second gate wiring, A device is provided on one side of the first surface of the semiconductor layer, comprising a second upper metal layer and a second lower metal layer provided between the second upper metal layer and the first surface, and comprising a third part extending along the second direction and a fourth part extending along the second direction and having the first electrode provided between the third part, the second gate wiring being electrically connected to the second gate electrode; a first gate electrode pad is provided on one side of the first surface of the semiconductor layer and is electrically connected to the first gate wiring; and a second gate electrode pad is provided on one side of the first surface of the semiconductor layer and is electrically connected to the second gate wiring; the first part is provided between the third part and the first electrode, the second part is provided between the fourth part and the first electrode, the first gate wiring and the second gate wiring intersect at a first intersection, and at the first intersection, the first lower metal layer and the second upper metal layer do not exist or the first upper metal layer and the second lower metal layer do not exist.

[0009] According to this embodiment, a semiconductor device capable of reducing the resistance of a gate wiring can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the semiconductor device according to the first embodiment.

[0011] Figure 2 It is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0012] Figure 3 It is a schematic plan view of the semiconductor device according to the first embodiment.

[0013] Figure 4 This is a schematic diagram of a portion of the semiconductor device according to the first embodiment.

[0014] Figure 5 It is a schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment.

[0015] Figure 6 It is a schematic diagram of the semiconductor device according to the first embodiment.

[0016] Figure 7 It is a schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment.

[0017] Figure 8 This is a schematic diagram of a comparative semiconductor device.

[0018] Figure 9 This is a schematic diagram of a semiconductor device according to a first modification of the first embodiment.

[0019] Figure 10 This is a schematic cross-sectional view of a portion of a semiconductor device according to a first modification of the first embodiment.

[0020] Figure 11 It is a schematic diagram of a semiconductor device according to a second modification of the first embodiment.

[0021] Figure 12 It is a schematic diagram of a semiconductor device according to a second modification of the first embodiment.

[0022] Figure 13 This is a schematic diagram of a semiconductor device according to a third modified example of the first embodiment.

[0023] Figure 14 This is a schematic diagram of a semiconductor device according to a third modified example of the first embodiment.

[0024] Figure 15 It is a schematic diagram of a semiconductor device according to a second embodiment.

[0025] Figure 16 This is a schematic diagram of a portion of a semiconductor device according to a second embodiment.

[0026] Figure 17 It is a schematic cross-sectional view of a portion of the semiconductor device according to the second embodiment.

[0027] Figure 18 It is a schematic diagram of a semiconductor device according to a second embodiment.

[0028] Figure 19 It is a schematic cross-sectional view of a portion of a semiconductor device according to a first modification of the second embodiment.

[0029] Description of Reference Numerals

[0030] 10 semiconductor layer

[0031] 11First gate wiring

[0032] 11a Part 1

[0033] 11b Part 2

[0034] 11c Part 7

[0035] 11x first lower metal layer

[0036] 11y first upper metal layer

[0037] 12 Second gate wiring

[0038] 12a Part 3

[0039] 12b Part 4

[0040] 12c Part 8

[0041] 12x second lower metal layer

[0042] 12y second upper metal layer

[0043] 13Third gate wiring

[0044] 13a Part 5

[0045] 13b Part 6

[0046] 13c Part 9

[0047] 13x third lower metal layer

[0048] 13y third upper metal layer

[0049] 21 emitter electrode (first electrode)

[0050] 21x fourth lower metal layer

[0051] 21y fourth upper metal layer

[0052] 22 collector electrode (second electrode)

[0053] 31 first gate electrode

[0054] 32 second gate electrode

[0055] 33 third gate electrode

[0056] 37 Second interlayer insulating layer (insulating layer)

[0057] 41 first gate trench (first trench)

[0058] 42 second gate trench (second trench)

[0059] 43 third gate trench (third trench)

[0060] 100IGBT (semiconductor device)

[0061] 101 first gate electrode pad

[0062] 102 second gate electrode pad

[0063] 103 third gate electrode pad

[0064] 200IGBT (semiconductor device)

[0065] F1 first page

[0066] F2 second page

[0067] J1 first intersection

[0068] J2 second intersection

[0069] J3 third intersection

[0070] d1 first distance

[0071] w1 first width

[0072] w2 second width

[0073] w3 third width

[0074] w4 fourth width

[0075] w5 fifth width DETAILED DESCRIPTION

[0076] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same reference numerals may be assigned to the same or similar components, and description of components that have been described once may be omitted as appropriate.

[0077] In this manual, when there is n + Type, n-type, n － In the case of the type description, it refers to the n-type impurity concentration in accordance with n + Type, n-type, n － In addition, when there is p + Type, p-type, p － In the case of the expression of type, it refers to the p-type impurity concentration according to p + Type, p-type, p － The order of types decreases.

[0078] (First embodiment)

[0079] A semiconductor device according to a first embodiment comprises: a semiconductor layer having a first surface and a second surface opposite to the first surface, comprising a plurality of first trenches provided on one side of the first surface and extending in a first direction parallel to the first surface, and a plurality of second trenches provided on one side of the first surface and extending in the first direction; a first electrode provided on one side of the first surface of the semiconductor layer; a second electrode provided on one side of the second surface of the semiconductor layer; a first gate electrode provided in the first trench; a second gate electrode provided in the second trench; a first gate wiring provided on one side of the first surface of the semiconductor layer, comprising a first upper metal layer and a first lower metal layer provided between the first upper metal layer and the first surface, and comprising a second trench provided along a second trench parallel to the first surface and perpendicular to the first direction. The invention further comprises a first gate wiring having a first portion extending in a first direction and a second portion extending in a second direction with a first electrode disposed therebetween, the first gate wiring being electrically connected to the first gate electrode; a second gate wiring being provided on one side of the first surface of the semiconductor layer, comprising a second upper metal layer and a second lower metal layer disposed between the second upper metal layer and the first surface, and comprising a third portion extending in the second direction and a fourth portion extending in the second direction with the first electrode disposed therebetween, the second gate wiring being electrically connected to the second gate electrode; a first gate electrode pad being provided on one side of the first surface of the semiconductor layer and electrically connected to the first gate wiring; and a second gate electrode pad being provided on one side of the first surface of the semiconductor layer and electrically connected to the second gate wiring. The first portion is provided between the third portion and the first electrode, and the second portion is provided between the fourth portion and the first electrode. The first gate wiring and the second gate wiring intersect at a first intersection, and at the first intersection, the first lower metal layer and the second upper metal layer are either absent or non-existent.

[0080] The semiconductor device of the first embodiment is a trench-gate IGBT 100 having a gate electrode in a trench formed in a semiconductor layer. The IGBT 100 has three independently controllable gates and is a triple-gate drive IGBT.

[0081] The IGBT100 of the first embodiment includes a semiconductor layer 10, a first gate wiring 11, a second gate wiring 12, a third gate wiring 13, a first contact portion 16, a second contact portion 17, a third contact portion 18, an emitter electrode 21 (first electrode), a collector electrode 22 (second electrode), a gate insulating film 23, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a first interlayer insulating layer 36, a second interlayer insulating layer 37 (insulating layer), a first gate electrode pad 101, a second gate electrode pad 102 and a third gate electrode pad 103.

[0082] The first gate wiring 11 includes a first portion 11a and a second portion 11b. The first gate wiring 11 includes a first lower metal layer 11x and a first upper metal layer 11y.

[0083] The second gate wiring 12 includes a third portion 12a and a fourth portion 12b. The second gate wiring 12 includes a second lower metal layer 12x and a second upper metal layer 12y.

[0084] The third gate wiring 13 includes a fifth portion 13a and a sixth portion 13b. The third gate wiring 13 includes a third lower metal layer 13x and a third upper metal layer 13y.

[0085] The emitter electrode 21 includes a fourth lower metal layer 21 x and a fourth upper metal layer 21 y .

[0086] A first gate trench 41 (first trench), a second gate trench 42 (second trench), a third gate trench 43 (third trench), a collector region 51 , a drift region 52 , a base region 53 , an emitter region 54 , and a contact region 55 are provided in the semiconductor layer 10 .

[0087] Figure 1 (a) Figure 1 (b) is a schematic diagram of the semiconductor device according to the first embodiment. Figure 1 (a) shows a layout pattern of the first gate wiring 11 , the second gate wiring 12 , the third gate wiring 13 , the first gate electrode pad 101 , the second gate electrode pad 102 , the third gate electrode pad 103 , and the emitter electrode 21 . Figure 1 (b) shows the layout pattern of the first gate trench 41 , the second gate trench 42 , and the third gate trench 43 .

[0088] like Figure 1 As shown in (a), first gate wiring 11 is connected to first gate electrode pad 101. First gate wiring 11 is electrically and physically connected to first gate electrode pad 101. First portion 11a of the first gate wiring extends along the second direction. Second portion 11b of the first gate wiring extends along the second direction. Emitter electrode 21 is provided between first portion 11a and second portion 11b.

[0089] The first gate wiring 11 surrounds the emitter electrode 21 .

[0090] like Figure 1As shown in (a), second gate wiring 12 is connected to second gate electrode pad 102. Second gate wiring 12 is electrically and physically connected to second gate electrode pad 102. Third portion 12a of the second gate wiring extends along the second direction. Fourth portion 12b of the second gate wiring extends along the second direction. Emitter electrode 21 is provided between third portion 12a and fourth portion 12b. Second gate wiring 12 surrounds emitter electrode 21.

[0091] The first portion 11 a of the first gate wiring is provided between the third portion 12 a of the second gate wiring and the emitter electrode 21 . The second portion 11 b of the first gate wiring is provided between the fourth portion 12 b of the second gate wiring and the emitter electrode 21 .

[0092] like Figure 1 As shown in (a), third gate wiring 13 is connected to third gate electrode pad 103. Third gate wiring 13 is electrically and physically connected to third gate electrode pad 103. Fifth portion 13a of the third gate wiring extends along the second direction. Sixth portion 13b of the third gate wiring extends along the second direction. Emitter electrode 21 is provided between fifth portion 13a and sixth portion 13b. Third gate wiring 13 surrounds emitter electrode 21.

[0093] The third portion 12a of the second gate wiring is provided between the fifth portion 13a of the third gate wiring and the emitter electrode 21. The fourth portion 12b of the second gate wiring is provided between the sixth portion 13b of the third gate wiring and the emitter electrode 21.

[0094] The first gate wiring 11 and the second gate wiring 12 intersect at the first intersection J1. The first gate wiring 11 and the third gate wiring 13 intersect at the second intersection J2. The second gate wiring 12 and the third gate wiring 13 intersect at the third intersection J3.

[0095] like Figure 1 As shown in (b), the first gate trench 41, the second gate trench 42 and the third gate trench 43 extend along the first direction.

[0096] Figure 2 It is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 yes Figure 1 AA' section of (a). Figure 2 This is a cross section including the emitter electrode 21 .

[0097] Figure 3 It is a schematic plan view of the semiconductor device according to the first embodiment. Figure 3 It is a top view of the first surface F1. Figure 2 yes Figure 3 A-A' section.

[0098] Semiconductor layer 10 has a first surface F1 and a second surface F2 facing first surface F1. Semiconductor layer 10 is made of, for example, single crystal silicon.

[0099] In this specification, a direction parallel to the first surface F1 is referred to as a first direction. Furthermore, a direction parallel to the first surface F1 and perpendicular to the first direction is referred to as a second direction. Furthermore, a direction normal to the first surface F1 is referred to as a third direction.

[0100] Emitter electrode 21 is provided on one side of first surface ( F1 ) of semiconductor layer 10 . At least a portion of emitter electrode 21 is in contact with first surface ( F1 ) of semiconductor layer 10 .

[0101] The emitter electrode 21 is made of metal and includes a fourth lower metal layer 21 x and a fourth upper metal layer 21 y . The fourth lower metal layer 21 x is provided between the fourth upper metal layer 21 y and the first surface F1 .

[0102] The fourth lower metal layer 21x is formed of a first material, which is a metal. The fourth upper metal layer 21y is formed of a second material, which is a metal.

[0103] The first material and the second material are different metals. The first material includes, for example, tungsten (W), molybdenum (Mo), or tantalum (Ta). The second material includes, for example, aluminum (Al) or copper (Cu).

[0104] The fourth lower metal layer 21x is, for example, a stacked film of titanium, titanium nitride, and tungsten, and the fourth upper metal layer 21y is, for example, a stacked film of titanium, titanium nitride, and aluminum.

[0105] The fourth lower metal layer 21x is electrically and physically connected to the fourth upper metal layer 21y. An insulating layer may be provided in a portion between the fourth lower metal layer 21x and the fourth upper metal layer 21y.

[0106] The emitter electrode 21 is electrically connected to the emitter region 54 and the contact region 55. An emitter voltage is applied to the emitter electrode 21. The emitter voltage is 0V, for example.

[0107] The collector electrode 22 is provided on one side of the second surface F2 of the semiconductor layer 10. At least a portion of the collector electrode 22 is in contact with the second surface F2 of the semiconductor layer 10. The collector electrode 22 is made of metal, for example.

[0108] The collector electrode 22 is electrically connected to the p-type collector region 51. A collector voltage is applied to the collector electrode 22. The collector voltage is, for example, 200 V or more and 6500 V or less.

[0109] The collector region 51 is a p-type semiconductor region. The collector region 51 is electrically connected to the collector electrode 22. The collector region 51 is in contact with the collector electrode 22. The collector region 51 serves as a source of holes when the IGBT 100 is in the on state.

[0110] The drift region 52 is n － The drift region 52 is provided between the collector region 51 and the first surface F1. The drift region 52 serves as a path for the on-current when the IGBT 100 is in the on-state. The drift region 52 is depleted when the IGBT 100 is in the off-state, maintaining the withstand voltage of the IGBT 100.

[0111] The base region 53 is a p-type semiconductor region and is provided between the drift region 52 and the first surface F1 . The base region 53 functions as a channel region of the transistor.

[0112] The emitter region 54 is n + The emitter region 54 is provided between the base region 53 and the first surface F1. The emitter region 54 is electrically connected to the emitter electrode 21. The emitter region 54 is in contact with the emitter electrode 21. The emitter region 54 serves as a source of electrons when the transistor is in the on state.

[0113] The contact area 55 is p + The contact region 55 is provided between the base region 53 and the first surface F1. The contact region 55 is provided adjacent to or separated from the emitter region 54. The contact region 55 is electrically connected to the emitter electrode 21.

[0114] A plurality of first gate trenches 41 are provided on one side of the first surface F1 of the semiconductor layer 10. Figure 3 As shown, the first gate trench 41 extends in a first direction parallel to the first plane F1 in the first plane F1. The first gate trench 41 has a stripe shape. A plurality of first gate trenches 41 are repeatedly arranged along a second direction orthogonal to the first direction. The first gate trenches 41 penetrate the base region 53 and reach the drift region 52.

[0115] A plurality of second gate trenches 42 are provided on one side of the first surface F1 of the semiconductor layer 10. Figure 3 As shown, the second gate trenches 42 extend along the first direction in the first plane F1. The second gate trenches 42 have a stripe shape. The second gate trenches 42 are repeatedly arranged along the second direction. The second gate trenches 42 penetrate the base region 53 and reach the drift region 52.

[0116] A plurality of third gate trenches 43 are provided on one side of the first surface F1 of the semiconductor layer 10. Figure 3As shown, the third gate trenches 43 extend along the first direction in the first plane F1. The third gate trenches 43 have a stripe shape. The third gate trenches 43 are repeatedly arranged along the second direction. The third gate trenches 43 penetrate the base region 53 and reach the drift region 52.

[0117] The first gate electrode 31 is disposed in the first gate trench 41 . The first gate electrode 31 is, for example, a semiconductor or metal. The first gate electrode 31 is, for example, polysilicon containing conductive impurities. The first gate electrode 31 is electrically connected to the first gate wiring 11 and the first gate electrode pad 101 .

[0118] The second gate electrode 32 is disposed in the second gate trench 42 . The second gate electrode 32 is, for example, a semiconductor or metal. The second gate electrode 32 is, for example, polysilicon containing conductive impurities. The second gate electrode 32 is electrically connected to the second gate wiring 12 and the second gate electrode pad 102 .

[0119] The third gate electrode 33 is disposed in the third gate trench 43 . The third gate electrode 33 is, for example, a semiconductor or metal. The third gate electrode 33 is, for example, polysilicon containing conductive impurities. The third gate electrode 33 is electrically connected to the third gate wiring 13 and the third gate electrode pad 103 .

[0120] The gate insulating film 23 is provided between the first gate electrode 31 and the semiconductor layer 10. The gate insulating film 23 is provided between the second gate electrode 32 and the semiconductor layer 10. The gate insulating film 23 is provided between the third gate electrode 33 and the semiconductor layer 10. The gate insulating film 23 is, for example, silicon oxide.

[0121] The first interlayer insulating layer 36 is provided between the first gate electrode 31 and the emitter electrode 21 . The first interlayer insulating layer 36 electrically isolates the first gate electrode 31 from the emitter electrode 21 .

[0122] The first interlayer insulating layer 36 is provided between the second gate electrode 32 and the emitter electrode 21 . The first interlayer insulating layer 36 electrically isolates the second gate electrode 32 from the emitter electrode 21 .

[0123] The first interlayer insulating layer 36 is provided between the third gate electrode 33 and the emitter electrode 21 . The first interlayer insulating layer 36 electrically isolates the third gate electrode 33 from the emitter electrode 21 .

[0124] The first interlayer insulating layer 36 is made of silicon oxide, for example.

[0125] Figure 4 (a) Figure 4 (b) is a schematic diagram of a portion of the semiconductor device according to the first embodiment. Figure 4 (a) is Figure 1An enlarged view of the first region R1 shown in (a). Figure 4 (b) is Figure 1 An enlarged view of the second region R2 shown in (a).

[0126] Figure 4 (a) Figure 4 (b) shows a layout pattern of the first gate wiring 11 , the second gate wiring 12 , the third gate wiring 13 , the first contact 16 , the second contact 17 , the third contact 18 , and the emitter electrode 21 .

[0127] like Figure 4 As shown in FIG. 1 , a first contact 16 is provided at a portion where the first portion 11 a of the first gate wiring intersects the first gate trench 41 . In the first contact 16 , the first portion 11 a is electrically and physically connected to the first gate electrode 31 provided in the first gate trench 41 .

[0128] like Figure 4 As shown in FIG. 1 , a second contact 17 is provided at a portion where the third portion 12a of the second gate wiring intersects the second gate trench 42. In the second contact 17, the third portion 12a is electrically and physically connected to the second gate electrode 32 provided in the second gate trench 42.

[0129] like Figure 4 As shown in FIG. 1 , a third contact portion 18 is provided at a portion where the fifth portion 13a of the third gate wiring intersects the third gate trench 43. In the third contact portion 18, the fifth portion 13a is electrically and physically connected to the third gate electrode 33 provided in the third gate trench 43.

[0130] like Figure 4 As shown in FIG. 1 , a first contact portion 16 is provided at a portion where the second portion 11b of the first gate wiring intersects the first gate trench 41. In the first contact portion 16, the second portion 11b is electrically and physically connected to the first gate electrode 31 provided in the first gate trench 41.

[0131] like Figure 4 As shown in FIG. 1 , a second contact portion 17 is provided at a portion where the fourth portion 12b of the second gate wiring intersects the second gate trench 42. In the second contact portion 17, the fourth portion 12b is electrically and physically connected to the second gate electrode 32 provided in the second gate trench 42.

[0132] like Figure 4As shown in FIG. 1 , a third contact portion 18 is provided at a portion where the sixth portion 13b of the third gate wiring intersects the third gate trench 43. In the third contact portion 18, the sixth portion 13b is electrically and physically connected to the third gate electrode 33 provided in the third gate trench 43.

[0133] Figure 5 It is a schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment. Figure 5 yes Figure 4 BB' section of (a).

[0134] The first gate wiring 11 is made of metal and includes a first lower metal layer 11x and a first upper metal layer 11y. The first lower metal layer 11x is provided between the first upper metal layer 11y and the first plane F1.

[0135] The second gate wiring 12 is made of metal and includes a second lower metal layer 12x and a second upper metal layer 12y. The second lower metal layer 12x is provided between the second upper metal layer 12y and the first surface F1.

[0136] The third gate wiring 13 is made of metal and includes a third lower metal layer 13x and a third upper metal layer 13y. The third lower metal layer 13x is provided between the third upper metal layer 13y and the first plane F1.

[0137] The first lower metal layer 11x, the second lower metal layer 12x, and the third lower metal layer 13x are formed of a first material. The first material is a metal. The first material of the first lower metal layer 11x, the second lower metal layer 12x, and the third lower metal layer 13x is the same as the first material of the fourth lower metal layer 21x of the emitter electrode 21.

[0138] The first upper metal layer 11y, the second upper metal layer 12y, and the third upper metal layer 13y are formed of a second material. The second material is a metal. The second material of the first upper metal layer 11y, the second upper metal layer 12y, and the third upper metal layer 13y is the same as the second material of the fourth upper metal layer 21y of the emitter electrode 21.

[0139] The first material and the second material are different metals. The first material includes, for example, tungsten (W), molybdenum (Mo), or tantalum (Ta). The second material includes, for example, aluminum (Al) or copper (Cu).

[0140] The first lower metal layer 11 x , the second lower metal layer 12 x , and the third lower metal layer 13 x are, for example, stacked films of titanium, titanium nitride, and tungsten.

[0141] The first upper metal layer 11 y , the second upper metal layer 12 y , and the third upper metal layer 13 y are, for example, stacked films of titanium, titanium nitride, and aluminum.

[0142] The first lower metal layer 11 x , the second lower metal layer 12 x , and the third lower metal layer 13 x are electrically and physically connected to the first upper metal layer 11 y , the second upper metal layer 12 y , and the third upper metal layer 13 y , respectively.

[0143] The first gate wiring 11 , the second gate wiring 12 , and the third gate wiring 13 each have a stacked structure of two different metal layers.

[0144] like Figure 5 As shown, the second interlayer insulating layer 37 is provided, for example, between a portion of the first lower metal layer 11x and a portion of the first upper metal layer 11y. The second interlayer insulating layer 37 is provided, for example, between a portion of the second lower metal layer 12x and a portion of the second upper metal layer 12y. The second interlayer insulating layer 37 is provided, for example, between a portion of the third lower metal layer 13x and a portion of the third upper metal layer 13y.

[0145] like Figure 5 As shown, the first lower metal layer 11 x of the first gate wiring is connected to the first gate electrode 31 at the first contact portion 16 .

[0146] Figure 6 (a) Figure 6 (b) is a schematic diagram of the semiconductor device according to the first embodiment. Figure 6 (a) shows a layout pattern of the first lower metal layer 11x of the first gate wiring, the second lower metal layer 12x of the second gate wiring, the third lower metal layer 13x of the third gate wiring, and the fourth lower metal layer 21x of the emitter electrode. Figure 6 (b) shows a layout pattern of the first upper metal layer 11y of the first gate wiring, the second upper metal layer 12y of the second gate wiring, the third upper metal layer 13y of the third gate wiring, and the fourth upper metal layer 21y of the emitter electrode.

[0147] In addition, Figure 6 (b) also shows the layout pattern of the first gate electrode pad 101, the second gate electrode pad 102 and the third gate electrode pad 103 formed by the same second material as the first upper metal layer 11y, the second upper metal layer 12y, the third upper metal layer 13y and the fourth upper metal layer 21y.

[0148] like Figure 6As shown in (a) of FIG. 1 , the first lower metal layer 11x surrounds the fourth lower metal layer 21x. The first lower metal layer 11x surrounds the emitter electrode 21. The first lower metal layer 11x has a ring shape within a plane parallel to the first plane F1.

[0149] like Figure 6 As shown in (a), the second lower metal layer 12x surrounds the fourth lower metal layer 21x. The second lower metal layer 12x surrounds the emitter electrode 21. The second lower metal layer 12x surrounds the first lower metal layer 11x. The second lower metal layer 12x is annular in a plane parallel to the first plane F1.

[0150] like Figure 6 As shown in (a), the third lower metal layer 13x surrounds the fourth lower metal layer 21x. The third lower metal layer 13x surrounds the emitter electrode 21. The third lower metal layer 13x surrounds the second lower metal layer 12x. The third lower metal layer 13x is annular in a plane parallel to the first plane F1.

[0151] like Figure 6 As shown in (a) of FIG. 1 , the first lower metal layer 11x of the first gate wiring does not exist at the first intersection J1 of the first gate wiring 11 and the second gate wiring 12. Figure 6 As shown in (b), the second upper metal layer 12y of the second gate wiring does not exist at the first intersection J1.

[0152] Figure 7 It is a schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment. Figure 7 It is a cross section of the first intersection J1. Figure 7 It is a cross section parallel to the first direction and perpendicular to the second direction.

[0153] like Figure 7 As shown, at the first intersection J1, with respect to the second gate wiring 12, only the second lower metal layer 12x of the second gate wiring is continuous along the first direction. Furthermore, at the first intersection J1, with respect to the first gate wiring 11, only the first upper metal layer 11y of the first gate wiring is continuous along the second direction perpendicular to the paper.

[0154] At the first intersection J1, the first gate wiring 11 and the second gate wiring 12 are separated by sandwiching the second interlayer insulating layer 37. Therefore, at the first intersection J1, the first gate wiring 11 and the second gate wiring 12 are not short-circuited.

[0155] like Figure 6 As shown in (a), the first lower metal layer 11x of the first gate wiring does not exist at the second intersection J2 of the first gate wiring 11 and the third gate wiring 13. Figure 6As shown in (b), the second upper metal layer 12y of the second gate wiring does not exist at the second intersection J2. Therefore, the first gate wiring 11 and the third gate wiring 13 are not short-circuited at the second intersection J2.

[0156] like Figure 6 As shown in (a), at the third intersection J3 between the second gate wiring 12 and the third gate wiring 13, the second lower metal layer 12x of the second gate wiring does not exist. Figure 6 As shown in FIG. 1( b ), the third upper metal layer 13 y of the third gate wiring does not exist at the third intersection J3 . Therefore, the second gate wiring 12 and the third gate wiring 13 are not short-circuited at the third intersection J3 .

[0157] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0158] The IGBT 100 of the first embodiment includes a first gate electrode 31 to which a first gate voltage (Vg1) is applied, a second gate electrode 32 to which a second gate voltage (Vg2) is applied, and a third gate electrode 33 to which a third gate voltage (Vg3) is applied. The IGBT 100 of the first embodiment includes a first transistor controlled by the first gate electrode 31, a second transistor controlled by the second gate electrode 32, and a third transistor controlled by the third gate electrode 33. For example, in Figure 2 The area surrounded by the dotted line T1 in FIG corresponds to the first transistor. Figure 2 The area surrounded by the dotted line T2 corresponds to the second transistor. Figure 2 The area enclosed by the dotted line T3 corresponds to the third transistor. By providing independent gate signals to the first, second, and third transistors, triple-gate drive of the IGBT 100 is possible. Triple-gate drive of the IGBT 100 can, for example, achieve both reduced on-resistance and reduced switching losses.

[0159] To perform triple-gate driving, three different gate voltages must be applied, and therefore three gate electrode pads are required. Furthermore, three gate wirings are required to connect the gate electrode pads to the gate electrodes.

[0160] Figure 8 This is a schematic diagram of a comparative semiconductor device. Figure 8 The first embodiment Figure 1 The corresponding figure of (a).

[0161] The semiconductor device of the comparative embodiment is a triple-gate driving IGBT 900. The comparative IGBT 900 differs from the IGBT 100 of the first embodiment in that the first gate wiring 11, the second gate wiring 12, and the third gate wiring 13 are formed of a single metal layer.

[0162] For example, Figure 8 In the example, from the end portion of the second gate wiring 12 ( Figure 8 Because the second gate wiring 12 surrounds the emitter electrode 21, the wiring length from the second gate electrode pad 102 to the gate electrode connected to the second gate wiring 12 at the end P1 becomes extremely long. Consequently, the resistance of the second gate wiring 12 up to the end P1 increases. Consequently, the wiring delay to the gate electrode connected to the second gate wiring 12 at the end P1 increases. Consequently, for example, increasing the speed of operation of the IGBT 900 becomes difficult.

[0163] Furthermore, in the comparative IGBT 900 , since the first gate wiring 11 , the second gate wiring 12 , and the third gate wiring 13 are formed of a single metal layer, the resistance per unit length of the gate wiring is also increased.

[0164] The first gate wiring 11, second gate wiring 12, and third gate wiring 13 of the IGBT 100 of the first embodiment are formed by a stacked structure of a first lower metal layer 11x and a first upper metal layer 11y, a second lower metal layer 12x and a second upper metal layer 12y, and a third lower metal layer 13x and a third upper metal layer 13y, respectively. This reduces the resistance per unit length of the gate wiring.

[0165] Furthermore, by forming the first gate wiring 11, the second gate wiring 12, and the third gate wiring 13 in a stacked structure, the gate wirings can intersect with each other. This shortens the length of the gate wiring from the electrode pad to the gate electrode, thereby reducing the resistance of the gate wiring.

[0166] According to the IGBT 100 of the first embodiment, by reducing the resistance of the gate wiring, for example, it is possible to increase the speed of operation of the IGBT 100 .

[0167] Furthermore, according to the IGBT 100 of the first embodiment, each gate wiring can be intersected, thereby increasing the degree of freedom in designing the layout pattern of the gate wiring. Therefore, for example, the chip size of the IGBT 100 can be reduced.

[0168] Furthermore, the first lower metal layer 11x, the second lower metal layer 12x, and the third lower metal layer 13x can be formed simultaneously with the fourth lower metal layer 21x of the emitter electrode 21. Furthermore, the first upper metal layer 11y, the second upper metal layer 12y, and the third upper metal layer 13y can be formed simultaneously with the fourth upper metal layer 21y of the emitter electrode 21. Consequently, an additional manufacturing step for forming a stacked structure of gate wiring is unnecessary, and an increase in the manufacturing cost of the IGBT 100 can be suppressed.

[0169] (First Modification)

[0170] The semiconductor device of the first modification of the first embodiment differs from the semiconductor device of the first embodiment in that the first upper metal layer of the second gate wiring surrounds the first electrode, and the third upper metal layer of the third gate wiring surrounds the first electrode.

[0171] The semiconductor device according to the first modified example of the first embodiment is an IGBT 110 .

[0172] Figure 9 (a) Figure 9 (b) is a schematic diagram of a semiconductor device according to a first modification of the first embodiment. Figure 9 (a) Figure 9 (b) is the same as that of the first embodiment. Figure 6 (a) Figure 6 (b) corresponds to the figure.

[0173] Figure 9 (a) shows a layout pattern of the first lower metal layer 11x of the first gate wiring, the second lower metal layer 12x of the second gate wiring, the third lower metal layer 13x of the third gate wiring, and the fourth lower metal layer 21x of the emitter electrode. Figure 9 (b) shows a layout pattern of the first upper metal layer 11y of the first gate wiring, the second upper metal layer 12y of the second gate wiring, the third upper metal layer 13y of the third gate wiring, and the fourth upper metal layer 21y of the emitter electrode.

[0174] in addition, Figure 9 (a) also shows a layout pattern of a first gate electrode pad 101, a second gate electrode pad 102 and a third gate electrode pad 103 formed of the same first material as the first lower metal layer 11x, the second lower metal layer 12x, the third lower metal layer 13x and the fourth lower metal layer 21x.

[0175] in addition, Figure 9(b) also shows the layout pattern of the first gate electrode pad 101, the second gate electrode pad 102 and the third gate electrode pad 103 formed by the same second material as the first upper metal layer 11y, the second upper metal layer 12y, the third upper metal layer 13y and the fourth upper metal layer 21y.

[0176] like Figure 9 As shown in (b), the first upper metal layer 11y surrounds the fourth upper metal layer 21y. The first upper metal layer 11y surrounds the emitter electrode 21. The first upper metal layer 11y has a ring shape in a plane parallel to the first plane F1.

[0177] like Figure 9 As shown in (b), the second upper metal layer 12y surrounds the fourth upper metal layer 21y. The second upper metal layer 12y surrounds the emitter electrode 21. The second upper metal layer 12y surrounds the first upper metal layer 11y. The second upper metal layer 12y is annular in a plane parallel to the first plane F1.

[0178] like Figure 9 As shown in (b), the third upper metal layer 13y surrounds the fourth upper metal layer 21y. The third upper metal layer 13y surrounds the emitter electrode 21. The third upper metal layer 13y surrounds the second upper metal layer 12y. The third upper metal layer 13y is annular in a plane parallel to the first plane F1.

[0179] like Figure 9 As shown in (a), at the first intersection J1 of the first gate wiring 11 and the second gate wiring 12, the second lower metal layer 12x of the second gate wiring does not exist. Figure 9 As shown in (b) of FIG. 5 , the first upper metal layer 11 y of the first gate wiring does not exist at the first intersection J1 .

[0180] Figure 10 This is a schematic cross-sectional view of a portion of a semiconductor device according to a first modification of the first embodiment. Figure 10 It is a cross section of the first intersection J1. Figure 10 It is a cross section parallel to the first direction and perpendicular to the second direction.

[0181] like Figure 10 As shown, at the first intersection J1, only the first lower metal layer 11x of the first gate wiring 11 continues in the second direction perpendicular to the paper. Also, at the first intersection J1, only the second upper metal layer 12y of the second gate wiring 12 continues in the first direction.

[0182] At the first intersection J1, the first gate wiring 11 and the second gate wiring 12 are separated by sandwiching the second interlayer insulating layer 37. Therefore, at the first intersection J1, the first gate wiring 11 and the second gate wiring 12 are not short-circuited.

[0183] like Figure 9 As shown in (a), at the second intersection J2 of the first gate wiring 11 and the third gate wiring 13, the third lower metal layer 13x of the third gate wiring does not exist. Figure 9 As shown in (b), the first upper metal layer 11y of the first gate wiring does not exist at the second intersection J2. Therefore, the first gate wiring 11 and the third gate wiring 13 are not short-circuited at the second intersection J2.

[0184] like Figure 9 As shown in (a), at the third intersection J3 between the second gate wiring 12 and the third gate wiring 13, the third lower metal layer 13x of the third gate wiring does not exist. Figure 9 As shown in FIG. 1( b ), the second upper metal layer 12 y of the second gate wiring does not exist at the third intersection J3 . Therefore, the second gate wiring 12 and the third gate wiring 13 are not short-circuited at the third intersection J3 .

[0185] According to the IGBT 110 of the first modification of the first embodiment, similarly to the IGBT 100 of the first embodiment, the resistance of the gate wiring can be reduced.

[0186] (Second Modification)

[0187] The semiconductor device of the second variant of the first embodiment differs from the semiconductor device of the first embodiment in that the first gate wiring includes a seventh portion arranged between the first portion and the second portion and extending along the second direction, the second gate wiring includes an eighth portion arranged between the third portion and the fourth portion and extending along the second direction, and the third gate wiring includes a ninth portion arranged between the fifth portion and the sixth portion and extending along the second direction.

[0188] The semiconductor device according to the second modified example of the first embodiment is an IGBT 120 .

[0189] Figure 11 (a) Figure 11 (b) is a schematic diagram of a semiconductor device according to a second modification of the first embodiment. Figure 11 (a) Figure 11 (b) is the same as that of the first embodiment. Figure 1 (a) Figure 1 (b) corresponds to the figure.

[0190] The first gate wiring 11 , the second gate wiring 12 , and the third gate wiring 13 include a seventh portion 11 c , an eighth portion 12 c , and a ninth portion 13 c , respectively.

[0191] The emitter electrode 21 includes a first region 21 a and a second region 21 b divided in the second direction.

[0192] The seventh portion 11c of the first gate wiring 11 is provided between the first portion 11a and the second portion 11b. The seventh portion 11c of the first gate wiring 11 extends in the second direction. The first region 21a of the emitter electrode 21 is provided between the first portion 11a and the seventh portion 11c. The second region 21b of the emitter electrode 21 is provided between the second portion 11b and the seventh portion 11c.

[0193] The eighth portion 12c of the second gate wiring 12 is provided between the third portion 12a and the fourth portion 12b. The eighth portion 12c of the second gate wiring 12 extends along the second direction. The first region 21a of the emitter electrode 21 is provided between the third portion 12a and the eighth portion 21c. The second region 21b of the emitter electrode 21 is provided between the fourth portion 12b and the eighth portion 12c.

[0194] Ninth portion 13c of third gate wiring 13 is provided between fifth portion 13a and sixth portion 13b. Ninth portion 13c of third gate wiring 13 extends along the second direction. First region 21a of emitter electrode 21 is provided between fifth portion 13a and ninth portion 13c. Second region 21b of emitter electrode 21 is provided between sixth portion 13b and ninth portion 13c.

[0195] The seventh portion 11 c of the first gate wiring 11 , the eighth portion 12 c of the second gate wiring 12 , and the ninth portion 13 c of the third gate wiring 13 are so-called gate fingers.

[0196] Figure 12 (a) Figure 12 (b) is a schematic diagram of a semiconductor device according to a second modification of the first embodiment. Figure 12 (a) Figure 12 (b) is the same as that of the first embodiment. Figure 6 (a) Figure 6 (b) corresponds to the figure.

[0197] Figure 12 (a) shows a layout pattern of the first lower metal layer 11x of the first gate wiring, the second lower metal layer 12x of the second gate wiring, the third lower metal layer 13x of the third gate wiring, and the fourth lower metal layer 21x of the emitter electrode. Figure 12(b) shows a layout pattern of the first upper metal layer 11y of the first gate wiring, the second upper metal layer 12y of the second gate wiring, the third upper metal layer 13y of the third gate wiring, and the fourth upper metal layer 21y of the emitter electrode.

[0198] In addition, Figure 12 (b) also shows the layout pattern of the first gate electrode pad 101, the second gate electrode pad 102 and the third gate electrode pad 103 formed by the same second material as the first upper metal layer 11y, the second upper metal layer 12y, the third upper metal layer 13y and the fourth upper metal layer 21y.

[0199] According to the IGBT 120 of the second modified example of the first embodiment, even when the gate wiring includes gate fingers, the resistance of the gate wiring can be reduced, similar to the IGBT 100 of the first embodiment.

[0200] (Third Modification)

[0201] The semiconductor device of the third modification of the first embodiment differs from the semiconductor device of the first embodiment in that the first gate wiring does not surround the first electrode, and the second gate wiring does not surround the first electrode.

[0202] The semiconductor device according to the third modified example of the first embodiment is an IGBT 130 .

[0203] Figure 13 (a) Figure 13 (b) is a schematic diagram of a semiconductor device according to a third modification of the first embodiment. Figure 13 (a) Figure 13 (b) is the same as that of the first embodiment. Figure 1 (a) Figure 1 (b) corresponds to the figure.

[0204] The first gate wiring 11 does not surround the emitter electrode 21 . The second gate wiring 12 does not surround the emitter electrode 21 . The third gate wiring 13 does not surround the emitter electrode 21 .

[0205] Figure 14 (a) Figure 14 (b) is a schematic diagram of a semiconductor device according to a third modification of the first embodiment. Figure 13 (a) Figure 13 (b) is the same as that of the first embodiment. Figure 6 (a) Figure 6 (b) corresponds to the figure.

[0206] Figure 14(a) shows a layout pattern of the first lower metal layer 11x of the first gate wiring, the second lower metal layer 12x of the second gate wiring, the third lower metal layer 13x of the third gate wiring, and the fourth lower metal layer 21x of the emitter electrode. Figure 14 (b) shows a layout pattern of the first upper metal layer 11y of the first gate wiring, the second upper metal layer 12y of the second gate wiring, the third upper metal layer 13y of the third gate wiring, and the fourth upper metal layer 21y of the emitter electrode.

[0207] in addition, Figure 14 (b) also shows the layout pattern of the first gate electrode pad 101, the second gate electrode pad 102 and the third gate electrode pad 103 formed by the same second material as the first upper metal layer 11y, the second upper metal layer 12y, the third upper metal layer 13y and the fourth upper metal layer 21y.

[0208] According to the IGBT 130 of the third modified example of the first embodiment, similarly to the IGBT 100 of the first embodiment, the resistance of the gate wiring can be reduced.

[0209] As described above, according to the first embodiment and the modified example, a semiconductor device capable of reducing the resistance of the gate wiring can be provided.

[0210] (Second embodiment)

[0211] A semiconductor device according to a second embodiment comprises: a semiconductor layer having a first surface and a second surface opposite to the first surface, comprising a plurality of first trenches provided on one side of the first surface and extending in a first direction parallel to the first surface, a plurality of second trenches provided on one side of the first surface and extending in the first direction, and a plurality of third trenches provided on one side of the first surface and extending in the first direction; a first electrode provided on one side of the first surface of the semiconductor layer; a second electrode provided on one side of the second surface of the semiconductor layer; a first gate electrode provided in the first trench; a second gate electrode provided in the second trench; and a third gate electrode provided in the third trench; a first gate wiring provided on one side of the first surface of the semiconductor layer, comprising a first upper metal layer and a first lower metal layer provided between the first upper metal layer and the first surface, and comprising a first portion extending in a second direction parallel to the first surface and perpendicular to the first direction, and a second portion extending in the second direction and having the first electrode provided between the first portion and the second portion. A first gate wiring is electrically connected to the first gate electrode. A second gate wiring is provided on one side of the first surface of the semiconductor layer and includes a third portion extending in the second direction and a fourth portion extending in the second direction with the first electrode provided therebetween. The second gate wiring is electrically connected to the second gate electrode. A third gate wiring is provided on one side of the first surface of the semiconductor layer and includes a third upper metal layer and a third lower metal layer provided between the third upper metal layer and the first surface, and includes a fifth portion extending in the second direction and a sixth portion extending in the second direction with the first electrode provided therebetween. The third gate wiring is electrically connected to the third gate electrode. A first gate electrode pad is provided on one side of the first surface of the semiconductor layer and electrically connected to the first gate wiring. A second gate electrode pad is provided on one side of the first surface of the semiconductor layer and electrically connected to the second gate wiring. A third gate electrode pad is provided on one side of the first surface of the semiconductor layer and electrically connected to the third gate wiring. The first portion is provided between the third portion and the first electrode, and the third portion is provided between the fifth portion and the first electrode. The first distance in the first direction between the first upper metal layer of the first portion and the third upper metal layer of the fifth portion is smaller than the first width of the third portion in the first direction. The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the first distance in the first direction between the upper metal layer of the first portion of the first gate wiring and the upper metal layer of the first portion of the third gate wiring is smaller than the first width of the first portion of the second gate wiring. Below, some of the details overlapping with the first embodiment may be omitted.

[0212] The semiconductor device of the second embodiment is a trench-gate IGBT 200 having a gate electrode in a trench formed in a semiconductor layer. The IGBT 200 has three independently controllable gates and is an IGBT capable of triple-gate driving.

[0213] The IGBT200 of the second embodiment includes a semiconductor layer 10, a first gate wiring 11, a second gate wiring 12, a third gate wiring 13, a first contact portion 16, a second contact portion 17, a third contact portion 18, an emitter electrode 21 (first electrode), a collector electrode 22 (second electrode), a gate insulating film 23, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a first interlayer insulating layer 36, a second interlayer insulating layer 37, a first gate electrode pad 101, a second gate electrode pad 102 and a third gate electrode pad 103.

[0214] The first gate wiring 11 includes a first portion 11a and a second portion 11b. The first gate wiring 11 includes a first lower metal layer 11x and a first upper metal layer 11y.

[0215] The second gate wiring 12 includes a third portion 12 a and a fourth portion 12 b .

[0216] The third gate wiring 13 includes a fifth portion 13a and a sixth portion 13b. The third gate wiring 13 includes a third lower metal layer 13x and a third upper metal layer 13y.

[0217] The emitter electrode 21 includes a fourth lower metal layer 21 x and a fourth upper metal layer 21 y .

[0218] A first gate trench 41 (first trench), a second gate trench 42 (second trench), a third gate trench 43 (third trench), a collector region 51 , a drift region 52 , a base region 53 , an emitter region 54 , and a contact region 55 are provided in the semiconductor layer 10 .

[0219] Figure 15 (a) Figure 15 (b) is a schematic diagram of a semiconductor device according to a second embodiment. Figure 15 (a) shows a layout pattern of the first gate wiring 11 , the second gate wiring 12 , the third gate wiring 13 , the first gate electrode pad 101 , the second gate electrode pad 102 , the third gate electrode pad 103 , and the emitter electrode 21 . Figure 15 (b) shows the layout pattern of the first gate trench 41 , the second gate trench 42 , and the third gate trench 43 .

[0220] like Figure 15As shown in (a), first gate wiring 11 is connected to first gate electrode pad 101. First gate wiring 11 is electrically and physically connected to first gate electrode pad 101. First portion 11a of the first gate wiring extends along the second direction. Second portion 11b of the first gate wiring extends along the second direction. Emitter electrode 21 is provided between first portion 11a and second portion 11b. First gate wiring 11 surrounds emitter electrode 21.

[0221] like Figure 15 As shown in (a), second gate wiring 12 is connected to second gate electrode pad 102. Second gate wiring 12 is electrically and physically connected to second gate electrode pad 102. Third portion 12a of the second gate wiring extends along the second direction. Fourth portion 12b of the second gate wiring extends along the second direction. Emitter electrode 21 is provided between third portion 12a and fourth portion 12b. Second gate wiring 12 surrounds emitter electrode 21.

[0222] The first portion 11 a of the first gate wiring is provided between the third portion 12 a of the second gate wiring and the emitter electrode 21 . The second portion 11 b of the first gate wiring is provided between the fourth portion 12 b of the second gate wiring and the emitter electrode 21 .

[0223] like Figure 15 As shown in (a), third gate wiring 13 is connected to third gate electrode pad 103. Third gate wiring 13 is electrically and physically connected to third gate electrode pad 103. Fifth portion 13a of the third gate wiring extends along the second direction. Sixth portion 13b of the third gate wiring extends along the second direction. Emitter electrode 21 is provided between fifth portion 13a and sixth portion 13b.

[0224] The third portion 12a of the third gate wiring is provided between the fifth portion 13a of the third gate wiring and the emitter electrode 21. The fourth portion 12b of the second gate wiring is provided between the sixth portion 13b of the third gate wiring and the emitter electrode 21.

[0225] The first gate wiring 11 and the second gate wiring 12 partially overlap each other. The second gate wiring 12 and the third gate wiring 13 partially overlap each other.

[0226] like Figure 15 As shown in (b), the first gate trench 41, the second gate trench 42 and the third gate trench 43 extend along the first direction.

[0227] Figure 16 (a) Figure 16 (b) is a schematic diagram of a portion of the semiconductor device according to the second embodiment. Figure 16 (a) is Figure 15 An enlarged view of the first region R1 shown in (a). Figure 16 (b) is Figure 15 An enlarged view of the second region R2 shown in (a).

[0228] Figure 16 (a) Figure 16 (b) shows a layout pattern of the first gate wiring 11 , the second gate wiring 12 , the third gate wiring 13 , the first contact 16 , the second contact 17 , the third contact 18 , and the emitter electrode 21 .

[0229] like Figure 16 As shown in FIG. 1 , a first contact 16 is provided at a portion where the first portion 11a of the first gate wiring intersects the first gate trench 41. At the first contact 16, the first portion 11a is electrically and physically connected to the first gate electrode 31 provided in the first gate trench 41.

[0230] like Figure 16 As shown in FIG. 1 , a second contact portion 17 is provided at a portion where the third portion 12a of the second gate wiring intersects the second gate trench 42. At the second contact portion 17, the third portion 12a is electrically and physically connected to the second gate electrode 32 provided in the second gate trench 42.

[0231] like Figure 16 As shown in FIG. 1 , a third contact 18 is provided at a portion where the fifth portion 13a of the third gate wiring intersects the third gate trench 43. At the third contact 18, the fifth portion 13a is electrically and physically connected to the third gate electrode 33 provided in the third gate trench 43.

[0232] like Figure 16 As shown in FIG. 1 , a first contact portion 16 is provided at a portion where the second portion 11b of the first gate wiring intersects the first gate trench 41. At the first contact portion 16, the second portion 11b is electrically and physically connected to the first gate electrode 31 provided in the first gate trench 41.

[0233] like Figure 16 As shown in FIG. 1 , a second contact portion 17 is provided at a portion where the fourth portion 12b of the second gate wiring intersects the second gate trench 42. At the second contact portion 17, the fourth portion 12b is electrically and physically connected to the second gate electrode 32 provided in the second gate trench 42.

[0234] like Figure 16As shown in FIG. 1 , a third contact 18 is provided at a portion where the sixth portion 13b of the third gate wiring intersects the third gate trench 43. At the third contact 18, the sixth portion 13b is electrically and physically connected to the third gate electrode 33 provided in the third gate trench 43.

[0235] Figure 17 It is a schematic cross-sectional view of a portion of the semiconductor device according to the second embodiment. Figure 17 yes Figure 16 (a) C-C' section.

[0236] The first gate wiring 11 is made of metal and includes a first lower metal layer 11x and a first upper metal layer 11y. The first lower metal layer 11x is provided between the first upper metal layer 11y and the first surface F1.

[0237] The second gate wiring 12 is made of metal.

[0238] The third gate wiring 13 is made of metal and includes a third lower metal layer 13x and a third upper metal layer 13y. The third lower metal layer 13x is provided between the third upper metal layer 13y and the first plane F1.

[0239] The first lower metal layer 11x, the second gate wiring 12, and the third lower metal layer 13x are formed of a first material. The first material is a metal. The first material of the first lower metal layer 11x, the second gate wiring 12, and the third lower metal layer 13x is the same as the first material of the fourth lower metal layer 21x of the emitter electrode 21.

[0240] The first upper metal layer 11 y and the second upper metal layer 12 y are formed of a second material. The second material is metal. The second material of the first upper metal layer 11 y and the third upper metal layer 13 y is the same as the second material of the fourth upper metal layer 21 y of the emitter electrode 21 .

[0241] The first material and the second material are different metals. The first material includes, for example, tungsten (W), molybdenum (Mo), or tantalum (Ta). The second material includes, for example, aluminum (Al) or copper (Cu).

[0242] The first lower metal layer 11 x , the second gate wiring 12 , and the third lower metal layer 13 x are, for example, stacked films of titanium, titanium nitride, and tungsten.

[0243] The first upper metal layer 11 y and the third upper metal layer 13 y are, for example, stacked films of titanium, titanium nitride, and aluminum.

[0244] The first lower metal layer 11 x and the third lower metal layer 13 x are electrically and physically connected to the first upper metal layer 11 y and the third upper metal layer 13 y , respectively.

[0245] The first gate wiring 11 and the third gate wiring 13 each have a stacked structure of two different metal layers.

[0246] like Figure 17 As shown, the second interlayer insulating layer 37 is provided, for example, between a portion of the first lower metal layer 11x and a portion of the first upper metal layer 11y. The second interlayer insulating layer 37 is provided, for example, between a portion of the second gate wiring 12 and a portion of the first upper metal layer 11y. The second interlayer insulating layer 37 is provided, for example, between a portion of the second gate wiring 12 and a portion of the third upper metal layer 13y. The second interlayer insulating layer 37 is provided, for example, between a portion of the third lower metal layer 13x and a portion of the third upper metal layer 13y.

[0247] like Figure 17 As shown, the first lower metal layer 11 x of the first gate wiring is connected to the first gate electrode 31 at the first contact portion 16 .

[0248] like Figure 17 As shown, a first distance ( ) in a first direction between the first upper metal layer 11y of the first portion 11a of the first gate wiring and the third upper metal layer 13y of the fifth portion 13a of the third gate wiring. Figure 17 d1) is greater than the first width ( Figure 17 w1) in is small.

[0249] like Figure 17 As shown, the first upper metal layer 11y of the first portion 11a of the first gate wiring overlaps with the third portion 12a of the second gate wiring in the third direction. In addition, the third upper metal layer 13y of the fifth portion 13a of the third gate wiring overlaps with the third portion 12a of the second gate wiring in the third direction.

[0250] like Figure 17 As shown, the first width w1 of the third portion 12a of the second gate wiring in the first direction is greater than the second width ( 11 x ) of the first lower metal layer 11x of the first portion 11a of the first gate wiring in the first direction. Figure 17 In addition, the first width w1 is wider than the third width ( Figure 17 w3) width in .

[0251] like Figure 17 As shown, the fourth width ( Figure 17The width w4 in the first direction is wider than the second width w2 of the first lower metal layer 11x of the first portion 11a. In addition, the fifth width ( Figure 17 The width w5) of the fifth portion 13a is wider than the third width w3 of the third lower metal layer 13x in the first direction.

[0252] Figure 18 (a) Figure 18 (b) is a schematic diagram of a semiconductor device according to a second embodiment. Figure 18 (a) Figure 18 (b) is the same as that of the first embodiment. Figure 6 (a) Figure 6 (b) corresponds to the figure.

[0253] Figure 18 (a) shows a layout pattern of the first lower metal layer 11 x , the second gate wiring 12 , the third lower metal layer 13 x , and the fourth lower metal layer 21 x . Figure 18 (b) shows the layout pattern of the first upper metal layer 11y, the third upper metal layer 13y and the fourth upper metal layer 21y.

[0254] In addition, Figure 18 (a) also shows a layout pattern of a second gate electrode pad 102 formed of the same first material as the first lower metal layer 11 x , the second gate wiring 12 , the third lower metal layer 13 x , and the fourth lower metal layer 21 x .

[0255] In addition, Figure 18 (b) also shows the layout pattern of the first gate electrode pad 101, the second gate electrode pad 102 and the third gate electrode pad 103 formed of the same second material as the first upper metal layer 11y, the third upper metal layer 13y and the fourth upper metal layer 21y.

[0256] like Figure 18 As shown in (a) of FIG. 2 , the second gate wiring 12 surrounds the fourth lower metal layer 21x of the emitter electrode. The second gate wiring 12 surrounds the emitter electrode 21. The second gate wiring 12 has a ring shape in a plane parallel to the first plane F1.

[0257] like Figure 18 As shown in (b), the first upper metal layer 11y surrounds the fourth upper metal layer 21y. The first upper metal layer 11y surrounds the emitter electrode 21. The first upper metal layer 11y has a ring shape in a plane parallel to the first plane F1.

[0258] Next, the operation and effects of the semiconductor device according to the second embodiment will be described.

[0259] The IGBT 200 of the second embodiment can achieve both reduction in on-resistance and reduction in switching loss by triple-gate driving, for example.

[0260] In the IGBT 200 of the second embodiment, at least a portion of the first gate wiring 11 is formed from a stacked structure of a first lower metal layer 11x and a first upper metal layer 11y. Furthermore, at least a portion of the third gate wiring 13 is formed from a stacked structure of a third lower metal layer 13x and a third upper metal layer 13y. This reduces the resistance per unit length of the gate wiring.

[0261] According to the IGBT 200 of the second embodiment, by reducing the resistance of the gate wiring, for example, it is possible to increase the speed of operation of the IGBT 200 .

[0262] In addition, in the IGBT200 of the second embodiment, as Figure 17 As shown, a first distance ( ) in a first direction between the first upper metal layer 11y of the first portion 11a of the first gate wiring and the third upper metal layer 13y of the fifth portion 13a of the third gate wiring. Figure 17 d1) is greater than the first width ( Figure 17 w1) is small. Therefore, the first upper metal layer 11y of the first portion 11a of the first gate wiring overlaps with the third portion 12a of the second gate wiring in the third direction. Furthermore, the third upper metal layer 13y of the fifth portion 13a of the third gate wiring overlaps with the third portion 12a of the second gate wiring in the third direction.

[0263] By arranging three gate wirings extending in the second direction in an overlapping manner, the width of the region where the gate wirings are provided in the first direction can be reduced. Therefore, for example, the chip size of the IGBT 200 can be reduced.

[0264] (First Modification)

[0265] The semiconductor device according to the first modification of the second embodiment differs from the semiconductor device according to the second embodiment in that the second gate wiring includes a lower metal layer and an upper metal layer.

[0266] Figure 19 It is a schematic cross-sectional view of a portion of a semiconductor device according to a first modification of the second embodiment. Figure 19 The second embodiment Figure 17 The corresponding figure.

[0267] The second gate wiring 12 includes a second lower metal layer 12x and a second upper metal layer 12y. The second lower metal layer 12x is provided between the second upper metal layer 12y and the first surface F1.

[0268] The first lower metal layer 11x, the second lower metal layer 12x, and the third lower metal layer 13x are formed of a first material. The first material is a metal. The first material of the first lower metal layer 11x, the second lower metal layer 12x, and the third lower metal layer 13x is the same as the first material of the fourth lower metal layer 21x of the emitter electrode 21.

[0269] The first upper metal layer 11y, the second upper metal layer 12y, and the third upper metal layer 13y are formed of a second material. The second material is a metal. The second material of the first upper metal layer 11y, the second upper metal layer 12y, and the third upper metal layer 13y is the same as the second material of the fourth upper metal layer 21y of the emitter electrode 21.

[0270] The first material and the second material are different metals. The first material includes, for example, tungsten (W), molybdenum (Mo), or tantalum (Ta). The second material includes, for example, aluminum (Al) or copper (Cu).

[0271] The first lower metal layer 11 x , the second lower metal layer 12 x , and the third lower metal layer 13 x are, for example, stacked films of titanium, titanium nitride, and tungsten.

[0272] The first upper metal layer 11 y , the second upper metal layer 12 y , and the third upper metal layer 13 y are, for example, stacked films of titanium, titanium nitride, and aluminum.

[0273] The first lower metal layer 11 x , the second lower metal layer 12 x , and the third lower metal layer 13 x are electrically and physically connected to the first upper metal layer 11 y , the second upper metal layer 12 y , and the third upper metal layer 13 y , respectively.

[0274] The first gate wiring 11 , the second gate wiring 12 , and the third gate wiring 13 each have a stacked structure of two different metal layers.

[0275] like Figure 19 As shown, a first distance ( ) in a first direction between the first upper metal layer 11y of the first portion 11a of the first gate wiring and the third upper metal layer 13y of the fifth portion 13a of the third gate wiring. Figure 19 d1) is greater than the first width ( d1 in the first direction) of the second lower metal layer 12x of the third portion 12a of the second gate wiring Figure 19 w1) in is small.

[0276] like Figure 19As shown, the first upper metal layer 11y of the first portion 11a of the first gate wiring overlaps with the second lower metal layer 12x of the third portion 12a of the second gate wiring in the third direction. In addition, the third upper metal layer 13y of the fifth portion 13a of the third gate wiring overlaps with the second lower metal layer 12x of the third portion 12a of the second gate wiring in the third direction.

[0277] like Figure 19 As shown, the first width w1 of the second lower metal layer 12x of the third portion 12a of the second gate wiring in the first direction is greater than the second width ( Figure 19 In addition, the first width w1 is wider than the third width ( Figure 19 w3) width in .

[0278] like Figure 19 As shown, the fourth width ( Figure 19 The width w4 in the first direction is wider than the second width w2 of the first lower metal layer 11x of the first portion 11a. In addition, the fifth width ( Figure 19 The width w5) of the fifth portion 13a is wider than the third width w3 of the third lower metal layer 13x in the first direction.

[0279] According to the IGBT of the second modified example of the second embodiment, the resistance of the gate wiring can be reduced, similarly to the IGBT 200 of the second embodiment. In particular, the resistance of the second gate wiring can be reduced by forming a stacked structure.

[0280] As described above, according to the second embodiment and the modified example, a semiconductor device capable of reducing the resistance of the gate wiring can be provided.

[0281] In the first embodiment or the second embodiment, an IGBT having three independently controllable gates is used as an example for description. However, the IGBT may also have a structure having two independently controllable gates. In this case, the number of gate wirings becomes two. In this case, for example, in the semiconductor device of the first embodiment, the third gate wiring is removed. Alternatively, the IGBT may have a structure having four or more independently controllable gates. In this case, the number of gate wirings becomes four or more. In this case, for example, in the semiconductor device of the first embodiment, a fourth gate wiring is provided outside the third gate wiring.

[0282] In the first embodiment or the second embodiment, the arrangement order of the grooves and the ratio of the number of the grooves are arbitrary and are not necessarily limited to the arrangement order and the ratio of the number of the grooves in the first embodiment or the second embodiment.

[0283] Furthermore, in the semiconductor device, a trench may be provided in which the conductive layer in the trench is not electrically connected to the gate wiring. For example, a trench may be provided in which the conductive layer in the trench is electrically connected to the emitter electrode.

[0284] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways and can be omitted, replaced, or modified in various ways without departing from the main purpose of the invention. For example, the constituent elements of one embodiment can be replaced with constituent elements of other embodiments or modified. These embodiments and their variations are included in the scope and main purpose of the invention and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor layer having a first surface and a second surface opposite to the first surface, comprising a plurality of first trenches provided on one side of the first surface and extending along a first direction parallel to the first surface, and a plurality of second trenches provided on one side of the first surface and extending along the first direction; a first electrode disposed on one side of the first surface of the semiconductor layer; a second electrode disposed on one side of the second surface of the semiconductor layer; a first gate electrode disposed in the first trench; a second gate electrode disposed in the second trench; a first gate wiring, provided on one side of the first surface of the semiconductor layer, comprising a first upper metal layer and a first lower metal layer provided between the first upper metal layer and the first surface, and comprising a first portion extending in a second direction parallel to the first surface and perpendicular to the first direction, and a second portion extending in the second direction and having the first electrode provided therebetween, the first gate wiring being electrically connected to the first gate electrode; a second gate wiring, provided on one side of the first surface of the semiconductor layer, comprising a second upper metal layer and a second lower metal layer provided between the second upper metal layer and the first surface, and comprising a third portion extending along the second direction and a fourth portion extending along the second direction and having the first electrode provided therebetween, the second gate wiring being electrically connected to the second gate electrode; a first gate electrode pad provided on one side of the first surface of the semiconductor layer and electrically connected to the first gate wiring; and a second gate electrode pad provided on one side of the first surface of the semiconductor layer and electrically connected to the second gate wiring; The first portion is provided between the third portion and the first electrode, The second portion is provided between the fourth portion and the first electrode, The first gate wiring and the second gate wiring intersect at a first intersection. The first lower metal layer and the second upper metal layer do not exist at the first intersection, or the first upper metal layer and the second lower metal layer do not exist.

2. The semiconductor device according to claim 1, wherein At a portion where the first portion intersects the first trench, the first portion is connected to the first gate electrode. At a portion where the second portion intersects the first trench, the second portion is connected to the first gate electrode. At a portion where the third portion intersects the second trench, the third portion is connected to the second gate electrode. The fourth portion is connected to the second gate electrode at a portion where the fourth portion intersects the second trench.

3. The semiconductor device according to claim 1, wherein The first gate wiring surrounds the first electrode, The second gate wiring surrounds the first electrode.

4. The semiconductor device according to claim 1, wherein The first lower metal layer surrounds the first electrode, The second lower metal layer surrounds the first electrode.

5. The semiconductor device according to claim 1, wherein The semiconductor layer further includes a plurality of third trenches disposed on one side of the first surface and extending along the first direction. The semiconductor device further comprises: a third gate electrode disposed in the third trench; a third gate wiring, provided on one side of the first surface of the semiconductor layer, comprising a third upper metal layer and a third lower metal layer provided between the third upper metal layer and the first surface, and comprising a fifth portion extending along the second direction and a sixth portion extending along the second direction and having the first electrode provided therebetween, the third gate wiring being electrically connected to the third gate electrode; as well as a third gate electrode pad provided on one side of the first surface of the semiconductor layer and electrically connected to the third gate wiring; The first gate wiring and the third gate wiring intersect at a second intersection. The first lower metal layer and the third upper metal layer do not exist at the second intersection, or the first upper metal layer and the third lower metal layer do not exist.

6. The semiconductor device according to claim 5, wherein At a portion where the fifth portion intersects the third trench, the fifth portion is connected to the third gate electrode. The sixth portion is connected to the third gate electrode at a portion where the sixth portion intersects the third trench.

7. The semiconductor device according to claim 5, wherein The second gate wiring intersects the third gate wiring at a third intersection. The second lower metal layer and the third upper metal layer do not exist at the third intersection, or the second upper metal layer and the third lower metal layer do not exist.

8. The semiconductor device according to claim 1, wherein The first lower metal layer and the second lower metal layer include tungsten, The first upper metal layer and the second upper metal layer include aluminum.

9. The semiconductor device according to claim 1, wherein At the first intersection, an insulating layer is provided between the first gate wiring and the second gate wiring.

10. The semiconductor device according to claim 1, wherein The first electrode includes a fourth upper metal layer and a fourth lower metal layer disposed between the fourth upper metal layer and the first surface. The fourth lower metal layer is made of the same material as the first lower metal layer and the second lower metal layer. The fourth upper metal layer is made of the same material as the first upper metal layer and the second upper metal layer.

11. A semiconductor device, characterized in that: have: a semiconductor layer having a first surface and a second surface opposite to the first surface, comprising a plurality of first trenches provided on one side of the first surface and extending along a first direction parallel to the first surface, a plurality of second trenches provided on one side of the first surface and extending along the first direction, and a plurality of third trenches provided on one side of the first surface and extending along the first direction; a first electrode disposed on one side of the first surface of the semiconductor layer; a second electrode disposed on one side of the second surface of the semiconductor layer; a first gate electrode disposed in the first trench; a second gate electrode disposed in the second trench; a third gate electrode disposed in the third trench; a first gate wiring, provided on one side of the first surface of the semiconductor layer, comprising a first upper metal layer and a first lower metal layer provided between the first upper metal layer and the first surface, and comprising a first portion extending in a second direction parallel to the first surface and perpendicular to the first direction, and a second portion extending in the second direction and having the first electrode provided therebetween, the first gate wiring being electrically connected to the first gate electrode; a second gate wiring provided on one side of the first surface of the semiconductor layer, comprising a third portion extending along the second direction and a fourth portion extending along the second direction and having the first electrode provided therebetween, the second gate wiring being electrically connected to the second gate electrode; a third gate wiring, provided on one side of the first surface of the semiconductor layer, comprising a third upper metal layer and a third lower metal layer provided between the third upper metal layer and the first surface, and comprising a fifth portion extending along the second direction and a sixth portion extending along the second direction and having the first electrode provided therebetween, the third gate wiring being electrically connected to the third gate electrode; a first gate electrode pad provided on one side of the first surface of the semiconductor layer and electrically connected to the first gate wiring; a second gate electrode pad provided on one side of the first surface of the semiconductor layer and electrically connected to the second gate wiring; as well as a third gate electrode pad provided on one side of the first surface of the semiconductor layer and electrically connected to the third gate wiring; The first portion is provided between the third portion and the first electrode, The third portion is provided between the fifth portion and the first electrode, A first distance in the first direction between the first upper metal layer of the first portion and the third upper metal layer of the fifth portion is smaller than a first width of the third portion in the first direction.

12. The semiconductor device according to claim 11, wherein The second gate wiring surrounds the first electrode.

13. The semiconductor device according to claim 11, wherein The first width is wider than the second width of the first portion of the first lower metal layer in the first direction, The first width is wider than a third width of the third lower metal layer of the fifth portion in the first direction.

14. The semiconductor device according to claim 11, wherein A fourth width of the first upper metal layer of the first portion in the first direction is wider than a second width of the first lower metal layer of the first portion in the first direction. A fifth width of the third upper metal layer of the fifth portion in the first direction is wider than a third width of the third lower metal layer of the fifth portion in the first direction.

15. The semiconductor device according to claim 11, wherein The first lower metal layer and the third lower metal layer include tungsten, The first upper metal layer and the third upper metal layer include aluminum, The second gate wiring includes tungsten.

16. The semiconductor device according to claim 11, wherein The second gate wiring further includes a second upper metal layer and a second lower metal layer provided between the second upper metal layer and the first surface.

17. The semiconductor device according to claim 11, wherein The first electrode includes a fourth upper metal layer and a fourth lower metal layer disposed between the fourth upper metal layer and the first surface. The fourth lower metal layer is made of the same material as the first lower metal layer and the third lower metal layer. The fourth upper metal layer is made of the same material as the first upper metal layer and the third upper metal layer.

Images