Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a semiconductor substrate, a drift layer of a first conductivity type, a base layer of a second conductivity type, a first emitter layer of the first conductivity type, a second emitter layer of the second conductivity type, a plurality of trench gates and a collector layer of the second conductivity type, wherein the trench gate includes a gate trench, a gate insulating film, a first gate electrode, a second gate electrode, and an isolation layer provided inside the gate trench with the gate insulating film interposed therebetween and located between the first gate electrode and the second gate electrode; in the second direction, the width of the gate trench is larger than the width of the base layer between the adjacent gate trenches, the width of the base layer between the adjacent gate trenches is larger than the width of the first gate electrode, and the width of the base layer between the adjacent gate trenches is larger than the width of the second gate electrode. According to the semiconductor device and the preparation method thereof, the conduction loss can be effectively reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Power semiconductor devices play a key role in power electronics conversion. As modern power systems continue to demand ever-increasing power density, efficiency, and reliability, IGBT (Insulated Gate Bipolar Transistor) technology is evolving toward high voltage, high frequency, high integration, and the integration of wide-bandgap materials. However, due to limitations in the physical properties of silicon materials, manufacturing process complexity, and cost factors, structural optimization and packaging innovation are still needed to overcome performance bottlenecks in the short term.

[0003] The high energy consumption of traditional IGBT devices has always restricted their application in high-voltage and high-power fields. High energy consumption leads to higher operating temperatures of the devices, which in turn causes degradation of the devices' high-temperature performance and lifespan, reducing the devices' application areas and reliability.

[0004] Therefore, improvements are needed to at least partially solve the above problems. Summary of the Invention

[0005] The present invention aims to at least partially address the above-mentioned problems. To this end, one object of the present invention is to provide a semiconductor device having low on-resistance and significantly reduced energy consumption. Another object of the present invention is to provide a method for manufacturing the semiconductor device.

[0006] The semiconductor device includes:

[0007] a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, wherein the first main surface and the second main surface are spaced apart in a first direction;

[0008] A drift layer of the first conductivity type is provided between the first main surface and the second main surface;

[0009] a base layer of the second conductivity type, disposed on a side of the drift layer facing the first main surface;

[0010] A first emitter layer of a first conductivity type is provided on a side of the base layer facing the first main surface, wherein the side of the first emitter layer facing the first main surface constitutes at least a portion of the first main surface;

[0011] a second emitter layer of a second conductivity type, disposed on a side of the base layer facing the first main surface, wherein the side of the second emitter layer facing the first main surface constitutes at least a portion of the first main surface;

[0012] a plurality of trench gates, the trench gates penetrating the first emitter layer and the base layer from the first main surface to reach the drift layer, the plurality of trench gates being spaced apart in a second direction, the second direction being perpendicular to the first direction;

[0013] a collector layer of the second conductivity type, disposed on a side of the drift layer facing the second main surface, wherein the side of the collector layer facing the second main surface constitutes at least a portion of the second main surface;

[0014] Wherein, the trench gate comprises:

[0015] a gate trench, penetrating the first emitter layer and the base layer from the first main surface to reach the drift layer;

[0016] a gate insulating film, disposed on an inner wall surface of the gate trench;

[0017] a first gate electrode disposed inside the gate trench via the gate insulating film;

[0018] a second gate electrode disposed inside the gate trench via the gate insulating film, and the first gate electrode and the second gate electrode are spaced apart from each other in the second direction;

[0019] an isolation layer, disposed inside the gate trench via the gate insulating film and located between the first gate electrode and the second gate electrode;

[0020] In the second direction, the width of the gate trench is greater than the width of the base layer between adjacent gate trenches, the width of the base layer between adjacent gate trenches is greater than the width of the first gate electrode, and the width of the base layer between adjacent gate trenches is greater than the width of the second gate electrode.

[0021] The above technical solution has the following advantages and beneficial effects: the semiconductor device has a split gate and a narrow mesa, which can reduce the extraction path of the second emitter holes and reduce the extraction of the drift region holes by the second emitter, thereby increasing the charge concentration in the drift region, reducing the drift region resistance, reducing the conduction voltage drop of the semiconductor device, and reducing the conduction loss of the semiconductor device. Furthermore, it can reduce the energy consumption of the semiconductor device, reduce the operating temperature of the semiconductor device, improve its high-temperature performance and service life, and enable the semiconductor device to be used in high-voltage and high-power fields.

[0022] In some embodiments, in the second direction, the width of the gate trench is 0.5μm-5μm, the width of the base layer between adjacent gate trenches is 0.5μm-2μm, the width of the first gate electrode is 10nm-250nm, and the width of the second gate electrode is 10nm-250nm.

[0023] The above technical solution has the following advantages and beneficial effects: it can significantly reduce the extraction of holes in the drift region by the second emitter, thereby increasing the charge concentration in the drift region, reducing the resistance of the drift region, reducing the conduction voltage drop of the semiconductor device, and reducing the conduction loss of the semiconductor device.

[0024] In some embodiments, the semiconductor device further includes a cathode layer of the first conductivity type, the cathode layer being disposed on a side of the drift layer facing the second main surface, and the side of the cathode layer facing the second main surface constituting at least a portion of the second main surface.

[0025] The above technical solution has the following advantages and beneficial effects: it can be effectively compatible with the design of power devices such as RC-IGBT and has wide applicability.

[0026] The method for preparing the semiconductor device comprises the following steps:

[0027] Providing a substrate of a first conductivity type, forming a plurality of trench gates spaced apart in a second direction on an upper portion of the substrate, wherein the trench gates include a gate trench, a gate insulating film, a first gate electrode, a second gate electrode, and an isolation layer, wherein the gate insulating film is disposed on an inner wall surface of the gate trench, the first gate electrode, the second gate electrode, and the isolation layer are disposed within the gate trench via the gate insulating film, the first gate electrode and the second gate electrode are spaced apart in the second direction, and the isolation layer is located between the first gate electrode and the second gate electrode;

[0028] forming a base layer of the second conductivity type, a first emitter layer of the first conductivity type, and a second emitter layer of the second conductivity type on an upper portion of the substrate by an ion implantation process, wherein in a first direction perpendicular to the second direction, the first emitter layer and the second emitter layer are both located above the base layer;

[0029] forming a collector layer of the second conductivity type at the lower portion of the substrate by an ion implantation process;

[0030] In which, in the second direction, the width of the gate trench is greater than the width of the base layer between adjacent gate trenches, the width of the base layer between adjacent gate trenches is greater than the width of the first gate electrode, and the width of the base layer between adjacent gate trenches is greater than the width of the second gate electrode.

[0031] The above technical solution has the following advantages and beneficial effects: the formed semiconductor device has a split gate and a narrow mesa, which can reduce the extraction path of the second emitter holes and reduce the extraction of the drift region holes by the second emitter, thereby increasing the charge concentration in the drift region, reducing the drift region resistance, reducing the conduction voltage drop of the semiconductor device, and reducing the conduction loss of the semiconductor device. Furthermore, it can reduce the energy consumption of the semiconductor device, reduce the operating temperature of the semiconductor device, improve its high-temperature performance and service life, and enable the semiconductor device to be used in high-voltage and high-power fields.

[0032] In some embodiments, in the second direction, the width of the gate trench is 0.5μm-5μm, the width of the base layer between adjacent gate trenches is 0.5μm-2μm, the width of the first gate electrode is 10nm-250nm, and the width of the second gate electrode is 10nm-250nm.

[0033] The above technical solution has the following advantages and beneficial effects: it can significantly reduce the extraction of holes in the drift region by the second emitter, thereby increasing the charge concentration in the drift region, reducing the resistance of the drift region, reducing the conduction voltage drop of the semiconductor device, and reducing the conduction loss of the semiconductor device.

[0034] In some embodiments, the preparation method further comprises:

[0035] A cathode layer of the first conductive type is formed at the lower portion of the substrate by an ion implantation process.

[0036] The above technical solution has the following advantages and beneficial effects: it can be effectively compatible with the design of power devices such as RC-IGBT and has wide applicability.

[0037] In some embodiments, forming a plurality of trench gates spaced apart in the second direction on the upper portion of the substrate includes:

[0038] forming a patterned first mask layer on the substrate, wherein the first mask layer exposes a portion of the substrate;

[0039] Using the first mask layer as a mask, etching the exposed substrate by a dry etching process to form a plurality of initial trenches spaced apart in the second direction;

[0040] Undercutting the initial trench by a wet etching process to form a gate trench;

[0041] removing the first mask layer, and forming a gate insulating film and an initial electrode in the gate trench, wherein the initial electrode is disposed inside the gate trench via the gate insulating film;

[0042] forming a patterned second mask layer over the substrate, the gate insulating film, and the initial electrode, wherein the second mask layer exposes a portion of the initial electrode;

[0043] Etching the exposed initial electrodes by a dry etching process until the gate insulating film is exposed, wherein the initial electrodes remaining after etching include the first gate electrodes and the second gate electrodes spaced apart in the second direction;

[0044] forming an isolation layer between the first gate electrode and the second gate electrode;

[0045] The first mask layer and the second mask layer are formed by using the same mask.

[0046] The above technical solution has the following advantages and beneficial effects: a mask layer can be formed multiple times using one mask plate and etched to form a split gate, which can effectively reduce process difficulty and process cost.

[0047] The method for preparing the semiconductor device comprises the following steps:

[0048] Providing a substrate of a first conductivity type, and forming a base layer of a second conductivity type, a first emitter layer of the first conductivity type, and a second emitter layer of the second conductivity type on an upper portion of the substrate by an ion implantation process, wherein in a first direction, the first emitter layer and the second emitter layer are both located above the base layer;

[0049] forming a plurality of trench gates spaced apart in a second direction on an upper portion of the substrate, wherein the second direction is perpendicular to the first direction, the trench gates comprising a gate trench, a gate insulating film, a first gate electrode, a second gate electrode, and an isolation layer, the gate trench penetrating the first emitter layer and the base layer, the gate insulating film being disposed on an inner wall surface of the gate trench, the first gate electrode, the second gate electrode, and the isolation layer being disposed within the gate trench via the gate insulating film, the first gate electrode and the second gate electrode being spaced apart in the second direction, and the isolation layer being located between the first gate electrode and the second gate electrode;

[0050] forming a collector layer of the second conductivity type at the lower portion of the substrate by an ion implantation process;

[0051] In which, in the second direction, the width of the gate trench is greater than the width of the base layer between adjacent gate trenches, the width of the base layer between adjacent gate trenches is greater than the width of the first gate electrode, and the width of the base layer between adjacent gate trenches is greater than the width of the second gate electrode.

[0052] The above technical solution has the following advantages and beneficial effects: the formed semiconductor device has a split gate and a narrow mesa, which can reduce the extraction path of the second emitter holes and reduce the extraction of the drift region holes by the second emitter, thereby increasing the charge concentration in the drift region, reducing the drift region resistance, reducing the conduction voltage drop of the semiconductor device, and reducing the conduction loss of the semiconductor device. Furthermore, it can reduce the energy consumption of the semiconductor device, reduce the operating temperature of the semiconductor device, improve its high-temperature performance and service life, and enable the semiconductor device to be used in high-voltage and high-power fields.

[0053] In some embodiments, in the second direction, the width of the gate trench is 0.5μm-5μm, the width of the base layer between adjacent gate trenches is 0.5μm-2μm, the width of the first gate electrode is 10nm-250nm, and the width of the second gate electrode is 10nm-250nm.

[0054] The above technical solution has the following advantages and beneficial effects: it can significantly reduce the extraction of holes in the drift region by the second emitter, thereby increasing the charge concentration in the drift region, reducing the resistance of the drift region, reducing the conduction voltage drop of the semiconductor device, and reducing the conduction loss of the semiconductor device.

[0055] In some embodiments, the preparation method further comprises:

[0056] A cathode layer of the first conductive type is formed on the lower portion of the substrate by an ion implantation process.

[0057] The above technical solution has the following advantages and beneficial effects: it can be effectively compatible with the design of power devices such as RC-IGBT and has wide applicability.

[0058] In some embodiments, forming a plurality of trench gates spaced apart in the second direction on the upper portion of the substrate includes:

[0059] forming a patterned first mask layer on the first emitter layer and the second emitter layer, wherein the first mask layer exposes a portion of the first emitter layer;

[0060] Using the first mask layer as a mask, etching the substrate by a dry etching process to form a plurality of initial trenches spaced apart in the second direction, wherein the initial trenches penetrate the first emitter layer and the base layer;

[0061] Undercutting the initial trench by a wet etching process to form a gate trench;

[0062] removing the first mask layer, and forming a gate insulating film and an initial electrode in the gate trench, wherein the initial electrode is disposed inside the gate trench via the gate insulating film;

[0063] forming a patterned second mask layer over the substrate, the gate insulating film, and the initial electrode, wherein the second mask layer exposes a portion of the initial electrode;

[0064] Etching the exposed initial electrodes by a dry etching process until the gate insulating film is exposed, wherein the initial electrodes remaining after etching include a first gate electrode and a second gate electrode spaced apart in the second direction;

[0065] forming an isolation layer between the first gate electrode and the second gate electrode;

[0066] The first mask layer and the second mask layer are formed by using the same mask.

[0067] The above technical solution has the following advantages and beneficial effects: a mask layer can be formed multiple times using one mask plate and etched to form a split gate, which can effectively reduce process difficulty and process cost.

[0068] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The following drawings of this application are hereby incorporated as part of this application for understanding this application. The drawings show the embodiments of this application and their descriptions, and are used to explain the device and principle of this application. In the drawings,

[0070] Figure 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;

[0071] Figure 2 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0072] Figure 3A-Figure 3I Schematic cross-sectional views of a structure obtained in various steps of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0073] Figure 4 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to another embodiment of the present application;

[0074] Figures 5A-5I Schematic cross-sectional view of a structure obtained in each step of a method for preparing a semiconductor device according to another embodiment of the present application.

[0075] Description of reference numerals:

[0076] 10-substrate, 11-first mask layer, 12-initial trench, 13-initial electrode, 14-second mask layer,

[0077] 100 - semiconductor substrate, 101 - first main surface, 102 - second main surface, 110 - drift layer, 120 - base layer, 130 - first emitter layer, 140 - second emitter layer, 150 - trench gate, 151 - gate trench, 152 - gate insulating film, 153 - first gate electrode, 154 - second gate electrode, 155 - isolation layer, 160 - collector layer, 170 - field stop layer. DETAILED DESCRIPTION

[0078] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, some technical features well known in the art are not described in order to avoid confusion with the present application.

[0079] It should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present application to those skilled in the art. In the drawings, the dimensions and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0080] It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0081] Spatially relative terms, such as "below," "beneath," "beneath," "above," "upper," etc., may be used herein for convenience to describe the relationship of one element or feature to other elements or features illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientations depicted in the figures.

[0082] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0083] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present application. Thus, variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments of the present application should not be limited to the specific shapes shown herein, but rather include shape deviations due to, for example, manufacturing. Therefore, what is shown in the figures is schematic in nature, and their shapes are not intended to show the actual shape of the device and are not intended to limit the scope of the present application.

[0084] Regarding the conductivity type of the semiconductor, in this application, the first conductivity type is n-type and the second conductivity type is p-type. However, these can be reversed, with the first conductivity type being p-type and the second conductivity type being n-type.

[0085] Refer to the attached Figure 1 A semiconductor device according to an embodiment of the present application is exemplarily described. The semiconductor device may be an IGBT device. The semiconductor device includes a semiconductor substrate 100, a drift layer 110 of a first conductivity type, a base layer 120 of a second conductivity type, a first emitter layer 130 of a first conductivity type, a second emitter layer 140 of a second conductivity type, a plurality of trench gates 150, and a collector layer 160 of a second conductivity type.

[0086] The semiconductor substrate 100 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101. The first main surface 101 and the second main surface 102 are spaced apart in a first direction. Figure 1 The up and down directions in .

[0087] The first conductive type drift layer 110 is disposed between the first main surface 101 and the second main surface 102. The drift layer 110 generally has a relatively low doping concentration, and thus has a relatively high resistance and can withstand a relatively high voltage.

[0088] The second conductivity type base layer 120 is provided on the side of the drift layer 110 facing the first main surface 101 .

[0089] The first emitter layer 130 of the first conductivity type is disposed on the side of the base layer 120 facing the first main surface 101. The side of the first emitter layer 130 facing the first main surface 101 constitutes at least a portion of the first main surface 101. The doping concentration of the first emitter layer 130 is greater than the doping concentration of the drift layer 110.

[0090] The second emitter layer 140 of the second conductivity type is disposed on the side of the base layer 120 facing the first main surface 101. The side of the second emitter layer 140 facing the first main surface 101 constitutes at least a portion of the first main surface 101. The doping concentration of the second emitter layer 140 is greater than that of the base layer 120.

[0091] A plurality of trench gates 150 penetrate the first emitter layer 130 and the base layer 120 from the first main surface 101 and reach the drift layer 110. The plurality of trench gates 150 are arranged at intervals in the second direction. The second direction is perpendicular to the first direction. Figure 1 Left and right direction in .

[0092] The collector layer 160 of the second conductivity type is disposed on the side of the drift layer 110 facing the second main surface 102 , and the side of the collector layer 160 facing the second main surface 102 constitutes at least a portion of the second main surface 102 . The doping concentration of the collector layer 160 is greater than that of the base layer 120 .

[0093] Illustratively, in this embodiment, the semiconductor device further includes a field stop (FieldStop) layer of the first conductivity type, and the field stop layer 170 is provided between the collector layer 160 and the drift layer 110, and the doping concentration of the field stop layer 170 is higher than the doping concentration of the drift layer 110. The main function of the field stop layer 170 is to terminate the electric field when the IGBT is in the off state, preventing the electric field from penetrating into the collector layer 160, thereby improving the voltage withstand capability of the device. When a high voltage is applied, the field stop layer 170 can withstand a portion of the electric field, so that the electric field gradually weakens before reaching the collector layer 160, thereby avoiding breakdown of the collector layer 160. The field stop layer 170 can also reduce the duration and amplitude of the tail current by adjusting the carrier distribution and extraction speed. The reduction of the tail current helps to reduce the turn-off loss.

[0094] Specifically, in this embodiment, the trench gate 150 includes a gate trench 151 , a gate insulating film 152 , a first gate electrode 153 , a second gate electrode 154 and an isolation layer 155 .

[0095] The gate trench 151 penetrates the first emitter layer 130 and the base layer 120 from the first main surface 101 and reaches the drift layer 110 .

[0096] The gate insulating film 152 is disposed on the inner wall surface of the gate trench 151. For example, the gate insulating film 152 may be made of silicon dioxide.

[0097] The first gate electrode 153 is disposed inside the gate trench 151 via the gate insulating film 152. That is, the first gate electrode 153 is isolated from the drift layer 110, the base layer 120, and the first emitter layer 130 by the gate insulating film 152. For example, the first gate electrode 153 may be made of polysilicon.

[0098] The second gate electrode 154 is disposed within the gate trench 151 via the gate insulating film 152, and the first gate electrode 153 and the second gate electrode 154 are spaced apart in the second direction. That is, the second gate electrode 154 is separated from the drift layer 110, the base layer 120, and the first emitter layer 130 by the gate insulating film 152. For example, the second gate electrode 154 can be made of polysilicon.

[0099] The isolation layer 155 is arranged inside the gate trench 151 across the gate insulating film 152, and is located between the first gate electrode 153 and the second gate electrode 154. The first gate electrode 153 and the second gate electrode 154 are isolated by the isolation layer 155. For example, the isolation layer 155 can be a silicon dioxide layer. The first gate electrode 153 and the second gate electrode 154 are separated gates. The setting of the separated gates can effectively reduce the electric field concentration at the bottom of the trench, optimize the electric field distribution, improve the reliability of the device, and effectively reduce the Miller capacitance, thereby increasing the switching speed and reducing the dynamic loss. In addition, the separated gates arranged at intervals in the second direction can also allow independent control of different channel regions, thereby achieving more refined current management.

[0100] In the second direction, the width of the gate trench 151 is greater than the width of the base layer 120 between adjacent gate trenches 151, the width of the base layer 120 between adjacent gate trenches 151 is greater than the width of the first gate electrode 153, and the width of the base layer 120 between adjacent gate trenches 151 is greater than the width of the second gate electrode 154.

[0101] That is, the semiconductor device of the present application is an IGBT device with a narrow mesa structure integrated in the cell area (the width of the mesa between adjacent grooves is small). The narrow mesa structure can reduce the extraction path of the holes in the second emitter layer 140 and reduce the extraction of holes in the drift layer 110 by the second emitter, thereby increasing the charge concentration in the drift region, reducing the resistance of the drift region, reducing the conduction voltage drop of the semiconductor device, and reducing the conduction loss of the semiconductor device. Furthermore, it can reduce the energy consumption of the semiconductor device, reduce the operating temperature of the semiconductor device, improve its high-temperature performance and service life, and enable the semiconductor device to be applied to high-voltage and high-power fields.

[0102] In this embodiment, in the second direction, the width of the gate trench 151 is 0.5μm-5μm, the width of the base layer 120 between adjacent gate trenches 151 is 0.5μm-2μm, the width of the first gate electrode 153 is 10nm-250nm, and the width of the second gate electrode 154 is 10nm-250nm. It should be noted that the width mentioned here may refer to the width at its widest point. Exemplarily, the depth of the gate trench 151 (the depth in the first direction) may be 5μm-20μm, and the aspect ratio of the gate trench 151 may be 4:1-6:1. Exemplarily, in the second direction, the width of the isolation layer 155 may be greater than 100nm, 200nm, 300nm or other suitable values. In some embodiments, the width of the isolation layer 155 may be greater than the width of the first gate electrode 153 and greater than the width of the second gate electrode 154. Exemplarily, the width of the first gate electrode 153 may be equal to the width of the second gate electrode 154.

[0103] By setting the widths of the gate trench 151, the base layer 120, the first gate electrode 153 and the second gate electrode 154 within the above range, the extraction of holes in the drift region by the second emitter can be significantly reduced, thereby increasing the charge concentration in the drift region, reducing the resistance of the drift region, reducing the conduction voltage drop of the semiconductor device, and reducing the conduction loss of the semiconductor device.

[0104] In some embodiments, the semiconductor device further includes a cathode layer of the first conductivity type, disposed on the side of the drift layer 110 facing the second main surface 102. The side of the cathode layer facing the second main surface 102 constitutes at least a portion of the second main surface 102. Specifically, the cathode layer is disposed on the side of the field stop layer 170 facing the second main surface 102, and the cathode layer and the collector layer 160 are arranged parallel to each other in the second direction. That is, the semiconductor device may be an RC-IGBT device. The above technical solution is effectively compatible with the design of power devices such as RC-IGBTs, and has broad applicability.

[0105] Please refer to the attached Figure 2 , Attachment Figure 3A-Figure 3I The method for manufacturing a semiconductor device according to an embodiment of the present application is exemplified. The semiconductor device may be the semiconductor device described above. Figure 2 , the preparation method comprises the following steps:

[0106] S10: A substrate 10 of a first conductive type is provided, and a plurality of trench gates 150 spaced apart in a second direction are formed on the upper portion of the substrate 10. The trench gates 150 include a gate trench 151, a gate insulating film 152, a first gate electrode 153, a second gate electrode 154, and an isolation layer 155. The gate insulating film 152 is disposed on the inner wall surface of the gate trench 151, and the first gate electrode 153, the second gate electrode 154, and the isolation layer 155 are disposed inside the gate trench 151 via the gate insulating film 152. The first gate electrode 153 and the second gate electrode 154 are spaced apart in the second direction, and the isolation layer 155 is located between the first gate electrode 153 and the second gate electrode 154.

[0107] S11: forming a second conductive type base layer 120, a first conductive type first emitter layer 130, and a second conductive type second emitter layer 140 on an upper portion of the substrate 10 by an ion implantation process, wherein in a first direction perpendicular to the second direction, the first emitter layer 130 and the second emitter layer 140 are both located above the base layer 120;

[0108] S12: forming a collector layer 160 of the second conductivity type at the bottom of the substrate 10 by an ion implantation process.

[0109] In which, in the second direction, the width of the gate trench 151 is greater than the width of the base layer 120 between adjacent gate trenches 151, the width of the base layer 120 between adjacent gate trenches 151 is greater than the width of the first gate electrode 153, and the width of the base layer 120 between adjacent gate trenches 151 is greater than the width of the second gate electrode 154.

[0110] The semiconductor device formed by the above steps is an IGBT device with a narrow mesa structure integrated in the cell area (the width of the mesa between adjacent grooves is small). The narrow mesa structure can reduce the extraction path of the holes in the second emitter layer 140 and reduce the extraction of holes from the drift layer 110 by the second emitter, thereby increasing the charge concentration in the drift region, reducing the resistance in the drift region, reducing the on-state voltage drop of the semiconductor device, and reducing the conduction loss of the semiconductor device. Furthermore, the energy consumption of the semiconductor device can be reduced, the operating temperature of the semiconductor device can be reduced, and its high-temperature performance and service life can be improved, so that the semiconductor device can be applied to high-voltage and high-power fields.

[0111] Please refer to the attached Figure 3A-Figure 3I A method for manufacturing a semiconductor device according to an embodiment of the present application (ie, steps S10 to S12 described above) is described in detail.

[0112] In step S10, first, see the attached Figure 3A, a patterned first mask layer 11 is formed on the substrate 10, wherein the first mask layer 11 exposes a portion of the substrate 10. Exemplarily, the substrate 10 may be a silicon substrate, and the first mask layer 11 may be a photoresist layer. In step S10, a mask plate may be used to form the patterned first mask layer 11 on the substrate 10 of the first conductivity type through a photolithography process (including coating, exposure, development, etc.). In some embodiments, the first mask layer 11 may include a photoresist layer and at least one mask material layer, and the mask material layer may be an oxide layer, a nitride layer, an oxynitride layer, etc. In step S10, the mask material layer may be deposited on the substrate 10 through a CVD process or other similar deposition process, and then a patterned photoresist layer may be formed on the mask material layer through a photolithography process using a mask plate, and then the mask material layer may be patterned through a dry or wet etching process using the photoresist layer as a mask to finally form the first mask layer 11.

[0113] Then, see the attached Figure 3B , using the first mask layer 11 as a mask, the exposed substrate 10 is etched by a dry etching process to form a second direction (ie Figure 3B The plurality of initial trenches 12 are spaced apart in the left and right directions. Exemplarily, the dry etching process may be reactive ion etching (RIE), inductively coupled plasma etching (ICP), capacitively coupled plasma etching (CCP), etc.

[0114] Then, see the attached Figure 3C , the initial trench 12 is undercut by a wet etching process to form a gate trench 151. That is, the substrate 10 is further etched by a wet etching process using the first mask layer 11 as a mask, thereby expanding the width of the initial trench 12 in the second direction to ultimately form the gate trench 151. The undercut depth can be strictly controlled according to the solution concentration and etching time.

[0115] Then, see the attached Figure 3DThe first mask layer 11 is removed, and a gate insulating film 152 and an initial electrode 13 are formed in the gate trench 151. The gate insulating film 152 is located on the inner wall surface of the gate trench 151, and the initial electrode 13 is disposed inside the gate trench 151 through the gate insulating film 152. Exemplarily, the first mask layer 11 can be removed by a wet etching process or a CMP (Chemical Mechanical Polishing) process; then, an insulating material layer is formed on the inner wall surface of the gate trench 151 and the upper surface of the substrate 10 by a thermal oxidation process or a CVD (Chemical Vapor Deposition) process; then, an electrode material is deposited on the gate insulating film 152 by a CVD process, and the deposited electrode material fills the gate trench 151; finally, the upper surface of the insulating material layer and the electrode material is polished to be flush with the upper surface of the substrate 10 by a CMP process to form a gate insulating film 152 (the gate insulating film 152 is the insulating material layer remaining after polishing) and an initial electrode 13 (the initial electrode 13 is the electrode material remaining after polishing) in the gate trench 151.

[0116] Then, see the attached Figure 3E A patterned second mask layer 14 is formed over the substrate 10, the gate insulating film 152, and the initial electrode 13, with the second mask layer 14 exposing a portion of the initial electrode 13. Exemplarily, the second mask layer 14 may be a photoresist layer, and a mask may be used to form the patterned second mask layer 14 over the substrate 10, the gate insulating film 152, and the initial electrode 13 through a photolithography process (including coating, exposure, and development). In some embodiments, the second mask layer 14 may include a photoresist layer and at least one mask material layer, which may be an oxide layer, a nitride layer, an oxynitride layer, or the like. The mask material layer may be deposited over the substrate 10, the gate insulating film 152, and the initial electrode 13 through a CVD process or other similar deposition process, and then a patterned photoresist layer may be formed on the mask material layer through a photolithography process using a mask. The mask material layer may then be patterned through a dry or wet etching process using the photoresist layer as a mask, ultimately forming the second mask layer 14.

[0117] Then, see the attached Figure 3F The exposed initial electrode 13 is etched by a dry etching process until the gate insulating film 152 is exposed. The remaining initial electrode 13 after etching includes the first gate electrode 153 and the second gate electrode 154 spaced apart in the second direction. Exemplarily, the dry etching process can be reactive ion etching, inductively coupled plasma etching, capacitively coupled plasma etching, etc.

[0118] Then, see the attached Figure 3G, forming an isolation layer 155 between the first gate electrode 153 and the second gate electrode 154. Exemplarily, an isolation material can be filled into the gate trench 151 through a CVD process, until the isolation material completely fills the gate trench 151. Then, a CMP process is used to grind the upper surface of the isolation material until it is flush with the upper surface of the substrate 10, thereby forming an isolation layer 155 between the first gate electrode 153 and the second gate electrode 154 (the isolation layer 155 is the remaining isolation material after grinding). The first gate electrode 153 and the second gate electrode 154 are electrically insulated by the isolation layer 155.

[0119] In this embodiment, the first mask layer 11 and the second mask layer 14 are formed by the same mask plate, that is, the embodiment of the present application uses a mask plate to form the mask layer multiple times and etch to form a split gate, without introducing additional mask plates, which can effectively reduce the process difficulty and process cost.

[0120] In step S11, see the attached Figure 3H First, a patterned mask layer is formed on the substrate 10 and the trench gate 150 through a photolithography process (the mask layer covers the trench gate 150). Then, using the mask layer as a mask, ions of the second conductivity type are implanted into the upper portion of the substrate 10 to form the base layer 120 on the upper portion of the substrate 10. Then, a high-temperature annealing (e.g., rapid thermal annealing) is performed to repair lattice damage and activate the impurity ions. Subsequently, ions of the first conductivity type and ions of the second conductivity type are implanted into the upper portion of the base layer 120 in a similar manner, and annealed for activation to form a first emitter layer 130 of the first conductivity type and a second emitter layer 140 of the second conductivity type.

[0121] In step S12, see the attached Figure 3I First, the lower side of the substrate 10 is thinned. Ions of the first conductivity type are then implanted into the lower portion of the substrate 10 to form a field stop layer 170. Ions of the second conductivity type are then implanted into the lower portion of the substrate 10 to form a collector layer 160. Finally, a high-temperature anneal is performed to repair lattice damage and activate the impurity ions. The portion of the substrate 10 between the field stop layer 170, the trench gate 150, and the base layer 120 serves as the drift layer 110.

[0122] This concludes the introduction to the relevant steps of the method for manufacturing a semiconductor device according to an embodiment of the present application. Following the aforementioned steps, other conventional steps for manufacturing an IGBT device may also be included, which will not be detailed here. Furthermore, in addition to the aforementioned steps, the method for manufacturing a semiconductor device according to this embodiment may also include other steps within or between the aforementioned steps. These steps can all be implemented using various processes in the prior art, which will not be detailed here.

[0123] In this embodiment, in the second direction, the width of the gate trench 151 is 0.5μm-5μm, the width of the base layer 120 between adjacent gate trenches 151 is 0.5μm-2μm, the width of the first gate electrode 153 is 10nm-250nm, and the width of the second gate electrode 154 is 10nm-250nm. It should be noted that the width mentioned here may refer to the width at its widest point. Exemplarily, the depth of the gate trench 151 (the depth in the first direction) may be 5μm-20μm, and the aspect ratio of the gate trench 151 may be 4:1-6:1. Exemplarily, in the second direction, the width of the isolation layer 155 may be greater than 100nm, 200nm, 300nm or other suitable values. In some embodiments, the width of the isolation layer 155 may be greater than the width of the first gate electrode 153 and greater than the width of the second gate electrode 154. Exemplarily, the width of the first gate electrode 153 may be equal to the width of the second gate electrode 154.

[0124] By setting the widths of the gate trench 151, the base layer 120, the first gate electrode 153 and the second gate electrode 154 within the above range, the extraction of holes in the drift region by the second emitter can be significantly reduced, thereby increasing the charge concentration in the drift region, reducing the resistance of the drift region, reducing the conduction voltage drop of the semiconductor device, and reducing the conduction loss of the semiconductor device.

[0125] In some embodiments, the preparation method further includes: forming a cathode layer of the first conductivity type under the substrate 10 through an ion implantation process. Specifically, in step S12, the lower side of the substrate 10 is first thinned, and then ions of the first conductivity type are implanted under the substrate 10 to form a field stop layer 170 under the substrate 10. Then, ions of the second conductivity type are implanted under the substrate 10 to form a collector layer 160 under the substrate 10. A high-temperature annealing process is then performed to repair lattice damage and activate impurity ions. A patterned mask layer is then formed on the side of the collector layer 160 away from the buffer layer. Using this mask layer as a mask, ions of the first conductivity type are implanted into the collector layer 160, and a high-temperature annealing process is performed to form a cathode layer. The cathode layer is disposed on the side of the field stop layer 170 away from the base layer 120, and the cathode layer and the collector layer 160 are disposed side by side in the second direction. That is, the formed semiconductor device can be an RC-IGBT device, that is, the above technical solution can be effectively compatible with the design of power devices such as RC-IGBT and has wide applicability.

[0126] Please refer to the attached Figure 4 , Attachment Figures 5A-5I The method for manufacturing a semiconductor device according to an embodiment of the present application is exemplified. The semiconductor device may be the semiconductor device described above. Figure 4 , the preparation method comprises the following steps:

[0127] S20: Providing a substrate 10 of the first conductivity type, and forming a base layer 120 of the second conductivity type, a first emitter layer 130 of the first conductivity type, and a second emitter layer 140 of the second conductivity type on the upper portion of the substrate 10 by an ion implantation process. In the first direction, the first emitter layer 130 and the second emitter layer 140 are both located above the base layer 120.

[0128] S21: A plurality of trench gates 150 spaced apart in a second direction are formed on the upper portion of the substrate 10. The second direction is perpendicular to the first direction, and the trench gate 150 includes a gate trench 151, a gate insulating film 152, a first gate electrode 153, a second gate electrode 154, and an isolation layer 155. The gate trench 151 penetrates the first emitter layer 130 and the base layer 120. The gate insulating film 152 is disposed on the inner wall surface of the gate trench 151. The first gate electrode 153, the second gate electrode 154, and the isolation layer 155 are disposed inside the gate trench 151 via the gate insulating film 152. The first gate electrode 153 and the second gate electrode 154 are spaced apart in the second direction, and the isolation layer 155 is located between the first gate electrode 153 and the second gate electrode 154.

[0129] S22 : forming a collector layer 160 of the second conductivity type at the bottom of the substrate 10 by an ion implantation process.

[0130] In which, in the second direction, the width of the gate trench 151 is greater than the width of the base layer 120 between adjacent gate trenches 151, the width of the base layer 120 between adjacent gate trenches 151 is greater than the width of the first gate electrode 153, and the width of the base layer 120 between adjacent gate trenches 151 is greater than the width of the second gate electrode 154.

[0131] The semiconductor device formed by the above steps is an IGBT device with a narrow mesa structure integrated in the cell area (the width of the mesa between adjacent grooves is small). The narrow mesa structure can reduce the extraction path of the holes in the second emitter layer 140 and reduce the extraction of holes from the drift layer 110 by the second emitter, thereby increasing the charge concentration in the drift region, reducing the resistance in the drift region, reducing the on-state voltage drop of the semiconductor device, and reducing the conduction loss of the semiconductor device. Furthermore, the energy consumption of the semiconductor device can be reduced, the operating temperature of the semiconductor device can be reduced, and its high-temperature performance and service life can be improved, so that the semiconductor device can be applied to high-voltage and high-power fields.

[0132] Please refer to the attached Figures 5A-5I A method for manufacturing a semiconductor device according to an embodiment of the present application (ie, steps S20 to S22 described above) is described in detail.

[0133] In step S20, see the attached Figure 5AFirst, ions of the second conductivity type are implanted on the upper portion of the substrate 10 to form the base layer 120 on the upper portion of the substrate 10. Then, ions of the first conductivity type are implanted on the upper portion of the base layer 120 to form the first emitter layer 130 on the upper portion of the base layer 120. Then, a patterned mask layer is formed on the first emitter layer 130. Using the mask layer as a mask, ions of the second conductivity type are implanted in the first emitter layer 130 to form the second emitter layer 140. Finally, a high-temperature annealing is performed to repair lattice damage and activate the impurity ions. For example, the substrate 10 may be a silicon substrate.

[0134] In step S21, first, see the attached Figure 5B A patterned first mask layer 11 is formed on the substrate 10 (i.e., on the first emitter layer 130 and the second emitter layer 140), wherein the first mask layer 11 exposes a portion of the first emitter layer 130. Exemplarily, the first mask layer 11 may be a photoresist layer. In step S21, a mask plate may be used to form the patterned first mask layer 11 on the substrate 10 through a photolithography process (including coating, exposure, development, etc.). In some embodiments, the first mask layer 11 may include a photoresist layer and at least one mask material layer. The mask material layer may be an oxide layer, a nitride layer, an oxynitride layer, etc. In step S21, the mask material layer may be deposited on the substrate 10 through a CVD process or other similar deposition process. Then, a patterned photoresist layer is formed on the mask material layer through a photolithography process using a mask plate. The mask material layer is then patterned through a dry or wet etching process using the photoresist layer as a mask to ultimately form the first mask layer 11.

[0135] Then, see the attached Figure 5C , using the first mask layer 11 as a mask, the exposed substrate 10 is etched by a dry etching process to form a second direction (ie Figure 5C Multiple initial trenches 12 are spaced apart in the left-right direction (in the middle and left-right directions). Exemplarily, the dry etching process may be reactive ion etching (RIE), inductively coupled plasma etching (ICP), capacitively coupled plasma etching (CCP), etc. The initial trenches 12 penetrate the first emitter layer 130 and the base layer 120, and the depth of the initial trenches 12 is greater than the sum of the thicknesses of the first emitter layer 130 and the base layer 120.

[0136] Then, see the attached Figure 5D, the initial trench 12 is undercut by a wet etching process to form a gate trench 151. That is, the substrate 10 is further etched by a wet etching process using the first mask layer 11 as a mask, thereby expanding the width of the initial trench 12 in the second direction to ultimately form the gate trench 151. The undercut depth can be strictly controlled according to the solution concentration and etching time.

[0137] Then, see the attached Figure 5E The first mask layer 11 is removed, and a gate insulating film 152 and an initial electrode 13 are formed in the gate trench 151. The gate insulating film 152 is located on the inner wall surface of the gate trench 151, and the initial electrode 13 is disposed inside the gate trench 151 through the gate insulating film 152. Illustratively, the first mask layer 11 can be removed by a wet etching process or a CMP (Chemical Mechanical Polishing) process; then, an insulating material layer is formed on the inner wall surface of the gate trench 151 and the upper surface of the substrate 10 by a thermal oxidation process or a CVD (Chemical Vapor Deposition) process; then, an electrode material is deposited on the gate insulating film 152 by a CVD process, and the deposited electrode material fills the gate trench 151; finally, the upper surfaces of the insulating material layer and the electrode material are polished to be flush with the upper surface of the substrate 10 (that is, the upper surfaces of the first emitter layer 130 and the second emitter layer 140) by a CMP process, so as to form a gate insulating film 152 (the gate insulating film 152 is the insulating material layer remaining after polishing) and an initial electrode 13 (the initial electrode 13 is the electrode material remaining after polishing) in the gate trench 151.

[0138] Then, see the attached Figure 5F A patterned second mask layer 14 is formed over the substrate 10, the gate insulating film 152, and the initial electrode 13, with the second mask layer 14 exposing a portion of the initial electrode 13. Exemplarily, the second mask layer 14 may be a photoresist layer, and a mask may be used to form the patterned second mask layer 14 over the substrate 10, the gate insulating film 152, and the initial electrode 13 through a photolithography process (including coating, exposure, and development). In some embodiments, the second mask layer 14 may include a photoresist layer and at least one mask material layer, which may be an oxide layer, a nitride layer, an oxynitride layer, or the like. The mask material layer may be deposited over the substrate 10, the gate insulating film 152, and the initial electrode 13 through a CVD process or other similar deposition process, and then a patterned photoresist layer may be formed on the mask material layer through a photolithography process using a mask. The mask material layer may then be patterned through a dry or wet etching process using the photoresist layer as a mask, ultimately forming the second mask layer 14.

[0139] Then, see the attached Figure 5GThe exposed initial electrode 13 is etched by a dry etching process until the gate insulating film 152 is exposed. The remaining initial electrode 13 after etching includes the first gate electrode 153 and the second gate electrode 154 spaced apart in the second direction. Exemplarily, the dry etching process can be reactive ion etching, inductively coupled plasma etching, capacitively coupled plasma etching, etc.

[0140] Then, see the attached Figure 5H , forming an isolation layer 155 between the first gate electrode 153 and the second gate electrode 154. Exemplarily, an isolation material can be filled into the gate trench 151 through a CVD process, until the isolation material completely fills the gate trench 151. Then, a CMP process is used to grind the upper surface of the isolation material until it is flush with the upper surface of the substrate 10, thereby forming an isolation layer 155 between the first gate electrode 153 and the second gate electrode 154 (the isolation layer 155 is the remaining isolation material after grinding). The first gate electrode 153 and the second gate electrode 154 are electrically insulated by the isolation layer 155.

[0141] In this embodiment, the first mask layer 11 and the second mask layer 14 are formed by the same mask plate, that is, the embodiment of the present application uses a mask plate to form the mask layer multiple times and etch to form a split gate, without introducing additional mask plates, which can effectively reduce the process difficulty and process cost.

[0142] In step S22, see the attached Figure 5I First, the lower side of the substrate 10 is thinned. Ions of the first conductivity type are then implanted into the lower portion of the substrate 10 to form a field stop layer 170. Ions of the second conductivity type are then implanted into the lower portion of the substrate 10 to form a collector layer 160. Finally, a high-temperature anneal is performed to repair lattice damage and activate the impurity ions. The portion of the substrate 10 between the field stop layer 170, the trench gate 150, and the base layer 120 serves as the drift layer 110.

[0143] This concludes the introduction to the relevant steps of the method for manufacturing a semiconductor device according to an embodiment of the present application. Following the aforementioned steps, other conventional steps for manufacturing an IGBT device may also be included, which will not be detailed here. Furthermore, in addition to the aforementioned steps, the method for manufacturing a semiconductor device according to this embodiment may also include other steps within or between the aforementioned steps. These steps can all be implemented using various processes in the prior art, which will not be detailed here.

[0144] In this embodiment, in the second direction, the width of the gate trench 151 is 0.5μm-5μm, the width of the base layer 120 between adjacent gate trenches 151 is 0.5μm-2μm, the width of the first gate electrode 153 is 10nm-250nm, and the width of the second gate electrode 154 is 10nm-250nm. It should be noted that the width mentioned here may refer to the width at its widest point. Exemplarily, the depth of the gate trench 151 (the depth in the first direction) may be 5μm-20μm, and the aspect ratio of the gate trench 151 may be 4:1-6:1. Exemplarily, in the second direction, the width of the isolation layer 155 may be greater than 100nm, 200nm, 300nm or other suitable values. In some embodiments, the width of the isolation layer 155 may be greater than the width of the first gate electrode 153 and greater than the width of the second gate electrode 154. Exemplarily, the width of the first gate electrode 153 may be equal to the width of the second gate electrode 154.

[0145] By setting the widths of the gate trench 151, the base layer 120, the first gate electrode 153 and the second gate electrode 154 within the above range, the extraction of holes in the drift region by the second emitter can be significantly reduced, thereby increasing the charge concentration in the drift region, reducing the resistance of the drift region, reducing the conduction voltage drop of the semiconductor device, and reducing the conduction loss of the semiconductor device.

[0146] In some embodiments, the preparation method further includes: forming a cathode layer of the first conductivity type under the substrate 10 through an ion implantation process. Specifically, in step S22, the lower side of the substrate 10 is first thinned, and then ions of the first conductivity type are implanted under the substrate 10 to form a field stop layer 170 under the substrate 10. Then, ions of the second conductivity type are implanted under the substrate 10 to form a collector layer 160 under the substrate 10. A high-temperature annealing process is then performed to repair lattice damage and activate impurity ions. A patterned mask layer is then formed on the side of the collector layer 160 away from the buffer layer. Using this mask layer as a mask, ions of the first conductivity type are implanted into the collector layer 160, and a high-temperature annealing process is performed to form a cathode layer. The cathode layer is disposed on the side of the field stop layer 170 away from the base layer 120, and the cathode layer and the collector layer 160 are disposed side by side in the second direction. That is, the formed semiconductor device can be an RC-IGBT device, that is, the above technical solution can be effectively compatible with the design of power devices such as RC-IGBT and has wide applicability.

[0147] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely illustrative and are not intended to limit the scope of the present application. Various changes and modifications may be made therein by those skilled in the art without departing from the scope and spirit of the present application. All such changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0148] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0149] Similarly, it should be understood that in order to streamline the present application and aid in understanding one or more of the various inventive aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, this approach of the present application should not be interpreted as reflecting the intention that the application claimed for protection requires more features than those explicitly recited in each claim. More precisely, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with fewer features than all the features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into the detailed description, with each claim itself serving as a separate embodiment of the present application.

[0150] Those skilled in the art will understand that, except where mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus disclosed herein may be combined in any combination. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that provides the same, equivalent, or similar purpose.

[0151] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of this application and to form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

[0152] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, wherein the first main surface and the second main surface are spaced apart in a first direction; A drift layer of the first conductivity type is provided between the first main surface and the second main surface; a base layer of the second conductivity type, disposed on a side of the drift layer facing the first main surface; A first emitter layer of a first conductivity type is provided on a side of the base layer facing the first main surface, wherein the side of the first emitter layer facing the first main surface constitutes at least a portion of the first main surface; a second emitter layer of a second conductivity type, disposed on a side of the base layer facing the first main surface, wherein the side of the second emitter layer facing the first main surface constitutes at least a portion of the first main surface; a plurality of trench gates, the trench gates penetrating the first emitter layer and the base layer from the first main surface to reach the drift layer, the plurality of trench gates being spaced apart in a second direction, the second direction being perpendicular to the first direction; a collector layer of the second conductivity type, disposed on a side of the drift layer facing the second main surface, wherein the side of the collector layer facing the second main surface constitutes at least a portion of the second main surface; Wherein, the trench gate comprises: a gate trench, penetrating the first emitter layer and the base layer from the first main surface to reach the drift layer; a gate insulating film, disposed on an inner wall surface of the gate trench; a first gate electrode disposed inside the gate trench via the gate insulating film; a second gate electrode disposed inside the gate trench via the gate insulating film, and the first gate electrode and the second gate electrode are spaced apart from each other in the second direction; an isolation layer, disposed inside the gate trench via the gate insulating film and located between the first gate electrode and the second gate electrode; In the second direction, the width of the gate trench is greater than the width of the base layer between adjacent gate trenches, the width of the base layer between adjacent gate trenches is greater than the width of the first gate electrode, and the width of the base layer between adjacent gate trenches is greater than the width of the second gate electrode.

2. The semiconductor device according to claim 1, wherein In the second direction, the width of the gate trench is 0.5 μm-5 μm, the width of the base layer between adjacent gate trenches is 0.5 μm-2 μm, the width of the first gate electrode is 10 nm-250 nm, and the width of the second gate electrode is 10 nm-250 nm.

3. The semiconductor device according to claim 1, wherein The semiconductor device further includes a cathode layer of the first conductivity type, which is disposed on a side of the drift layer facing the second main surface. The side of the cathode layer facing the second main surface constitutes at least a portion of the second main surface.

4. A method for preparing a semiconductor device, characterized in that: The steps include: Providing a substrate of a first conductivity type, forming a plurality of trench gates spaced apart in a second direction on an upper portion of the substrate, wherein the trench gates include a gate trench, a gate insulating film, a first gate electrode, a second gate electrode, and an isolation layer, wherein the gate insulating film is disposed on an inner wall surface of the gate trench, the first gate electrode, the second gate electrode, and the isolation layer are disposed within the gate trench via the gate insulating film, the first gate electrode and the second gate electrode are spaced apart in the second direction, and the isolation layer is located between the first gate electrode and the second gate electrode; forming a base layer of the second conductivity type, a first emitter layer of the first conductivity type, and a second emitter layer of the second conductivity type on an upper portion of the substrate by an ion implantation process, wherein in a first direction perpendicular to the second direction, the first emitter layer and the second emitter layer are both located above the base layer; forming a collector layer of the second conductivity type at the lower portion of the substrate by an ion implantation process; In which, in the second direction, the width of the gate trench is greater than the width of the base layer between adjacent gate trenches, the width of the base layer between adjacent gate trenches is greater than the width of the first gate electrode, and the width of the base layer between adjacent gate trenches is greater than the width of the second gate electrode.

5. The preparation method according to claim 4, characterized in that In the second direction, the width of the gate trench is 0.5 μm-5 μm, the width of the base layer between adjacent gate trenches is 0.5 μm-2 μm, the width of the first gate electrode is 10 nm-250 nm, and the width of the second gate electrode is 10 nm-250 nm.

6. The preparation method according to claim 4, characterized in that The preparation method further comprises: A cathode layer of the first conductive type is formed at the lower portion of the substrate by an ion implantation process.

7. The preparation method according to claim 4, characterized in that The method of forming a plurality of trench gates spaced apart in the second direction on the upper portion of the substrate comprises: forming a patterned first mask layer on the substrate, wherein the first mask layer exposes a portion of the substrate; Using the first mask layer as a mask, etching the exposed substrate by a dry etching process to form a plurality of initial trenches spaced apart in the second direction; Undercutting the initial trench by a wet etching process to form a gate trench; removing the first mask layer, and forming a gate insulating film and an initial electrode in the gate trench, wherein the initial electrode is disposed inside the gate trench via the gate insulating film; forming a patterned second mask layer over the substrate, the gate insulating film, and the initial electrode, wherein the second mask layer exposes a portion of the initial electrode; Etching the exposed initial electrodes by a dry etching process until the gate insulating film is exposed, wherein the initial electrodes remaining after etching include the first gate electrodes and the second gate electrodes spaced apart in the second direction; forming an isolation layer between the first gate electrode and the second gate electrode; The first mask layer and the second mask layer are formed by using the same mask.

8. A method for preparing a semiconductor device, characterized in that: The steps include: Providing a substrate of a first conductivity type, and forming a base layer of a second conductivity type, a first emitter layer of the first conductivity type, and a second emitter layer of the second conductivity type on an upper portion of the substrate by an ion implantation process, wherein in a first direction, the first emitter layer and the second emitter layer are both located above the base layer; forming a plurality of trench gates spaced apart in a second direction on an upper portion of the substrate, wherein the second direction is perpendicular to the first direction, the trench gates comprising a gate trench, a gate insulating film, a first gate electrode, a second gate electrode, and an isolation layer, the gate trench penetrating the first emitter layer and the base layer, the gate insulating film being disposed on an inner wall surface of the gate trench, the first gate electrode, the second gate electrode, and the isolation layer being disposed within the gate trench via the gate insulating film, the first gate electrode and the second gate electrode being spaced apart in the second direction, and the isolation layer being located between the first gate electrode and the second gate electrode; forming a collector layer of the second conductivity type at the lower portion of the substrate by an ion implantation process; In which, in the second direction, the width of the gate trench is greater than the width of the base layer between adjacent gate trenches, the width of the base layer between adjacent gate trenches is greater than the width of the first gate electrode, and the width of the base layer between adjacent gate trenches is greater than the width of the second gate electrode.

9. The preparation method according to claim 8, characterized in that In the second direction, the width of the gate trench is 0.5 μm-5 μm, the width of the base layer between adjacent gate trenches is 0.5 μm-2 μm, the width of the first gate electrode is 10 nm-250 nm, and the width of the second gate electrode is 10 nm-250 nm.

10. The preparation method according to claim 8, characterized in that The preparation method further comprises: A cathode layer of the first conductive type is formed on the lower portion of the substrate by an ion implantation process.

11. The preparation method according to claim 8, characterized in that The method of forming a plurality of trench gates spaced apart in the second direction on the upper portion of the substrate comprises: forming a patterned first mask layer on the first emitter layer and the second emitter layer, wherein the first mask layer exposes a portion of the first emitter layer; Using the first mask layer as a mask, etching the substrate by a dry etching process to form a plurality of initial trenches spaced apart in the second direction, wherein the initial trenches penetrate the first emitter layer and the base layer; Undercutting the initial trench by a wet etching process to form a gate trench; removing the first mask layer, and forming a gate insulating film and an initial electrode in the gate trench, wherein the initial electrode is disposed inside the gate trench via the gate insulating film; forming a patterned second mask layer over the substrate, the gate insulating film, and the initial electrode, wherein the second mask layer exposes a portion of the initial electrode; Etching the exposed initial electrodes by a dry etching process until the gate insulating film is exposed, wherein the initial electrodes remaining after etching include a first gate electrode and a second gate electrode spaced apart in the second direction; forming an isolation layer between the first gate electrode and the second gate electrode; The first mask layer and the second mask layer are formed by using the same mask.

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