Method for manufacturing semiconductor device and semiconductor device

Abstract

The embodiment relates to a semiconductor device manufacturing method and a semiconductor device. A method of manufacturing a semiconductor device includes: forming a trench and a mesa portion in a semiconductor layer; forming a field plate electrode in the groove; forming a silicon nitride film on the field plate electrode, the mesa part and the upper side wall of the mesa part; forming a silicon oxide film in the trench and on the mesa portion by a chemical vapor deposition method after the silicon nitride film is formed; removing the silicon oxide film on the mesa part through a chemical mechanical polishing method; after the silicon oxide film on the mesa part is removed, the silicon nitride film on the upper side wall of the mesa part and the silicon nitride film on the mesa part are removed; and forming a gate electrode on the silicon oxide film in the trench after removing the silicon nitride film.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2024-064889 (filing date: April 12, 2024), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0004] Some power devices have a structure in which a field plate electrode is provided in a trench, and a gate electrode is provided on the field plate electrode via an insulating layer. Summary of the Invention

[0005] According to an embodiment, a method for manufacturing a semiconductor device has the following steps: forming a groove and a mesa portion adjacent to the groove in a semiconductor layer; forming a field plate electrode in the groove via a field insulating film; forming a silicon nitride film on the field plate electrode, on the mesa portion, and on the upper sidewall of the mesa portion adjacent to the trench above the field plate electrode; after forming the silicon nitride film, forming a silicon oxide film in the trench and on the mesa portion by chemical vapor deposition; removing the silicon oxide film on the mesa portion by chemical mechanical polishing to expose the silicon nitride film on the mesa portion; after removing the silicon oxide film on the mesa portion, removing the silicon nitride film on the upper sidewall of the mesa portion and the silicon nitride film on the mesa portion; and after removing the silicon nitride film, forming a gate electrode on the silicon oxide film in the trench.

[0006] According to this embodiment, a method for manufacturing a semiconductor device and a semiconductor device capable of suppressing charge trapping at the bottom of a trench can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to an embodiment.

[0008] Figure 2 (a) and (b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0009] Figure 3 (a) and (b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0010] Figure 4 (a) and (b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0011] Figure 5 (a) and (b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0012] Figure 6 (a) and (b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0013] Figure 7 (a) and (b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0014] The following describes the embodiments with reference to the accompanying drawings. In the drawings, identical structures are denoted by identical reference numerals. In the drawings shown below, directions are represented by the X-axis, Y-axis, and Z-axis. The direction along the X-axis is referred to as the first direction X. The direction along the Y-axis is referred to as the second direction Y, which is orthogonal to the first direction X. The direction along the Z-axis is referred to as the third direction Z, which is orthogonal to the first direction X and the second direction Y. In this specification, the thickness in a particular direction refers to the maximum thickness in that particular direction.

[0015] like Figure 1 As shown, the semiconductor device 1 of the embodiment includes a first electrode 31, a second electrode 32, and a semiconductor layer 10 disposed between the first electrode 31 and the second electrode 32 in the third direction Z. The semiconductor device 1 has, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure. The first electrode 31 is the drain electrode in the MOSFET, and the second electrode 32 is the source electrode in the MOSFET. For example, a positive potential is applied to the first electrode 31, and 0 V is applied to the second electrode 32. In the on-state where the gate voltage of the gate electrode 40 described later is higher than the threshold voltage, current flows in the longitudinal direction (third direction Z) between the first electrode 31 and the second electrode 32 through the semiconductor layer 10. In the third direction Z, the direction from the first electrode 31 toward the second electrode 32 is defined as upward or above, and the direction from the second electrode 32 toward the first electrode 31 is defined as downward or below.

[0016] The semiconductor layer 10 is, for example, a silicon layer. In this specification, the first conductivity type in the semiconductor layer 10 is n-type and the second conductivity type is p-type. Alternatively, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0017] The semiconductor layer 10 includes an n-type first semiconductor layer 11, a p-type second semiconductor layer 12 provided on the first semiconductor layer 11, and an n-type third semiconductor layer 13 provided on the second semiconductor layer 12. The n-type impurity concentration of the third semiconductor layer 13 is higher than the n-type impurity concentration of the first semiconductor layer 11. The semiconductor layer 10 also includes an n-type fourth semiconductor layer 14 provided between the first electrode 31 and the first semiconductor layer 11. The fourth semiconductor layer 14 is in contact with the first electrode 31 and is electrically connected to the first electrode 31.

[0018] Alternatively, the semiconductor device 1 may be an IGBT (Insulated Gate Bipolar Transistor) having a p-type fourth semiconductor layer 14 disposed between the first electrode 31 and the first semiconductor layer 11. In the IGBT, an n-type buffer layer having a higher n-type impurity concentration than that of the first semiconductor layer 11 may be disposed between the n-type first semiconductor layer 11 and the p-type fourth semiconductor layer 14.

[0019] The semiconductor layer 10 includes a plurality of mesa portions 10A arranged in a first direction X. The mesa portion 10A extends, for example, in a second direction Y. The mesa portion 10A includes a portion of a first semiconductor layer 11 , a second semiconductor layer 12 provided on a portion of the first semiconductor layer 11 , and a third semiconductor layer 13 provided on the second semiconductor layer 12 .

[0020] The semiconductor device 1 includes a plurality of trench structures 20 arranged in the first direction X. The trench structures 20 extend, for example, in the second direction Y. The trench structures 20 are adjacent to the mesa portion 10A in the first direction X.

[0021] The trench structure 20 includes a gate electrode 40 , a gate insulating film 80 , a field plate electrode 50 , a first insulating layer 60 , and a field insulating film 70 .

[0022] The side surface of the gate electrode 40 faces the second semiconductor layer 12 in the first direction X, with the gate insulating film 80 interposed therebetween. The gate electrode 40 extends in the second direction Y. For example, the end portion of the gate electrode 40 in the second direction Y is connected to a gate wiring (not shown). In the on-state where the gate voltage of the gate electrode 40 is higher than the threshold voltage, an n-channel (inversion layer) is formed in the region of the second semiconductor layer 12 facing the gate electrode 40.

[0023] The gate insulating film 80 is located between the gate electrode 40 and the second semiconductor layer 12 in the first direction X. The gate insulating film 80 is, for example, a silicon oxide film.

[0024] The field plate electrode 50 is located below the gate electrode 40 in the third direction Z. The field plate electrode 50 extends in the second direction Y. For example, the end of the field plate electrode 50 in the second direction Y is connected to the second electrode 32. The field plate electrode 50 can mitigate the longitudinal electric field (the electric field in the third direction Z) generated in the semiconductor layer 10, thereby improving the withstand voltage of the semiconductor device 1. The field plate electrode 50 can be electrically connected to the gate electrode 40.

[0025] The first insulating layer 60 is provided between the field plate electrode 50 and the gate electrode 40 in the third direction Z. The first insulating layer 60 includes a first silicon oxide film 61 , a silicon nitride film 62 , and a second silicon oxide film 63 .

[0026] The first silicon oxide film 61 is provided between the field plate electrode 50 and the silicon nitride film 62 in the third direction Z. The silicon nitride film 62 is provided between the first silicon oxide film 61 and the second silicon oxide film 63 in the third direction Z. The second silicon oxide film 63 is provided between the silicon nitride film 62 and the gate electrode 40 in the third direction Z. The thickness of the silicon nitride film 62 located between the first silicon oxide film 61 and the second silicon oxide film 63 in the third direction Z is thinner than the thickness of the second silicon oxide film 63 in the third direction Z. The thickness of the silicon nitride film 62 in the third direction Z may also be thinner than the thickness of the first silicon oxide film 61 in the third direction Z.

[0027] The third silicon oxide film 81 is provided between the first insulating layer 60 and the mesa portion 10A in the first direction X. The silicon nitride film 62 is provided between the second silicon oxide film 63 and the third silicon oxide film 81 in the first direction X. The third silicon oxide film 81 is provided between the silicon nitride film 62 and the mesa portion 10A in the first direction X.

[0028] The field insulating film 70 is provided between the field plate electrode 50 and the first semiconductor layer 11 in the first direction X and the third direction Z. The field insulating film 70 is a silicon oxide film and does not contain silicon nitride. By excluding silicon nitride from the bottom of the trench structure 20, where electric field strength is likely to increase, charge trapping at the bottom of the trench structure 20 can be suppressed. This can minimize degradation in characteristics such as withstand voltage of the semiconductor device 1 and reduce reliability degradation over time.

[0029] In the region adjacent to both side surfaces of the first silicon oxide film 61 in the first direction X, the silicon nitride film 62 is located between the field insulating film 70 and the second silicon oxide film 63 in the third direction Z. Furthermore, the silicon nitride film 62 covers both side surfaces of the first silicon oxide film 61 in the first direction X. The silicon nitride film 62 has a concave portion outside the portion on the first silicon oxide film 61 (outside in the first direction X).

[0030] The second electrode 32 is provided on the semiconductor layer 10. The second electrode 32 contacts the third semiconductor layer 13, for example, via a trench contact structure. A portion (contact portion) 32A of the second electrode 32 penetrates the third semiconductor layer 13 and reaches the second semiconductor layer 12. The third semiconductor layer 13 and the second semiconductor layer 12 are in contact with the portion 32A of the second electrode 32 and are electrically connected to the second electrode 32. The p-type impurity concentration of the portion of the second semiconductor layer 12 that the portion 32A of the second electrode 32 contacts can be higher than the p-type impurity concentration of the portion of the second semiconductor layer 12 that forms the channel. The second electrode 32 can also contact the upper surface of the third semiconductor layer 13.

[0031] The second insulating layer 90 is provided between the gate electrode 40 and the second electrode 32 in the third direction Z. The second insulating layer 90 mainly contains silicon oxide, for example, and may further contain boron, phosphorus, and the like.

[0032] Next, refer to Figure 2 (a)~ Figure 7 (b) The method for manufacturing the semiconductor device according to the embodiment will be described. The method for manufacturing the semiconductor device according to the embodiment can include the steps described below.

[0033] like Figure 2 As shown in (a), a plurality of trenches T arranged in a first direction X are formed in the semiconductor layer 10. For example, the plurality of trenches T are formed by RIE (Reactive Ion Etching). By forming the plurality of trenches T in the semiconductor layer 10, mesa portions 10A are formed between adjacent trenches T in the first direction X.

[0034] After the trench T and the mesa portion 10A are formed in the semiconductor layer 10, Figure 2 As shown in (b), a field insulating film 70 is formed in the trench T. For example, a silicon oxide film can be formed by chemical vapor deposition (CVD). The field insulating film 70 can also be formed by thermal oxidation. The field insulating film 70 is continuously formed on the inner walls (sidewalls and bottom) of the trench T and the upper surface of the mesa portion 10A.

[0035] After forming the field insulating film 70, an electrode material that will become the field plate electrode 50 is embedded in the trench T through the field insulating film 70. For example, the electrode material is embedded in the trench T by a CVD method. The electrode material is also deposited on the field insulating film 70 formed on the mesa portion 10A. The upper surface of the electrode material in the trench T is retreated by isotropic or anisotropic etching. The electrode material formed on the mesa portion 10A is also removed. As a result, Figure 3 As shown in FIG. 5 ( a ), an electrode material is left on the bottom side of the trench T as a field plate electrode 50 .

[0036] As the material of the field plate electrode 50, for example, polycrystalline silicon or amorphous silicon doped with phosphorus or boron can be used. For example, phosphorus or boron can be doped when the polycrystalline silicon is formed in the trench T. Alternatively, phosphorus or boron can be implanted into the polycrystalline silicon by ion implantation after the polycrystalline silicon is formed in the trench T. Alternatively, phosphorus can be diffused into the polycrystalline silicon by a high-temperature heat treatment including POCl3.

[0037] After forming the field plate electrode 50, the upper portion of the field plate electrode 50 is oxidized as needed. For example, the upper portion of the field plate electrode 50 is oxidized by thermal oxidation. However, this step may not be performed.

[0038] After forming the field plate electrode 50, the field insulating film 70 formed on the upper sidewall 10B of the mesa portion 10A is removed. The upper sidewall 10B of the mesa portion 10A is adjacent to the upper portion of the trench T above the field plate electrode 50. For example, the field insulating film 70 formed on the upper sidewall 10B of the mesa portion 10A is removed by wet etching or isotropic dry etching. Figure 4 As shown in FIG. 5 ( a ), the field insulating film 70 on the mesa portion 10A and the field plate electrode 50 is also removed.

[0039] like Figure 4 As shown in FIG. 5 ( a ), the field insulating film 70 in contact with the side surface and the lower end of the field plate electrode 50 remains in the trench T.

[0040] In addition, Figure 3 After the step (a), the field insulating film 70 on the upper sidewall 10B and the field insulating film 70 on the mesa portion 10A may be removed without oxidizing the upper portion of the field plate electrode 50 .

[0041] When the field insulating film 70 on the upper sidewall 10B and the field insulating film 70 on the mesa portion 10A are removed after oxidizing the upper portion of the field plate electrode 50 , the depth of the recessed portion 110 can be reduced.

[0042] After removing the field insulating film 70 on the upper sidewall 10B, the mesa portion 10A and the field plate electrode 50, Figure 4 As shown in (b), the upper sidewall 10B is thermally oxidized to form a third silicon oxide film 81 on the upper sidewall 10B. The upper portion of the field plate electrode 50 is also thermally oxidized to form the first silicon oxide film 61 on the field plate electrode 50. The upper surface of the mesa portion 10A is also thermally oxidized to form the third silicon oxide film 81 on the mesa portion 10A.

[0043] After the third silicon oxide film 81 is formed, Figure 5As shown in (a), a silicon nitride film 62 is formed, for example, by CVD. The silicon nitride film 62 is continuously formed on the inner surface of the recessed portion 110, including the upper surface of the first silicon oxide film 61 on the field plate electrode 50, the third silicon oxide film 81 on the mesa portion 10A, the third silicon oxide film 81 on the upper sidewall 10B, and both side surfaces in the first direction X of the first silicon oxide film 61.

[0044] After the silicon nitride film 62 is formed, as shown in FIG. Figure 5 As shown in FIG. 5( b ), a second silicon oxide film 63 is formed in the trench T and on the mesa portion 10A by chemical vapor deposition. For example, the second silicon oxide film 63 is formed by HDP-CVD (High Density Plasma Chemical Vapor Deposition) using high-density plasma.

[0045] The second silicon oxide film 63 is formed on the silicon nitride film 62 on the first silicon oxide film 61 , in the recess 110 , on the silicon nitride film 62 on the upper sidewall 10B, and on the silicon nitride film 62 on the mesa portion 10A.

[0046] By forming the second silicon oxide film 63 by chemical vapor deposition, the thickness of the second silicon oxide film 63 formed on the upper sidewall 10B of the mesa portion 10A (the thickness in the first direction X) can be made thinner than the thickness of the second silicon oxide film 63 formed on the field plate electrode 50 (the thickness in the third direction Z) and the thickness of the second silicon oxide film 63 formed on the upper surface of the mesa portion 10A (the thickness in the third direction Z). In other words, the thickness of the second silicon oxide film 63 formed on the sidewall within the trench T can be suppressed, while the thickness of the second silicon oxide film 63 formed on the field plate electrode 50 can be increased.

[0047] During the formation of the second silicon oxide film 63, the portion of the second silicon oxide film 63 deposited on the mesa portion 10A close to the opening of the trench T is easily etched, and the film thickness of the second silicon oxide film 63 deposited on the mesa portion 10A (the film thickness in the third direction Z) becomes the thickest near the center of the mesa portion 10A in the first direction X.

[0048] After the second silicon oxide film 63 is formed, the second silicon oxide film 63 on the mesa portion 10A is removed by chemical mechanical polishing (CMP). Figure 6As shown in (a), the silicon nitride film 62 on the mesa portion 10A is exposed. The silicon nitride film 62 formed on the mesa portion 10A functions as a stopper when the second silicon oxide film 63 on the mesa portion 10A is removed by CMP. When the silicon nitride film 62 on the mesa portion 10A is exposed, the CMP of the second silicon oxide film 63 is stopped. Since the silicon nitride film 62, which serves as a CMP stopper, is not formed at the bottom of the trench T, charge trapping at the bottom of the trench T can be suppressed.

[0049] After the second silicon oxide film 63 on the mesa portion 10A is removed by CMP, the second silicon oxide film 63 remaining on the silicon nitride film 62 on the upper sidewall 10B is removed by, for example, wet etching or isotropic dry etching. Figure 6 As shown in (a), the silicon nitride film 62 of the upper sidewall 10B is exposed. By forming the second silicon oxide film 63 so that the film thickness of the second silicon oxide film 63 on the field plate electrode 50 is thicker than the film thickness of the second silicon oxide film 63 on the upper sidewall 10B, the second silicon oxide film 63 on the upper sidewall 10B can be removed while the second silicon oxide film 63 on the field plate electrode 50 remains.

[0050] After removing the second silicon oxide film 63 on the mesa portion 10A and the second silicon oxide film 63 on the upper sidewall 10B, the silicon nitride film 62 exposed in the mesa portion 10A and the silicon nitride film 62 exposed in the upper sidewall 10B are removed. The silicon nitride film 62 is removed by a method that makes the etching rate of the silicon nitride film 62 higher than the etching rate of the silicon oxide film. For example, the silicon nitride film 62 can be removed by wet etching using hot phosphoric acid or isotropic dry etching.

[0051] The first silicon oxide film 61 on the field plate electrode 50 , the silicon nitride film 62 on the first silicon oxide film 61 , the second silicon oxide film 63 on the silicon nitride film 62 , the silicon nitride film 62 in the recess 110 , and the second silicon oxide film 63 in the recess 110 remain.

[0052] By removing the silicon nitride film 62 on the mesa portion 10A and the silicon nitride film 62 on the upper sidewall 10B, Figure 6 As shown in (b), the third silicon oxide film 81 on the mesa portion 10A and the third silicon oxide film 81 on the upper sidewall 10B are exposed.

[0053] For example, an additional silicon oxide film is formed on the third silicon oxide film 81 of the upper side wall 10B by CVD. Figure 7 As shown in (a), a gate insulating film 80 is formed on the upper sidewall 10B. In this case, the gate insulating film 80 includes a third silicon oxide film 81 formed by thermal oxidation and a silicon oxide film formed by CVD. In addition, the silicon oxide film formed by CVD is also formed on the second silicon oxide film 63.

[0054] Alternatively, the third silicon oxide film 81 remaining on the upper side wall 10B may be used as the gate insulating film 80 . In this case, the gate insulating film 80 is a single-layer film of the third silicon oxide film 81 .

[0055] Alternatively, after the third silicon oxide film 81 remaining on the upper side wall 10B is removed by etching, the gate insulating film 80 may be formed on the upper side wall 10B by thermal oxidation.

[0056] After the gate insulating film 80 is formed, as shown in FIG. Figure 7 As shown in FIG. 5 ( b ), the gate electrode 40 is formed on the second silicon oxide film 63 in the trench T.

[0057] For example, a gate electrode material is embedded in the trench T by CVD. The gate electrode material is also deposited on the mesa portion 10A. The upper surface of the gate electrode material in the trench T is retreated by isotropic or anisotropic etching. The gate electrode material formed on the mesa portion 10A is also removed. Figure 7 As shown in FIG. 5 ( b ), the gate electrode 40 remains on the second silicon oxide film 63 in the trench T.

[0058] As the material for the gate electrode 40, for example, polycrystalline silicon or amorphous silicon doped with phosphorus or boron can be used. For example, phosphorus or boron can be doped when the polycrystalline silicon is formed in the trench T. Alternatively, phosphorus or boron can be implanted into the polycrystalline silicon by ion implantation after the polycrystalline silicon is formed in the trench T. Alternatively, phosphorus can be diffused into the polycrystalline silicon by a high-temperature heat treatment containing POCl3. Metal can be used as the material for the gate electrode 40.

[0059] After the gate electrode 40 is formed, the second semiconductor layer 12 and the third semiconductor layer 13 are formed on the semiconductor layer 10 by, for example, ion implantation. Subsequently, the second insulating layer 90 and the second electrode 32 are formed.

[0060] While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention and within the scope of the invention set forth in the claims and their equivalents.

[0061] Description of Reference Numerals

[0062] 1…Semiconductor device, 10…Semiconductor layer, 10A…Mesa portion, 10B…Upper sidewall, 11…First semiconductor layer, 12…Second semiconductor layer, 13…Third semiconductor layer, 14…Fourth semiconductor layer, 20…Trench structure, 31…First electrode, 32…Second electrode, 40…Gate electrode, 50…Field plate electrode, 60…First insulating layer, 61…First silicon oxide film, 62…Silicon nitride film, 63…Second silicon oxide film, 70…Field insulating film, 80…Gate insulating film, 81…Third silicon oxide film, 90…Second insulating layer, 110…Recess, T…Trench

Claims

1. A method for manufacturing a semiconductor device, wherein: The process is as follows: forming a trench and a mesa portion adjacent to the trench in the semiconductor layer; forming a field plate electrode in the trench via a field insulating film; forming a silicon nitride film on the field plate electrode, on the mesa portion, and on an upper sidewall of the mesa portion adjacent to the trench above the field plate electrode; After forming the silicon nitride film, forming a silicon oxide film in the trench and on the mesa portion by chemical vapor deposition; removing the silicon oxide film on the mesa portion by chemical mechanical polishing to expose the silicon nitride film on the mesa portion; After removing the silicon oxide film on the mesa portion, removing the silicon nitride film on the upper sidewall of the mesa portion and the silicon nitride film on the mesa portion; as well as After the silicon nitride film is removed, a gate electrode is formed on the silicon oxide film in the trench.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: In the step of forming the silicon oxide film, a film thickness of the silicon oxide film formed on the upper sidewall of the mesa portion is thinner than a film thickness of the silicon oxide film formed on the field plate electrode.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The method further includes oxidizing an upper portion of the field plate electrode before forming the silicon nitride film.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The method further includes removing the field insulating film formed on the upper sidewall of the mesa portion before forming the silicon nitride film.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The method further includes the step of oxidizing the upper sidewall after removing the field insulating film on the upper sidewall and before forming the silicon nitride film.

6. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The method further includes removing the silicon oxide film formed on the silicon nitride film on the upper side wall before removing the silicon nitride film on the upper side wall.

7. A semiconductor device, wherein: have: a mesa portion comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer and having a higher first conductivity type impurity concentration than the first semiconductor layer; as well as a trench structure portion, adjacent to the mesa portion, comprising a gate electrode, a gate insulating film provided between the gate electrode and the second semiconductor layer, a field plate electrode located below the gate electrode, an insulating layer provided between the field plate electrode and the gate electrode, and a field insulating film provided between the field plate electrode and the first semiconductor layer; The insulating layer includes a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. The first silicon oxide film is provided between the field plate electrode and the silicon nitride film. The silicon nitride film is provided between the first silicon oxide film and the second silicon oxide film. The second silicon oxide film is provided between the silicon nitride film and the gate electrode. The thickness of the silicon nitride film is thinner than the thickness of the second silicon oxide film. The field insulating film does not include silicon nitride.

8. The semiconductor device according to claim 7, wherein The thickness of the silicon nitride film is thinner than the thickness of the first silicon oxide film.

9. The semiconductor device according to claim 7 or 8, wherein The silicon nitride film has a concave portion outside a portion on the first silicon oxide film.

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