Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors, and the manufacturing method comprises the steps: providing a substrate which is internally provided with a well region; forming a photoresist pattern on the well region as a mask, and injecting ions into the well region to form a pair of first lightly doped regions with the well region as an interval; forming a gate structure on the substrate between the pair of first lightly doped regions; injecting ions into the first lightly doped regions by taking the gate structure as a mask to form a pair of second lightly doped regions by taking the well region as an interval, and enabling the orthographic projection of the gate structure on the surface of the substrate to partially coincide with the second lightly doped regions; forming a side wall structure on the side wall of the gate structure; and injecting ions into the second lightly doped region by taking the side wall structure and the gate structure as masks to form a source region and a drain region. According to the semiconductor device and the manufacturing method thereof provided by the invention, device performance reduction caused by light doping offset can be avoided, gate-induced drain leakage current is reduced, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] As the integration density of semiconductor devices continues to increase, the characteristic size of transistors gradually decreases, and the length of the transistor channel also gradually decreases. Semiconductor devices are prone to short channel effect (Shot Channel Effect) and hot carrier injection (HCI) effect. The short channel effect and hot carrier injection effect will cause the transistor to turn on prematurely.

[0003] To prevent transistor performance degradation caused by hot carrier injection, the current method is to form a lightly doped drain (LDD) region before forming the source and drain to mitigate the electric field between the channel and drain regions. However, during the formation of the LDD, the injected ions easily penetrate the gate structure and enter the channel region. Forming the LDD before the gate structure can cause the LDD and gate structure to shift, resulting in a shift in electrical performance. Summary of the Invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same. The semiconductor device and the method for manufacturing the same provided by the present invention can avoid the degradation of device performance due to light doping offset, reduce gate induced drain leakage current, improve the energy efficiency, stability and reliability of the semiconductor device, extend the service life of the semiconductor device, and reduce maintenance costs.

[0005] To solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: Providing a substrate, wherein a well region is formed in the substrate; forming a photoresist pattern on the well region; Using the photoresist pattern as a mask, ions are implanted into the well region to form a pair of first lightly doped regions separated by the well region; forming a gate structure on the substrate between a pair of the first lightly doped regions; Using the gate structure as a mask, ions are implanted into the first lightly doped region to form a pair of second lightly doped regions separated by the well region, wherein the orthographic projection of the gate structure on the substrate surface partially overlaps with the second lightly doped region, with a set overlap dimension; forming a sidewall structure on a sidewall of the gate structure; Using the sidewall structure and the gate structure as masks, ions are implanted into the second lightly doped region to form a source region and a drain region.

[0006] In one embodiment of the present invention, the manufacturing method includes: forming an oxide film on the substrate, and forming a photoresist pattern on the oxide film; Performing tilted ion implantation on the well regions on both sides of the photoresist pattern to form a pair of the first lightly doped regions; removing the photoresist pattern, forming a polysilicon film on the oxide film, and forming the gate structure and gate oxide layer through a photolithography process and an etching process; and Using the gate structure as a mask, oblique ion implantation is performed on the first lightly doped regions on both sides of the gate structure to form the second lightly doped regions.

[0007] In one embodiment of the present invention, an implantation angle when forming the second lightly doped region is smaller than an implantation angle when forming the first lightly doped region.

[0008] In one embodiment of the present invention, the mask used in the photolithography process is the same as the mask used to form the photoresist pattern.

[0009] In one embodiment of the present invention, the source region and the drain region are formed by vertical ion implantation, and the depths of the source region and the drain region are greater than the depth of the first lightly doped region.

[0010] In one embodiment of the present invention, the depth of the first lightly doped region is greater than the thickness of the gate structure, and the depth of the second lightly doped region is less than the thickness of the gate structure.

[0011] In one embodiment of the present invention, the orthographic projection of the gate structure on the substrate surface partially overlaps with the second lightly doped regions on both sides, and the overlapping dimensions of the two second lightly doped regions and the gate structure are equal.

[0012] In one embodiment of the present invention, a distance separating the well regions between a pair of the first lightly doped regions is smaller than a distance separating the well regions between a pair of the second lightly doped regions.

[0013] The present invention further provides a semiconductor device, comprising at least: a substrate, wherein a well region is provided in the substrate; a pair of first lightly doped regions, spaced apart and arranged in the well region; a gate structure, disposed on the substrate between adjacent first lightly doped regions; a pair of second lightly doped regions, spaced apart and disposed in the first lightly doped region on both sides of the gate structure; Sidewall structures are provided on both sides of the gate structure; and The source region and the drain region are respectively arranged in the second lightly doped region on both sides of the gate structure.

[0014] In an embodiment of the present invention, the gate structure at least covers a portion of the first lightly doped region on one side.

[0015] In summary, the present invention provides a semiconductor device and a method for manufacturing the same. By improving the semiconductor device and the method for manufacturing the same, the unexpected technical effect of the present application is that it can compensate for the problem of lightly doped regions and gate structure offset caused by the first formation of lightly doped regions, thereby improving the performance of the semiconductor device. It can effectively reduce the electric field near the source and drain, thereby reducing the probability of high-energy carriers being generated in the source and drain regions, reducing the risk of hot carrier effects, helping to reduce leakage current near the source and drain, and improving the performance and reliability of the device. It can avoid the degradation of device performance caused by lightly doped offset, reduce gate-induced drain leakage current, improve the energy efficiency, stability and reliability of semiconductor devices, extend the service life of semiconductor devices, and reduce maintenance costs. The second lightly doped region can reduce the electrical characteristic offset caused by misalignment when the gate structure and the first lightly doped region are misaligned, and the doped ions in the lightly doped region will not penetrate the gate structure into the channel region, thereby improving the conductivity, threshold voltage, stability and reliability of the semiconductor device.

[0016] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0019] Figure 2 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[0020] Figure 3 FIG. 1 is a schematic diagram of forming a well region in a substrate according to an embodiment of the present invention.

[0021] Figure 4 FIG. 4 is a schematic diagram of forming a first lightly doped region in one embodiment of the present invention.

[0022] Figure 5 FIG. 1 is a schematic diagram of forming a gate structure according to an embodiment of the present invention.

[0023] Figure 6 FIG. 4 is a schematic diagram of forming a second lightly doped region in one embodiment of the present invention.

[0024] Figure 7 FIG. 1 is a schematic diagram of forming a source region and a drain region in one embodiment of the present invention.

[0025] Figure 8 Schematic diagram of the relationship between the position offset and the turn-off current ratio in Example 1 and Comparative Example 1.

[0026] Figure 9 Schematic diagram of the simulation results of the inter-band channel current intensity distribution in Example 1 and Comparative Example 1.

[0027] Figure 10 Schematic diagram of the intensity of the inter-band channel current in Example 1 and Comparative Example 1.

[0028] Figure 11 Schematic diagram of the concentration ratio of the lightly doped region in the embodiment and the comparative example. DETAILED DESCRIPTION

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0031] In the description of this specification, it should be understood that the directions or positional relationships indicated by terms such as "center," "upper," "lower," "front," "back," "left," and "right" are based on the directions or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this solution and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific direction, be constructed, or operate in a specific direction. Therefore, they should not be construed as limitations on this solution. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0032] See also Figure 1 As shown, Figure 1This is a schematic cross-sectional view of a semiconductor device 11 according to an embodiment of the present invention. Semiconductor device 11 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), or a medium-voltage MOS transistor. Semiconductor device 11 is, for example, used in a display driver IC platform and operates at a voltage of 6V to 8V. In this embodiment, semiconductor device 11 is described using an n-channel MOS transistor (NMOS) as an example.

[0033] See also Figure 1 As shown, in one embodiment of the present invention, the semiconductor device 11 is, for example, disposed in a well region 14 of a substrate 12 , wherein the substrate 12 is, for example, a silicon wafer, and the well region 14 is, for example, a doped region doped with p-type impurities such as boron (B).

[0034] See also Figure 1 As shown, in one embodiment of the present invention, a shallow trench isolation (STI) structure 13 is provided between adjacent components for insulation between adjacent components, and the material of the shallow trench isolation structure 13 is, for example, silicon oxide. The source region 21, the drain region 22, the first lightly doped regions 23a and 23b, the second lightly doped regions 24a and 24b, and the gate oxide layer 16 are surrounded by the shallow trench isolation structure 13.

[0035] See also Figure 1 As shown, in one embodiment of the present invention, a gate oxide layer 16 and a gate structure 15 are formed on the surface of the well region 14. The gate structure 15 is formed on the gate oxide layer 16. The material of the gate structure 15 is, for example, polysilicon. The polysilicon is doped with n-type impurities such as phosphorus (P) or arsenic (As). In other embodiments, the gate structure 15 may also be a metal layer, a metal silicide layer, a stack of a polysilicon layer and a metal layer, or a stack of a polysilicon layer and a metal silicide layer.

[0036] See also Figure 1 As shown, in one embodiment of the present invention, the gate oxide layer 16 is made of, for example, silicon oxide. Side wall spacers 17 are provided on the sides of the gate structure 15 and the gate oxide layer 16 , and the side wall spacers 17 are, for example, silicon oxide or silicon nitride films, or a stack of layers.

[0037] See also Figure 1As shown, in one embodiment of the present invention, a channel region 18 is formed on the surface of the well region 14. The channel region 18 is located below the gate structure 15. The channel region 18 is doped with p-type impurities, such as boron, to adjust the threshold voltage of the semiconductor device 11. The channel region 18 is separated from the gate structure 15 by a gate oxide layer 16. A source region 21 and a drain region 22 are spaced apart on both sides of the channel region 18. The source region 21 and the drain region 22 are doped with n-type impurities, such as phosphorus or arsenic.

[0038] See also Figure 1 As shown, in one embodiment of the present invention, a pair of first lightly doped regions, denoted as 23a and 23b, are spaced apart on either side of the channel region 18. The first lightly doped region 23a is connected to the source region 21, and the first lightly doped region 23b is connected to the drain region 22. The doping type of the first lightly doped regions 23a and 23b is, for example, n-type, and the impurities are, for example, phosphorus. The first lightly doped regions 23a and 23b extend from the surface of the well region 14 into the well region, and extend from the surface of the well region 14 to the junction position with the well region 14. The first lightly doped regions 23a and 23b form a PN junction with the well region 14, and the vertical distance in the depth direction is defined as the depth of the first lightly doped region. The thickness of the gate structure 15 is denoted as Tg, and the depth of the first lightly doped region in the well region 14 is denoted as Df, where Df>Tg.

[0039] See also Figure 1As shown, in one embodiment of the present invention, a pair of second lightly doped regions, denoted as 24a and 24b, are spaced apart on both sides of the channel region 18. The second lightly doped region 24a is connected to the source region 21, and the second lightly doped region 24b is connected to the drain region 22. The positions of each second lightly doped region 24a and 24b are determined by a set overlap dimension OL, wherein the set overlap dimension OL is the dimension of overlap between the orthographic projection of the gate structure 15 on the surface of the substrate 12 and the second lightly doped regions 24a and 24b on both sides. In this embodiment, the overlap dimension OL is set to be equal at the two second lightly doped regions 24a and 24b. Since the second lightly doped regions 24a and 24b are formed relative to the gate structure 15 by self-alignment, the overlap dimension OL between the second lightly doped region 24a and the gate structure 15 is equal to the overlap dimension OL between the second lightly doped region 24b and the gate structure 15. The second lightly doped regions 24a and 24b are connected to the corresponding first lightly doped regions 23a and 23b. The doping type of the second lightly doped regions 24a and 24b is, for example, n-type, and the impurities are, for example, phosphorus. The second lightly doped regions 24a and 24b extend from the surface of the well region 14 into the well region, and the vertical distance in the depth direction is defined as the depth of the second lightly doped regions until the extension stops. A PN junction is formed between the second lightly doped regions 24a and 24b and the well region 14. The depth of the second lightly doped regions in the well region 14 is denoted as Ds, and Ds is <Tg。

[0040] See also Figure 1 As shown, in one embodiment of the present invention, before forming the gate structure 15, a pair of first lightly doped regions 23a and 23b are first formed, and the overlap between the first lightly doped regions 23a and 23b and the gate structure 15 is greater than the overlap dimension OL. In other words, the distance separating the well region 14 between the pair of first lightly doped regions 23a and 23b is smaller than the distance separating the well region 14 between the pair of second lightly doped regions 24a and 24b. That is, the distance between the first lightly doped region 23a and the first lightly doped region 23b is smaller than the distance between the second lightly doped region 24a and the second lightly doped region 24b. By increasing the overlap between the first lightly doped regions 23a, 23b and the gate structure 15, and setting the depth of the first lightly doped regions 23a, 23b to be greater than the thickness of the gate structure 15, the electric field between the source region 21, the drain region 22 and the channel region 18 can be fully mitigated, thereby reducing the probability of high-energy carriers being generated in the source / drain regions, reducing the risk of hot carrier effects, helping to reduce the leakage current near the source and drain, and improving the performance and reliability of the device.

[0041] See also Figure 1As shown, in one embodiment of the present invention, the depths of the source region 21 and the drain region 22 are greater than the depth Df of the first lightly doped regions 23a and 23b, and the depth Df of the first lightly doped regions 23a and 23b is greater than the depth Ds of the second lightly doped regions 24a and 24b.

[0042] See also Figure 2 As shown, in another embodiment of the present invention, in the semiconductor device 11, due to the misalignment between the photolithography process for forming the first lightly doped regions 23a and 23b and the photolithography process for forming the gate structure 15, the position of the gate structure 15 is shifted relative to the position of the first lightly doped regions 23a and 23b, i.e., the gate structure 15 covers at least a portion of the first lightly doped region on one side. In this case, in the semiconductor device 11, the relative positional relationship between the gate structure 15 and the two second lightly doped regions 24a and 24b, the source region 21, and the drain region 22 remains constant. Therefore, the overlap dimension OL between the second lightly doped region 24a and the gate structure 15 is equal to the overlap dimension OL between the second lightly doped region 24b and the gate structure 15. Since the source region 21 and the drain region 22 are self-aligned after the gate structure 15 and the spacer 17 are formed, the distance between the source region 21 and the adjacent side surface of the gate structure 15 is equal to the distance between the drain region 22 and the adjacent side surface of the gate structure 15.

[0043] See also Figures 1 to 2 As shown, in one embodiment of the present invention, by setting the depth Df of the first lightly doped regions 23a and 23b to be greater than the film thickness Tg of the gate structure 15, and by providing a large overlap between the first lightly doped regions 23a and 23b and the gate structure 15, the electric field between the drain region 22 and the channel region 18 can be sufficiently mitigated. However, when the position of the gate structure 15 is shifted relative to the position of the first lightly doped regions 23a and 23b, if the first lightly doped region 23b on the drain region 22 side does not overlap with the gate structure 15, or if the overlap is small, the ion concentration of the lightly doped region in the gate-drain overlap region is significantly reduced, that is, the doping concentration in the region where gate-induced drain leakage (GIDL) is generated is low. Therefore, the electric field between the drain region 22 and the channel region 18 cannot be fully mitigated.

[0044] See also Figure 2As shown, in another embodiment of the present invention, by determining a predetermined overlap dimension OL, the second lightly doped regions 24a and 24b are formed to overlap with the gate structure 15. The second lightly doped regions 24a and 24b are formed directly below the boundary between the gate structure 15 and the spacer structure 17 and are located on the surface of the well region 14. The second lightly doped regions 24a and 24b can serve as GIDL generation regions to suppress GIDL. Even if the depth Ds of the second lightly doped regions 24a and 24b is less than the film thickness Tg of the gate structure 15, the electric field in the GIDL generation region can be mitigated. Because the depth Ds of the second lightly doped regions 24a and 24b is less than the film thickness Tg of the gate structure 15, when ions are self-alignedly implanted to form the second lightly doped regions 24a and 24b after the gate structure 15 is formed, the implanted ions will not penetrate the gate structure 15. That is, the implanted n-type impurities will not invade the channel region 18 between the source region 21 and the drain region 22, and will not affect the threshold voltage and other characteristics of the semiconductor device 11. This is because the ions implanted during the formation of the second lightly doped regions 24a and 24b did not enter the channel region 18, and the first lightly doped regions 23a and 23b were formed before the gate structure 15 was formed. Therefore, the channel region 18 does not contain the ions contained in the first lightly doped regions 23a and 23b. Therefore, the channel region 18 does not contain the ions that form the lightly doped regions.

[0045] See also Figures 3 to 7 As shown in FIG. 1 , in one embodiment of the present invention, a method for manufacturing a semiconductor device 11 is described. Figure 3 As shown, the substrate 12 is, for example, a p-type silicon wafer, and a shallow trench isolation structure 13 is formed in the substrate 12. P-type ions such as boron (B) are implanted into the substrate 12 and annealed to form a well region 14.

[0046] See also Figure 1 、 Figure 4As shown, in one embodiment of the present invention, first lightly doped regions 23a and 23b are formed in the substrate 12 before forming the gate structure 15. Specifically, an oxide film 32 is formed on the substrate 12 having the shallow trench isolation structure 13 and the well region 14. In subsequent processes, the oxide film 32 forms, for example, the gate oxide layer 16. The thickness of the oxide film 32 is, for example, 18 nm. A photoresist is coated on the oxide film 32 and patterned. A photoresist pattern 31 covering a portion of the well region 14 is formed on each transistor to form a pair of first lightly doped regions 23a and 23b. When forming the first lightly doped regions 23a and 23b, the photoresist pattern 31 is used as a mask to perform tilted ion implantation of n-type ions, such as phosphorus, wherein the ion implantation angle is α, which is the angle between the implantation direction and the normal of the substrate 12. The range of the implantation angle α is, for example, 40°, and the ion implantation energy is, for example, 50 KeV to 90 KeV, and the ion implantation dose is, for example, 1.0×10 13 atoms / cm 2 ~3.0×10 13 atoms / cm 2 In a specific embodiment of the present invention, when forming the first lightly doped regions 23a and 23b, the ion implantation energy is, for example, 70 KeV, and the ion implantation dose is, for example, 2.0×10 13 atoms / cm 2 By tilting the ion implantation, the first lightly doped regions 23a and 23b can relax the electric field between the drain region 22 and the channel region 18 to be formed later, thereby reducing impact ionization. In order to relax the electric field between the drain region 22 and the channel region 18 and reduce impact ionization, the depth Df of the first lightly doped regions 23a and 23b is, for example, 200nm to 300nm, and the doping concentration is, for example, 1.0×10 18 atoms / cm 3 ~1.0×10 19 atoms / cm 3 The depth Df is greater than the thickness Tg of the gate structure 15 to be formed later. By forming the photoresist pattern 31 , the pair of first lightly doped regions 23 a and 23 b are separated from each other by the well region 14 below the photoresist pattern 31 .

[0047] See also Figures 4 and 5As shown, in one embodiment of the present invention, in the substrate 12, for each transistor, a gate oxide layer 16 and a gate structure 15 are formed on the well region 14 between the first lightly doped regions 23a and 23b. Specifically, after removing the photoresist pattern 31, a high-doping concentration n-type polysilicon film is formed on the oxide film 32, and the film thickness of the polysilicon film is set to be equal to the film thickness of the gate structure 15. The film thickness of the polysilicon film is less than the depth Df of the first lightly doped regions 23a and 23b, and in a specific embodiment, is set to 100nm, for example. The patterning of the gate structure 15 and the gate oxide layer 16 is completed through a photolithography process and an etching process. In one embodiment of the present application, the mask used for patterning the gate structure 15 and the gate oxide layer 16 is, for example, the same as the mask used to form the photoresist pattern 31, so that the overlap between the gate structure 15 and the first lightly doped regions 23a and 23b after the etching process is controlled to be within a predetermined management range. However, due to alignment deviation, the overlap amount between the gate structure 15 and the first lightly doped region 23 a and the overlap amount between the gate structure 15 and the first lightly doped region 23 b may be different.

[0048] See also Figure 6 As shown, in one embodiment of the present invention, second lightly doped regions 24a and 24b are formed in the substrate 12. The second lightly doped regions 24a and 24b correspond to the first lightly doped regions 23a and 23b, respectively. When forming the second lightly doped regions 24a and 24b, the gate structure 15 is used as a mask and n-type ions such as phosphorus and arsenic are self-alignedly implanted by tilted ion implantation. The ion implantation angle is β, which is the angle between the implantation direction and the normal of the substrate 12. The range of the implantation angle β is, for example, smaller than the implantation angle α, and is, for example, 30°. The ion implantation energy is, for example, 10 KeV to 30 KeV, and the ion implantation dose is, for example, 5.0×10 12 atoms / cm 2 ~2.0×10 13 atoms / cm 2 In a specific embodiment of the present invention, when forming the second lightly doped regions 24a and 24b, the ion implantation energy is, for example, 20 KeV, and the ion implantation dose is, for example, 1.0×10 13 atoms / cm 2 The second lightly doped regions 24a and 24b formed by the tilted ion implantation can ensure the ion concentration of the lightly doped regions in the GIDL generation area and alleviate the electric field between the drain region 22 and the channel region 18 formed subsequently. The depth Ds of the second lightly doped regions 24a and 24b is, for example, 40nm to 80nm, and the doping concentration is, for example, 1.0×10 18 atoms / cm 3 ~5×10 18 atoms / cm 3, and the depth Ds is less than the film thickness Tg of the gate structure 15. Therefore, when forming the second lightly doped regions 24a and 24b, the dopant ions in the lightly doped regions will not penetrate the gate structure 15 and enter the channel region. Since the second lightly doped regions 24a and 24b are formed by self-alignment relative to the gate structure 15, the second lightly doped regions 24a and 24b overlap with the gate structure 15 by a predetermined overlap dimension OL.

[0049] See also Figure 7 As shown, in one embodiment of the present invention, a source region 21 and a drain region 22 are formed in the substrate 12. Specifically, after the second lightly doped regions 24a and 24b are formed, an insulating film such as a silicon oxide film (not shown in the figure) is formed on the substrate 12, and the insulating film is etched by anisotropic etching to form a sidewall structure 17 along the side of the gate structure 15 and the gate oxide layer 16. The gate structure 15 and the sidewall structure 17 are used as masks, and n-type ions such as phosphorus and arsenic are self-alignedly implanted by vertical ion implantation to form the source region 21 and the drain region 22. In one specific embodiment of the present invention, the ion implantation energy is, for example, 20 KeV, and the ion implantation dose is, for example, 5.0×10 15 atoms / cm 2 . By simultaneously controlling the implantation energy and the implantation dose, the depths of the source region 21 and the drain region 22 formed are greater than the depth Df of the first lightly doped regions 23a and 23b, and the source region 21 and the drain region 22 are separated by the spacer structure 17 and the channel region 18. The first lightly doped regions 23a, 23b and the second lightly doped regions 24a and 24b are arranged below the spacer structure 17 between the source region 21 and the drain region 22 and the channel region 18. Since the source region 21 and the drain region 22 are self-aligned with respect to the spacer structure 17, they overlap with the spacer structure 17 with a predetermined overlap size. For each transistor, the first lightly doped region 23a and the second lightly doped region 24a are connected to the source region 21, and the first lightly doped region 23b and the second lightly doped region 24b are connected to the drain region 22. By forming a second lightly doped region, device performance degradation caused by lightly doped offset can be avoided, gate-induced drain leakage current can be reduced, the energy efficiency, stability and reliability of semiconductor devices can be improved, the service life of semiconductor devices can be extended, and maintenance costs can be reduced.

[0050] See also Figure 8 As shown, in one embodiment of the present invention, the characteristics of the semiconductor device 11 are verified by simulation. Figure 2 The device shown is used as Example 1, and a device obtained by omitting the second lightly doped regions 24a and 24b is used as Comparative Example 1. Figure 8, the relationship between the position offset of the first lightly doped regions 23a and 23b relative to the gate structure and the off-current ratio (Loff Ratio) of the semiconductor device 11 is shown. The horizontal axis represents the size of the position offset, and the positive side of the horizontal axis represents the offset Sf, which is as follows: Figure 2 In the case where the first lightly doped regions 23a and 23b are shifted toward the drain region 22 relative to the gate structure 15, the offset Sf represented by the negative side is as follows: Figure 2 The first lightly doped regions 23a and 23b are shifted toward the source region 21 relative to the gate structure 15. The vertical axis represents the off-current ratio of the semiconductor device 11. The off-current ratio is a value normalized by setting the current value when the position shift Sf is zero to 1.

[0051] See also Figure 8 As shown, when the first lightly doped regions 23a and 23b are offset toward the drain region 22 relative to the gate structure 15, the turn-off current ratio increases. However, compared with Comparative Example 1, the turn-off current ratio of Example 1 is less affected by the offset. When the offset Sf is 0.08 μm, the turn-off current ratio of Example 1 is suppressed to about 1 / 10 of the turn-off current ratio of Comparative Example 1. It can be considered that in Comparative Example 1, the overlap between the first lightly doped region 23b and the gate structure 15 is small, and the turn-off current ratio increases due to the electric field between the drain region 22 and the channel region 18. In contrast, in this Example 1, the electric field between the drain region 22 and the channel region 18 is relaxed by the second lightly doped region 24b, thereby reducing the turn-off current ratio.

[0052] See also Figure 9 The figure shows the simulation results of the channel current intensity distribution between bands. Figure 10 As shown in FIG. 1 , a graph showing the intensity of the band-to-band channel current is shown. The band-to-band channel current may cause GIDL. In Example 1 and Comparative Example 1, the position offset Sf is set to 0.08 μm. Figure 9 As shown in the figure, compared with the comparative example 1, the generation area of ​​the inter-band channel current in the embodiment 1 (the lighter gray range) is significantly reduced, and the number of carriers generated per unit time (carriers / cm 3 / s) is reduced, so the generated inter-band channel current is reduced. Figure 10 As shown, compared with Comparative Example 1, the intensity of the inter-band channel current of Example 1 is also reduced.

[0053] See also Figure 11As shown, the simulation results of the LDD ion concentration of the first lightly doped region 23a (23b), the second lightly doped region 24a (24b), and the source region 21 (or the drain region 22) on the surface of the well region 14 are shown. Including Example 1, Example 2, Comparative Example 1 and Comparative Example 2, wherein Example 1 is a case where the offset Sf in the present application is positionally shifted in the direction of reducing the overlap size OL, Example 2 is a case where the offset Sf in the present application is 0, Comparative Example 1 is a case where the offset Sf is positionally shifted in the direction of reducing the overlap size OL when the second lightly doped region 24a (24b) is not provided, and Comparative Example 2 is a case where the offset Sf is 0 when the second lightly doped region 24a (24b) is not provided, showing the LDD concentration of the surface of the well region 14 relative to the lateral position, and the LDD concentration ratio represents the value normalized by setting the ion concentration of the source region 21 (or the drain region 22) to 1. As shown Figure 11 As shown, the LDD concentration ratio gradually decreases from the source region 21 (or drain region 22) toward the gate structure 15. Since the second lightly doped region 24a (24b) is omitted in the comparative example, the LDD concentration is relatively low compared to the embodiment. In particular, in the case of misalignment in Comparative Example 1, the LDD concentration ratio is significantly reduced compared to the case without misalignment (Comparative Example 2). In the present application, in Example 1, even in the case of misalignment, the change in the LDD concentration ratio is suppressed. The area on the surface of the well region 14 immediately below the boundary between the gate structure 15 and the sidewall structure 17 is the GIDL generation region. In order to suppress GIDL, the LDD concentration needs to be increased. However, in the present application, whether there is a misalignment or not, the LDD concentration in the GIDL generation region is maintained at a high level of more than 1 / 3 of the ion concentration of the source region 21 (or the drain region 22), so that the effect of the second lightly doped region 24a (24b) can be confirmed, and when misalignment occurs between the gate structure and the first lightly doped region, the electrical characteristic deviation caused by the misalignment can be reduced, thereby improving the conductivity, threshold voltage, stability and reliability of the semiconductor device.

[0054] In summary, the present invention provides a semiconductor device and a method for manufacturing the same. By improving the semiconductor device and the method for manufacturing the same, the unexpected technical effect of the present application is that it can compensate for the problem of lightly doped regions and gate structure offset caused by the first formation of lightly doped regions, thereby improving the performance of the semiconductor device. It can effectively reduce the electric field near the source and drain, thereby reducing the probability of high-energy carriers being generated in the source and drain regions, reducing the risk of hot carrier effects, helping to reduce leakage current near the source and drain, and improving the performance and reliability of the device. It can avoid the degradation of device performance caused by lightly doped offset, reduce gate-induced drain leakage current, improve the energy efficiency, stability and reliability of semiconductor devices, extend the service life of semiconductor devices, and reduce maintenance costs. The second lightly doped region can reduce the electrical characteristic offset caused by misalignment when the gate structure and the first lightly doped region are misaligned, and the doped ions in the lightly doped region will not penetrate the gate structure into the channel region, thereby improving the conductivity, threshold voltage, stability and reliability of the semiconductor device.

[0055] The above description of the illustrated embodiments of the present invention (including that described in the Abstract) is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. Although specific embodiments of the present invention and examples of the present invention are described herein for illustrative purposes only, as those skilled in the art will recognize and appreciate, various equivalent modifications are possible within the spirit and scope of the present invention. As noted, modifications may be made to the present invention in light of the above description of the illustrated embodiments of the present invention, and such modifications will be within the spirit and scope of the present invention.

[0056] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, such as the technical solutions formed by replacing the above features with (but not limited to) technical features with similar functions disclosed in this application. In addition to the technical features described in the specification, the remaining technical features are known technologies to those skilled in the art. In order to highlight the innovative features of the present invention, the remaining technical features will not be repeated here.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, wherein a well region is formed in the substrate; forming a photoresist pattern on the well region; Using the photoresist pattern as a mask, ions are implanted into the well region to form a pair of first lightly doped regions separated by the well region; forming a gate structure on the substrate between a pair of the first lightly doped regions; Using the gate structure as a mask, ions are implanted into the first lightly doped region to form a pair of second lightly doped regions separated by the well region, wherein the orthographic projection of the gate structure on the substrate surface partially overlaps with the second lightly doped region, with a set overlap dimension; forming a sidewall structure on a sidewall of the gate structure; Using the sidewall structure and the gate structure as masks, ions are implanted into the second lightly doped region to form a source region and a drain region.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The production method comprises: forming an oxide film on the substrate, and forming a photoresist pattern on the oxide film; Performing tilted ion implantation on the well regions on both sides of the photoresist pattern to form a pair of the first lightly doped regions; removing the photoresist pattern, forming a polysilicon film on the oxide film, and forming the gate structure and gate oxide layer through a photolithography process and an etching process; and Using the gate structure as a mask, oblique ion implantation is performed on the first lightly doped regions on both sides of the gate structure to form the second lightly doped regions.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: An implantation angle when forming the second lightly doped region is smaller than an implantation angle when forming the first lightly doped region.

4. The method for manufacturing a semiconductor device according to claim 2, wherein: The mask used in the photolithography process is the same as the mask used to form the photoresist pattern.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The source region and the drain region are formed by vertical ion implantation, and the depths of the source region and the drain region are greater than the depth of the first lightly doped region.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The depth of the first lightly doped region is greater than the thickness of the gate structure, and the depth of the second lightly doped region is less than the thickness of the gate structure.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The orthographic projection of the gate structure on the substrate surface partially overlaps with the second lightly doped regions on both sides, and the overlapping dimensions of the two second lightly doped regions and the gate structure are equal.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: A distance separating the well regions between a pair of the first lightly doped regions is smaller than a distance separating the well regions between a pair of the second lightly doped regions.

9. A semiconductor device, characterized in that: At least: a substrate, wherein a well region is provided in the substrate; a pair of first lightly doped regions, spaced apart and arranged in the well region; a gate structure, disposed on the substrate between adjacent first lightly doped regions; a pair of second lightly doped regions, spaced apart and disposed in the first lightly doped region on both sides of the gate structure; Sidewall structures are provided on both sides of the gate structure; as well as The source region and the drain region are respectively arranged in the second lightly doped region on both sides of the gate structure.

10. The semiconductor device according to claim 9, wherein The gate structure at least covers a portion of the first lightly doped region on one side.

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