Gate all-around field effect transistor

Abstract

A gate-all-around field effect transistor (GAAFET) includes a substrate, a source electrode structure, a drain electrode structure, at least one channel, and a gate electrode structure. The gate electrode structure includes at least one gate electrode and at least one gate electrode. The source electrode structure and the drain electrode structure are arranged on the substrate. Each of the at least one channel extends between the source structure and the drain structure. The gate structure is disposed between the source structure and the drain structure and surrounds the at least one channel. When the GAAFET is operated in a saturated state, each of the at least one channel includes a first region, a second region, and a first electrical junction between the first region and the second region. The first region is adjacent to the drain structure, and the second region is adjacent to the first region.

Description

Technical Field

[0001] The present disclosure relates to a gate-all-around field-effect transistor (GAAFET), and more particularly to a highly reliable GAAFET.

[0002] Prior Art

[0003] A gate-all-around field-effect transistor (GAAFET) is a type of transistor developed as a potential replacement for FinFET transistors in semiconductor technology. As the name suggests, the gate of a GAAFET surrounds the channel on all four sides, allowing for a larger contact area between the gate and the channel, thereby enhancing the gate's control over current.

[0004] Although GAAFET has been regarded as an advanced FET that can provide better performance in a smaller base area, GAAFET also faces some challenges caused by the continuous shrinking of technology. For example, due to the reduction in channel length, GAAFET may be affected by short channel effects. In addition, the junction breakdown voltage of GAAFET may be quite low, making it difficult to use in high voltage applications, such as one-time programming (OTP) memory applications where high voltage operation is required for programming. Therefore, how to develop more reliable GAAFET for application in a wider range of fields has become an urgent problem to be solved.

[0005] This prior art section provides background information only. The statements in this prior art section are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this prior art section shall be used as an admission that any part of this application (including this prior art section) constitutes prior art to the present disclosure. Summary of the Invention

[0006] One aspect of the present disclosure provides a gate-all-around field-effect transistor (GAAFET). The GAAFET includes a substrate, a source structure, a drain structure, at least one channel, and a gate structure. The source structure is disposed on the substrate, and the drain structure is disposed on the substrate. Each of the at least one channel extends between the source structure and the drain structure. The gate structure is disposed between the source structure and the drain structure and surrounds the at least one channel. When the GAAFET operates in a saturated state, each of the at least one channel includes a first region, a second region, and a first electrical junction between the first region and the second region. The first region is adjacent to the drain structure, and the second region is adjacent to the first region.

[0007] Because the GAAFET channel has regions with different equivalent carrier densities, it can induce additional junctions within the channel, thereby improving the GAAFET's reliability in resisting short channel effects. In addition, the induced junction also helps to weaken the electric field formed at the drain, thereby helping to increase the GAAFET's breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A more complete understanding of the present disclosure can be obtained by referring to the detailed description and claims in conjunction with the accompanying drawings, in which like reference numerals in different drawings refer to like elements.

[0009] Figure 1 FIG. 1 illustrates a gate-all-around field-effect transistor (GAAFET) according to a comparative embodiment of the present disclosure;

[0010] Figure 2 Draw Figure 1 The source structure, drain structure and charge distribution between the channels of the GAAFET are shown.

[0011] Figure 3 A GAAFET according to an embodiment of the present disclosure is shown;

[0012] Figure 4 An embodiment of the present disclosure is shown. Figure 3 A perspective view of the channel of the GAAFET is shown;

[0013] Figure 5 An embodiment of the present disclosure is shown. Figure 3 Band diagram of different regions of the channel of the GAAFET shown;

[0014] Figure 6 An embodiment of the present disclosure is shown. Figure 3 The source structure, drain structure and charge distribution between the channels of the GAAFET shown;

[0015] Figure 7 A GAAFET according to another embodiment of the present disclosure is shown;

[0016] Figure 8 An embodiment of the present disclosure is shown. Figure 7 The source structure, drain structure and charge distribution between the channels of the GAAFET shown;

[0017] Figure 9 illustrates a channel according to an embodiment of the present disclosure;

[0018] Figure 10 illustrates a channel according to another embodiment of the present disclosure;

[0019] Figure 11illustrates a channel according to another embodiment of the present disclosure;

[0020] Figure 12 illustrates a channel according to another embodiment of the present disclosure;

[0021] Figure 13 illustrates a channel according to another embodiment of the present disclosure;

[0022] Figure 14 A GAAFET according to another embodiment of the present disclosure is shown;

[0023] Figure 15 A GAAFET according to another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0024] Figure 1 A gate all-around field effect transistor (GAAFET) 900 according to a comparative embodiment of the present disclosure is shown. Figure 1 In the embodiment of the present invention, GAAFET 900 includes substrate 910, source structure 920, drain structure 930, channel 940, gate structure 950, spacers 960 and 962, and dielectric layers 970 and 972. GAAFET 900 can be an N-channel metal-oxide silicon (NMOS) transistor. In this case, source structure 920 and drain structure 930 are doped with N-type carriers, while channel 940 is lightly doped with P-type carriers. Gate structure 950 includes dielectric layer 952 and gate layer 954 surrounded by dielectric layer 952.

[0025] Figure 2 FIG. 9 illustrates the charge distribution between the source structure 920, the drain structure 930, and the channel 940 when the GAAFET 900 is operated in saturation. Figure 2 As shown, since a positive voltage is applied to the drain structure, the drain structure 930 and the channel 940 are reverse biased, thereby forming a depletion region DA near the junction JA2. Near the source structure 920, the channel 940 is in reverse mode, so there is no depletion region at the junction JA1. Since the channel length of the GAAFET 900 is quite short, when a high positive voltage is applied to the drain structure 930, the depletion region DA may expand to the source structure. In this case, short channel effects may be triggered, such as drain induced barrier lowering (DIBL) or channel punchthrough. In other words, the GAAFET 900 faces the challenge of short channel effects.

[0026] In addition, if Figure 2 As shown, an electric field EA is formed at junction JA2 by the fixed donor and acceptor. In this case, when the drain structure 930 receives a high voltage and the source structure 920 receives a low voltage (e.g., 0V), the electric field EA at junction JA2 is further enhanced. The strong electric field EA may cause damage to GAAFET 900. In other words, the low breakdown voltage of GAAFET 900 makes it unsuitable for use in one-time programmable (OTP) memory cells, because OTP memory cells are typically programmed using a large voltage difference.

[0027] Figure 3 A GAAFET 100 according to one embodiment of the present disclosure is shown. Compared to the GAAFET 900, the GAAFET 100 may have a higher breakdown voltage and be less susceptible to short channel effects.

[0028] The GAAFET 100 includes a substrate 110, a source structure 120, a drain structure 130, a channel 140, a gate structure 150, spacers 160 and 162, and dielectric layers 170 and 172. The source structure 120 and the drain structure 130 are disposed on the substrate 110, with the dielectric layer 170 disposed between the source structure 120 and the substrate 110, and the dielectric layer 172 disposed between the drain structure 130 and the substrate 110.

[0029] The gate structure 150 includes a dielectric layer 152 and a gate layer 154 surrounded by the dielectric layer 152. The dielectric layer 152 may include silicon oxide, silicon nitride, or a high-K dielectric material. The gate layer 154 may include polysilicon or a metal gate electrode. The gate structure 150 is disposed between the source structure 120 and the drain structure 130, the spacer 160 is disposed between the gate structure 150 and the source structure 120, and the spacer 162 is disposed between the gate structure 150 and the drain structure 130. The channel 140 extends between the source structure 120 and the drain structure 130, and the gate structure 150 surrounds the channel 140. In other words, as Figure 3 As shown, the channel 140 may pass through the gate structure 150 and contact the source structure 120 and the drain structure 130 at its two ends.

[0030] In some embodiments, channel 140 may be formed from nanowires, such as rectangular nanowires or cylindrical nanowires. Furthermore, channel 140 may include region 142A, region 142B, and region 142C. Region 142A is adjacent to source structure 120, region 142C is adjacent to drain structure 130, and region 142B is located between regions 142A and 142C. Figure 4 A perspective view of a channel 140 is shown according to one embodiment of the present disclosure.

[0031] like Figure 4 As shown, the height H1 of the region 142A and the height H3 of the region 142C are greater than the height H2 of the region 142B, wherein the heights H1, H2, and H3 are measured along the stacking direction Z of the gate structure 150 and the channel 140. Figure 3 As shown, regions 142A and 142C are surrounded by spacers 160 and 162 , while region 142B is surrounded by dielectric layer 152 .

[0032] Figure 5 The energy band diagram of regions 142A / 142C and 142B of the channel 140 according to one embodiment of the present disclosure is shown. Generally speaking, the gate structure 150 (such as the gate layer 154) can lower the Fermi level of the channel 140 and thus bend the band of the channel 140. Specifically, around the surface of the channel 140, the top of the valence band (hereinafter referred to as "potential Ev") is raised to be close to the Fermi potential Ef, while the bottom of the conduction band (hereinafter referred to as "potential Ec") is raised to be away from the Fermi potential. In this case, Figure 5 As shown, compared with region 142B, region 142A and region 142C are less affected by the gate structure 150 due to their greater height and coverage by spacers 160 and 162. As a result, on average, the potential Ev and Ec of region 142B will be higher than the potential Ev and Ec of regions 142A and 142C. Therefore, although the three regions 142A, 142B and 142C were originally doped with the same concentration of carriers (or undoped) when the channel 140 was formed, the equivalent carrier density of region 142B will still be higher than the equivalent carrier density of region 142A and the equivalent carrier density of region 142C. For example, if the channel 140 was originally doped with a P-type concentration P-, the equivalent carrier concentrations of regions 142A and 142C may become P, and the equivalent carrier concentration of region 142B may become P+, ​​as shown in FIG. Figure 6 shown.

[0033] Figure 6 FIG. 1 shows the charge distribution between the source structure 120, the drain structure 130 and the channel 140 when the GAAFET 100 is operated in saturation. Figure 6As shown, because region 142A and region 142B have different equivalent carrier densities, an electrical junction (or induced junction) JB1 can be formed at the interface between region 142A and region 142B. Similarly, an electrical junction JB2 can be formed at the interface between region 142B and region 142C. In other words, the GAAFET 100 can have four junctions along the path from the drain structure 130 to the source structure 120: junction JA2' between the drain structure 130 and the channel 140, junction JB2 between region 142C and region 142B, junction JB1 between region 142B and region 142A, and junction JA1' between the channel 140 and the source structure 120. In some embodiments, the height H1 of region 142A and the height H3 of region 142C can be more than twice the height H2 of region 142B, so that observable junctions JB1 and JB2 can be formed in the channel 140. However, the present disclosure is not limited thereto.

[0034] In this case, when the GAAFET 100 is operated in saturation, compared to Figure 2 As shown, the depletion region DA is formed due to the diffusion of mobile charges from the junction JA2 in the GAAFET 900. In this embodiment, charges can diffuse from the two junctions JA2' and JB2 to form the depletion regions DA' and DB in the GAAFET 100. Figure 6 The depletion region DA' at the junction JA2' shown is larger than Figure 2 The depletion area DA at the junction JA2 is shown to be small.

[0035] Furthermore, with Figure 2 Compared to the electric field EA formed at junction JA2 in GAAFET 900, the electric field EA' formed at junction JA2' in GAAFET 100 is weakened by the new electric field EB formed at the additional junction JB2. In other words, the two junctions JA2' and JB2 can cooperate to absorb the drain-to-source bias; therefore, GAAFET 100 can withstand a higher breakdown voltage.

[0036] Because the channel 140 of the GAAFET 100 can include different regions with different equivalent carrier densities, an additional junction JB2 can be formed in the channel 140 adjacent to the drain structure 130. This, in turn, can generate an additional electric field EB adjacent to the drain structure 130, thereby improving the reliability of the GAAFET 100 by counteracting short channel effects. Furthermore, the additional junction JB2 can help weaken the electric field formed at the junction JA2′, thereby helping to increase the breakdown voltage of the GAAFET 100.

[0037] like Figure 3As shown, regions 142A, 142B, and 142C may have lengths L1, L2, and L3, respectively, measured along the extension direction X of channel 140. In some embodiments, length L2 may be greater than lengths L1 and L3. Furthermore, in some embodiments, lengths L1 and L3 of regions 142A and 142C may be adjusted as desired. For example, increasing lengths L1 and L3 of regions 142A and 142C may increase the breakdown voltage of GAAFET 100; however, this may also increase the on-resistance of GAAFET 100.

[0038] Figure 7 A GAAFET 200 according to another embodiment of the present disclosure is shown. The GAAFET 200 includes a substrate 210, a source structure 220, a drain structure 230, a channel 240, a gate structure 250, spacers 260 and 262, and dielectric layers 270 and 272. The gate structure 250 includes a dielectric layer 252 and a gate layer 254. The GAAFET 200 differs from the GAAFET 100 in that the GAAFET 200 includes multiple channels 240. In addition, it can be noted that in Figure 3 In FIG, region 142A of channel 140 is surrounded by spacer 160, while region 142C of channel 140 is surrounded by spacer 162. Furthermore, region 142B of channel 140 is surrounded by dielectric layer 152. However, in FIG. Figure 7 In the embodiment, although the channel 240 also includes regions 242A, 242B, and 242C (wherein the heights of the regions 242A and 242C are greater than the height of the region 242B), the regions 242A and 242C are only partially surrounded by the spacers 260 and 262 .

[0039] Specifically, region 242A includes two portions 242A1 and 242A2. Portion 242A1 is adjacent to source structure 220, while portion 242A2 is distal to source structure 220. In this case, portion 242A1 is surrounded by spacer 260, while portion 242A2 is surrounded by dielectric layer 252 of gate structure 250. Therefore, portion 242A1 surrounded by spacer 260 is less affected by gate structure 250 than portion 242A2. Consequently, the equivalent carrier density (e.g., P-) of portion 242A1 is lower than the equivalent carrier density (e.g., P) of portion 242A2. In some embodiments, when viewed along direction Y, which is perpendicular to directions X and Z, the cross-section of gate layer 254 between two channels 240 may form a cross shape.

[0040] Figure 8 FIG2 shows the charge distribution between the source structure 220, the drain structure 230 and the channel 240 when the GAAFET 200 is operated in saturation. Figure 8As shown, due to the different equivalent carrier densities, an electrical junction JB3″ may be generated between the two portions 242A1 and 242A2.

[0041] Similarly, region 242C includes two portions 242C1 and 242C2. Portion 242C1 is adjacent to drain structure 230, while portion 242C2 is distal from drain structure 230. Furthermore, portion 242C1 is surrounded by spacers 262, while portion 242C2 is surrounded by dielectric layer 252 of gate structure 250. Therefore, the equivalent carrier density (e.g., P-) of portion 242C1 is lower than the equivalent carrier density (e.g., P) of portion 242C2. Consequently, an electrical junction JB4″ is generated between portions 242C1 and 242C2.

[0042] That is, in this embodiment, four junctions JB1″, JB2″, JB3″, and JB4″ may be induced in channel 240. Specifically, junction JB3″ may be induced between portion 242A1 and portion 242A2 of region 242A, junction JB1″ may be induced between region 242A and region 242B, junction JB2″ may be induced between region 242B and region 242C, and junction JB4″ may be induced between portion 242C2 and portion 242C1 of region 242C. In some instances, junction JB3″ and junction JB1″ may be very close, so they may merge into a larger junction. Similarly, junction JB2″ and junction JB4″ may merge into a larger junction. Therefore, when the GAAFET 200 operates in a saturation state, the electric field is dispersed to the induction junctions JA2′, JB4″, and JB2″ to form electric fields EA″, EB1″, and EB2″, thereby reducing the electric field applied to the drain structure 230. As a result, the breakdown voltage of the GAAFET 200 can be increased. In addition, since the depletion region is distributed to more junctions and its size is reduced, the reliability of the GAAFET 200 in resisting short channel effects can also be improved.

[0043] Reference Figure 3. In the GAAFET 100, the region 142A includes sidewalls 144A and 146A that are perpendicular to the extension direction X of the channel 140, wherein the sidewall 144A is connected to the upper surface of the region 142B farther from the substrate 110, and the sidewall 146A is connected to the lower surface of the region 142B closer to the substrate 110. Similarly, the region 142C includes sidewalls 144C and 146C that are perpendicular to the extension direction X of the channel 140, wherein the sidewall 144C is connected to the upper surface of the region 142B farther from the substrate 110, and the sidewall 146C is connected to the lower surface of the region 142B closer to the substrate 110. However, the present disclosure is not limited to this. In some embodiments, the sidewalls 144A, 146A, 144C, and 146C may not be perpendicular to the extension direction X of the channel 140.

[0044] Figure 9 Channel 340 is shown according to one embodiment of the present disclosure. Figure 9 As shown, channel 340 includes regions 342A, 342B, and 342C. Region 342A is coupled to source structure 120, region 342C is coupled to drain structure 130, and region 342B is disposed between regions 342A and 342C. In this embodiment, region 342A includes sidewalls 344A and 346A that slope from one side of region 342A (i.e., the side adjacent to region 342B) toward the other side of region 342A (i.e., the side adjacent to source structure 120). Therefore, a height A11 of sidewall 344A located near source structure 120 is higher than a height A12 of sidewall 344A located near region 342B, and a height A21 of sidewall 346A located near source structure 120 is lower than a height A22 of sidewall 346A located near region 342B.

[0045] Similarly, region 342C includes sidewalls 344C and 346C, which slope from one side of region 342C (i.e., the side adjacent to region 342B) toward the other side of region 342C (i.e., the side adjacent to drain structure 130). Therefore, height A31 of sidewall 344C located near drain structure 130 is higher than height A32 of sidewall 344C located near region 342B. Furthermore, height A41 of sidewall 346C located near drain structure 130 is lower than height A42 of sidewall 346C located near region 342B. In this embodiment, heights A11, A12, A21, A22, A31, A32, A41, and A42 can be measured along direction Z.

[0046] Figure 10Channel 440 is further illustrated according to another embodiment of the present disclosure. Channel 440 includes regions 442A, 442B, and 442C. Region 442A includes sidewalls 444A and 446A, and region 442C includes sidewalls 444C and 446C. Channel 440 differs from channel 340 in that sidewalls 444A, 446A, 444C, and 446C are steeper than sidewalls 344A, 346A, 344C, and 446C. Therefore, region 442A further includes a planar surface parallel to direction X that connects sidewalls 444A and 446A to source structure 120. Furthermore, region 442C further includes a planar surface parallel to direction X that connects sidewalls 444C and 446C to drain structure 130.

[0047] In some embodiments, when viewed in a direction Y perpendicular to the directions X and Z, the cross-section of the channel 140, 240, 340, or 440 may be as follows: Figure 3 、 7 , 9 and 10 shown in the dumbbell shape.

[0048] Furthermore, in some embodiments, region 142A of channel 140 may include only one sidewall connected to the upper surface or lower surface of region 142B, and a height difference may still be created between regions 142A and 142B. Figure 11 Channel 140' is shown according to another embodiment of the present disclosure. Channel 140' differs from channel 140 in that region 142A' includes a sidewall 144A' connected to the upper surface of region 142B', while region 142C' includes a sidewall 144C' connected to the upper surface of region 142B'.

[0049] Figure 12 Channel 340' is shown according to another embodiment of the present disclosure. Channel 340' differs from channel 340 in that region 342A' includes a sidewall 344A' connected to the upper surface of region 342B', while region 342C' includes a sidewall 344C' connected to the upper surface of region 342B'.

[0050] Figure 13 Channel 440' is shown according to another embodiment of the present disclosure. Channel 440' differs from channel 440 in that region 442A' includes a sidewall 444A' connected to region 442B', while region 442C' includes a sidewall 444C' connected to the upper surface of region 442B'.

[0051] In some embodiments, when viewed in a direction Y perpendicular to the directions X and Z, the cross section of the channel 140', 340', or 440' may be as follows: Figure 11 、 12and the U-shape shown in 13.

[0052] In some embodiments, in direction X, Figure 9-13 Each channel in may have two outer regions surrounded by spacers (e.g., Figure 9 342A and 342C), similar to the reference Figure 3 In some embodiments, in direction X, Figure 9-13 Each channel in the may have two outer regions that are partially surrounded by spacers and partially surrounded by dielectric layers (e.g., Figure 9 342A and 342C), similar to the reference Figure 7 Furthermore, although the above method can be used to form different regions with different heights in the channel so that the channel has multiple regions with different equivalent carrier densities, the channel can also be formed with multiple regions with different equivalent carrier densities by surrounding different regions of the channel with dielectric layers with different thicknesses.

[0053] Figure 14 A GAAFET 500 according to one embodiment of the present disclosure is shown. GAAFET 500 includes a substrate 510, a source structure 520, a drain structure 530, a channel 540, a gate structure 550, spacers 560 and 562, and dielectric layers 570 and 572. Gate structure 550 includes dielectric layer 552 and gate layer 554. GAAFET 500 differs from GAAFET 200 in that, in each channel 540, the thickness of dielectric layer 552 stacked on regions 542A and 542C is greater than the thickness of dielectric layer 552 stacked on region 542B.

[0054] In this embodiment, because the dielectric layer 552 is thicker near regions 542A and 542C, regions 542A and 542C are less affected by the gate structure 550 than region 542B. Therefore, even though regions 542A, 542B, and 542C may have the same height, the equivalent carrier density in region 542B is still higher than the equivalent carrier density in regions 542A and 542C. This creates an electrical junction between regions 542A and 542B, and between regions 542B and 542C, thereby increasing the breakdown voltage of the GAAFET 500 and protecting the GAAFET 500 from short channel effects. In some embodiments, when viewed along direction Y, which is perpendicular to directions X and Z, the cross-section of the gate layer 554 between the two channels 540 may form a cross shape.

[0055] In GAAFET 500 , dielectric layer 552 may be thicker both above and below regions 542A and 542C; however, the disclosure is not limited in this regard. Figure 15A GAAFET 500' is shown according to one embodiment of the present disclosure. The GAAFET 500' includes a substrate 510, a source structure 520, a drain structure 530, a channel 540', a gate structure 550', spacers 560 and 562, and dielectric layers 570 and 572. The gate structure 550' includes a dielectric layer 552' and a gate layer 554'. The GAAFET 500' differs from the GAAFET 500 in that the dielectric layer 552' is thicker only above regions 542A' and 542C', while the dielectric layer 552' has the same thickness below regions 542A', 542B', and 542C'. In some embodiments, when viewed in a direction Y perpendicular to the directions X and Z, the cross-section of the gate layer 554' between the two channels 540' may protrude into the substrate.

[0056] Furthermore, in the previous embodiments, each of the channels 140, 240, 340, 440, 540, 140', 340', 440', and 540' may include three regions, however, the present disclosure is not limited thereto. In some embodiments, one of the regions with a lower equivalent carrier density may be omitted. For example, in most applications of NMOS transistors, since the voltage received by the drain is generally higher than the voltage received by the source, a short channel effect (e.g., DIBL) may occur on the drain side. Therefore, the region with a lower equivalent carrier density and close to the source structure may be omitted, while the region with a lower equivalent carrier density and close to the drain structure may be retained, thereby maintaining protection for the drain structure.

[0057] For example, in some embodiments, the region 142A in the channel 140 can be omitted, and the region 142B can be extended and coupled to the source structure 120. In this case, no Figure 6 Junction JB1 is shown. However, since region 142C of channel 140 is retained, junction JB2 between regions 142B and 142C can still be initiated, thereby protecting drain structure 130 and preventing short channel effects. Similarly, in each of channels 240, 340, 440, 540, 140', 340', 440', and 540', region 242A, 342A, 442A, 542A, 142A', 342A', 442A', or 542A' can be omitted, while region 242C, 342C, 442C, 542C, 142C', 342C', 442C', or 542C' can be retained.

[0058] In summary, the GAAFET provided by the embodiments of the present disclosure can have multiple regions with different equivalent carrier densities in the channel to induce additional junctions within the channel, thereby improving the reliability of the GAAFET by combating short channel effects. Furthermore, the induced junctions can help weaken the electric field generated at the drain, thereby helping to increase the breakdown voltage of the GAAFET.

[0059] Explanation of symbols

[0060] 900, 100, 200, 500, 500': GAAFET

[0061] 910,110,210,510: Substrate

[0062] 920, 120, 220, 520: Source structure

[0063] 930,130,230,530: drain structure

[0064] 940,140,240,340,440,140',340',440',540,540': Channel

[0065] 950,150,250,550,550': Gate structure

[0066] 954,154,254,554,554': Gate layer

[0067] 960,962,160,162,260,262,560,562: spacers

[0068] 952,970,972,152,170,172,270,272,252: dielectric layer

[0069] JA1,JA2,JA1',JB1,JA2',JB2,JB1",JB2",JB3",JB4": connection

[0070] DA,DB,DA': depleted area

[0071] EA,EB,EA',EA",EB1",EB1",EB2": electric field

[0072] 142A, 142B, 142C, 242A, 242B, 242C: Area

[0073] 144A, 146A, 144C, 146C: sidewall

[0074] L1, L2, L3: length

[0075] H1, H2, H3: Height

[0076] Ef: Fermi potential

[0077] Ec, Ev: electric potential

[0078] 242A1, 242A2, 242C1, 242C2: Part

[0079] 342A, 342B, 342C, 442A, 442B, 442C, 142A', 142B', 142C': Area 344A, 346A, 344C, 346C, 444A, 446A, 444C, 446C: Sidewall

[0080] A11, A12, A21, A22, A31, A32, A41, A42: Altitude position

[0081] 342A',342B',342C',442A',442B',442C': Area

[0082] 144A', 144C', 344A', 344C', 444A', 444C': sidewalls

[0083] 542A, 542B, 542C, 542A', 542B', 542C': Area

[0084] 552,570,572,552': dielectric layer

Claims

1. A gate-all-around field-effect transistor, comprising: a substrate; a source structure disposed on the substrate; a drain structure disposed on the substrate; at least one channel, each extending between the source structure and the drain structure; and a gate structure disposed between the source structure and the drain structure and surrounding the at least one channel; in: When the gate-all-around field effect transistor operates in a saturation state, each of the at least one channel includes a first region, a second region, and a first electrical junction between the first region and the second region, and The first region is adjacent to the drain structure, and the second region is adjacent to the first region. 2 . The gate-all-around field-effect transistor as claimed in claim 1 , wherein an equivalent carrier density of the second region is higher than an equivalent carrier density of the first region.

3. The gate-all-around field-effect transistor as claimed in claim 1 , wherein a height of the first region is greater than a height of the second region, and the height of the first region and the height of the second region are measured along a stacking direction of the at least one channel and the gate structure. 4 . The gate-all-around field effect transistor as claimed in claim 3 , wherein the height of the first region is higher than twice the height of the second region.

5. The gate-all-around field effect transistor according to claim 3, wherein: A first side of the first region is adjacent to the drain structure, and a second side of the first region is adjacent to the second region. The first region includes a first sidewall that slopes from the second side to the first side; and A first height position of the first sidewall at the first side is higher than a second height position of the first sidewall at the second side.

6. The gate-all-around field effect transistor according to claim 5, wherein: The first region further includes a second sidewall inclined from the second side to the first side. The first sidewall is connected to an upper surface of the second region farther from the substrate, and the second sidewall is connected to a lower surface of the second region closer to the substrate; as well as A first height position of the second sidewall at the first side is lower than a second height position of the second sidewall at the second side. 7 . The gate-all-around field effect transistor as claimed in claim 3 , wherein the first region comprises a first sidewall perpendicular to an extension direction of the at least one channel.

8. The gate-all-around field effect transistor according to claim 7, wherein: The first region further includes a second sidewall perpendicular to the extension direction of the at least one channel; and The first side wall is connected to an upper surface of the second region farther from the substrate, and the second side wall is connected to a lower surface of the second region closer to the substrate. 9 . The gate-all-around field effect transistor as claimed in claim 1 , further comprising a spacer disposed between the drain structure and the gate structure, wherein a first portion of the first region is surrounded by the spacer. 10 . The gate-all-around field effect transistor as claimed in claim 9 , wherein a second portion of the first region is surrounded by a dielectric layer of the gate structure. 11 . The gate-all-around field effect transistor of claim 10 , wherein each of the at least one channel further comprises a second electrical junction between the first portion of the first region and the second portion of the first region.

12. The gate-all-around field effect transistor of claim 1 , wherein: Each of the at least one channel further includes a third region adjacent to the source structure. The second area is located between the first area and the third area; and An equivalent carrier density of the second region is higher than an equivalent carrier density of the third region.

13. The gate-all-around field effect transistor of claim 12 , further comprising: a first spacer disposed between the drain structure and the gate structure; and a second spacer disposed between the source structure and the gate structure, A first portion of the first region is surrounded by the first spacer, and a first portion of the third region is surrounded by the second spacer. 14 . The gate-all-around field effect transistor as claimed in claim 13 , wherein a second portion of the first region and a second portion of the third region are surrounded by a dielectric layer of the gate structure.

15. The gate-all-around field-effect transistor of claim 1 , wherein the gate structure comprises a dielectric layer surrounding the at least one channel, and a thickness of the dielectric layer stacked on the first region of each of the at least one channel is greater than a thickness of the dielectric layer stacked on the second region of each of the at least one channel. 16 . The gate-all-around field effect transistor of claim 15 , wherein a thickness of the dielectric layer under the first region of each of the at least one channel is greater than a thickness of the dielectric layer under the second region of each of the at least one channel.

17. The gate-all-around field effect transistor according to claim 1 , wherein the at least one channel and the gate structure are stacked along a first direction, and the at least one channel extends along a second direction perpendicular to the first direction. in: The gate structure includes a gate layer and a gate dielectric layer; and When viewed along a third direction perpendicular to the first direction and the second direction, a cross section of the gate layer is in a cross shape.

18. The gate-all-around field effect transistor according to claim 1 , wherein the at least one channel and the gate structure are stacked along a first direction, and the at least one channel extends along a second direction perpendicular to the first direction. in: The gate structure includes a gate layer and a gate dielectric layer; and When viewed along a third direction perpendicular to the first direction and the second direction, a cross section of the gate layer protrudes toward the substrate.

19. The gate-all-around field effect transistor according to claim 1 , wherein the at least one channel and the gate structure are stacked along a first direction, and the at least one channel extends along a second direction perpendicular to the first direction. in: When viewed along a third direction perpendicular to the first direction and the second direction, a cross-section of the at least one channel is in a dumbbell shape.

20. The gate-all-around field effect transistor of claim 1 , wherein the at least one channel and the gate structure are stacked along a first direction, and the at least one channel extends along a second direction perpendicular to the first direction. in: When viewed along a third direction perpendicular to the first direction and the second direction, a cross-section of the at least one channel is U-shaped.

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