Preparation method of semiconductor device

Abstract

The invention provides a preparation method of a semiconductor device, and the method comprises the steps: providing a substrate which comprises a high-voltage region, a source-drain region and an isolation region; forming a silicon nitride layer to cover the substrate, and etching to remove at least a part of thickness of the silicon nitride layer on the isolation region; etching to remove partial thickness of the silicon nitride layer on the high-voltage region, wherein the silicon nitride layer on the high-voltage region and the silicon nitride layer on the source-drain region have a height difference after etching; etching the substrate by taking the silicon nitride layer as a mask so as to form an isolation groove in the isolation region, synchronously etching and removing the silicon nitride layer on the high-voltage region, enabling the high-voltage region and the source-drain region to have a height difference after etching, and enabling the top edge of the high-voltage region to be arc-shaped; a first oxide layer is formed to fill the isolation groove and cover the high-voltage region, the surface of the first oxide layer is flat, and the first oxide layer on the high-voltage region serves as a gate oxide layer. The problem of foot warping at the edge of the high-voltage area can be solved, and the preparation cost is not additionally increased.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device. Background Art

[0002] Due to their high operating voltages, high-voltage semiconductor devices typically require thicker gate oxide layers. In current fabrication processes, isolation trenches are typically dry-etched first, resulting in angled sidewalls. An isolation material layer is then deposited to fill the trenches. Next, a recess is dry-etched in the high-voltage region, where the gate oxide layer grows. This step often results in warped edges at the high-voltage region.

[0003] Figure 1 This is a cross-sectional diagram of a method for preparing a semiconductor device in the prior art after forming an isolation trench. Figure 1 A substrate 10 is provided, the substrate 10 includes a high-voltage area 11, a first silicon nitride layer 21 is formed on the substrate 10, the first silicon nitride layer 21 is patterned using a mask, and after patterning, the first silicon nitride layer 21 is used as a hard mask to dry-etch the substrate 10 to form a plurality of isolation trenches 30, and a portion of the substrate 10 between two adjacent isolation trenches 30 is the high-voltage area 11.

[0004] Figure 2 Schematic diagram of a cross section after depositing an isolation material layer in a method for preparing a semiconductor device in the prior art. Figure 3 This is a cross-sectional view of a method for preparing a semiconductor device in the prior art after removing the first silicon nitride layer. Figure 2 , depositing an isolation material layer to fill the isolation trench 30 to obtain a trench isolation structure 32; please refer to Figure 3 , and remove the remaining first silicon nitride layer 21.

[0005] Figure 4 This is a cross-sectional diagram of a method for preparing a semiconductor device in the prior art after forming a second silicon nitride layer and a patterned photoresist layer. Figure 4 , a second silicon nitride layer 22 and a patterned photoresist layer 40 are sequentially formed on the substrate 10 and the trench isolation structure 32 .

[0006] Figure 5 This is a cross-sectional diagram of a method for preparing a semiconductor device in the prior art after etching a high-voltage area to form a groove. Figure 6 This is a partial electron microscope diagram of the process for preparing semiconductor devices in the prior art after etching the high voltage area to form a groove. Figure 5, the second silicon nitride layer 22 is etched using the patterned photoresist layer 40 to expose the high-voltage area 11, and then the high-voltage area 11 is dry-etched to form a groove 12, and then the second silicon nitride layer 22 and the patterned photoresist layer 40 are removed; because the sidewall of the isolation trench has a certain angle, the edge of the high-voltage area 11 is not etched regularly after etching, thereby forming a warped corner ( Figure 5 This step will cause the loss of the isolation material layer in the isolation trench. Figure 6 The black upward-curved portion in the circular virtual frame is the formed warp angle, and the black area in the figure is the high-voltage area, and the trench isolation structures are on both sides of the high-voltage area.

[0007] Figure 7 Schematic diagram of a cross section after a gate oxide layer is formed in a method for preparing a semiconductor device in the prior art. Figure 8 This is a partial electron microscope diagram of the gate oxide layer after forming the gate oxide layer in the manufacturing method of the semiconductor device in the prior art. Figure 7 , a gate oxide layer 50 is grown in the groove. Since the previous etching step will cause the isolation material layer in the isolation trench to be lost, after the gate oxide layer 50 is formed, the surface close to the gate oxide layer 50 and the trench isolation structure 32 will be uneven, affecting the subsequent preparation window. Please refer to Figure 8 ,The depression in the circular dotted box indicates that the surface close to the gate oxide layer and the trench isolation structure is uneven.

[0008] At present, the usual way to improve the warping phenomenon is to use over-etching to reduce the degree of warping. However, due to the angle problem of the isolation trench, the warping cannot be completely eliminated, and excessive etching will also cause excessive loss of the isolation material layer in the isolation trench, making the surface close to the gate oxide layer and the trench isolation structure uneven, affecting the subsequent preparation window. In summary, after the gate oxide layer is formed, the following problems may occur: First, the warping phenomenon causes the gate oxide layer at the edge of the high-voltage area to be thinner, affecting the reliability of the device; second, the thin gate oxide layer at the edge of the high-voltage area reduces the equivalent oxide layer thickness of the device, exacerbating the impact of the short channel effect; third, the warping at the edge of the high-voltage area makes it easier for the electric field of the device to concentrate during operation, which will increase carrier scattering and affect the electrical performance of the device; fourth, the surface above the high-voltage area is uneven, affecting the subsequent preparation window. Summary of the Invention

[0009] The object of the present invention is to provide a method for preparing a semiconductor device, which can solve the problem of curled-off legs at the edge of a high-voltage region without increasing the preparation cost.

[0010] In order to achieve the above object, the present invention provides a method for preparing a semiconductor device, comprising: Providing a substrate, wherein the substrate includes a high voltage region, a source / drain region, and an isolation region; forming a silicon nitride layer to cover the substrate, and etching away at least a portion of the thickness of the silicon nitride layer on the isolation region; Etching and removing a portion of the thickness of the silicon nitride layer on the high voltage region, so that after etching, there is a height difference between the silicon nitride layer on the high voltage region and the silicon nitride layer on the source and drain regions; The substrate is etched using the silicon nitride layer as a mask to form an isolation trench in the isolation region, and the silicon nitride layer on the high-voltage region is simultaneously etched and removed, wherein after etching, there is a height difference between the high-voltage region and the source and drain regions, and the top edge of the high-voltage region is curved; A first oxide layer is formed to fill the isolation trench and cover the high-voltage region, and the surface of the first oxide layer is flat. The first oxide layer on the high-voltage region serves as a gate oxide layer.

[0011] Optionally, the step of etching and removing a portion of the thickness of the silicon nitride layer on the isolation region includes: forming a first patterned photoresist layer covering the silicon nitride layer on the high voltage region and the source / drain region; Using the first patterned photoresist layer as a mask, etching and removing a portion of the thickness of the silicon nitride layer on the isolation region; The first patterned photoresist layer is removed.

[0012] Optionally, the step of etching and removing a portion of the thickness of the silicon nitride layer on the high-voltage region includes: forming a second patterned photoresist layer to cover the silicon nitride layer on the isolation region and the source / drain region; Using the second patterned photoresist layer as a mask, etching away a portion of the thickness of the silicon nitride layer on the high-voltage region, wherein after etching, the thickness of the silicon nitride layer on the high-voltage region is between the thickness of the silicon nitride layer on the isolation region and the thickness of the silicon nitride layer on the source and drain regions; The second patterned photoresist layer is removed.

[0013] Optionally, before etching the substrate using the silicon nitride layer as a mask, the method further includes etching away a remaining thickness of the silicon nitride layer on the isolation region.

[0014] Optionally, the step of etching and removing the silicon nitride layer on the isolation region includes: forming a first patterned photoresist layer covering the silicon nitride layer on the high voltage region and the source / drain region; Using the first patterned photoresist layer as a mask, etching and removing the silicon nitride layer on the isolation region; The first patterned photoresist layer is removed.

[0015] Optionally, the step of etching and removing a portion of the thickness of the silicon nitride layer on the high-voltage region includes: forming a second patterned photoresist layer to cover the silicon nitride layer on the source and drain regions and the isolation region; Using the second patterned photoresist layer as a mask, etching and removing a portion of the thickness of the silicon nitride layer above the high voltage area; The second patterned photoresist layer is removed.

[0016] Optionally, after etching the substrate using the silicon nitride layer as a mask, a partial thickness of the silicon nitride layer remains on the source and drain regions.

[0017] Optionally, after etching the substrate using the silicon nitride layer as a mask, the method further includes removing the silicon nitride layer remaining on the source and drain regions.

[0018] Optionally, after removing the silicon nitride layer retained on the source and drain regions, the method further includes forming a second oxide layer on the surface of the substrate using a thermal oxidation process.

[0019] Optionally, the step of forming the first oxide layer to fill the isolation trench and cover the high voltage area includes: Depositing and forming the first oxide layer to fill the isolation trench and cover the source / drain region and the high voltage region; A chemical mechanical polishing process is performed on the first oxide layer to polish and remove the first oxide layer on the source and drain regions to expose surfaces of the source and drain regions.

[0020] The preparation method of the semiconductor device provided by the present invention includes: providing a substrate, the substrate including a high-voltage region, a source-drain region and an isolation region; forming a silicon nitride layer to cover the substrate, and etching to remove at least a portion of the thickness of the silicon nitride layer on the isolation region; etching to remove a portion of the thickness of the silicon nitride layer on the high-voltage region, after etching, the silicon nitride layer on the high-voltage region and the silicon nitride layer on the source-drain region have a height difference; etching the substrate using the silicon nitride layer as a mask to form an isolation trench in the isolation region, and the silicon nitride layer on the high-voltage region is synchronously etched and removed, after etching, the high-voltage region and the source-drain region have a height difference, and the top edge of the high-voltage region is arc-shaped; forming a first oxide layer to fill the isolation trench and cover the high-voltage region, and the surface of the first oxide layer is flat, and the first oxide layer on the high-voltage region serves as a gate oxide layer. The unexpected technical effect of the present invention is that by first etching the silicon nitride layer, the silicon nitride layer on the high-voltage area and the silicon nitride layer on the source and drain areas have a height difference, and then the substrate is etched using the silicon nitride layer as a mask to form an isolation trench. After etching, the high-voltage area and the source and drain areas have a height difference, and the top edge of the high-voltage area is arc-shaped, so that the edge of the high-voltage area will not have a curled foot, thereby solving the curled foot problem of the edge of the high-voltage area, and after forming a first oxide layer to fill the isolation trench and cover the high-voltage area, the surface of the first oxide layer is flat, and the present invention does not require a new mask, and will not increase the preparation cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a cross-sectional schematic diagram of a method for preparing a semiconductor device in the prior art after forming an isolation trench.

[0022] Figure 2 It is a cross-sectional schematic diagram of a method for preparing a semiconductor device in the prior art after depositing an isolation material layer.

[0023] Figure 3 It is a cross-sectional schematic diagram of a method for preparing a semiconductor device in the prior art after removing the first silicon nitride layer.

[0024] Figure 4 The present invention is a cross-sectional schematic diagram of a method for preparing a semiconductor device in the prior art after forming a second silicon nitride layer and a patterned photoresist layer.

[0025] Figure 5 The present invention is a cross-sectional schematic diagram of a method for preparing a semiconductor device in the prior art after etching a high-voltage area to form a groove.

[0026] Figure 6 This is a partial electron microscope schematic diagram of the process for preparing a semiconductor device in the prior art after etching a high-voltage area to form a groove.

[0027] Figure 7 It is a cross-sectional schematic diagram of a method for preparing a semiconductor device in the prior art after a gate oxide layer is formed.

[0028] Figure 8 This is a partial electron microscope diagram of a method for preparing a semiconductor device in the prior art after forming a gate oxide layer.

[0029] Figure 9 The present invention provides a flow chart of a method for preparing a semiconductor device.

[0030] Figure 10 This is a schematic cross-sectional view after etching a portion of the silicon nitride layer on the isolation region in the method for manufacturing a semiconductor device provided in the first embodiment of the present invention.

[0031] Figure 11 This is a schematic cross-sectional view after etching the silicon nitride layer on the high-voltage area in the method for manufacturing a semiconductor device provided in the first embodiment of the present invention.

[0032] Figure 12 This is a schematic cross-sectional view after etching the remaining silicon nitride layer on the isolation region in the method for manufacturing a semiconductor device provided in the first embodiment of the present invention.

[0033] Figure 13 This is a schematic cross-sectional view of the semiconductor device manufacturing method provided in the first embodiment of the present invention after the isolation trench is formed.

[0034] Figure 14This is a schematic cross-sectional view of the semiconductor device manufacturing method after forming the second oxide layer according to the first embodiment of the present invention.

[0035] Figure 15 This is a schematic cross-sectional view of the semiconductor device manufacturing method provided in the first embodiment of the present invention after the first oxide layer is formed.

[0036] Figure 16 This is a schematic cross-sectional view of a semiconductor device after a chemical mechanical polishing process is performed in the method for manufacturing the semiconductor device provided in the first embodiment of the present invention.

[0037] Figure 17 This is a schematic cross-sectional view after etching the silicon nitride layer on the isolation region in the method for manufacturing a semiconductor device provided in the second embodiment of the present invention.

[0038] Figure 18 This is a schematic cross-sectional view after etching the silicon nitride layer on the high-voltage area in the method for manufacturing a semiconductor device provided in the second embodiment of the present invention.

[0039] in, Figures 1 to 8 The accompanying drawings are: 10 - substrate; 11 - high voltage region; 12 - groove; 21 - first silicon nitride layer; 22 - second silicon nitride layer; 30 - isolation trench; 32 - trench isolation structure; 40 - patterned photoresist layer; 50 - gate oxide layer.

[0040] Figures 10 to 18 The accompanying drawings are: 100 - substrate; 110 - high voltage region; 120 - isolation region; 130 - source and drain region; 200 - silicon nitride layer; 310 - first patterned photoresist layer; 320 - second patterned photoresist layer; 400 - isolation trench; 510 - first oxide layer; 520 - second oxide layer. DETAILED DESCRIPTION

[0041] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0042] Please refer to Figure 9 The present invention provides a method for preparing a semiconductor device, comprising: Step S1: providing a substrate, the substrate including a high voltage region, a source / drain region, and an isolation region; Step S2: forming a silicon nitride layer to cover the substrate, and etching to remove at least a portion of the thickness of the silicon nitride layer on the isolation region; Step S3: etching and removing a portion of the silicon nitride layer on the high voltage region, so that there is a height difference between the silicon nitride layer on the high voltage region and the silicon nitride layer on the source and drain regions after etching; Step S4: etching the substrate using the silicon nitride layer as a mask to form an isolation trench in the isolation region, and simultaneously removing the silicon nitride layer on the high-voltage region. After etching, there is a height difference between the high-voltage region and the source and drain regions, and the top edge of the high-voltage region is curved. Step S5: forming a first oxide layer to fill the isolation trench and cover the high voltage area, wherein the surface of the first oxide layer is flat, and the first oxide layer on the high voltage area serves as a gate oxide layer.

[0043] The present invention etches the silicon nitride layer first so that the silicon nitride layer on the high-voltage area and the silicon nitride layer on the source and drain areas have a height difference, and then etches the substrate using the silicon nitride layer as a mask to form an isolation trench. After etching, the high-voltage area and the source and drain areas have a height difference, and the top edge of the high-voltage area is arc-shaped, so that the edge of the high-voltage area does not have a curled foot, thereby solving the curled foot problem of the edge of the high-voltage area. After forming a first oxide layer to fill the isolation trench and cover the high-voltage area, the surface of the first oxide layer is flat. In addition, the present invention does not require a new mask and does not increase the preparation cost.

[0044] Example 1 The following combination Figures 10 to 16 The method for manufacturing the semiconductor device provided in this embodiment is described in detail.

[0045] Please refer to Figure 10 , perform step S1: provide a substrate 100, wherein the substrate 100 is preferably a silicon substrate; the substrate 100 includes a high-voltage region 110, a source-drain region 130 and an isolation region 120, and the isolation region 120 is located between the source-drain region 130 and the high-voltage region 110. The semiconductor device of this embodiment is a high-voltage device, and the source-drain region 130 and the high-voltage region 110 need to be isolated by the isolation region 120.

[0046] Please refer to Figure 10 , step S2 is performed: a silicon nitride layer 200 is formed to cover the substrate 100 (the high-voltage region 110, the source / drain region 130, and the isolation region 120), and a first patterned photoresist layer 310 is formed to cover the silicon nitride layer 200 on the high-voltage region 110 and the source / drain region 130; then, using the first patterned photoresist layer 310 as a mask, a portion of the silicon nitride layer 200 on the isolation region 120 is etched away, and then the first patterned photoresist layer 310 is removed. In this embodiment, etching away a portion of the silicon nitride layer 200 on the isolation region 120, while retaining a portion of the silicon nitride layer 200 on the isolation region 120, can protect the surface of the isolation region 120 from contact with the subsequently formed second patterned photoresist layer.

[0047] Please refer to Figure 11, perform step S3: form a second patterned photoresist layer 320 to cover the silicon nitride layer 200 on the isolation region 120 and the source / drain region 130, exposing the silicon nitride layer 200 on the high-voltage region 110. Since a portion of the silicon nitride layer 200 is retained on the isolation region 120, the second patterned photoresist layer 320 does not directly contact the surface of the isolation region 120, thereby avoiding the generation of photoresist residue on the surface of the isolation region 120 after removing the second patterned photoresist layer 320; and then, use the second patterned photoresist layer 320 as a mask to etch away the silicon nitride layer 200 on the high-voltage region 110. The silicon nitride layer 200 has a partial thickness. After etching, the silicon nitride layer 200 on the high-voltage area 110 and the silicon nitride layer 200 on the source and drain areas 130 have a height difference. Specifically, the top surface of the silicon nitride layer 200 on the high-voltage area 110 is lower than the top surface of the silicon nitride layer 200 on the source and drain areas 130 (the height difference between the two top surfaces is h1). After etching, the thickness of the silicon nitride layer 200 on the high-voltage area 110 is between the thickness of the silicon nitride layer 200 on the isolation area 120 and the thickness of the silicon nitride layer 200 on the source and drain areas 130. The second patterned photoresist layer 320 is then removed.

[0048] For further information, please refer to Figure 12 Since part of the silicon nitride layer 200 remains on the isolation region 120, before etching the substrate 100 using the silicon nitride layer 200 as a mask, the remaining thickness of the silicon nitride layer 200 on the isolation region 120 is further removed by etching. This step of etching adopts dry etching, does not require a mask, and directly etches the silicon nitride layer 200. Since the thickness of the silicon nitride layer 200 on the high voltage region 110, the source and drain regions 130, and the isolation region 120 is different, the silicon nitride layer 200 on the high voltage region 110, the source and drain regions 130, and the isolation region 120 are etched synchronously by controlling the etching time, so that the etching stops on the surface of the isolation region 120. After etching, the silicon nitride layer 200 remains on the high voltage region 110 and the source and drain regions 130, and there is a height difference between the silicon nitride layer 200 on the high voltage region 110 and the source and drain regions 130 (the height difference is still substantially the same as before etching, which is h1).

[0049] In this embodiment, the etching conditions for etching away the remaining thickness of the silicon nitride layer 200 on the isolation region 120 are: the etching gas includes CF4 and O2, and the etching is performed at a pressure of 50mtorr and a power of 400W. Under these etching conditions, the etching rate of the silicon nitride layer 200 is 300Å / min. Since the thickness of the silicon nitride layer 200 on the high-voltage region 110, the source and drain region 130 and the isolation region 120 is different, for example, the thickness of the silicon nitride layer 200 on the source and drain region 130 is 300Å, the thickness of the silicon nitride layer 200 on the high-voltage region 110 is 200Å, and the thickness of the silicon nitride layer 200 on the isolation region 120 is 100Å, then according to the above-mentioned etching conditions, the etching time can be selected as 20s. After the etching is completed, the thickness of the silicon nitride layer 200 on the source and drain region 130 is 200Å, the thickness of the silicon nitride layer 200 on the high-voltage region 110 is 100Å, and there is no silicon nitride layer 200 on the isolation region 120.

[0050] Please refer to Figure 13 , performing step S4: etching the substrate 100 (the isolation region 120 and the high voltage region 110 ) using the silicon nitride layer 200 as a mask to form an isolation trench 400 in the isolation region 120 . Since the high-voltage region 110 and the source-drain region 130 have a silicon nitride layer 200 as a mask, the isolation region 120 is not blocked and will be etched in large quantities to form an isolation trench 400. Moreover, since the thickness of the silicon nitride layer 200 on the high-voltage region 110 is thinner than the thickness of the silicon nitride layer 200 on the source-drain region 130, the silicon nitride layer 200 on the source-drain region 130 and the high-voltage region 110 are synchronously etched during the etching process, resulting in the silicon nitride layer 200 on the high-voltage region 110 being synchronously etched and removed, and part of the thickness of the high-voltage region 110 will be etched away, so that after etching, the high-voltage region 110 and the source-drain region 130 have a height difference, specifically, the top surface of the high-voltage region 110 is lower than the top surface of the source-drain region 130 (the height difference between the two top surfaces is h2. Since the etching involves different materials, the height difference h2 after etching may be different from h1). This step uses dry etching. After etching, the sidewalls of the isolation trench 400 are inclined, and the top edge of the high-voltage area 110 is in a smooth arc shape, so that the edge of the high-voltage area 110 does not curl, thereby solving the curling problem of the edge of the high-voltage area 110.

[0051] In this embodiment, the etching conditions for etching the substrate 100 using the silicon nitride layer 200 as a mask are as follows: the etching gas includes hydrogen bromide and helium, the etching is performed at a pressure of 20mtorr to 30mtorr and a power of 200W. Under these etching conditions, the etching rate for the substrate 100 (made of silicon) is 2000Å / min, and the etching rate for the silicon nitride layer 200 is 100Å / min. Due to the different materials and etching rates of the substrate 100 and the silicon nitride layer 200, the silicon nitride layer 200 on the source and drain regions 130 and the high-voltage region 110 are simultaneously etched when etching to form the isolation trench 400. For example, if the depth requirement of the isolation trench 400 is 3000Å, then according to the above etching conditions, the etching time can be selected as 90s. The etching conditions can be used to accurately adjust the thickness of the remaining silicon nitride layer 200 on the high-voltage region 110 and the source and drain region 130 in advance so that the etching reaches the target depth of the isolation trench 400 and the etching depth of the high-voltage region 110 reaches the expected set value.

[0052] Furthermore, after etching the substrate 100 using the silicon nitride layer 200 as a mask, a partial thickness of the silicon nitride layer 200 remains on the source and drain regions 130 to avoid etching the source and drain regions 130. By controlling the thickness difference between the high-voltage region 110 and the silicon nitride layer 200 on the source and drain regions 130 (i.e., adjusting the height difference), the depth of the isolation trench 400 and the thickness of the high-voltage region 110 etched away can be controlled.

[0053] Furthermore, after etching the substrate 100 using the silicon nitride layer 200 as a mask, the silicon nitride layer 200 remaining on the source and drain regions 130 is removed by wet etching using hot phosphoric acid.

[0054] For further information, please refer to Figure 14 After removing the silicon nitride layer 200 retained on the source and drain regions 130, the method further includes forming a second oxide layer 520 on the surface of the substrate 100 using a thermal oxidation process. Specifically, the second oxide layer 520 is formed to cover the inner wall of the isolation trench 400, the high-voltage region 110 and the source and drain regions 130. The second oxide layer 520 is formed by high-temperature oxidation of the substrate 100, which can repair damage to the surface of the substrate 100 and improve electrical parameters. The second oxide layer 520 is thin and has high density. The thickness of the second oxide layer 520 is less than the height difference between the high-voltage region 110 and the source and drain regions 130. Preferably, the thickness of the second oxide layer 520 is less than half of the height difference between the high-voltage region 110 and the source and drain regions 130.

[0055] Please refer to Figure 15 and 16, perform step S5: deposit and form a first oxide layer 510 to fill the isolation trench 400 and cover the source and drain regions 130 and the high-voltage region 110, and then perform thermal annealing on the first oxide layer 510 to improve its density and improve defects; then, perform a chemical mechanical polishing process on the first oxide layer 510 to polish away the first oxide layer 510 on the source and drain regions 130 to expose the surface of the source and drain regions 130. After polishing, the surface of the first oxide layer 510 is flat, and the first oxide layer 510 on the high-voltage region 110 serves as a gate oxide layer.

[0056] In this embodiment, the silicon nitride layer is first etched so that the silicon nitride layer on the high-voltage area and the silicon nitride layer on the source and drain areas have a height difference, and then the substrate is etched using the silicon nitride layer as a mask to form an isolation trench. After etching, the high-voltage area and the source and drain areas have a height difference, and the top edge of the high-voltage area is arc-shaped, so that the edge of the high-voltage area does not have a warped foot, thereby solving the warped foot problem of the edge of the high-voltage area, and after forming a first oxide layer to fill the isolation trench and cover the high-voltage area, the surface of the first oxide layer is flat, which is conducive to the subsequent preparation of the window; and in the prior art, a mask (two masks) is used when etching to form the isolation trench and etching the high-voltage area. In this embodiment, a mask (two masks) is used when etching the silicon nitride layer in the isolation area and the silicon nitride layer of the silicon nitride in the high-voltage area. Therefore, this embodiment does not require a new mask and will not increase the preparation cost.

[0057] Example 2 Please refer to Figure 17 and Figure 18 The difference between this embodiment and the first embodiment is that in step S2, the entire silicon nitride layer 200 on the isolation region 120 is etched away (the silicon nitride layer 200 is not retained, refer to Figure 17 ), and in step S3, a second patterned photoresist layer 320 is formed to cover the silicon nitride layer 200 on the source and drain regions 130 and the isolation region 120 (the second patterned photoresist layer 320 is in direct contact with the isolation region 120, refer to Figure 18 Therefore, since the silicon nitride layer 200 is not retained on the isolation region 120, this embodiment does not require additional etching to remove the silicon nitride layer 200 retained on the isolation region 120 as in the first embodiment.

[0058] For details, please refer to Figure 17 The step of etching and removing the silicon nitride layer 200 on the isolation region 120 includes: forming a first patterned photoresist layer 310 to cover the silicon nitride layer 200 on the high-voltage region 110 and the source and drain region 130; then, using the first patterned photoresist layer 310 as a mask, etching and removing the silicon nitride layer 200 on the isolation region 120, and then removing the first patterned photoresist layer 310.

[0059] Please refer to Figure 18The step of etching away a portion of the thickness of the silicon nitride layer 200 on the high-voltage region 110 includes: forming a second patterned photoresist layer 320 to cover the silicon nitride layer 200 on the source and drain regions 130 and the isolation region 120; then, using the second patterned photoresist layer 320 as a mask, etching away a portion of the thickness of the silicon nitride layer 200 on the high-voltage region 110, after etching, the silicon nitride layer 200 on the high-voltage region 110 and the silicon nitride layer 200 on the source and drain regions 130 have a height difference, specifically, the top surface of the silicon nitride layer 200 on the high-voltage region 110 is lower than the top surface of the silicon nitride layer 200 on the source and drain regions 130 (the height difference between the two top surfaces is h1); then, removing the second patterned photoresist layer 320.

[0060] In summary, the preparation method of the semiconductor device provided by the present invention includes: providing a substrate, the substrate including a high-voltage region, a source and drain region, and an isolation region; forming a silicon nitride layer to cover the substrate, and etching to remove at least part of the thickness of the silicon nitride layer on the isolation region; etching to remove part of the thickness of the silicon nitride layer on the high-voltage region, and after etching, the silicon nitride layer on the high-voltage region and the silicon nitride layer on the source and drain region have a height difference; etching the substrate using the silicon nitride layer as a mask to form an isolation trench in the isolation region, and the silicon nitride layer on the high-voltage region is synchronously etched and removed, and after etching, the high-voltage region and the source and drain region have a height difference, and the top edge of the high-voltage region is arc-shaped; forming a first oxide layer to fill the isolation trench and cover the high-voltage region, and the surface of the first oxide layer is flat, and the first oxide layer on the high-voltage region serves as a gate oxide layer. The unexpected technical effect of the present invention is that by first etching the silicon nitride layer, the silicon nitride layer on the high-voltage area and the silicon nitride layer on the source and drain areas have a height difference, and then the substrate is etched using the silicon nitride layer as a mask to form an isolation trench. After etching, the high-voltage area and the source and drain areas have a height difference, and the top edge of the high-voltage area is arc-shaped, so that the edge of the high-voltage area will not have a curled foot, thereby solving the curled foot problem of the edge of the high-voltage area, and after forming a first oxide layer to fill the isolation trench and cover the high-voltage area, the surface of the first oxide layer is flat, and the present invention does not require a new mask, and will not increase the preparation cost.

[0061] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, wherein the substrate includes a high voltage region, a source / drain region, and an isolation region; forming a silicon nitride layer to cover the substrate, and etching away at least a portion of the thickness of the silicon nitride layer on the isolation region; Etching and removing a portion of the thickness of the silicon nitride layer on the high voltage region, so that after etching, there is a height difference between the silicon nitride layer on the high voltage region and the silicon nitride layer on the source and drain regions; The substrate is etched using the silicon nitride layer as a mask to form an isolation trench in the isolation region, and the silicon nitride layer on the high-voltage region is simultaneously etched and removed, wherein after etching, there is a height difference between the high-voltage region and the source and drain regions, and the top edge of the high-voltage region is curved; A first oxide layer is formed to fill the isolation trench and cover the high-voltage region, and the surface of the first oxide layer is flat. The first oxide layer on the high-voltage region serves as a gate oxide layer.

2. The method for preparing a semiconductor device according to claim 1, wherein: The step of etching and removing a portion of the thickness of the silicon nitride layer on the isolation region comprises: forming a first patterned photoresist layer covering the silicon nitride layer on the high voltage region and the source / drain region; Using the first patterned photoresist layer as a mask, etching and removing a portion of the thickness of the silicon nitride layer on the isolation region; The first patterned photoresist layer is removed.

3. The method for preparing a semiconductor device according to claim 2, wherein: The step of etching and removing a portion of the thickness of the silicon nitride layer on the high voltage area comprises: forming a second patterned photoresist layer to cover the silicon nitride layer on the isolation region and the source / drain region; Using the second patterned photoresist layer as a mask, etching away a portion of the thickness of the silicon nitride layer on the high-voltage region, wherein after etching, the thickness of the silicon nitride layer on the high-voltage region is between the thickness of the silicon nitride layer on the isolation region and the thickness of the silicon nitride layer on the source and drain regions; The second patterned photoresist layer is removed.

4. The method for preparing a semiconductor device according to claim 2, wherein: Before etching the substrate using the silicon nitride layer as a mask, the method further includes etching away the remaining thickness of the silicon nitride layer on the isolation region.

5. The method for preparing a semiconductor device according to claim 1, wherein: The step of etching and removing the silicon nitride layer on the isolation region comprises: forming a first patterned photoresist layer covering the silicon nitride layer on the high voltage region and the source / drain region; Using the first patterned photoresist layer as a mask, etching and removing the silicon nitride layer on the isolation region; The first patterned photoresist layer is removed.

6. The method for preparing a semiconductor device according to claim 5, wherein: The step of etching and removing a portion of the thickness of the silicon nitride layer on the high voltage area comprises: forming a second patterned photoresist layer to cover the silicon nitride layer on the source and drain regions and the isolation region; Using the second patterned photoresist layer as a mask, etching and removing a portion of the thickness of the silicon nitride layer above the high voltage area; The second patterned photoresist layer is removed.

7. The method for preparing a semiconductor device according to claim 1, wherein: After the substrate is etched using the silicon nitride layer as a mask, a portion of the silicon nitride layer remains on the source and drain regions.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: After etching the substrate using the silicon nitride layer as a mask, the method further includes removing the silicon nitride layer remaining on the source and drain regions.

9. The method for preparing a semiconductor device according to claim 8, wherein: After removing the silicon nitride layer retained on the source and drain regions, the method further includes forming a second oxide layer on the surface of the substrate using a thermal oxidation process.

10. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming the first oxide layer to fill the isolation trench and cover the high voltage area includes: Depositing and forming the first oxide layer to fill the isolation trench and cover the source / drain region and the high voltage region; A chemical mechanical polishing process is performed on the first oxide layer to polish and remove the first oxide layer on the source and drain regions to expose surfaces of the source and drain regions.

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