Formation method of semiconductor structure
By forming a protective layer structure at the junction of the semiconductor structure to block the removal of the first work function layer, the problems of adjacent area damage and threshold voltage offset in the prior art are solved, improving electrical performance and reducing production costs.
Patent Information
- Application Number
- CN202410391756.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-01
- Publication Date
- 2025-10-21
AI Technical Summary
Existing techniques for removing the gate dielectric layer of transistors in semiconductor structures can easily lead to damage to adjacent areas and threshold voltage shifts, affecting electrical performance.
During the formation of a semiconductor structure, a protective layer structure is formed at the junction, with its top higher than the top of the channel structure layer, to isolate the first device region from the second device region. The first work function layer is then removed using a maskless etching process, reducing the impact on adjacent areas.
It reduces the risk of damage to the adjacent area, improves the threshold voltage offset, enhances the electrical performance of the semiconductor structure, and reduces production costs.
Smart Images
Figure CN120826014A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving towards higher component density and higher integration. Semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the component density and integration of semiconductor devices increase, the size of transistors must continue to shrink to accommodate the reduction in process nodes.
[0003] Therefore, in order to better adapt to the requirements of device size scaling, semiconductor processes have gradually begun to transition from planar transistors to three-dimensional transistors with higher power efficiency, such as FinFET (Field-Effect Transistor) and Gate-all-around (GAA) transistors. Among them, gate-all-around transistors include vertical gate-all-around transistors and horizontal gate-all-around transistors. In a gate-all-around transistor, the gate surrounds the area where the channel is located from all sides. Compared with planar transistors, the gate of a gate-all-around transistor has stronger control over the channel and can better suppress the short channel effect.
[0004] As device sizes continue to shrink, improving the performance of all-around gate structure devices becomes increasingly difficult and challenging. Summary of the Invention
[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is conducive to further improving the performance of the semiconductor structure.
[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including adjacent first and second device regions, and a channel structure layer suspended on the substrate, the channel structure layer including one or more channel layers spaced sequentially from bottom to top; forming a gate dielectric layer on the surface of the channel layer in the first and second device regions; forming a protective layer structure at the junction of the first device region and the second device region, and the top of the protective layer structure is higher than the top of the channel structure layer; forming a first work function layer on the surface of the gate dielectric layer in the first and second device regions; after forming the protective layer structure, removing the first work function layer in the first device region.
[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0008] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising forming a gate dielectric layer on the surface of the channel layer in the first device region and the second device region; forming a protective layer structure at the junction of the first device region and the second device region, with the top of the protective layer structure being higher than the top of the channel structure layer; forming a first work function layer on the surface of the gate dielectric layer in the first device region and the second device region; and removing the first work function layer in the first device region after forming the protective layer structure. Therefore, during the process of removing the first work function layer in the first device region, since the protective layer structure is located at the junction of the first device region and the second device region, and the top of the protective layer structure is higher than the top of the channel structure layer, the protective layer structure can serve to block the first device region from the second device region, thereby reducing the impact of the process of removing the first work function layer in the first device region on the second device region, thereby reducing the loss of the first work function layer in the second device region, correspondingly reducing the risk of damage to the gate dielectric layer in the second device region, improving the threshold voltage offset problem between the first device region and the second device region, and thereby improving the electrical performance of the semiconductor structure.
[0009] In an optional solution, the step of forming the protective layer structure at the junction of the first device region and the second device region includes: forming a first protective layer in the first device region and the second device region to conformally cover the substrate and the channel structure layer, with the first protective layer between adjacent channel structure layers forming a groove; forming a second protective layer in the first device region and the second device region to fill the groove; removing the first protective layer from the side of the second protective layer, and the remaining stack of the first protective layer and the second protective layer serving as the protective layer structure. In an embodiment of the present invention, the groove is formed by the conformal covering first protective layer, and the groove is filled with the second protective layer, so that the protective layer structure formed by the first protective layer on the side of the second protective layer can be removed using a maskless etching process, thereby eliminating the need for additional masks during the process of forming the protective layer structure, thereby reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figures 1 to 7 A schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;
[0011] Figures 8 to 21 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0012] Currently, the performance of semiconductor structures still needs to be improved. This paper analyzes the reasons why the performance of semiconductor structures needs to be improved by combining a method for forming a semiconductor structure. Figures 1 to 7 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.
[0013] refer to Figure 1 A substrate 10 is provided, wherein the substrate 10 includes adjacent first device regions I' and second device regions II', and a channel structure layer 11 suspended on the substrate 10, wherein the channel structure layer 11 includes one or more channel layers 12 spaced apart from each other from bottom to top; a gate dielectric layer 13 is formed on the surface of the channel layer 12 of the first device region I' and the second device region II', and a first work function layer 14 surrounding and covering the gate dielectric layer 13.
[0014] refer to Figure 2 A mask layer 15 covering the first work function layer 14 is formed on the substrate 10 where the channel layer 12 is exposed.
[0015] refer to Figure 3 In the first device region I', the mask layer 15 covering the channel structure layer 11 is removed.
[0016] refer to Figure 4 After removing the mask layer 15 covering the channel structure layer 11, in the first device region I', the mask layer 15 located between adjacent channel layers 12 and the mask layer 15 between the channel layer 12 and the substrate 10 are removed.
[0017] refer to Figure 5 , remove the first work function layer 14 of the first device region I'.
[0018] refer to Figure 6 After removing the first work function layer 14 of the first device region I', the mask layer 15 of the second device region II' is removed.
[0019] refer to Figure 7 A second work function layer 16 covering the surface of the gate dielectric layer 13 is formed in the first device region I′, and the second work function layer 16 also covers the first work function layer 14 in the second device region II′.
[0020] The research found that Figure 4As shown, in order to remove the mask layer 15 located between adjacent channel layers 12 and the mask layer 15 between the channel layer 12 and the substrate 10, a lateral etching process is usually used to remove the remaining mask layer 15. The lateral etching process is likely to cause excessive consumption of the mask layer 15 of the second device region II', and accordingly, the risk of the first work function layer 14 of the second device region II' being exposed is increased. In the subsequent step of removing the first work function layer 14 of the first device region I', the probability of the first work function layer 14 in the second device region II' being damaged is increased, thereby increasing the risk of damage to the gate dielectric layer 13 in the second device region II', causing the threshold voltage (Vt) of the first device region I' and the second device region II' to shift, thereby affecting the electrical performance of the semiconductor structure.
[0021] In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first device region and a second device region adjacent to each other, and a channel structure layer suspended on the substrate, the channel structure layer including one or more channel layers spaced apart from bottom to top; forming a gate dielectric layer on the surface of the channel layer in the first device region and the second device region; forming a protective layer structure at the junction of the first device region and the second device region, and the top of the protective layer structure is higher than the top of the channel structure layer; forming a first work function layer on the surface of the gate dielectric layer in the first device region and the second device region; after forming the protective layer structure, removing the first work function layer in the first device region.
[0022] In the solution disclosed in the embodiment of the present invention, in the process of removing the first work function layer of the first device area, since the protective layer structure is located at the junction of the first device area and the second device area, and the top of the protective layer structure is higher than the top of the channel structure layer, the protective layer structure can play a role in blocking the first device area and the second device area, which is beneficial to reducing the impact of the process of removing the first work function layer of the first device area on the second device area, thereby reducing the loss of the first work function layer in the second device area, and correspondingly reducing the risk of damage to the gate dielectric layer in the second device area, improving the problem of threshold voltage offset between the first device area and the second device area, and thereby improving the electrical performance of the semiconductor structure.
[0023] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0024] Figures 8 to 21 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0025] refer to Figure 8, providing a substrate 20, the substrate 20 includes a first device region I and a second device region II adjacent to each other, and a channel structure layer 21 suspended on the substrate 20, the channel structure layer 21 includes one or more channel layers 22 spaced apart from each other in sequence from bottom to top.
[0026] Substrate 20 provides a process platform for subsequent process steps. In this embodiment, substrate 20 is used to form a fully enclosed gate transistor. In other embodiments, the substrate can also be used to form a forksheet transistor or a complementary field-effect transistor (CFET).
[0027] In this embodiment, the base 20 is a three-dimensional structure, comprising a substrate 201 and protruding structures 202 separated from the substrate 201 in the first device region I and the second device region II. Specifically, the protruding structures 202 may be fins protruding from the substrate 201.
[0028] In this embodiment, the material of the substrate 201 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
[0029] In this embodiment, the raised structure 202 and the substrate 201 are integrally formed, i.e., the raised structure 202 and the substrate 201 are etched from the same semiconductor material in the same step. In other embodiments, the raised structure and the substrate may not be integrally formed, and the raised structure may be epitaxially grown on the semiconductor layer on the substrate, thereby achieving precise control of the raised structure height.
[0030] Therefore, in this embodiment, the material of the raised structure 202 is the same as that of the substrate 201, that is, silicon. In other embodiments, the material of the raised structure 202 may be a semiconductor material suitable for forming a fin, such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the raised structure may also be different from that of the substrate.
[0031] In this embodiment, the devices formed in the first device region I and the devices formed in the second device region II have different channel conductivity types. Specifically, because the devices formed in the first device region I and the devices formed in the second device region II have different channel conductivity types, the devices formed in the first device region I and the devices formed in the second device region II perform different functions. That is, the chip formed by the first device region I and the second device region II can perform multiple functions, thereby improving the multifunctionality of the chip.
[0032] At the same time, precisely because the channel conductivity types of the device formed in the first device region I and the device formed in the second device region II are different, the work function layers subsequently formed in the first device region I and the second device region II are usually not exactly the same, for example, different materials, different thicknesses, or different film layer stacking types.
[0033] In this embodiment, the first device region I is used to form a first-type transistor, and the second device region II is used to form a second-type transistor. The first-type transistor and the second-type transistor have different channel conductivity types. Specifically, the first-type transistor is an NMOS transistor, and the second-type transistor is a PMOS transistor. In other embodiments, the first-type transistor is a PMOS transistor, and the second-type transistor is an NMOS transistor.
[0034] In this embodiment, both the first-type transistor and the second-type transistor are all-around-gate transistors.
[0035] It should be noted that, in other embodiments, the threshold voltage (Vt) of the device formed in the first device area and the device formed in the second device area may be different. In this case, the channel conductivity type of the device formed in the first device area and the device formed in the second device area may be the same or different.
[0036] In this embodiment, the channel structure layer 21 is used to provide a conductive channel of the field effect transistor. Specifically, the channel layer 22 provides a conductive channel of the field effect transistor.
[0037] In this embodiment, the material of the channel layer 22 includes one or more of silicon, silicon germanium, germanium, and Group III-V semiconductor materials. The material of the channel layer 22 is determined according to the channel conductivity type and performance requirements of the transistor.
[0038] In this embodiment, the method for forming a semiconductor structure further includes: forming an isolation layer 28 surrounding the protrusion structure 202 on the substrate 201 , wherein the isolation layer 28 exposes the channel structure layer 21 .
[0039] In this embodiment, the isolation layer 28 is used to electrically isolate adjacent devices. Specifically, the isolation layer 28 serves as a shallow trench isolation (STI) structure.
[0040] In this embodiment, the isolation layer 28 may be made of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
[0041] Continue to refer Figure 8 , a gate dielectric layer 23 is formed on the surface of the channel layer 22 in the first device region I and the second device region II.
[0042] The gate dielectric layer 23 is a part of the gate structure and is used to isolate the gate electrode layer and the channel in the gate structure. In addition, the gate dielectric layer 23 is used to reduce the probability of leakage in the semiconductor structure, thereby improving the reliability of the semiconductor structure.
[0043] The material of the gate dielectric layer 23 may be selected from one or more of HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 , SiO 2 and La 2 O 3 .
[0044] In this embodiment, the gate dielectric layer 23 is made of a high-K dielectric material. It should be noted that a high-K dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-K gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. As an example, the gate dielectric layer 23 is made of HfO2.
[0045] refer to Figures 9 to 12 A protection layer structure 26 is formed at the junction of the first device region I and the second device region II, and the top of the protection layer structure 26 is higher than the top of the channel structure layer 21.
[0046] The protection structure 26 is used to block the first device region I and the second device region II during the process of removing the first work function layer of the first device region I.
[0047] Since the protective layer structure 26 is located at the junction of the first device region I and the second device region II, and the top of the protective layer structure 26 is higher than the top of the channel structure layer 21, in the process of removing the first work function layer of the first device region I, the protective layer structure 26 can play a role in blocking the first device region I and the second device region II, which is beneficial to reducing the impact of the process of removing the first work function layer of the first device region I on the second device region II, thereby reducing the loss of the first work function layer in the second device region II, and correspondingly reducing the risk of damage to the gate dielectric layer 23 in the second device region II, improving the problem of threshold voltage offset between the first device region I and the second device region II, and thereby improving the electrical performance of the semiconductor structure.
[0048] Specifically, the step of forming the protective layer structure 26 at the junction of the first device region I and the second device region II includes: referring to Figure 9 , forming a first protective layer 26A conformally covering the substrate 20 and the channel structure layer 21 in the first device region I and the second device region II, and the first protective layer 26A between adjacent channel structure layers 21 forms a groove 27; Figures 10 and 11, forming a second protective layer 26B filling the groove 27 in the first device region I and the second device region II; Figure 12 , the first protective layer 26A on the side of the second protective layer 26B is removed, and the remaining stack of the first protective layer 26A and the second protective layer 26B serves as the protective layer structure 26.
[0049] It should be noted that a groove 27 is formed by a conformal covering first protective layer 26A, and a second protective layer 26B is filled in the groove 27, so that the first protective layer 26A on the side of the second protective layer 26B can be removed by a maskless etching process, so that no additional mask is required in the process of forming the protective layer structure 26, thereby reducing production costs.
[0050] Moreover, the first protective layer 26A between adjacent channel structure layers 21 forms a groove 27, that is, the lateral width of the groove 27 can be adjusted by the thickness of the first protective layer 26A, thereby adjusting the lateral width of the protective layer structure 26, which is beneficial to avoid the limitation of the lateral width of the protective layer structure 26 by the limit of lithography resolution.
[0051] Specifically, the step of forming the second protection layer 26B filling the groove 27 in the first device region I and the second device region II includes: referring to Figure 10 , forming a second protective material layer 26C filling the groove 27 in the first device region I and the second device region II; Figure 11 , taking the top of the first protective layer 26A as the stopping position, the second protective material layer 26C is planarized, and the remaining second protective material layer 26C serves as the second protective layer 26B.
[0052] It should be noted that the top of the first protective layer 26A is used as the stopping position, and the second protective material layer 26C is flattened, that is, the top of the first protective layer 26A is exposed to facilitate the subsequent removal of the first protective layer 26A on the side of the second protective layer 26B, thereby improving the quality of the protective layer structure 26. At the same time, the second protective material layer 26C is flattened to form the second protective layer 26B, which is beneficial to improving the lateral dimensional accuracy of the second protective layer 26B.
[0053] In this embodiment, the process of planarizing the second protective material layer 26C includes a chemical mechanical polishing process.
[0054] Specifically, the chemical mechanical polishing process can reduce surface roughness, improve device reliability, speed, and yield, and improve step coverage and remove surface defects. This results in a relatively flat surface formed by the top surface of second protective layer 26B and first protective layer 26A, with a low probability of surface damage, thereby improving the reliability of subsequent processes.
[0055] In this embodiment, the process of forming the first protection layer 26A conformally covering the substrate 20 and the channel structure layer 21 in the first device region I and the second device region II includes an atomic layer deposition process.
[0056] The atomic layer deposition process has the characteristics of good gap filling performance and step coverage. Therefore, the first protective layer 26A formed by the atomic layer deposition process is of high quality and good thickness uniformity, which is correspondingly beneficial to improving the formation quality of the first protective layer 26A.
[0057] In this embodiment, the process of forming the second protection layer 26B filling the groove 27 in the first device region I and the second device region II includes a fluid chemical vapor deposition process.
[0058] The fluid chemical vapor deposition process has good gap filling capabilities and is suitable for filling spaces with high aspect ratios. It is beneficial to reduce the probability of defects such as voids in the second protective layer 26B, thereby correspondingly improving the quality of the second protective layer 26B, and further improving the quality of the protective layer structure 26, thereby correspondingly improving the barrier capability of the protective layer structure 26.
[0059] In this embodiment, the material of the first protective layer 26A includes silicon nitride, and the material of the second protective layer 26B includes silicon oxide.
[0060] It should be noted that silicon nitride and silicon oxide have a high selectivity ratio. In the subsequent process of removing the first protective layer 26A on the side of the second protective layer 26B, by setting the material of the first protective layer 26A to silicon nitride and the material of the second protective layer 26B to silicon oxide, the impact of the process of removing the first protective layer 26A on the second protective layer 26B can be effectively reduced, thereby improving the quality of the second protective layer 26B and correspondingly improving the quality of the protective layer structure 26.
[0061] Moreover, this also facilitates the use of the etching selectivity ratio between the second protective layer 26B and the first protective layer 26A to remove the first protective layer 26A on the side of the second protective layer 26B using a maskless etching process.
[0062] Specifically, the process of removing the first protective layer 26 from the side of the second protective layer 26B includes an anisotropic dry etching or wet etching process. It is understood that during the step of removing the first protective layer 26 from the side of the second protective layer 26B, a high selectivity is achieved between the first protective layer 26 and the second protective layer 26B, thereby minimizing damage to the second protective layer 26B.
[0063] It should be noted that in the step of forming the protective layer structure 26 at the junction of the first device region I and the second device region II, the value h by which the top of the protective layer structure 26 is higher than the top of the channel structure layer 21 should not be too large or too small. If the value h by which the top of the protective layer structure 26 is higher than the top of the channel structure layer 21 is too large, the depth-to-width ratio of the protective layer structure 26 is likely to be large, which may increase the probability of collapse of the protective layer structure 26. If the value h by which the top of the protective layer structure 26 is higher than the top of the channel structure layer 21 is too small, the protective layer structure 26 may not effectively block the first device region I from the second device region II during the removal of the first work function layer in the first device region I, thereby increasing the risk of loss of the first work function layer in the second device region II and, correspondingly, increasing the risk of damage to the gate dielectric layer 23 in the second device region II. Therefore, in this embodiment, the top of the protective layer structure 26 is 2nm to 10nm higher than the top of the channel structure layer 21.
[0064] It should also be noted that in the step of forming the protective layer structure 26 at the junction of the first device region I and the second device region II, with the arrangement direction of the first device region I and the second device region II as the horizontal direction, the lateral dimension w of the protective layer structure 26 should not be too large or too small. If the lateral dimension w of the protective layer structure 26 is too large, it is easy to cause part of the protective layer structure 26 to remain on the isolation layer 28 during the subsequent removal of the protective structure 26, making the surface of the isolation layer 28 uneven and affecting the reliability of the subsequent process. If the lateral dimension w of the protective layer structure 26 is too small, it is easy to cause the protective layer structure 26 to be ineffective in blocking the first device region I and the second device region II during the removal of the first work function layer of the first device region I, thereby increasing the risk of loss of the first work function layer in the second device region II, and correspondingly increasing the risk of damage to the gate dielectric layer 23 in the second device region II. Therefore, in this embodiment, the lateral dimension w of the protective layer structure 26 is 2nm to 5nm.
[0065] In one embodiment, since the first work function layer is formed after the protective layer structure 26 is formed, reasonably setting the lateral dimension w of the protective layer structure 26 and the value h at which the top of the protective layer structure 26 is higher than the top of the channel structure layer 21 is beneficial to providing a sufficient process window for forming the first work function layer.
[0066] It is understood that in other embodiments, the material layer of the protective layer structure may be patterned by photolithography and etching processes as needed to form a protective layer structure protruding at the junction of the first device region I and the second device region II. Accordingly, in this case, the protective layer structure may also be a single-layer structure.
[0067] refer to Figure 13 , forming a first work function layer 24 on the surface of the gate dielectric layer 23 in the first device region I and the second device region II.
[0068] The first work function layer 24 is used to adjust the threshold voltage of the device in the second device region II.
[0069] In this embodiment, the material of the first work function layer 24 includes titanium nitride or tantalum nitride. The material of the first work function layer 24 is determined according to the performance of the device in the second device region II.
[0070] Specifically, titanium nitride or tantalum nitride is a commonly used material for the work function layer, and thus has the characteristic of low process cost.
[0071] In this embodiment, the first work function layer 24 is formed after the protective layer structure 26 is formed, thereby reducing damage to the first work function layer 24 caused by the process of forming the protective layer structure 26 .
[0072] For example, since the first protective layer 26A needs to be removed during the formation of the protective layer structure 26, the first work function layer 24 is formed after the protective layer structure 26 is formed. This can reduce the probability of the first work function layer 24 in the second device area II being lost during the removal of the first protective layer 26A, thereby improving the quality of the first work function layer 24 in the second device area II.
[0073] Moreover, since the first work function layer 24 is formed after the protective layer structure 26 is formed, the first work function layer 24 will not be formed at the junction of the first device area I and the second device area II under the blocking of the protective layer structure 26. Therefore, after the first work function layer 24 of the first device area I is subsequently removed, it is beneficial to ensure the removal effect of the first work function layer 24 in the first device area I.
[0074] It should be noted that, in other embodiments, according to actual needs, a protection layer structure protruding at the junction of the first device region and the second device region may also be formed after the first work function layer is formed.
[0075] Combined with reference Figures 14 to 17 In this embodiment, after the protection layer structure 26 is formed, the first work function layer 24 of the first device region I is removed.
[0076] It should be noted that the protective layer structure 26 is located at the junction of the first device area I and the second device area II, and the top of the protective layer structure 26 is higher than the top of the channel structure layer 21. Therefore, after the protective structure 26 is formed, during the process of removing the first work function layer 24 of the first device area I, the protective structure 26 can block the first device area I and the second device area II, that is, it can protect the first work function layer 24 of the second device area II, thereby reducing the loss of the first work function layer 24 in the second device area II.
[0077] In this embodiment, the step of removing the first work function layer 24 of the first device region I includes: referring to Figure 14 , forming a mask material layer 29A covering the first device region I and the second device region II, wherein the mask material layer 29A covers the protection layer structure 26; Figures 15 and 16 , removing the mask material layer 29A of the first device region I to form a mask layer 29, wherein the mask layer 29 at least covers the sidewall of the protection layer structure 26 facing the second device region II; Figure 17 , removing the first work function layer 24 of the first device region I exposed by the mask layer 29.
[0078] Specifically, after the protection layer structure 26 is formed, a mask layer 29 is formed, and the mask layer 29 at least covers the sidewall of the protection layer structure 26 facing the second device region II.
[0079] It should be noted that since the mask layer 29 is formed after the protective layer structure 26 is formed, in the subsequent process of removing the mask material layer 29A of the first device area I, the protective layer structure 26 blocks the first device area I and the second device area II, thereby reducing the sidewall loss of the mask layer 29 of the second device area II. Further, in the subsequent process of removing the first work function layer 24 in the first device area I, the mask layer 29 located in the second device area II protects the first work function layer 24, thereby reducing the risk of damage to the first work function layer 24 in the second device area II.
[0080] In which, the mask layer 29 at least covers the side wall of the protective layer structure 26 facing the second device region II, thereby reducing the probability of a gap appearing between the side wall of the protective layer structure 26 and the mask layer 29, and further reducing the probability of the mask layer 29 being damaged through the gap during the subsequent removal of the mask material layer 29A of the first device region I.
[0081] In this embodiment, the mask layer 29 covers a portion of the top of the protection layer structure 26 , thereby increasing the process window when patterning the mask material layer 29A to form the mask layer 29 .
[0082] In this embodiment, the mask material layer 29A includes a first mask layer 29B located on top of the first device region I and the second device region II, and a second mask layer 29C located on top of the first mask layer 29B.
[0083] In this embodiment, the material of the first mask layer 29B includes a bottom anti-reflective coating (BARC), and the material of the second hard mask layer 29C includes a low temperature oxide (LTO).
[0084] It should be noted that BARC is used to reduce the amount of light reflected back to the mask layer 29A from the surface of the substrate 20 during the exposure process of forming the mask layer 29, so as to reduce the standing wave effect. At the same time, LTO is used to provide a uniform surface, which helps to further reduce the reflection of light on the surface of the substrate 20, thereby further reducing the standing wave effect and obtaining better quality of the mask layer 29.
[0085] In this embodiment, the mask material layer 29A in the first device region I is removed by photolithography and etching processes to form a mask layer 29 .
[0086] In this embodiment, the step of removing the mask material layer 29A of the first device area I to form the mask layer 29 includes: longitudinally etching the mask material layer 29A of the first device area I by an anisotropic etching process; after performing the longitudinal etching, laterally etching the mask material layer 29A between adjacent channel layers 22 of the first device area I by an isotropic etching process.
[0087] Most of the mask material layer 29A of the first device area I is removed through an anisotropic etching process to ensure that the mask material layer 29A above the substrate 20 and above the channel structure layer 21 of the first device area I can be fully exposed, which can easily improve the effect of the subsequent lateral etching process of the mask material layer 29A between adjacent channel layers 22 of the first device area I.
[0088] The mask material layer 29A between adjacent channel layers 22 of the first device area I is laterally etched through an isotropic etching process, which is beneficial for completely removing the first work function layer 24 located between adjacent channel layers 22 and between the channel layer 22 and the substrate 20, and can easily improve the effect of subsequent removal of the first work function layer 24 of the first device area I.
[0089] It should be noted that, under the blocking effect of the protection layer structure 26 , the influence of the lateral etching performed in the first device region I on the second device region II is reduced.
[0090] Specifically, since the mask layer 29 at least covers the side wall of the protection layer structure 26 facing the second device region II, the lateral etching causes less loss to the mask layer 29 on the channel structure layer 21 covering the second device region II under the blocking effect of the protection layer structure 26.
[0091] In this embodiment, a wet etching process is adopted to remove the first work function layer 24 of the first device region I, which is conducive to completely removing the first work function layer 24 of the first device region I.
[0092] Continue to refer Figure 17 In the step of removing the first work function layer 24 of the first device region I, the second mask layer 29C is also removed.
[0093] refer to Figure 18 After removing the first work function layer 24 of the first device region I, the mask layer 29 of the second device region II is removed.
[0094] Specifically, the mask layer 29 in the second device region II is removed to fully expose the second device region II so that the subsequent second work function layer covers the first work function layer 24 in the second device region II. As an example, the remaining mask layer 29 in the second device region II is removed by an ashing process.
[0095] refer to Figure 19 After removing the first work function layer 24 of the first device region I, the method further includes: removing the protective layer structure 26.
[0096] Specifically, the protective layer structure 26 is removed so that the surface of the isolation layer 28 on the substrate 20 is flat, thereby improving the reliability of subsequent processes.
[0097] In this embodiment, the process of removing the protective layer structure 26 includes a dry etching process.
[0098] Specifically, the dry etching process has good selectivity and can etch the material of the protective layer structure 26 while reducing damage to other material film layers (for example, the isolation layer 28). At the same time, the dry etching process can accurately control the etching rate, thereby accurately removing the protective layer structure 26.
[0099] In this embodiment, the process parameters of the dry etching process include: the etching gas includes a mixed gas of CH2F2 and CH4, the volume ratio of the etching gas CH2F2:CH4 is 5:1 to 1:1, and the process time is 60s to 200s.
[0100] The volume ratio of the etching gas CH2F2:CH4 in the etching process should not be too large or too small. If the volume ratio of the etching gas in the etching process is too large, it is easy to increase the probability of damage to other film layers (for example, the isolation layer 28). If the volume ratio of the etching gas in the etching process is too small, it is easy to cause the residual of the protective layer structure 26, which in turn makes the surface of the isolation layer 28 uneven, affecting the reliability of subsequent processes. Therefore, in this embodiment, the volume ratio of the etching gas is 5:1 to 1:1.
[0101] The etching process time should be neither too long nor too short. If the etching process time is too long, the probability of damage to other film layers (e.g., the channel structure layer 21) is increased. If the etching process time is too short, the residual protective layer structure 26 will cause the surface of the isolation layer 28 to be uneven, affecting the reliability of subsequent processes. Therefore, in this embodiment, the process time is 60s to 200s.
[0102] refer to Figure 20 After removing the protective layer structure 26 , the method for forming the semiconductor structure further includes: forming a second work function layer 25 in the first device region I that covers the surface of the gate dielectric layer 23 .
[0103] The second work function layer 25 is used to adjust the threshold voltage of the device in the first device region I.
[0104] In this embodiment, the material of the second work function layer 25 includes titanium nitride or tantalum nitride. The material of the second work function layer 25 is determined according to the performance of the device in the first device region I.
[0105] Specifically, titanium nitride or tantalum nitride is a commonly used material for the work function layer, and thus has the characteristic of low process cost.
[0106] In this embodiment, in the step of forming the second work function layer 25 in the first device region I, the second work function layer 25 also covers the first work function layer 24 in the second device region II.
[0107] Specifically, the threshold voltage of the transistor is determined by the thickness of the work function layer. In this embodiment, the channel conductivity type of the device formed in the first device area I and the device formed in the second device area II are different, that is, the threshold voltage is different. Therefore, the second work function layer 25 also covers the first work function layer 24 of the second device area II to ensure that the work function layer thicknesses of the first device area I and the second device area II are different.
[0108] refer to Figure 21 After removing the first work function layer 24 of the first device region I, the method for forming the semiconductor structure further includes: forming a gate structure 30 that spans the channel structure layer 21 and surrounds the channel layer 22.
[0109] In this embodiment, when the device is operating, the gate structure 30 is used to control the opening and closing of the conductive channel. Specifically, the gate structure 30 is a metal gate structure.
[0110] In this embodiment, the gate structure 30 includes a gate dielectric layer 23 , a first work function layer 24 and a second work function layer 25 located on the gate dielectric layer 23 in the first device region I and the second device region II, and a gate electrode layer 31 located on the second work function layer 25 .
[0111] The gate electrode layer 31 is used for subsequent electrical connection with external structures.
[0112] In this embodiment, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.
[0113] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first device region and a second device region adjacent to each other, and a channel structure layer suspended on the substrate, the channel structure layer comprising one or more channel layers sequentially spaced from bottom to top; forming a gate dielectric layer on surfaces of the channel layer in the first device region and the second device region; forming a protective layer structure at the junction of the first device region and the second device region, wherein the top of the protective layer structure is higher than the top of the channel structure layer; forming a first work function layer on the surface of the gate dielectric layer in the first device region and the second device region; After forming the protection layer structure, the first work function layer in the first device region is removed.
2. The method for forming a semiconductor structure according to claim 1, wherein: After removing the first work function layer in the first device region, the method further includes: removing the protective layer structure.
3. The method for forming a semiconductor structure according to claim 2, wherein: After removing the protection layer structure, the method for forming a semiconductor structure further includes: forming a second work function layer in the first device region to cover the surface of the gate dielectric layer.
4. The method for forming a semiconductor structure according to claim 3, wherein: In the step of forming the second work function layer in the first device region, the second work function layer also covers the first work function layer in the second device region.
5. The method for forming a semiconductor structure according to claim 3, wherein: The material of the first work function layer and the material of the second work function layer both include titanium nitride or tantalum nitride.
6. The method for forming a semiconductor structure according to claim 2, wherein: The process of removing the protective layer structure includes a dry etching process.
7. The method for forming a semiconductor structure according to claim 6, wherein: The process parameters of the dry etching process include: the etching gas includes a mixed gas of CH2F2 and CH4, the volume ratio of the etching gas CH2F2:CH4 is 5:1 to 1:1, and the process time is 60s to 200s.
8. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the protective layer structure at the junction of the first device area and the second device area includes: forming a first protective layer conformally covering the substrate and the channel structure layer in the first device region and the second device region, wherein the first protective layer between adjacent channel structure layers forms a groove; forming a second protection layer filling the groove in the first device region and the second device region; The first protective layer on the side of the second protective layer is removed, and the remaining stack of the first protective layer and the second protective layer serves as the protective layer structure.
9. The method for forming a semiconductor structure according to claim 8, wherein: The process of forming the first protection layer conformally covering the substrate and the channel structure layer in the first device region and the second device region includes an atomic layer deposition process.
10. The method for forming a semiconductor structure according to claim 8, wherein: The process of forming the second protection layer filling the groove in the first device region and the second device region includes a fluid chemical vapor deposition process.
11. The method for forming a semiconductor structure according to claim 8, wherein: The material of the first protection layer includes silicon nitride, and the material of the second protection layer includes silicon oxide.
12. The method for forming a semiconductor structure according to claim 8, wherein: The step of forming a second protective layer filling the groove in the first device area and the second device area includes: forming a second protective material layer filling the groove in the first device area and the second device area; using the top of the first protective layer as a stopping position, flattening the top of the second protective material layer, and the remaining second protective material layer serves as a second protective layer.
13. The method for forming a semiconductor structure according to claim 12, wherein: The process of planarizing the second protective material layer includes a chemical mechanical polishing process.
14. The method for forming a semiconductor structure according to claim 1, wherein: The step of removing the first work function layer in the first device region includes: forming a mask material layer covering the first device region and the second device region, wherein the mask material layer covers the protection layer structure; removing the mask material layer in the first device region to form a mask layer, wherein the mask layer at least covers a sidewall of the protection layer structure facing the second device region; The first work function layer in the first device region exposed by the mask layer is removed.
15. The method for forming a semiconductor structure according to claim 14, wherein: The step of removing the mask material layer in the first device area to form a mask layer includes: vertically etching the mask material layer in the first device area through an anisotropic etching process; after performing the vertical etching, laterally etching the mask material layer between adjacent channel layers in the first device area through an isotropic etching process.
16. The method for forming a semiconductor structure according to any one of claims 1 to 15, wherein: In the step of forming a protection layer structure at the junction of the first device region and the second device region, the top of the protection layer structure is 2 nm to 10 nm higher than the top of the channel structure layer.
17. The method for forming a semiconductor structure according to any one of claims 1 to 15, wherein: In the step of forming a protection layer structure at the junction of the first device region and the second device region, with the arrangement direction of the first device region and the second device region as the lateral direction, the lateral dimension of the protection layer structure is 2 nm to 5 nm.
18. The method for forming a semiconductor structure according to any one of claims 1 to 15, wherein: After forming the protection layer structure, the first work function layer is formed.
19. The method for forming a semiconductor structure according to any one of claims 1 to 15, wherein: After removing the first work function layer in the first device region, the method for forming a semiconductor structure further includes: forming a gate structure that spans the channel structure layer and surrounds the channel layer.
20. The method for forming a semiconductor structure according to any one of claims 1 to 15, wherein: The device formed in the first device region and the device formed in the second device region have different channel conductivity types.