Light emitting device and display apparatus including same

Abstract

The light emitting element may include: a light emitting stack pattern including a first semiconductor layer, an active layer, and a second semiconductor layer; and an insulating film surrounding an outer peripheral surface of the light emitting stack pattern. The insulating film may include: a first layer; a second layer surrounding the first layer; and a third layer surrounding the second layer. The first layer and the third layer may include the same material.

Description

Technical Field

[0001] The present disclosure generally relates to a light emitting element and a display device including the same. Background Art

[0002] Recently, as interest in information display increases, research and development of display devices have been continuously conducted. Summary of the Invention

[0003] Technical issues

[0004] Embodiments provide a light emitting element having improved reliability and a display device including the same.

[0005] Technical Solution

[0006] According to aspects of the present disclosure, a light-emitting element is provided, which includes: a light-emitting stacking pattern including a first semiconductor layer, an active layer, and a second semiconductor layer; and an insulating film surrounding the outer peripheral surface of the light-emitting stacking pattern, wherein the insulating film includes: a first layer; a second layer surrounding the first layer; and a third layer surrounding the second layer, and wherein the first layer and the third layer include the same material.

[0007] The first layer and the third layer may include ZrO x 、SiO x 、HFO x 、BeO、Ta x O y 、Al x O y 、La x O y 、Nb x O y 、TiO x 、CeO x 、MgO、Y x O y and Sr x O y At least one of .

[0008] The first layer and the third layer may include AlN, AlGaN, InGaN, SiN x 、AlO x N y 、HfN、ZrN、HFO x N y and ZrO x N y At least one of .

[0009] The first layer may have a thickness of 5 nm or less, and the third layer may have a thickness of 10 nm or less.

[0010] The second layer may include a material different from that of the first and third layers.

[0011] The first layer may be directly disposed on an outer peripheral surface of each of the first semiconductor layer, the active layer, and the second semiconductor layer.

[0012] The first semiconductor layer may include an N-type semiconductor layer doped with an N-type dopant, and the second semiconductor layer may include a P-type semiconductor layer doped with a P-type dopant.

[0013] The light emitting stack pattern may further include an electrode layer disposed on the second semiconductor layer. The insulating film may be directly disposed on an outer peripheral surface of each of the first semiconductor layer, the active layer, the second semiconductor layer, and the electrode layer.

[0014] The insulating film may further include a fourth layer surrounding the third layer. The fourth layer may include an inorganic insulating material and may have a thickness thicker than that of each of the first to third layers.

[0015] The insulating film may further include a fifth layer surrounding the fourth layer. The fifth layer may include an inorganic insulating material and may have a thickness thicker than that of each of the first to fourth layers.

[0016] According to another aspect of the present disclosure, a light-emitting element is provided, which includes: a light-emitting stacking pattern, including a first semiconductor layer, an active layer, a second semiconductor layer and an electrode layer stacked in sequence along one direction; and an insulating film surrounding the outer peripheral surface of the light-emitting stacking pattern, wherein the insulating film includes: a first layer, directly arranged on the outer peripheral surface of the light-emitting stacking pattern to surround the light-emitting stacking pattern; a second layer, surrounding the first layer; a third layer, surrounding the second layer; a fourth layer, surrounding the third layer; and a fifth layer, surrounding the fourth layer, and wherein the first layer and the third layer include the same material, and the second layer includes a material different from the materials of the first layer and the third layer.

[0017] The first layer and the third layer may include ZrO x 、SiO x 、HFO x 、BeO、Ta x O y 、Al x O y 、La x O y 、Nb x O y 、TiO x 、CeO x 、MgO、Y x O y and Sr x O y At least one of .

[0018] The first layer and the third layer may include AlN, AlGaN, InGaN, SiN x 、AlO x N y 、HfN、ZrN、HfO x N y and ZrO x N y At least one of .

[0019] The first layer may have a thickness of 5 nm or less, and the third layer may have a thickness of 10 nm or less.

[0020] The fourth layer and the fifth layer may include an inorganic insulating material.

[0021] According to another aspect of the present disclosure, a display device is provided, which includes: a substrate; a first electrode and a second electrode, which are arranged on the substrate to be spaced apart from each other; and a light-emitting element, which is located on the substrate, the light-emitting element including a first end electrically connected to the first electrode and a second end electrically connected to the second electrode, wherein the light-emitting element includes: a light-emitting stacking pattern, including a first semiconductor layer located at the second end, an active layer arranged on the first semiconductor layer, a second semiconductor layer arranged on the active layer, and an electrode layer arranged on the second semiconductor layer and located at the first end; and an insulating film, which surrounds the outer peripheral surface of the light-emitting stacking pattern, wherein the insulating film includes: a first layer, which is directly arranged on the outer peripheral surface of the light-emitting stacking pattern; a second layer, which surrounds the first layer; and a third layer, which surrounds the second layer, and wherein the first layer and the third layer include the same material, and the second layer includes a material different from the materials of the first layer and the third layer.

[0022] The first layer and the third layer may include ZrO x 、SiO x 、HFO x 、BeO、Ta x O y 、Al x O y 、La x O y 、Nb x O y 、TiO x 、CeO x 、MgO、Y x O y and Sr x O y At least one of .

[0023] The first layer and the third layer may include AlN, AlGaN, InGaN, SiN x 、AlO x Ny 、HfN、ZrN、HfO x N y and ZrO x N y At least one of .

[0024] The first layer may have a thickness of 5 nm or less, and the third layer may have a thickness of 10 nm or less.

[0025] The display device may further include: an emission area and a non-emission area, in which light is emitted from the light-emitting element, and the non-emission area surrounds the emission area; a first alignment electrode arranged between the substrate and the first electrode, the first alignment electrode electrically connected to the first electrode; a second alignment electrode arranged between the substrate and the second electrode, the second alignment electrode electrically connected to the second electrode; a first dam located in the non-emission area, the first dam including an opening corresponding to the emission area; a second dam located on the first dam; a color conversion layer surrounded by the second dam, the color conversion layer being located above the light-emitting element; and a color filter arranged on the color conversion layer.

[0026] Technical Effects

[0027] According to the present disclosure, a multilayer insulating film comprising a first layer, a second layer, and a third layer is provided on the outer peripheral surface of a light-emitting stack pattern comprising a first semiconductor layer, an active layer, and a second semiconductor layer, and the first layer and the third layer are configured using the same material. Consequently, surface defects in the light-emitting stack pattern are effectively controlled, and the protective layer properties of the insulating film are improved. Consequently, the lifespan and efficiency of the light-emitting element can be improved.

[0028] According to the present disclosure, a display device including the light emitting element described above can be provided.

[0029] The effects of the present disclosure are not limited to the foregoing, and other various effects are expected herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic perspective view of a light emitting element according to an embodiment of the present disclosure.

[0031] Figure 2 It is from Figure 1 Schematic diagram of the light-emitting element as viewed from the top shown in FIG.

[0032] Figure 3 yes Figure 1 Schematic cross-sectional view of a light emitting element shown in .

[0033] Figure 4 is a schematic perspective view of a light emitting element according to an embodiment of the present disclosure.

[0034] Figure 5 It is from Figure 4 Schematic diagram of the light-emitting element as viewed from the top shown in FIG.

[0035] Figure 6 yes Figure 3 Schematic cross-sectional view of a light emitting element shown in .

[0036] Figure 7 is a schematic perspective view of a light emitting element according to an embodiment of the present disclosure.

[0037] Figure 8 It is from Figure 7 Schematic diagram of the light-emitting element as viewed from the top shown in FIG.

[0038] Figure 9 yes Figure 5 Schematic cross-sectional view of a light emitting element shown in .

[0039] Figure 10 is a schematic plan view of a display device according to an embodiment of the present disclosure.

[0040] Figure 11 It is shown that the Figure 10 Schematic circuit diagram of the electrical connection relationship of components in each of the pixels shown in FIG.

[0041] Figure 12 is a schematic plan view illustrating a pixel according to an embodiment of the present disclosure.

[0042] Figure 13 and Figure 14 It is along Figure 12 Schematic cross-sectional view taken along line II' shown in FIG.

[0043] Figure 15 It shows Figure 13 Schematic enlargement of the portion EA shown in .

[0044] Figure 16 and Figure 17 is with Figure 12 The schematic cross-sectional view corresponding to the line II' shown in FIG. DETAILED DESCRIPTION

[0045] The present disclosure can be applied to various variations and different shapes, so only specific examples are used to explain it in detail. However, the examples are not limited to certain shapes, but are applicable to all variations and equivalent materials and replacements. The included drawings illustrate how the drawings are expanded for better understanding.

[0046] The same numbers always refer to the same elements. In the accompanying drawings, for clarity, the thickness of some lines, layers, components, elements or features may be exaggerated. It will be understood that although the terms "first", "second" and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present disclosure, the "first" element discussed below may also be referred to as the "second" element. As used herein, unless the context clearly indicates otherwise, the singular form is intended to also include the plural form.

[0047] It will also be understood that the terms "comprises" and / or "includes," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or parts, but do not preclude the presence and / or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof. Furthermore, a statement that an element, such as a layer, region, substrate, or plate, is placed "on" or "above" another element not only indicates that the element is placed "directly" "on" the other element or "just" "above" the other element, but also indicates that there are elements interposed between the element and the other element. Conversely, a statement that an element, such as a layer, region, substrate, or plate, is placed "below" or "below" another element not only indicates that the element is placed "directly" "below" the other element or "just" "below" the other element, but also indicates that there are elements interposed between the element and the other element.

[0048] Hereinafter, exemplary embodiments of the present disclosure and items required for those skilled in the art to easily understand the contents of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, unless the context clearly indicates otherwise, the singular form in the present disclosure is intended to also include the plural form.

[0049] Figure 1 is a schematic perspective view of a light emitting element LD according to an embodiment of the present disclosure. Figure 2 It is from Figure 1 Schematic diagram of a light-emitting element LD shown in FIG. 1 as viewed from the top. Figure 3 yes Figure 1 Schematic cross-sectional view of a light emitting element LD shown in FIG.

[0050] refer to Figures 1 to 3 The light emitting element LD may have a shape extending in one direction. Assuming that the extending direction of the light emitting element LD is the length direction, the light emitting element LD may include a first end portion EP1 and a second end portion EP2 facing each other along the length direction.

[0051] The light emitting element LD may include a light emitting stack pattern 10 and an insulating film 14 surrounding an outer peripheral surface of the light emitting stack pattern 10. For example, the light emitting element LD may include a light emitting stack pattern 10 (or light emitting pattern) in which a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13 are stacked on each other, and the insulating film 14 surrounding an outer peripheral surface of the light emitting stack pattern 10.

[0052] The light-emitting element LD can be provided in various shapes. For example, the light-emitting element LD can have a rod-like shape, a bar-like shape, a column-like shape, etc. that is long in its longitudinal direction (for example, its aspect ratio is greater than 1). In addition, the light-emitting element LD can have a rod-like shape, a bar-like shape, a column-like shape, etc. that is short in its longitudinal direction. However, the shape of the light-emitting element LD is not limited thereto. The shape of the light-emitting element LD can correspond to the shape of the light-emitting stacking pattern 10. For example, when the light-emitting stacking pattern 10 has a columnar shape such as a cylinder, the light-emitting element LD can also have a cylindrical shape.

[0053] The light emitting element LD may include, for example, a light emitting diode (LED) manufactured small enough to have a diameter D and / or a length L of the nanometer (or nanometer) to micrometer (micrometer) order.

[0054] When the light-emitting element LD is long in its longitudinal direction, the diameter D of the light-emitting element LD may be about 0.5 μm to about 6 μm, and the length L of the light-emitting element LD may be about 1 μm to about 10 μm. However, the diameter D and the length L of the light-emitting element LD are not limited thereto, and the size of the light-emitting element LD may vary depending on the required conditions (or design conditions) of the lighting device or self-luminous display device to which the light-emitting element LD is applied.

[0055] One of the first semiconductor layer 11 and the second semiconductor layer 13 may be located at the first end EP1 of the light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be located at the second end EP2 of the light emitting element LD. For example, the second semiconductor layer 13 (or a P-type semiconductor layer) or the electrode layer 15 in ohmic contact with the second semiconductor layer 13 may be located at the first end EP1 of the light emitting element LD, and the first semiconductor layer 11 (or an N-type semiconductor layer) may be located at the second end EP2 of the light emitting element LD.

[0056] The first semiconductor layer 11 may include, for example, at least one N-type semiconductor layer. For example, the first semiconductor layer 11 may include at least one semiconductor material selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an N-type semiconductor layer doped with a first conductive dopant (or N-type dopant) such as Si, Ge, or Sn. However, the material constituting the first semiconductor layer 11 is not limited thereto. Furthermore, the first semiconductor layer 11 may be configured using a variety of materials.

[0057] The active layer 12 can emit light with a wavelength of about 400nm to about 900nm and use a double heterostructure. The light emitted from the active layer 12 can be emitted not only to the outer surface of the light-emitting element LD in the length direction, but also to both ends of the light-emitting element LD. The directionality of the light emitted from the active layer 12 is not limited to one direction. In an embodiment, an encapsulation layer doped with a conductive dopant can be formed on the top and / or bottom of the active layer 12 along the length direction of the light-emitting element LD. The encapsulation layer may include an AlGaN layer or an InAlGaN layer. In some embodiments, materials such as AlGaN or AlInGaN can be used to form the active layer 12. In addition, the active layer 12 can be configured using various materials. The active layer 12 may include a first surface in contact with the first semiconductor layer 11 and a second surface in contact with the second semiconductor layer 13.

[0058] When an electric field having a predetermined or selected voltage or higher is applied to both ends of the light-emitting element LD, the light-emitting element LD can emit light when electron-hole pairs are recombined in the active layer 12. By using this principle to control light emission of the light-emitting element LD, the light-emitting element LD can be used as a light source for various light-emitting devices (including pixels of display devices).

[0059] The second semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer having a different type from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one P-type semiconductor material. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a P-type semiconductor layer doped with a second conductive dopant (or P-type dopant) such as Mg, Zn, Ca, Sr, or Ba. However, the material constituting the second semiconductor layer 13 is not limited thereto. Furthermore, the second semiconductor layer 13 may be configured using a variety of materials.

[0060] The first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses along the length direction of the light emitting element LD. For example, the first semiconductor layer 11 may have a thickness relatively thicker than the second semiconductor layer 13 along the length direction of the light emitting element LD. However, the present disclosure is not limited thereto. In some embodiments, the first semiconductor layer 11 and the second semiconductor layer 13 may have substantially similar or substantially equal thicknesses along the length direction of the light emitting element LD.

[0061] Despite Figure 3 , each of the first semiconductor layer 11 and the second semiconductor layer 13 is configured with one layer, but the present disclosure is not limited thereto. In an embodiment, each of the first semiconductor layer 11 and the second semiconductor layer 13 may further include at least one layer, for example, an encapsulation layer and / or a tensile strain barrier reduction (TSBR) layer, depending on the material of the active layer 12.

[0062] In an embodiment, the light emitting element LD (or the light emitting stack pattern 10 ) may include an electrode layer 15 disposed on the second semiconductor layer 13 .

[0063] The electrode layer 15 may be an ohmic contact electrode, but the present disclosure is not limited thereto. In some embodiments, the electrode layer 15 may be a Schottky contact electrode. Figure 10 In the case where the electrode layer 15 is electrically connected to the alignment electrode or electrodes in ... x ), indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO).

[0064] The insulating film 14 may be provided on the outer peripheral surface (or outer surface) of the light emitting stack pattern 10, which includes the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the electrode layer 15 stacked on each other in one direction (e.g., from the second end portion EP2 toward the first end portion EP1). For example, the insulating film 14 may surround the outer peripheral surface of the light emitting stack pattern 10. In some embodiments, the insulating film 14 may surround only a portion of the light emitting stack pattern 10.

[0065] The insulating film 14 may expose two ends having different polarities of the light emitting stack pattern 10. For example, the insulating film 14 may expose a portion of the electrode layer 15 at the first end EP1 of the light emitting stack pattern 10 and a portion of the first semiconductor layer 11 at the second end EP2 of the light emitting stack pattern 10.

[0066] The insulating film 14 can prevent short circuits that may occur when the active layer 12 contacts a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, the insulating film 14 minimizes surface defects of the light-emitting stack pattern 10, thereby improving the lifespan and luminous efficiency of the light-emitting element LD. In addition, when a plurality of light-emitting elements LD are densely arranged, the insulating film 14 can prevent undesirable short circuits that may occur between the light-emitting elements LD.

[0067] The insulating film 14 may be provided to surround the outer peripheral surface of the light emitting stack structure 10. The outer peripheral surface of the light emitting stack structure 10 may be a side surface excluding the first end portion EP1 and the second end portion EP2 of the light emitting element LD.

[0068] The insulating film 14 may be provided to surround the outer peripheral surface (surface or outer surface) of each of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the electrode layer 15. The insulating film 14 may be provided to surround the outer peripheral surfaces of all of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the electrode layer 15, or may be provided to surround the outer peripheral surfaces of some of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the electrode layer 15. The insulating film 14 may be formed in a region where the light-emitting stack pattern 10 has a high surface defect concentration to effectively control surface defects of the light-emitting stack pattern 10.

[0069] The insulating film 14 may include a transparent insulating material. Various materials having insulating properties may be used as the material of the insulating film 14.

[0070] The insulating film 14 may be provided in a multilayer form including at least three layers. In an embodiment, the insulating film 14 may include a first FRL layer, a second SNL layer, and a third TIL layer. The first FRL layer may be directly provided on the outer peripheral surface of the light-emitting stack pattern 10 to surround the light-emitting stack pattern 10. The second SNL layer may be provided on the first FRL layer to surround the first FRL layer. The third TIL layer may be provided on the second SNL layer to surround the second SNL layer.

[0071] The third layer TIL may be an outer peripheral surface (or surface) of the light emitting element LD. For example, the third layer TIL may be located at the outermost portion of the side surface of the light emitting element LD.

[0072] The first layer FRL may include a first surface FRLa and a second surface FRLb facing each other in the longitudinal direction of the light emitting element LD. In a direction perpendicular to the longitudinal direction of the light emitting element LD, the first surface FRLa may be located on the same line as the second end EP2 of the light emitting element LD, and the second surface FRLb may be located on the same line as the first end EP1 of the light emitting element LD. However, the present disclosure is not limited thereto.

[0073] The second layer SNL may include a first surface SNLa and a second surface SNLb facing each other in the longitudinal direction of the light emitting element LD. In a direction perpendicular to the longitudinal direction of the light emitting element LD, the first surface SNLa may be located on the same line as the second end portion EP2 of the light emitting element LD, and the second surface SNLb may be located on the same line as the first end portion EP1 of the light emitting element LD. However, the present disclosure is not limited thereto.

[0074] The third layer TIL may include a first surface TILa and a second surface TILb facing each other in the longitudinal direction of the light-emitting element LD. In a direction perpendicular to the longitudinal direction of the light-emitting element LD, the first surface TILa may be located on the same line as the second end portion EP2 of the light-emitting element LD, and the second surface TILb may be located on the same line as the first end portion EP1 of the light-emitting element LD. However, the present disclosure is not limited thereto.

[0075] In an embodiment, the first FRL layer and the third TIL layer may include the same material. For example, the first FRL layer and the third TIL layer may include zirconium oxide (ZrO x ), silicon oxide (SiO x ), hafnium oxide (HfO x ), beryllium oxide (BeO), tantalum oxide (Ta x O y ), aluminum oxide (Al x O y ), lanthanum oxide (La x O y ), niobium oxide (Nb x O y ), titanium oxide (TiO x ), cerium oxide (CeO x ), magnesium oxide (MgO), yttrium oxide (Y x O y ) and strontium oxide (Sr x O y ). In addition, the first FRL layer and the third TIL layer may include aluminum nitride (AlN), hafnium nitride (HfN), zirconium nitride (ZrN), silicon nitride (SiN x ), aluminum oxide nitride (AlOx N y ), Hafnium Oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y ), at least one of AlGaN and InGaN. In an embodiment, the first FRL layer and the third TIL layer may include zirconium oxide (ZrO x ), hafnium oxide (HfO x ), zirconium nitride (ZrN), hafnium nitride (HfN), zirconium oxynitride (ZrO x N y ) and hafnium oxynitride (HfO x N y ) at least one of the following.

[0076] The second layer SNL may be configured with a material different from that of the first layer FRL and the third layer TIL. The second layer SNL may be configured with a material different from that of the first layer FRL and the third layer TIL among the materials exemplified as the materials constituting the first layer FRL and the third layer TIL. For example, the first layer FRL and the third layer TIL may include zirconium oxide (ZrO x ), hafnium oxide (HfO x ), zirconium nitride (ZrN), hafnium nitride (HfN), zirconium oxynitride (ZrO x N y ) and hafnium oxynitride (HfO x N y ), the second layer SNL may include aluminum oxide (Al x O y ).

[0077] The first FRL layer may surround the outer peripheral surface of the light emitting stack pattern 10 with a thickness d1 of 5 nm or less. The first FRL layer may be configured to have a relatively thin thickness d1 compared to the second SNL layer and the third TIL layer. The second SNL layer may have a thickness d2 thicker than the thickness of the first FRL layer, and the second SNL layer may surround the first FRL layer. The third TIL layer may have a thickness d3 relatively thicker than the thickness of each of the first FRL layer and the second SNL layer. However, the present disclosure is not limited thereto. In some embodiments, the third TIL layer may be formed to be thinner than the first FRL layer.

[0078] The first layer FRL can be applied in a desired shape to completely surround the side surfaces and both ends of the light-emitting stack structure 10, the second layer SNL can be applied to completely surround the first layer FRL, and the third layer TIL can be applied to completely surround the second layer SNL. Portions of the first layer FRL, the second layer SNL, and the third layer TIL can be removed so that a portion of the electrode layer 15 located at the first end EP1 of the light-emitting element LD and a portion of the first semiconductor layer 11 located at the second end EP2 of the light-emitting element LD are exposed in a subsequent etching process, thereby ultimately forming an insulating film 14 surrounding the outer peripheral surface (e.g., the side surface excluding the first end EP1 and the second end EP2) of the light-emitting stack structure 10. However, the method of forming the insulating film 14 is not limited thereto.

[0079] An etching process may generally be performed to manufacture the light emitting stack pattern 10. When atoms of the peripheral surface (or surface) of the light emitting stack pattern 10 are partially lost due to the etching process, surface defects of the light emitting stack pattern 10 may occur due to vacancies or dangling bonds. In the case where the light emitting element LD has a size of nanometers or micrometers, the surface defects of the light emitting stack pattern 10 may further increase as the ratio of the surface area to the volume becomes larger. The first layer FRL may be directly provided on the peripheral surface of the light emitting stack pattern 10 to reduce surface defects occurring in the manufacturing process of the light emitting stack pattern 10. For example, in the case where the first layer FRL includes zirconium oxide (ZrO x ), hafnium oxide (HfO x ), zirconium nitride (ZrN), hafnium nitride (HfN), zirconium oxynitride (ZrO x N y ) and hafnium oxynitride (HfO x N y ), lattice defects that may occur between the first layer FRL and the light emitting stack pattern 10 can be reduced. When the first layer FRL is properly grown on the peripheral surface of the light emitting stack pattern 10, the peripheral surface of the light emitting stack pattern 10 is protected, thereby reducing surface defects of the light emitting stack pattern 10.

[0080] When the thickness d1 of the first FRL layer is 5 nm or less (i.e., when the thickness d1 of the first FRL layer is thin compared to typical thin-film processes), only the interface characteristics between the light-emitting stack pattern 10 and the first FRL layer can be controlled. However, when the thickness d1 of the first FRL layer increases (or when another layer made of the same material as the first FRL layer surrounds the first FRL layer), the first FRL layer itself has thin-film characteristics, and therefore, the characteristics of the insulating film 14 (e.g., the characteristics of the protective layer protecting the light-emitting stack pattern 10) may deteriorate. The reliability of the light-emitting element LD may be degraded due to the deterioration of the characteristics of the insulating film 14.

[0081] In an embodiment, by providing a second layer SNL configured using a material different from that of the first layer FRL on the first layer FRL, and providing a third layer TIL configured using a material different from that of the second layer SNL on the second layer SNL, the insulating film 14 surrounding the outer peripheral surface of the light-emitting stack pattern 10 has a discontinuous portion, thereby reducing degradation of the characteristics of the insulating film 14. Therefore, the reliability of the light-emitting element LD can be improved.

[0082] As described above, when the insulating film configured as a multilayer including the first FRL layer, the second SNL layer, and the third TIL layer is provided on the peripheral surface (or surface) of the light emitting stack pattern 10 so as to surround the peripheral surface of the light emitting stack pattern 10, due to the interaction between the first FRL layer, the second SNL layer, and the third TIL layer, surface defects of the light emitting stack pattern 10 can be easily or effectively controlled, and the protective layer characteristics of the insulating film 14 can be improved. Therefore, the reliability (or luminous efficiency) of the light emitting element LD can be improved.

[0083] The light emitting element LD described above may be grown and manufactured on a substrate (not shown) for epitaxial growth.

[0084] Light-emitting elements LD can be used as light sources in various display devices. Light-emitting elements LD can be manufactured using a surface treatment process. For example, when multiple light-emitting elements LD are mixed in a liquid solution (or solvent) to be provided to each pixel region (e.g., the emission region of each pixel (or each sub-pixel)), each light-emitting element LD can be surface-treated so that the light-emitting elements LD are uniformly dispersed in the solution instead of unevenly agglomerated.

[0085] The emitting component including the light emitting element LD described above can be used for various types of devices requiring a light source, including display devices.

[0086] Figure 4 is a schematic perspective view of a light emitting element LD according to an embodiment of the present disclosure. Figure 5 It is from Figure 4 Schematic diagram of a light-emitting element LD shown in FIG. 1 as viewed from the top. Figure 6 yes Figure 3 Schematic cross-sectional view of a light emitting element LD shown in FIG.

[0087] about Figures 4 to 6 With regard to the embodiment shown in FIG, parts different from those of the above-described embodiment will be mainly described to avoid redundancy.

[0088] refer to Figures 4 to 6 The light emitting element LD may include a light emitting stack pattern 10 and an insulating film 14 surrounding an outer peripheral surface (or surface) of the light emitting stack pattern 10 .

[0089] The light emitting stack pattern 10 may include a first semiconductor layer 11 , an active layer 12 , a second semiconductor layer 13 , and an electrode layer 15 stacked on each other in a length direction of the light emitting element LD.

[0090] The insulating film 14 may be provided in the form of a multilayer including at least four layers. In an embodiment, the insulating film 14 may include a first layer FRL, a second layer SNL, a third layer TIL, and a fourth layer FUL. The first layer FRL may be directly provided on the outer peripheral surface of the light emitting stack pattern 10 to surround the light emitting stack pattern 10. The second layer SNL may be provided on the first layer FRL to surround the first layer FRL. The third layer TIL may be provided on the second layer SNL to surround the second layer SNL. The fourth layer FUL may be provided on the third layer TIL to surround the third layer TIL. The first layer FRL, the second layer SNL, and the third layer TIL may be reference layers. Figures 1 to 3 Described are the first layer FRL, the second layer SNL, and the third layer TIL.

[0091] The fourth layer FUL may be an outer peripheral surface (or surface) of the light emitting element LD. For example, the fourth layer FUL may be located at the outermost portion of the side surface of the light emitting element LD.

[0092] The fourth layer FUL may include a first surface FULa and a second surface FULb facing each other in the longitudinal direction of the light-emitting element LD. In a direction perpendicular to the longitudinal direction of the light-emitting element LD, the first surface FULa may be located on the same line as the second end portion EP2 of the light-emitting element LD, and the second surface FULb may be located on the same line as the first end portion EP1 of the light-emitting element LD. However, the present disclosure is not limited thereto.

[0093] The first FRL layer and the third TIL layer may include the same material. For example, the first FRL layer and the third TIL layer may include zirconium oxide (ZrO x ), silicon oxide (SiO x ), hafnium oxide (HfO x), beryllium oxide (BeO x ), tantalum oxide (Ta x O y ), aluminum oxide (Al x O y ), lanthanum oxide (La x O y ), niobium oxide (Nb x O y ), titanium oxide (TiO x ), cerium oxide (CeO x ), magnesium oxide (MgO x ), yttrium oxide (Y x O y ) and strontium oxide (Sr x O y ). In addition, the first FRL layer and the third TIL layer may include aluminum nitride (AlN), hafnium nitride (HfN), zirconium nitride (ZrN), silicon nitride (SiN x ), aluminum oxide nitride (AlO x N y ), Hafnium Oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y ), at least one of AlGaN and InGaN. In an embodiment, the first FRL layer and the third TIL layer may include zirconium oxide (ZrO x ), hafnium oxide (HfO x ), zirconium nitride (ZrN), hafnium nitride (HfN), zirconium oxynitride (ZrO x N y ) and hafnium oxynitride (HfO x N y ) at least one of the following.

[0094] The second layer SNL may utilize a material configuration different from that of the first layer FRL and the third layer TIL described above.

[0095] The fourth layer FUL may include an inorganic insulating material. The fourth layer FUL may be configured using a material different from that of the first layer FRL and the third layer TIL described above. In addition, the fourth layer FUL may be configured using the same material as the second layer SNL, or a material different from that of the second layer SNL. The fourth layer FUL may be configured using a material different from that of the first layer FRL and the third layer TIL among the materials exemplified as the materials constituting the first layer FRL and the third layer TIL. For example, when the first layer FRL and the third layer TIL include zirconium oxide (ZrO x), hafnium oxide (HfO x ), zirconium nitride (ZrN), hafnium nitride (HfN), zirconium oxynitride (ZrO x N y ) and hafnium oxynitride (HfO x N y ), the fourth layer FUL may include silicon oxide (SiO x ).

[0096] The fourth layer FUL together with the first layer FRL, the second layer SNL, and the third layer TIL may expose each of a portion of the electrode layer 15 at the first end EP1 of the light emitting element LD and a portion of the first semiconductor layer 11 at the second end EP2 of the light emitting element LD.

[0097] The fourth layer FUL may have a thickness d4 relatively thicker than each of the first layer FRL, the second layer SNL, and the third layer TIL. For example, the fourth layer FUL may have a thickness d4 of about 10 nm to about 40 nm, but the present disclosure is not limited thereto.

[0098] When the fourth layer FUL is arranged on the third layer TIL to surround the third layer TIL, surface defects of the light-emitting stack pattern 10 occurring in the manufacturing process are reduced, lattice defects existing between the light-emitting stack pattern 10 and the first layer FRL, the second layer SNL and the third layer TIL are further reduced, and the active layer 12 (or the light-emitting layer) is further prevented from short-circuiting with external conductive materials, thereby improving the reliability of the light-emitting element LD.

[0099] Figure 7 is a schematic perspective view of a light emitting element LD according to an embodiment of the present disclosure. Figure 8 It is from Figure 7 Schematic diagram of a light-emitting element LD shown in FIG. 1 as viewed from the top. Figure 9 yes Figure 5 Schematic cross-sectional view of a light emitting element LD shown in FIG.

[0100] about Figures 7 to 9 With respect to the embodiment shown in FIG, parts different from those of the above-described embodiment will be described to avoid redundancy.

[0101] refer to Figures 7 to 9 The light emitting element LD may include a light emitting stack pattern 10 and an insulating film 14 surrounding an outer peripheral surface (or surface) of the light emitting stack pattern 10 .

[0102] The light emitting stack pattern 10 may include a first semiconductor layer 11 , an active layer 12 , a second semiconductor layer 13 , and an electrode layer 15 stacked on each other in a length direction of the light emitting element LD.

[0103] The insulating film 14 may be provided in the form of a multilayer including at least five layers. In an embodiment, the insulating film 14 may include a first layer FRL, a second layer SNL, a third layer TIL, a fourth layer FUL, and a fifth layer FFL. The first layer FRL may be directly provided on the outer peripheral surface of the light emitting stack pattern 10 to surround the light emitting stack pattern 10. The second layer SNL may be provided on the first layer FRL to surround the first layer FRL. The third layer TIL may be provided on the second layer SNL to surround the second layer SNL. The fourth layer FUL may be provided on the third layer TIL to surround the third layer TIL. The fifth layer FFL may be provided on the fourth layer FUL to surround the fourth layer FUL. The first layer FRL, the second layer SNL, the third layer TIL, and the fourth layer FUL may be reference layers. Figures 1 to 6 The first layer FRL, the second layer SNL, the third layer TIL and the fourth layer FUL are described.

[0104] The fifth layer FFL may be an outer peripheral surface (or surface) of the light emitting element LD. For example, the fifth layer FFL may be located at the outermost portion of the side surface of the light emitting element LD.

[0105] The fifth layer FFL may include a first surface FFLa and a second surface FFLb facing each other in the longitudinal direction of the light-emitting element LD. In a direction perpendicular to the longitudinal direction of the light-emitting element LD, the first surface FFLa may be located on the same line as the second end portion EP2 of the light-emitting element LD, and the second surface FFLb may be located on the same line as the first end portion EP1 of the light-emitting element LD. However, the present disclosure is not limited thereto.

[0106] The first FRL layer and the third TIL layer may include the same material. For example, the first FRL layer and the third TIL layer may include zirconium oxide (ZrO x ), hafnium oxide (HfO x ), zirconium nitride (ZrN), hafnium nitride (HfN), zirconium oxynitride (ZrO x N y ) and hafnium oxynitride (HfO x N y ) at least one of the following.

[0107] The second layer SNL may utilize a material configuration different from that of the first layer FRL and the third layer TIL described above.

[0108] The fourth layer FUL may include an inorganic insulating material. For example, the fourth layer FUL may include silicon oxide (SiO x ).

[0109] The fifth FFL layer may include an inorganic insulating material. The fifth FFL layer may be configured with a material different from that of the first FRL layer and the third TIL layer described above. In addition, the fifth FFL layer may be configured with the same material as the fourth FUL layer, or may be configured with a material different from that of the fourth FUL layer. For example, the fifth FFL layer may include aluminum oxide (Al x O y ).

[0110] The fifth layer FFL together with the first layer FRL, the second layer SNL, the third layer TIL and the fourth layer FUL may expose each of a portion of the electrode layer 15 at the first end EP1 of the light emitting element LD and a portion of the first semiconductor layer 11 at the second end EP2 of the light emitting element LD.

[0111] The fifth FFL layer may have a thickness d5 that is relatively thicker than each of the first FRL layer, the second SNL layer, the third TIL layer, and the fourth FUL layer. For example, the fifth FFL layer may have a thickness d5 of about 40 nm or more, but the present disclosure is not limited thereto. In some embodiments, the fifth FFL layer may have a thickness d5 that is substantially similar to or substantially equal to that of the fourth FUL layer.

[0112] When the fifth layer FFL is arranged on the fourth layer FUL to surround the fourth layer FUL, surface defects of the light-emitting stack pattern 10 occurring in the manufacturing process are further reduced, lattice defects existing between the light-emitting stack pattern 10 and the first layer FRL, the second layer SNL, the third layer TIL and the fourth layer FUL are further reduced, and the active layer 12 (or the light-emitting layer) is further prevented from short-circuiting with external conductive materials, thereby further improving the reliability of the light-emitting element LD.

[0113] Hereinafter, an example of a display device using the above-described light emitting element LD as a light source will be described.

[0114] Figure 10 is a schematic plan view of a display device DD according to an embodiment of the present disclosure.

[0115] exist Figure 10 , for convenience of description, the structure of the display device DD (eg, the display panel DP provided in the display device DD) is briefly illustrated based on the display area DA displaying an image.

[0116] refer to Figure 10 , according to the driving light emitting element LD (see Figure 1According to the method of "LD" shown in FIG, the display device DD can be classified into a passive matrix display device and an active matrix display device. For example, when the display device DD is implemented as an active matrix display device, each of the pixels PXL may include a driving transistor for controlling the amount of current supplied to the light emitting element LD, a switching transistor for transmitting a data signal to the driving transistor, and the like.

[0117] The display panel DP (or display device DD) may include a substrate SUB and pixels PXL disposed on the substrate SUB. Each of the pixels PXL may include at least one light emitting element LD.

[0118] The substrate SUB may include a display area DA and a non-display area NDA.

[0119] The display area DA may be a region in which pixels PXL for displaying an image are disposed.

[0120] The non-display area NDA may be positioned adjacent to the display area DA. The non-display area NDA may be provided on at least one side of the display area DA. For example, the non-display area NDA may surround the periphery (or edge) of the display area DA. A line portion electrically connected to each pixel PXL and a driver electrically connected to the line portion and driving the pixel PXL may be provided in the non-display area NDA.

[0121] The line portion may electrically connect the driver and each pixel PXL to each other. The line portion may include a fan-out line. The fan-out line may be electrically connected to the pixel circuit (see FIG. 1 ) of each pixel PXL. Figure 11 In addition, the fan-out line can be electrically connected to each control line and sensing line electrically connected to the pixel circuit PXC to compensate for the electrical characteristic changes of each pixel PXL in real time.

[0122] The substrate SUB may include a transparent insulating material to allow light to pass therethrough. The substrate SUB may be a rigid substrate or a flexible substrate.

[0123] The rigid substrate may be, for example, at least one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0124] The flexible substrate may be at least one of a film substrate and a plastic substrate including a polymer organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0125] One area on the substrate SUB may be set as a display area, such that the pixels PXL are disposed in the display area, and another area on the substrate SUB may be set as a non-display area NDA. For example, the substrate SUB may include a display area DA including pixel areas in which corresponding pixels PXL are disposed, and a non-display area NDA disposed at the periphery of the display area DA (or adjacent to the display area DA).

[0126] Each of the pixels PXL may be disposed in the display area DA of the substrate SUB. The plurality of pixels PXL may be disposed in a matrix arrangement along pixel rows (or pixel columns) extending in a first direction DR1 and pixel columns (or pixel rows) extending in a second direction DR2 intersecting the first direction DR1, but the arrangement structure of the pixels PXL is not limited thereto.

[0127] Each pixel PXL may include a pixel circuit layer (see FIG. Figure 13 "PCL" shown in ) and the display element layer (see Figure 13 ”DPL” shown in the ).

[0128] A pixel circuit PXC disposed on a substrate SUB and including a plurality of transistors and signal lines electrically connected to the transistors may be disposed in a pixel circuit layer PCL. For example, each transistor may have a form in which a semiconductor layer, a gate electrode, a first terminal, and a second terminal are stacked on top of each other, with an insulating layer interposed between the semiconductor layer, the gate electrode, the first terminal, and the second terminal. The semiconductor layer may include amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon, an organic semiconductor, and / or an oxide semiconductor. The semiconductor layer may include a channel region, a source region, and a drain region. The gate electrode, the first terminal, and the second terminal may include one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo), but the present disclosure is not limited thereto. In addition, the pixel circuit layer PCL may include at least one insulating layer.

[0129] The display element layer DPL may be disposed on the pixel circuit layer PCL. An emission component including at least one light emitting element LD that emits light (see Figure 11 The “EMU” shown in FIG) may be located in the display element layer DPL. Electrodes electrically connected to the light emitting element LD may be provided in the emission unit EMU. Components of each pixel PXL will be described in detail later.

[0130] Each pixel PXL may include at least one light-emitting element LD driven by a corresponding scan signal and a corresponding data signal. The light-emitting element LD may have a size ranging from nanometers (or nanometers) to micrometers (or microns) and may be connected in parallel to adjacent light-emitting elements. However, the present disclosure is not limited thereto. The light-emitting element LD may constitute the light source of each pixel PXL.

[0131] Figure 11 It is shown that the Figure 10 Schematic circuit diagram of the electrical connection relationship of components in each of the pixels PXL shown in FIG.

[0132] For example, Figure 11 The electrical connection relationship of components included in the pixel PXL applicable to the active matrix display device according to the embodiment of the present disclosure is shown. However, the connection relationship of the components of each pixel PXL is not limited thereto.

[0133] refer to Figure 10 and Figure 11 , the pixel PXL may include an emission part EMU generating light having brightness corresponding to the data signal. In addition, the pixel PXL may include a pixel circuit PXC for driving the emission part EMU.

[0134] The emission unit EMU may include a plurality of light-emitting elements LD connected in parallel between a first power line PL1 and a second power line PL2. The first power line PL1 is connected to a first driving power source to which a first driving power source VDD is applied, and the second power line PL2 is connected to a second driving power source VSS to which a second driving power source VSS is applied. For example, the light-emitting element EMU may include a first electrode PE1 (or a first pixel electrode) connected to the first driving power source VDD via the pixel circuit PXC and the first power line PL1, a second electrode PE2 (or a second pixel electrode) connected to the second driving power source VSS via the second power line PL2, and the plurality of light-emitting elements LD connected in parallel between the first electrode PE1 and the second electrode PE2 in the same direction. In an embodiment, the first electrode PE1 may be an anode electrode, and the second electrode PE2 may be a cathode electrode.

[0135] Each of the light-emitting elements LD included in the emission unit EMU may include one end (or first end EP1) electrically connected to a first driving power source VDD via a first electrode PE1 and another end (or second end EP2) electrically connected to a second driving power source VSS via a second electrode PE2. The first driving power source VDD and the second driving power source VSS may have different potentials. For example, the first driving power source VDD may be set to a high potential power source, and the second driving power source VSS may be set to a low potential power source. During the light-emitting period of the pixel PXL, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to be equal to or higher than the threshold voltage of the light-emitting element LD.

[0136] As described above, the light emitting elements connected in parallel between the first electrode PE1 and the second electrode PE2 to which different power supply voltages are supplied in the same direction (eg, forward direction) may respectively constitute effective light sources.

[0137] The light-emitting element LD of the emission unit EMU can emit light having a brightness corresponding to the drive current supplied by the corresponding pixel circuit PXC. For example, during each frame period, a drive current corresponding to the grayscale level of the corresponding frame data of the pixel circuit PXC can be supplied to the emission unit EMU. The drive current supplied to the emission unit EMU can be divided to flow through each of the light-emitting elements LD. Therefore, when each light-emitting element LD emits light having a brightness corresponding to the current flowing therethrough, the emission unit EMU can emit light having a brightness corresponding to the drive current.

[0138] Although an embodiment has been described in which both ends of the light-emitting element LD are connected in the same direction between the first driving power supply VDD and the second driving power supply VSS, the present disclosure is not limited thereto. In some embodiments, in addition to the light-emitting element LD forming the corresponding effective light source, the emitting unit EMU may further include at least one reverse light-emitting element LDr. The reverse light-emitting element LDr is connected in parallel with the light-emitting element LD forming the effective light source between the first electrode PE1 and the second electrode PE2, and may be connected between the first electrode PE1 and the second electrode PE2 in a direction opposite to the direction in which the light-emitting element LD is connected. Although a predetermined or selected driving voltage (e.g., a forward driving voltage) is applied between the first electrode PE1 and the second electrode PE2, the reverse light-emitting element LDr remains in an inactive state, and therefore, substantially no current flows through the reverse light-emitting element LDr.

[0139] The pixel circuit PXC can be electrically connected to the scan line Si and the data line Dj of the pixel PXL. In addition, the pixel circuit PXC can be connected to the control line CLi and the sensing line SENj of the pixel PXL. For example, when the pixel PXL is arranged in the i-th row and the j-th column of the display area DA, the pixel circuit PXC of the pixel PXL can be electrically connected to the i-th scan line Si, the j-th data line Dj, the i-th control line CLi, and the j-th sensing line SENj of the display area DA.

[0140] The pixel circuit PXC may include first to third transistors T1 to T3 and a storage capacitor Cst.

[0141] The first transistor T1 is a driving transistor for controlling the driving current applied to the emission component EMU and can be electrically connected between the first driving power supply VDD and the emission component EMU. Specifically, the first terminal of the first transistor T1 can be connected to the first driving power supply VDD through the first power line PL1, the second terminal of the first transistor T1 can be connected to the second node N2, and the gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the amount of driving current applied from the first driving power supply VDD to the emission component EMU through the second node N2 according to the voltage applied to the first node N1. In an embodiment, the first terminal of the first transistor T1 can be a drain electrode, and the second terminal of the first transistor T1 can be a source electrode. However, the present disclosure is not limited to this. In some embodiments, the first terminal can be a source electrode, and the second terminal can be a drain electrode.

[0142] The second transistor T2 is a switching transistor that selects and activates the pixel PXL in response to a scan signal, and the second transistor T2 can be electrically connected between the data line Dj and the first node N1. The first terminal of the second transistor T2 can be electrically connected to the data line Dj, the second terminal of the second transistor T2 can be electrically connected to the first node N1, and the gate electrode of the second transistor T2 can be electrically connected to the scan line Si. The first terminal and the second terminal of the second transistor T2 are different terminals. For example, when the first terminal is a drain electrode, the second terminal can be a source electrode.

[0143] When a scan signal having a gate-on voltage (e.g., a high-level voltage) is supplied from the scan line Si, the second transistor T2 may be turned on to electrically connect the data line Dj and the first node N1 to each other. The first node N1 is a point at which the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are connected to each other. The second transistor T2 may transmit a data signal to the gate electrode of the first transistor T1.

[0144] The third transistor T3 can connect the first transistor T1 to the sensing line SENj to obtain a sensing signal through the sensing line SENj and, using the sensing signal, detect characteristics of the pixel PXL, including the threshold voltage of the first transistor T1. Information about the characteristics of the pixel PXL can be used to convert image data, thereby compensating for characteristic variations between pixels PXL. The second terminal of the third transistor T3 can be electrically connected to the second terminal of the first transistor T1, the first terminal of the third transistor T3 can be electrically connected to the sensing line SENj, and the gate electrode of the third transistor T3 can be electrically connected to the control line CLi. In addition, the first terminal of the third transistor T3 can be electrically connected to an initialization power supply. The third transistor T3 is an initialization transistor capable of initializing the second node N2 and can be turned on when a sensing control signal is provided from the control line CLi to transmit the voltage of the initialization power supply to the second node N2. Therefore, the storage capacitor Cst electrically connected to the second node N2 can be initialized.

[0145] The storage capacitor Cst may include a first storage electrode (or lower electrode) and a second storage electrode (or upper electrode). The first storage electrode of the storage capacitor Cst may be electrically connected to the first node N1, and the second storage electrode of the storage capacitor Cst may be electrically connected to the second node N2. The storage capacitor Cst is charged with a data voltage corresponding to the data signal provided to the first node N1 during one frame period. Therefore, the storage capacitor Cst may store a voltage corresponding to the difference between the voltage of the gate electrode of the first transistor T1 and the voltage of the second node N2.

[0146] Although already Figure 11 , the light-emitting elements LD constituting the emission unit EMU are all connected in parallel, but the present disclosure is not limited thereto. In some embodiments, the emission unit EMU may be configured to include at least one series stage comprising a plurality of light-emitting elements LD connected in parallel. For example, the emission unit EMU may be configured in a hybrid series / parallel configuration.

[0147] Despite Figure 11 , the first transistor T1, the second transistor T2, and the third transistor T3 included in the pixel circuit PXC are all N-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be replaced by a P-type transistor. Figure 11 , an embodiment in which the emission unit EMU is connected between the pixel circuit PXC and the second driving power source VSS is disclosed, but the emission unit EMU may be connected between the first driving power source VDD and the pixel circuit PXC.

[0148] The structure of the pixel circuit PXC can be modified and implemented in various ways. For example, the pixel circuit PXC may further include at least one transistor element (such as a transistor element for initializing the first node N1 and / or a transistor element for controlling the emission time of the light-emitting element LD) or other circuit elements (such as a boosting capacitor for boosting the voltage of the first node N1).

[0149] In the following embodiments, for ease of description, the transverse direction (or X-axis direction) on a plane is represented as a first direction DR1, the longitudinal direction (or Y-axis direction) on a plane is represented as a second direction DR2, and the longitudinal direction on a cross section is represented as a third direction DR3.

[0150] Figure 12 is a schematic plan view illustrating a pixel PXL according to an embodiment of the present disclosure.

[0151] refer to Figures 10 to 12 The pixel PXL may be located in a pixel area PXA prepared (or provided) in the display area DA of the substrate SUB. The pixel area PXA may include an emission area EMA and a non-emission area NEA.

[0152] The pixel PXL may include a first bank BNK1 in the non-emission area NEA and a light emitting element LD in the emission area EMA.

[0153] The first bank BNK1 is a structure that defines (or divides) the pixel area PXA (or the emission area EMA) of each of the pixel PXL and adjacent pixels PXL adjacent thereto, and may be, for example, a pixel defining layer.

[0154] In an embodiment, the first bank BNK1 may be a structure that defines each emission area EMA to which the light-emitting element LD is to be supplied in a process of supplying (or inputting) the light-emitting element LD to the pixel PXL. For example, the emission area EMA of the pixel PXL is divided by the first bank BNK1 so that a mixed liquid (e.g., ink) including a desired number and / or desired type of light-emitting elements LD can be supplied to the emission area EMA.

[0155] The first bank BNK1 may include at least one light-blocking material and / or at least one reflective material (or light-scattering material) to prevent light leakage defects, such as light leaking between a pixel PXL and adjacent pixels PXL. In some embodiments, the first bank BNK1 may include a transparent material (or substance). The transparent material may include, for example, polyamide resin, polyimide resin, etc., but the present disclosure is not limited thereto. In another embodiment, a reflective material layer may be separately disposed and / or separately formed on the first bank BNK1 to further improve the efficiency of light emission from the pixel PXL.

[0156] The first bank BNK1 may include at least one opening OP exposing components thereunder in the pixel area PXA. In an embodiment, the emission area EMA of the pixel PXL and the opening OP of the first bank BNK1 may correspond to each other.

[0157] The electrode separation area ESA may be located in the non-emission area NEA of each pixel PXL and may be a region where the first alignment electrode ALE1 in each pixel PXL is separated from the first alignment electrode ALE1 in the adjacent pixel PXL disposed in the second direction DR2.

[0158] A pixel PXL may include an electrode PE disposed in at least the emission area EMA, a light-emitting element LD electrically connected to the electrode PE, an alignment electrode ALE disposed at a position corresponding to the electrode PE, and a bank pattern BNP. For example, the pixel PXL may include first and second electrodes PE1 and PE2 disposed in at least the emission area EMA, the light-emitting element LD, first and second alignment electrodes ALE1 and ALE2, and first and second bank patterns BNP1 and BNP2. The number, shape, size, and arrangement of each of the electrodes PE and / or alignment electrodes ALE may vary depending on the structure of the pixel PXL (e.g., the emission unit EMU).

[0159] In an embodiment, the bank pattern BNP, the alignment electrode ALE, the light emitting element LD, and the electrode PE may be sequentially arranged relative to one surface of the substrate SUB on which the pixel PXL is arranged, but the present disclosure is not limited thereto. In some embodiments, the positions and formation order of the electrode patterns constituting the pixel PXL (or the emission unit EMU) may be variously changed. Figures 13 to 15 The stacking structure (or cross-sectional structure) of the pixel PXL is described.

[0160] The bank patterns BNP may be provided in at least the emission area EMA and spaced apart from each other in the first direction DR1 in the emission area EMA. Each of the bank patterns BNP may extend along the second direction DR2. The bank patterns BNP may include a first bank pattern BNP1 and a second bank pattern BNP2 arranged to be spaced apart from each other in the first direction DR1.

[0161] Each bank pattern BNP (also referred to as a "wall pattern," "protrusion pattern," "support pattern," or "wall structure") may have a uniform width in the emission area EMA. When viewed in a planar manner, each of the first bank pattern BNP1 and the second bank pattern BNP2 may have a rod-like shape having a predetermined width along its extension direction in the emission area EMA, but the present disclosure is not limited thereto.

[0162] The bank pattern BNP may support each of the first and second alignment electrodes ALE1 and ALE2 to change a surface profile (or shape) of each of the first and second alignment electrodes ALE1 and ALE2 so that light emitted from the light emitting element LD is guided to an image display direction (or front direction) of the display device DD.

[0163] The bank patterns BNP may have the same width or different widths. For example, the first bank pattern BNP1 and the second bank pattern BNP2 may have the same width or different widths in the first direction DR1 in at least the emission area EMA.

[0164] Each of the first bank pattern BNP1 and the second bank pattern BNP2 may partially overlap the corresponding alignment electrode ALE in at least the emission area EMA. For example, the first bank pattern BNP1 may be located on the bottom of the first alignment electrode ALE1 so as to overlap a region of the first alignment electrode ALE1, and the second bank pattern BNP2 may be located on the bottom of the second alignment electrode ALE2 so as to overlap a region of the second alignment electrode ALE2. The bank pattern BNP, together with the alignment electrode ALE, may be a structure that precisely defines the alignment position of the light-emitting element LD in the emission area EMA of the pixel PXL.

[0165] When the bank pattern BNP is provided on the bottom of one region of each alignment electrode ALE in the emission area EMA, one region of each alignment electrode ALE may protrude upward from the pixel PXL in the region where the bank pattern BNP is formed. Thus, the bank pattern BNP, as a wall structure, may be formed around the periphery of the light-emitting element LD. For example, the wall structure may be formed in the emission area EMA so as to face the first end EP1 and the second end EP2 of the light-emitting element LD.

[0166] In embodiments, when the bank pattern BNP and / or the alignment electrode ALE include / contain a reflective material, a reflective wall structure may be formed around the periphery of the light-emitting element LD. Therefore, when light emitted from the light-emitting element LD faces upward (or in an image display direction) of the pixel PXL, the luminous efficiency of the pixel PXL may be further improved.

[0167] The alignment electrodes ALE may be located in at least the emission area EMA and spaced apart from each other in the first direction DR1 in the emission area EMA. Each of the alignment electrodes ALE may extend in the second direction DR2. The alignment electrodes ALE may include a first alignment electrode ALE1 and a second alignment electrode ALE2 that are spaced apart from each other in the first direction DR1 and extend in the second direction DR2.

[0168] In a manufacturing process of the display device DD, after the light emitting element LD is provided and aligned in the emission area EMA, at least one of the first alignment electrode ALE1 and the second alignment electrode ALE2 may be separated from the other electrode (e.g., the alignment electrode ALE provided in an adjacent pixel adjacent to each pixel PXL in the second direction DR2). For example, in a manufacturing process of the display device DD, after the light emitting element LD is provided and aligned in the emission area EMA, the first alignment electrode ALE1 may be separated from the first alignment electrode ALE1 provided in an adjacent pixel PXL adjacent to the corresponding pixel PXL.

[0169] The first alignment electrode ALE1 may be electrically connected to the reference electrode through the first contact portion CNT1 Figure 11 The first contact portion CNT1 may be formed by opening a region of the insulating layer between the first alignment electrode ALE1 and the storage capacitor Cst. The second alignment electrode ALE2 may be electrically connected to a second power supply line (see FIG. 1 ) electrically connected to the pixel circuit PXC through the second contact portion CNT2. Figure 11 The second contact portion CNT2 may be formed by opening a region of the insulating layer between the second alignment electrode ALE2 and the second power line PL2.

[0170] The first contact portion CNT1 and the second contact portion CNT2 may be located in the non-emission area NEA to overlap with the first bank BNK1, but the present disclosure is not limited thereto. In some embodiments, both the first contact portion CNT1 and the second contact portion CNT2 may be located in the emission area EMA. Alternatively, one of the first contact portion CNT1 and the second contact portion CNT2 may be located in the non-emission area NEA, and the other of the first contact portion CNT1 and the second contact portion CNT2 may be located in the emission area EMA.

[0171] During the alignment process of the light-emitting element LD, each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may be provided with a predetermined or selected alignment signal. For example, the first alignment electrode ALE1 may be provided with a first alignment signal during the alignment process of the light-emitting element LD, and the second alignment electrode ALE2 and the further second alignment electrode ALE2 may be provided with a second alignment signal during the alignment process of the light-emitting element LD. The first alignment signal and the second alignment signal may be signals having a voltage difference and / or a phase difference to such an extent that the light-emitting element LD can be aligned between the alignment electrodes ALE. At least one of the first alignment signal and the second alignment signal may be an AC signal, but the present disclosure is not limited thereto.

[0172] At least two light emitting elements LD may be aligned in the emission area EMA (or the pixel area PXA) and / or may be disposed in the emission area EMA (or the pixel area PXA).

[0173] The light emitting element LD may be provided between the first alignment electrode ALE1 and the second alignment electrode ALE2. When viewed in a plane, each of the light emitting elements LD may include a first end portion EP1 and a second end portion EP2 located at both ends in the length direction (e.g., first direction DR1) thereof (or facing each other in the length direction (e.g., first direction DR1) thereof. In an embodiment, the second semiconductor layer (see FIG. 1 ) including a P-type semiconductor layer is provided. Figure 3 The electrode layer of the ohmic contact (see "13") Figure 3 ” 15 ” shown in ” can be located at the first end portion EP1 (or P-type end portion), and the first semiconductor layer including the N-type semiconductor layer (see Figure 3 The “11” shown in FIG may be located at the second end portion EP2 (or the N-type end portion).

[0174] The light-emitting elements LD may be arranged to be spaced apart from each other and aligned substantially parallel to each other. The distance between the light-emitting elements LD is not particularly limited. In some embodiments, a plurality of light-emitting elements LD may be arranged adjacent to each other to form a group, and another plurality of light-emitting elements LD may be arranged to form a group with the other plurality of light-emitting elements LD spaced apart from each other by a certain distance. The light-emitting elements LD may have a non-uniform density but may be aligned in one direction.

[0175] The light-emitting element LD can be provided to the pixel area PXA (or the emission area EMA) through an inkjet printing process, a slit coating process, or various other processes. For example, the light-emitting element LD can be mixed in a volatile solvent and provided to the pixel area PXA through the inkjet printing process or the slit coating process. When an alignment signal corresponding to each of the first alignment electrode ALE1 and the second alignment electrode ALE2 is applied, an electric field can be formed between the first alignment electrode ALE1 and the second alignment electrode ALE2. Therefore, the light-emitting element LD can be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2. After the light-emitting element LD is aligned, the solvent can be volatilized or removed through another process, so that the light-emitting element LD can be stably aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0176] The electrodes PE (or pixel electrodes) may be provided in at least the emission area EMA, and each electrode PE may be provided at a position corresponding to at least one alignment electrode ALE and at least one light-emitting element LD. For example, each electrode PE may be formed on each alignment electrode ALE and the corresponding light-emitting element LD so as to overlap with the alignment electrode ALE and the corresponding light-emitting element LD. Thus, the electrode PE may be electrically connected to at least the light-emitting element LD.

[0177] The electrode PE may include a first electrode PE1 and a second electrode PE2 disposed to be spaced apart from each other.

[0178] A first electrode PE1 ("first pixel electrode" or "anode") may be formed on the first alignment electrode ALE1 and the first end portion EP1 of each of the light-emitting elements LD to be electrically connected to the first end portion EP1 of each of the light-emitting elements LD. Furthermore, the first electrode PE1 may be in direct contact with the first alignment electrode ALE1 through a first contact hole CH1 in at least the non-emission area NEA, thereby being electrically and / or physically connected to the first alignment electrode ALE1. The first contact hole CH1 may be formed by removing a portion of at least one insulating layer between the first electrode PE1 and the first alignment electrode ALE1. A portion of the first alignment electrode ALE1 may be exposed by the first contact hole CH1.

[0179] The pixel circuit PXC, the first alignment electrode ALE1 , and the first electrode PE1 may be electrically connected to each other through the first contact portion CNT1 and the first contact hole CH1 .

[0180] In the above-described embodiment, the first alignment electrode ALE1 and the first electrode PE1 are connected to each other while being in direct contact with each other through the first contact hole CH1. However, the present disclosure is not limited thereto. In some embodiments, to prevent malfunctions caused by the material characteristics of the first alignment electrode ALE1, the first electrode PE1 may be in direct contact with the pixel circuit PXC instead of directly contacting the first alignment electrode ALE1, thereby being electrically connected to the pixel circuit PXC.

[0181] The first electrode PE1 may have a rod-like shape extending along the second direction DR2, but the present disclosure is not limited thereto. The shape of the first electrode PE1 may be variously modified as long as the first electrode PE1 is stably electrically and / or physically connected to the first end portion EP1 of the light-emitting element LD. In addition, the shape of the first electrode PE1 may be variously modified by considering the arrangement and connection relationship between the first electrode PE1 and the first alignment electrode ALE1 disposed below the first electrode PE1.

[0182] A second electrode PE2 ("second pixel electrode" or "cathode") may be formed on the second alignment electrode ALE2 and the second end portion EP2 of each of the light-emitting elements LD to be electrically connected to the second end portion EP2 of each of the light-emitting elements LD. Furthermore, the second electrode PE2 may be in direct contact with the second alignment electrode ALE2 via a second contact hole CH2, thereby being electrically and / or physically connected to the second alignment electrode ALE2. The second contact hole CH2 may be formed by removing a portion of at least one insulating layer between the second electrode PE2 and the second alignment electrode ALE2. A portion of the second alignment electrode ALE2 may be exposed by the second contact hole CH2.

[0183] The second power line PL2 , the second alignment electrode ALE2 , and the second electrode PE2 may be electrically connected to each other through the second contact portion CNT2 and the second contact hole CH2 .

[0184] In the above-described embodiment, the second alignment electrode ALE2 and the second electrode PE2 are connected to each other while being in direct contact with each other through the second contact hole CH2. However, the present disclosure is not limited thereto. In some embodiments, to prevent malfunctions caused by the material characteristics of the second alignment electrode ALE2, the first electrode EP1 may be in direct contact with the second power line PL2 instead of being in direct contact with the second alignment electrode ALE2, thereby being electrically connected to the second power line PL2.

[0185] The second electrode PE2 may have a rod-like shape extending along the second direction DR2, but the present disclosure is not limited thereto. The shape of the second electrode PE2 may be variously modified as long as the second electrode PE1 is stably electrically and / or physically connected to the second end portion EP2 of the light-emitting element LD. In addition, the shape of the second electrode PE2 may be variously modified by considering the arrangement and connection relationship between the second electrode PE2 and the second alignment electrode ALE2 disposed below the second electrode PE2.

[0186] In the following, reference will be made to Figures 13 to 15 A stack structure (or cross-sectional structure) of the pixel PXL according to the above-described embodiment is described.

[0187] Figure 13 and Figure 14 It is along Figure 12 Schematic cross-sectional view taken along line II' shown in FIG. Figure 15 It shows Figure 13 Schematic enlargement of the portion EA shown in .

[0188] Figure 14 Shown Figure 13A modification example of the embodiment shown in FIG. 1 is provided regarding the formation process of the first electrode PE1 and the second electrode PE2 and the presence of the third insulating layer INS3. Figure 14 illustratively shows an embodiment in which the first electrode PE1 and the second electrode PE2 are formed through the same process and the third insulating layer INS3 is omitted.

[0189] exist Figures 13 to 15 In the embodiment shown in , the stacked structure (or cross-sectional structure) of the pixel PXL is simplified and illustrated, such as each electrode is illustrated as an electrode having a signal layer, and each insulating layer is illustrated as an insulating layer provided as a single layer, but the present disclosure is not limited thereto.

[0190] about Figures 13 to 15 With respect to the embodiment shown in FIG, parts different from those of the above-described embodiment will be mainly described to avoid redundancy.

[0191] refer to Figures 10 to 15 , the pixel PXL may include a substrate SUB, a pixel circuit layer PCL and a display element layer DPL.

[0192] The pixel circuit layer PCL and the display element layer DPL can be arranged on one surface of the substrate SUB so as to overlap each other. For example, the display area DA of the substrate SUB may include the pixel circuit layer PCL arranged on one surface of the substrate SUB and the display element layer DPL arranged on the pixel circuit layer PCL. However, in some embodiments, the relative positions of the pixel circuit layer PCL and the display element DPL on the substrate SUB may vary. When the pixel circuit layer PCL and the display element layer DPL are arranged as separate layers and overlap each other, a layout space for forming each of the pixel circuit PXC and the emission unit EMU on a plane can be sufficiently ensured.

[0193] The substrate SUB may include a transparent insulating material to allow light to pass therethrough. The substrate SUB may be a rigid substrate or a flexible substrate.

[0194] The circuit elements constituting the pixel circuit PXC of the corresponding pixel PXL and predetermined or selected signal lines electrically connected to the circuit elements may be provided in each pixel region PXA of the pixel circuit layer PCL. In addition, the alignment electrode ALE, the light emitting element LD, and / or the electrode PE constituting the emission unit EMU of the corresponding pixel PXL may be provided in each pixel region PXA of the display element layer DPL.

[0195] In addition to circuit elements and signal lines, the pixel circuit layer PCL may further include at least one insulating layer. For example, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, a passivation layer PSV, and a via layer VIA stacked on top of each other along a third direction DR3 on the substrate SUB.

[0196] The buffer layer BFL may be completely disposed on the substrate SUB. The buffer layer BFL may prevent impurities from diffusing into the transistor T included in the pixel circuit PXC. The buffer layer BFL may be an inorganic insulating layer including an inorganic material. For example, the buffer layer BFL may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ), but the present disclosure is not limited thereto. The buffer layer BFL may be a single layer, but may also be a multilayer layer comprising at least two layers. If the buffer layer BFL is a multilayer layer, the multilayer layers may be formed of the same material or different materials. The buffer layer BFL may be omitted depending on the material of the substrate SUB, process conditions, and other factors.

[0197] The gate insulating layer GI may be completely disposed on the buffer layer BFL. The gate insulating layer GI may include the same material as the buffer layer BFL described above, or may include an appropriate (or selected) material among the materials exemplified as the materials constituting the buffer layer BFL. For example, the gate insulating layer GI may be an inorganic insulating layer including an inorganic material.

[0198] The interlayer insulating layer ILD may be completely disposed on the gate insulating layer GI and / or may be completely formed on the gate insulating layer GI. The interlayer insulating layer ILD may include the same material as the buffer layer BFL, or include an appropriate (or selected) material among the materials exemplified as the materials constituting the buffer layer BFL.

[0199] The passivation layer PSV may be completely disposed on the interlayer insulating layer ILD and / or may be completely formed on the interlayer insulating layer ILD. The passivation layer PSV may include the same material as the buffer layer BFL, or include an appropriate (or selected) material among the materials exemplified as the materials constituting the buffer layer BFL.

[0200] The via layer VIA may be completely disposed on the passivation layer PSV and / or may be completely formed on the passivation layer PSV. The via layer VIA may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, silicon oxide (SiO x ), silicon nitride (SiN x), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x The organic insulating layer may include, for example, at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0201] The via layer VIA may serve as a planarization layer that reduces a step difference caused by components of the pixel circuit PXC located below the via layer VIA in the pixel circuit layer PCL.

[0202] The pixel circuit layer PCL may include at least one conductive layer disposed between the insulating layers described above. For example, the pixel circuit layer PCL may include a first conductive layer disposed between the substrate SUB and the buffer layer BFL, a second conductive layer disposed on the gate insulating layer GI, a third conductive layer disposed on the interlayer insulating layer ILD, and a fourth conductive layer disposed on the passivation layer PSV. However, the insulating layer and the conductive layer are not limited to the embodiments described above. In some embodiments, in addition to the insulating layer and the conductive layer described above, another insulating layer and another conductive layer may be disposed in the pixel circuit layer PCL.

[0203] The first conductive layer may be formed in a single layer including one selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), any alloys thereof, or mixtures thereof. Furthermore, the first conductive layer may be formed in a double-layer structure or a multi-layer structure including molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) as a low-resistance material to reduce wiring resistance. Each of the second to fourth conductive layers may include the same material as the first conductive layer, or may include at least one appropriate material among the materials exemplified as the materials constituting the first conductive layer. However, the present disclosure is not limited thereto.

[0204] The pixel circuit PXC provided in the pixel circuit layer PCL may include at least one transistor T. The transistor T may include a reference Figure 11 For example, the transistor T may be one of the first transistor T1, the second transistor T2, and the third transistor T3 described above. Figure 11 The first transistor T1 is described.

[0205] The transistor T may include a semiconductor pattern and a gate electrode GE overlapping at least a portion of the semiconductor pattern. The semiconductor pattern may include a channel region ACT, a first contact region SE (or second terminal), and a second contact region DE (or first terminal). The first contact region SE may be a source region, and the second contact region DE may be a drain region.

[0206] The gate electrode GE may be disposed on the gate insulating layer GI and / or may be formed on the gate electrode GE to correspond to the channel region ACT of the semiconductor pattern. For example, the gate electrode GE may be a second conductive layer located between the gate insulating layer GI and the interlayer insulating layer ILD. The gate electrode GE may be disposed on the gate insulating layer GI to overlap with the channel region ACT of the semiconductor pattern.

[0207] The semiconductor pattern may be disposed on the buffer layer BFL and / or may be formed on the buffer layer BFL. The channel region ACT, the first contact region SE, and the second contact region DE may correspond to a semiconductor pattern made of polycrystalline silicon, amorphous silicon, an oxide semiconductor, or the like. The channel region ACT, the first contact region SE, and the second contact region DE may be formed from a semiconductor layer that is not doped with impurities or is doped with impurities. For example, the first contact region SE and the second contact region DE may be formed from a semiconductor layer that is doped with impurities, and the channel region ACT may be formed from a semiconductor layer that is not doped with impurities. The impurities may include, for example, N-type impurities, but the present disclosure is not limited thereto.

[0208] The channel region ACT may overlap with the gate electrode GE of the transistor T.

[0209] The first contact region SE (or second terminal) of the transistor T may be connected to one end of the channel region ACT and may be electrically connected to the bridge pattern BRP through the first connection member TE1. The second contact region DE (or first terminal) of the transistor T may be connected to the other end of the channel region ACT and may be electrically connected to the second connection member TE2.

[0210] The first connection member TE1 may be disposed on the interlayer insulating layer ILD and / or may be formed on the interlayer insulating layer ILD. For example, the first connection member TE1 may be configured using a third conductive layer. One end of the first connection member TE1 may be electrically and / or physically connected to the first contact region SE of the transistor T via a contact hole sequentially passing through the interlayer insulating layer ILD and the gate insulating layer GI. Furthermore, the other end of the first connection member TE1 may be electrically and / or physically connected to the bridge pattern BRP via a contact hole passing through the passivation layer PSV located on the interlayer insulating layer ILD.

[0211] The bridge pattern BRP may be disposed on the passivation layer PSV and / or may be formed on the passivation layer PSV. For example, the bridge pattern BRP may be configured using a fourth conductive layer. One end of the bridge pattern BRP may be connected to the first contact region SE of the transistor T via a first connection member TE1. Furthermore, the other end of the bridge pattern BRP may be electrically and / or physically connected to the bottom metal layer BML via a contact hole sequentially passing through the passivation layer PSV, the interlayer insulating layer ILD, the gate insulating layer GI, and the buffer layer BFL. The bottom metal layer BML and the first contact region SE of the transistor T may be electrically connected to each other via the bridge pattern BRP and the first connection member TE1.

[0212] In some embodiments, the bridge pattern BRP may be electrically connected to some components (eg, the first alignment electrode ALE1 of the display element layer DPL) through a contact hole passing through the via layer VIA.

[0213] The bottom metal layer BML may be a first conductive layer disposed on the substrate SUB. The bottom metal layer BML may be electrically connected to the transistor T to widen the driving range of a predetermined or selected voltage provided to the gate electrode GE of the transistor T. For example, the bottom metal layer BML may be electrically connected to the first contact region SE of the transistor T to stabilize the channel region ACT of the transistor T. Furthermore, when the bottom metal layer BML is electrically connected to the first contact region SE of the transistor T, floating of the bottom metal layer BML may be prevented.

[0214] The second connection member TE2 may be provided on the interlayer insulating layer ILD and / or may be formed on the interlayer insulating layer ILD. For example, the second connection member TE2 may be a third conductive layer. One end of the second connection member TE2 may be electrically and / or physically connected to the second contact region DE of the transistor T via a contact hole passing through the interlayer insulating layer ILD and the gate insulating layer GI.

[0215] In the above-described embodiment, the case where the transistor T is a thin film transistor having a top gate structure has been described. However, the present disclosure is not limited thereto, and the structure of the transistor T may be variously modified.

[0216] A passivation layer PSV may be disposed over the transistor T and the first and second connection members TE1 and TE2 and / or may be formed over the transistor T and the first and second connection members TE1 and TE2.

[0217] The pixel circuit layer PCL may include a predetermined or selected power line disposed on and / or formed on the passivation layer PSV. For example, the pixel circuit layer PCL may include a second power line disposed on the passivation layer PSV. The second power line PL2 may be configured using a fourth conductive layer. The voltage of the second drive power supply VSS may be applied to the second power line VSS. Although the case where the second power line PL2 is disposed on the passivation layer PSV has been described, the present disclosure is not limited thereto. In some embodiments, the second power line PL2 may be disposed on an insulating layer different from the passivation layer among the insulating layers included in the pixel circuit layer PCL.

[0218] The via layer VIA may be disposed above the bridge pattern BRP and the second power line PL2 and / or may be formed above the bridge pattern BRP and the second power line PL2. The via layer VIA may be partially opened to include a first contact portion CNT1 exposing a portion of the bridge pattern BRP and a second contact portion CNT2 exposing a portion of the second power line PL2.

[0219] The display element layer DPL may be disposed on the via layer VIA. The display element layer DPL may include a light emitting element layer LDL including a light emitting element LD that emits light.

[0220] The light emitting element layer LDL may include first and second bank patterns BNP1 and BNP2 , first and second alignment electrodes ALE1 and ALE2 , a first bank BNK1 , a light emitting element LD, and first and second electrodes PE1 and PE2 .

[0221] The first and second bank patterns BNP1 and BNP2 may be located on the via layer VIA. For example, the first and second bank patterns BNP1 and BNP2 may protrude in the third direction DR3 on one surface of the via layer VIA. A region of each of the first and second alignment electrodes ALE1 and ALE2, disposed on the first and second bank patterns BNP1 and BNP2, may protrude in the third direction DR3 (or the thickness direction of the substrate SUB).

[0222] The first and second bank patterns BNP1 and BNP2 may include an inorganic insulating layer containing an inorganic material or an organic insulating layer containing an organic material. In some embodiments, the first and second bank patterns BNP1 and BNP2 may include a single organic insulating layer and / or a single inorganic insulating layer, but the present disclosure is not limited thereto. In some embodiments, the first and second bank patterns BNP1 and BNP2 may be arranged in a multilayer form, with at least one organic insulating layer and at least one inorganic insulating layer stacked therebetween. However, the materials of the first and second bank patterns BNP1 and BNP2 are not limited to the embodiments described above. In some embodiments, the first and second bank patterns BNP1 and BNP2 may include a conductive material (or substance).

[0223] The first bank pattern BNP1 may be located on a bottom of the first alignment electrode ALE1 in the emission area EMA, thereby overlapping the first alignment electrode ALE1. The second bank pattern BNP2 may be located on a bottom of the second alignment electrode ALE2 in the emission area EMA, thereby overlapping the second alignment electrode ALE2.

[0224] The first and second bank patterns BNP1 and BNP2 may have a cross-section having a trapezoidal shape whose width gradually narrows from one surface (or top surface) of the via layer VIA toward its top along the third direction DR3 , but the present disclosure is not limited thereto.

[0225] Each of the first and second bank patterns BNP1 and BNP2 may function as a reflective member. For example, each of the first and second bank patterns BNP1 and BNP2, together with the alignment electrode ALE disposed on top of each of the first and second bank patterns BNP1 and BNP2, may function as a reflective member that guides light emitted from each light-emitting element LD in an image display direction of the display device DD, thereby improving light emission efficiency of the pixel PXL.

[0226] The first and second alignment electrodes ALE1 and ALE2 may be located on the first and second bank patterns BNP1 and BNP2 and on the via layer VIA.

[0227] The first alignment electrode ALE1 and the second alignment electrode ALE2 may be disposed on the same plane and have the same thickness in the third direction DR3 . The first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed simultaneously or continuously through the same process.

[0228] The first and second alignment electrodes ALE1 and ALE2 can be configured using a reflective material to allow light emitted from the light-emitting element LD to travel in the image display direction (or forward direction) of the display device DD. For example, the first and second alignment electrodes ALE1 and ALE2 can be made of a conductive material (or substance). The conductive material can include an opaque metal that is suitable for reflecting light emitted from the light-emitting element LD in the image display direction of the display device DD.

[0229] Each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed as a single layer, but the present disclosure is not limited thereto. In some embodiments, each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may be provided and / or formed as a multilayer in which at least two materials selected from metals, alloys, conductive oxides, and conductive polymers are stacked. Each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed as a multilayer including at least two layers to minimize distortion caused by signal delay when a signal is transmitted to both ends (e.g., the first end EP1 and the second end EP2) of each light-emitting element LD.

[0230] When the first and second alignment electrodes ALE1 and ALE2 are configured using a reflective conductive material, light emitted from the first and second end portions EP1 and EP2 of each of the light emitting elements LD can further advance in the image display direction of the display device DD.

[0231] A first insulating layer INS1 may be disposed on the first and second alignment electrodes ALE1 and ALE2 .

[0232] The first insulating layer INS1 may be disposed on the alignment electrode ALE and the via layer VIA. The first insulating layer INS1 may be partially opened to expose components located thereunder in at least the non-emission area NEA. For example, the first insulating layer INS1 may be partially opened to include a first contact hole CH1 that exposes a region of the first alignment electrode ALE1 due to removal of one region in at least the non-emission area NEA, and a second contact hole CH2 that exposes a region of the second alignment electrode ALE2 due to removal of another region in at least the non-emission area.

[0233] The first insulating layer INS1 may be formed as an inorganic insulating layer made of an inorganic material. The first insulating layer INS1 may be configured as a single layer or multiple layers. In the case where the first insulating layer INS1 is configured as a multiple layer, the first insulating layer INS1 may be configured as a distributed Bragg reflector structure in which first and second inorganic layers having different refractive indices are alternately stacked.

[0234] The first insulating layer INS1 may be disposed entirely throughout the emission area EMA and the non-emission area NEA of each pixel PXL, but the present disclosure is not limited thereto. In some embodiments, the first insulating layer INS1 may be located only in a specific area (eg, the emission area EMA) of each pixel PXL.

[0235] The first bank BNK may be located on the first insulating layer INS1 .

[0236] The first bank BNK1 may be disposed on the first insulating layer INS1 in the non-emission area NEA. The first bank BNK1 may be a pixel defining layer formed between adjacent pixels PXL to surround the emission area EMA of each pixel PXL, thereby dividing (or defining) the emission area EMA of the corresponding pixel PXL.

[0237] The first bank BNK1 and the first bank pattern BNP1 and the second bank pattern BNP2 may be formed by different processes and disposed in different layers, but the present disclosure is not limited thereto. In some embodiments, the first bank BNK1 and the first bank pattern BNP1 and the second bank pattern BNP2 may be formed by different processes but may be disposed in the same layer. Alternatively, the first bank BNK1 and the first bank pattern BNP1 and the second bank pattern BNP2 may be formed by the same process and disposed in the same layer.

[0238] The light-emitting element LD may be provided and aligned in the emission area EMA of the pixel PXL, where the first insulating layer INS1 and the first bank BNK are formed. For example, the light-emitting element LD may be provided (or input) to the emission area EMA using an inkjet printing process, etc., and aligned between the alignment electrodes ALE by an electric field formed by a predetermined or selected signal (or alignment signal) applied to each of the alignment electrodes ALE. For example, the light-emitting element LD may be aligned on the first insulating layer INS1 between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0239] In an implementation, each of the light emitting elements LD may include a light emitting stack structure 10 and an insulating film 14 surrounding the light emitting stack structure 10 .

[0240] The light emitting stack pattern 10 may include a first semiconductor layer 11, an active layer 12 (or a light emitting layer), a second semiconductor layer 13, and an electrode layer 15, which are sequentially stacked in a direction from the second end portion EP2 toward the first end portion EP1 of the light emitting element LD. The first semiconductor layer 11 may include an nN-type semiconductor layer, and the second semiconductor layer 13 may include a P-type semiconductor layer.

[0241] The insulating film 14 may include a first layer FRL surrounding an outer peripheral surface (or surface) of the light emitting stack pattern 10, a second layer SNL surrounding the first layer FRL, and a third layer TIL surrounding the second layer SNL. Each of the first layer FRL, the second layer SNL, and the third layer TIL may expose each of a portion of the electrode layer 15 located at the first end portion EP1 of the light emitting element LD and a portion of the first semiconductor layer 11 located at the second end portion EP2 of the light emitting element LD having different polarities.

[0242] The first FRL layer and the third TIL layer may include the same material. The second SNL layer may include a material different from that of the first FRL layer and the third TIL layer. In some embodiments, the first FRL layer and the third TIL layer may include zirconium oxide (ZrO x ), hafnium oxide (HfO x ), zirconium nitride (ZrN), hafnium nitride (HfN), zirconium oxynitride (ZrO x N y ) and hafnium oxynitride (HfO x N y ), and the second layer SNL may include aluminum oxide (Al 2 O 3 ).

[0243] The third layer of TIL may be configured to have a thickness relatively thicker than each of the first layer of FRL and the second layer of SNL. Specifically, the third layer of TIL may be configured to have a thickness thicker than the first layer of FRL. For example, the first layer of FRL may have a thickness of 5 nm or less, and the third layer of TIL may have a thickness of 10 nm or less.

[0244] When the multilayer insulating film 14 including the first FRL layer, the second SNL layer, and the third TIL layer is provided on the peripheral surface (or surface) of the light emitting stack pattern 10, thereby surrounding the peripheral surface of the light emitting stack structure 10, due to the interaction between the first FRL layer, the second SNL layer, and the third TIL layer, surface defects of the light emitting stack structure 10 can be easily or effectively controlled, and the protective layer characteristics of the insulating film 14 can be improved. Therefore, the luminous efficiency of the light emitting element LD can be improved.

[0245] A second insulating layer INS2 (or insulating pattern) may be provided on each of the light emitting elements LD. The second insulating layer INS2 may be located on each of the light emitting elements LD and partially cover an outer peripheral surface (or surface) of each of the light emitting elements LD, thereby exposing the first end portion EP1 and the second end portion EP2 of each of the light emitting elements LD to the outside.

[0246] The second insulating layer INS2 may include an inorganic insulating layer containing an inorganic material or an organic insulating layer. For example, the second insulating layer INS2 may include an inorganic insulating layer suitable for protecting the active layer 12 of each of the light emitting elements LD from external oxygen, moisture, etc. The second insulating layer INS2 may be configured as a single layer or multiple layers.

[0247] The second insulating layer INS2 is formed on the light emitting element LD that has been completely aligned in the emission area EMA of each pixel PXL, thereby preventing the light emitting element LD from being separated from the position where the light emitting element LD is aligned.

[0248] The electrode PE may be formed on the first end EP1 and the second end EP2 of the light emitting element LD not covered by the second insulating layer INS2. For example, the first electrode PE1 may be formed on the first end EP1 of the light emitting element LD, and the second electrode PE2 may be formed on the second end EP2 of the light emitting element LD.

[0249] The first electrode PE1 may be disposed on top of the first alignment electrode ALE1 to overlap with the first alignment electrode ALE1 , and the second electrode PE2 may be disposed on top of the second alignment electrode ALE2 to overlap with the second alignment electrode ALE2 .

[0250] The first electrode PE1 may be electrically connected to the first alignment electrode ALE1 through the first contact hole CH1 of the first insulating layer INS1 , and the second electrode PE2 may be electrically connected to the second alignment electrode ALE2 through the second contact hole CH2 of the first insulating layer INS1 .

[0251] Each of the first electrode PE1 and the second electrode PE2 can be configured using various transparent conductive materials. For example, each of the first electrode PE1 and the second electrode PE2 can include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide, and can be substantially transparent or translucent to meet a predetermined transmittance. Therefore, light emitted from the first end EP1 and the second end EP2 of the light-emitting element LD can be emitted to the outside of the display device DD while passing through the first electrode PE1 and the second electrode PE2.

[0252] In an embodiment, the first electrode PE1 and the second electrode PE2 may be formed in different layers or the same layer. In some embodiments, the relative positions and / or formation order of the first electrode PE1 and the second electrode PE2 may be variously changed.

[0253] exist Figure 13In the embodiment shown in , a first electrode PE1 can be first formed adjacent to one side surface (e.g., the left side surface) of the second insulating layer INS2. Subsequently, a third insulating layer INS3 can be formed to cover the first electrode PE1. The third insulating layer INS3 can be located above and cover the first electrode PE1 (or prevent the first electrode PE1 from being exposed to the outside), thereby protecting the first electrode PE1. The third insulating layer INS3 can include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material. Furthermore, the third insulating layer INS3 can be formed as a single layer or multiple layers. The second electrode PE2 can be formed on the third insulating layer INS3.

[0254] In the above-described embodiment, the second electrode PE2 is formed after the first electrode PE1 and the third insulating layer INS3 are formed. However, the present disclosure is not limited thereto. In some embodiments, the second electrode PE2 may be formed first, adjacent to the other side surface (e.g., the right side surface) of the second insulating layer INS2. The third insulating layer INS3 may be formed on the second electrode PE2, and the first electrode PE1 may be formed on the third insulating layer INS3.

[0255] In the case where the electrodes provided on the first end portion EP1 and the second end portion EP2 of each light emitting element LD are provided in different layers, Figure 13 Similar to the embodiment shown in , the electrodes can be stably separated from each other, and thus electrical stability between the first end portion EP1 and the second end portion EP2 of the light emitting element LD can be ensured.

[0256] exist Figure 14 In the embodiment shown in , the first electrode PE1 and the second electrode PE2 can be formed simultaneously, and the second insulating layer INS2 is interposed between the first electrode PE1 and the second electrode PE2. For example, the first electrode PE1 can be positioned adjacent to one side surface (e.g., the left side surface) of the second insulating layer INS2, and the second electrode PE2 can be positioned adjacent to the other side surface (e.g., the right side surface) of the second insulating layer INS2. The first electrode PE1 can directly contact the first end portion EP1 of the light-emitting element LD, thereby being electrically connected to the light-emitting element LD. The second electrode PE2 can directly contact the second end portion EP2 of the light-emitting element LD, thereby being electrically connected to the light-emitting element LD. Figure 14 In the embodiment shown in , when the first electrode PE1 and the second electrode PE2 provided on the first end portion EP1 and the second end portion EP2 of the light emitting element LD are provided in the same layer and formed simultaneously, the manufacturing process of the pixel PXL can be simplified and the manufacturing efficiency can be improved.

[0257] In some embodiments, at least one overcoat layer (eg, a layer for planarizing the top surface of the display element layer DPL) may be further disposed on top of the first electrode PE1 and the second electrode PE2.

[0258] In other embodiments, an optical layer including a color conversion layer and a color filter layer may be selectively provided on top of the display element layer DPL, the optical layer converting the light emitted from the light emitting element LD into light having excellent color reproducibility and releasing the converted light. Figure 16 and Figure 17 The optical layer is described in detail.

[0259] Figure 16 and Figure 17 is with Figure 12 The schematic cross-sectional view corresponding to the line II' shown in FIG.

[0260] Figure 16 and Figure 17 The embodiment shown in FIG shows different variations of the position of the color conversion layer CCL. For example, Figure 16 0 discloses an embodiment in which an optical layer LCL including a color conversion layer CCL and a color filter layer CFL is positioned on top of a light emitting element layer LDL through a continuous process, and Figure 17 , discloses an embodiment in which an optical layer LCL including a color conversion layer CCL and a color filter layer CFL is positioned on a light emitting element layer LDL through an adhesion process using an intermediate layer CTL.

[0261] about Figure 16 and Figure 17 With regard to the embodiment shown in FIG, parts different from those of the above-described embodiment will be mainly described to avoid redundancy.

[0262] refer to Figure 12 and Figure 16 Each pixel PXL may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and an encapsulation layer ENC. The display element layer DPL may include a light emitting element layer LDL and an optical layer LCL.

[0263] The light emitting element layer LDL may include first and second bank patterns BNP1 and BNP2 , first and second alignment electrodes ALE1 and ALE2 , a first bank BNK1 , a light emitting element LD, and first and second electrodes PE1 and PE2 .

[0264] The optical layer LCL may include a color conversion layer CCL and a color filter layer CFL. In addition, the optical layer LCL may include a second bank BNK2 and a first capping layer CPL1.

[0265] The second bank BNK2 may be disposed on the first bank BNK1 in the non-emission area NEA of the pixel PXL. The second bank BNK2 may be a dam structure surrounding the emission area EMA of the pixel PXL and defining a position where the color conversion layer CCL is to be provided, thereby defining the emission area EMA.

[0266] The second bank BNK2 may include a light-blocking material. For example, the second bank BNK2 may be a black matrix, but the present disclosure is not limited thereto. In some embodiments, the second bank BNK2 may include at least one light-blocking material and / or at least one reflective material to allow light emitted from the color conversion layer CCL to travel further in the image display direction, thereby improving the luminous efficiency of the color conversion layer CCL.

[0267] The color conversion layer CCL may include color conversion particles QD corresponding to a specific color. For example, the color conversion layer CCL may include color conversion particles QD for converting light emitted from the light emitting element LD into light of a specific color (or light with excellent color reproducibility).

[0268] In the case where the pixel PXL is a red pixel, the color conversion layer CCL of the pixel PXL may include color conversion particles QD of red quantum dots that convert light emitted from the light emitting element LD into red light.

[0269] In the case where the pixel PXL is a green pixel, the color conversion layer CCL of the pixel PXL may include color conversion particles QD of green quantum dots that convert light emitted from the light emitting element LD into green light.

[0270] If pixel PXL is a blue pixel, the color conversion layer CCL of pixel PXL may include color conversion particles QD comprising blue quantum dots that convert light emitted from light-emitting element LD into blue light. In some embodiments, if pixel PXL is a blue pixel, pixel PXL may include a light scattering layer comprising light scattering particles SCT, rather than a color conversion layer CCL comprising color conversion particles QD. For example, if light-emitting element LD emits blue light, pixel PXL may include a light scattering layer comprising light scattering particles SCT. In some embodiments, the light scattering layer described above may be omitted. In other embodiments, if pixel PXL is a blue pixel, a transparent polymer may be provided instead of a color conversion layer CCL.

[0271] The first capping layer CPL1 may be disposed on the color conversion layer CCL and the second bank BNK2 .

[0272] The first capping layer CPL1 may be completely disposed in the display area where the pixels are located (see Figure 10”DA” shown in ), so as to cover the second bank BNK2 and the color conversion layer CCL.

[0273] The first capping layer CPL1 may be an inorganic layer including an inorganic material. The first capping layer CPL1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and such as aluminum oxide (AlO x The first capping layer CPL1 completely covers the second bank BNK2 and the color conversion layer CCL, thereby blocking external moisture, oxygen, etc. from being introduced into the color conversion layer CCL.

[0274] In some embodiments, the first capping layer CPL1 may reduce a step difference due to components disposed therebelow and have a flat surface. For example, the first capping layer CPL1 may be an organic layer including an organic material, but the present disclosure is not limited thereto.

[0275] The color filter layer CFL may be disposed on the first capping layer CPL1 .

[0276] The color filter layer CFL may include color filters corresponding to the emission area EMA of each pixel PXL. For example, the color filter layer CFL may include a first color filter CF1 disposed on the color conversion layer CCL of one pixel PXL (hereinafter referred to as the "first pixel"), a second color filter disposed on the color conversion layer of an adjacent pixel adjacent to the first pixel PXL (hereinafter referred to as the "second pixel"), and a third color filter CF3 disposed on the color conversion layer of an adjacent pixel adjacent to the second pixel (hereinafter referred to as the "third pixel").

[0277] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged while overlapping each other in the non-emission area NEA to serve as a light blocking member for blocking light interference between adjacent pixels PXL. Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a color filter material for allowing light converted in the corresponding color conversion layer CCL to selectively pass therethrough. For example, the first color filter CF1 may be a red filter, the second color filter CF2 may be a green filter, and the third color filter CF3 may be a blue filter. However, the present disclosure is not limited thereto.

[0278] The encapsulation layer ENC may be disposed on the color filter layer CFL.

[0279] The encapsulation layer ENC may include a second capping layer CPL2. The second capping layer CPL2 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The second capping layer CPL2 may completely cover the components located below the second capping layer CPL2, thereby preventing external moisture, humidity, etc. from being introduced into the color filter layer CFL. In some embodiments, the encapsulation layer ENC may function as a planarization layer for reducing step differences generated by components of the color filter layer CFL located below the encapsulation layer ENC.

[0280] The second capping layer CPL2 may be formed as a multilayer. For example, the second capping layer CPL2 may include at least two inorganic insulating layers and at least one organic insulating layer interposed between the at least two inorganic insulating layers. However, the material and / or structure of the second capping layer CPL2 may be variously modified. In some embodiments, at least one overcoat layer, at least one filler layer, and / or another substrate may be further provided on top of the second capping layer CPL2.

[0281] In the pixel PXL according to the embodiment described above, the color conversion layer CCL and the color filter layer CFL are disposed above the light emitting element LD through a continuous process, thereby releasing light with excellent color reproducibility through the color conversion layer CCL and the color filter layer CFL. Therefore, the luminous efficiency of the pixel PXL can be improved.

[0282] In some embodiments, as Figure 17 As shown in , the optical layer LCL can be formed on one surface of the base layer BSL through a continuous process to form a separate substrate (e.g., an upper substrate), which is separate from the substrate SUB (e.g., a lower substrate) on which the light-emitting element layer LDL is disposed. The upper substrate can be bonded to the light-emitting element layer LDL via an intermediate layer CTL. An insulating layer can be provided over the first and second electrodes PE1 and PE2 to prevent certain components of the display element layer LDL (e.g., the first and second electrodes PE1 and PE2) from being exposed to the outside during the bonding process between the light-emitting element layer LDL and the upper substrate.

[0283] The intermediate layer CTL may be a transparent adhesive layer (or adhesion layer), such as an optically clear adhesive, for enhancing adhesion between the display element layer DPL and the upper substrate (or optical layer LCL), but the present disclosure is not limited thereto. In some embodiments, the intermediate layer CTL may be a refractive index conversion layer for converting the refractive index of light emitted from the light-emitting element LD and then traveling toward the upper substrate, thereby improving the luminance of the pixel PXL. In some embodiments, the intermediate layer CTL may include a filler configured using an insulating material having both insulating and adhesive properties.

[0284] The upper substrate may include a base layer BSL and an optical layer LCL. The optical layer LCL may include a color filter layer CFL, a second bank BNK2, a color conversion layer CCL, and a fifth insulating layer INS5.

[0285] The base layer BSL may be a rigid substrate or a flexible substrate, and the material and properties of the base layer BSL are not particularly limited. The base layer BSL may be configured using the same material as the substrate SUB or a different material from that of the substrate SUB.

[0286] The color filter layer CFL may be disposed on one surface of the base layer BSL so as to face the display element layer LDL. The first color filter CF1 of the color filter layer CFL may be disposed on one surface of the base layer BSL so as to correspond to the color conversion layer CCL in the emission area EMA. The first, second, and third color filters CF1, CF2, and CF3 of the color filter layer CFL may be disposed so as to overlap with each other in the non-emission area NEA. Therefore, the first, second, and third color filters CF1, CF2, and CF3 of the color filter layer CFL may function as a light blocking member.

[0287] A fourth insulating layer INS4 may be disposed between the color filter layer CFL and the color conversion layer CCL.

[0288] The fourth insulating layer INS4 may be located on the color filter layer CFL, thereby covering the color filter layer CFL. Therefore, the fourth insulating layer INS4 may protect the color filter layer CFL. The fourth insulating layer INS4 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0289] The second bank BNK2 and the color conversion layer CCL may be located on one surface of the fourth insulating layer INS4 .

[0290] The fifth insulating layer INS5 may be entirely disposed on the second bank BNK2 and the color conversion layer CCL.

[0291] The fifth insulating layer INS5 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) or may include at least one of aluminum oxide (AlO x ) of at least one of metal oxides. However, the present disclosure is not limited thereto. In some embodiments, the fifth insulating layer INS5 may be configured as an organic layer including an organic material. The fifth insulating layer INS5 may be located above the color conversion layer CCL, thereby protecting the color conversion layer CCL from external moisture, humidity, and the like. This may also improve the reliability of the color conversion layer CCL.

[0292] Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art at the time of filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless specifically indicated otherwise.

[0293] Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the scope of the present disclosure as set forth in the following claims.

Claims

1. Light-emitting element, including: A light-emitting stack pattern comprising a first semiconductor layer, an active layer and a second semiconductor layer; as well as an insulating film surrounding an outer peripheral surface of the light emitting stack pattern, Wherein, the insulating film comprises: First floor; a second layer surrounding the first layer; and a third layer, surrounding the second layer, and The first layer and the third layer comprise the same material.

2. The light-emitting element according to claim 1, wherein The first layer and the third layer include ZrO x 、SiO x 、HFO x 、BeO、Ta x O y 、Al x O y 、La x O y 、Nb x O y 、TiO x 、CeO x 、MgO、Y x O y and Sr x O y At least one of .

3. The light-emitting element according to claim 1, wherein The first layer and the third layer include AlN, AlGaN, InGaN, SiN x 、AlO x N y 、HfN、ZrN、HfO x N y and ZrO x N y At least one of .

4. The light-emitting element according to claim 3, wherein The first layer has a thickness of 5 nm or less, and the third layer has a thickness of 10 nm or less. The light-emitting element according to claim 1 , wherein The second layer includes a material different from the materials of the first and third layers. The light-emitting element according to claim 1 , wherein The first layer is directly disposed on an outer peripheral surface of each of the first semiconductor layer, the active layer, and the second semiconductor layer.

7. The light-emitting element according to claim 1, wherein The first semiconductor layer includes an N-type semiconductor layer doped with an N-type dopant, and the second semiconductor layer includes a P-type semiconductor layer doped with a P-type dopant.

8. The light-emitting element according to claim 7, wherein The light emitting stack pattern further includes an electrode layer disposed on the second semiconductor layer, and Here, the insulating film is directly provided on an outer peripheral surface of each of the first semiconductor layer, the active layer, the second semiconductor layer, and the electrode layer.

9. The light-emitting element according to claim 1, wherein The insulating film further includes a fourth layer surrounding the third layer, and The fourth layer includes an inorganic insulating material and has a thickness thicker than that of each of the first to third layers.

10. The light-emitting element according to claim 9, wherein The insulating film further includes a fifth layer surrounding the fourth layer, and The fifth layer includes an inorganic insulating material and has a thickness thicker than that of each of the first to fourth layers.

11. Light-emitting element, including: A light-emitting stacked pattern comprises a first semiconductor layer, an active layer, a second semiconductor layer and an electrode layer stacked in sequence along one direction; as well as an insulating film surrounding an outer peripheral surface of the light emitting stack pattern, Wherein, the insulating film comprises: a first layer directly disposed on the outer peripheral surface of the light emitting stack pattern to surround the light emitting stack pattern; a second layer surrounding the first layer; a third layer, surrounding the second layer; a fourth layer surrounding the third layer; and a fifth layer, surrounding the fourth layer, and The first layer and the third layer include the same material, and the second layer includes a material different from that of the first layer and the third layer.

12. The light-emitting element according to claim 11, wherein The first layer and the third layer include ZrO x 、SiO x 、HFO x 、BeO、Ta x O y 、Al x O y 、La x O y 、Nb x O y 、TiO x 、CeO x 、MgO、Y x O y and Sr x O y At least one of .

13. The light-emitting element according to claim 11, wherein The first layer and the third layer include AlN, AlGaN, InGaN, SiN x 、AlO x N y 、HfN、ZrN、HfO x N y and ZrO x N y At least one of .

14. The light-emitting element according to claim 11, wherein The first layer has a thickness of 5 nm or less, and the third layer has a thickness of 10 nm or less.

15. The light-emitting element according to claim 11, wherein The fourth layer and the fifth layer include an inorganic insulating material.

16. A display device comprising: substrate; a first electrode and a second electrode, disposed on the substrate to be spaced apart from each other; as well as a light emitting element located on the substrate, the light emitting element including a first end electrically connected to the first electrode and a second end electrically connected to the second electrode, Wherein, the light emitting element includes: a light emitting stack pattern comprising a first semiconductor layer located at the second end portion, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer, and an electrode layer disposed on the second semiconductor layer and located at the first end portion; and an insulating film surrounding an outer peripheral surface of the light emitting stack pattern, Wherein, the insulating film comprises: a first layer disposed directly on the outer peripheral surface of the light-emitting stack pattern; a second layer surrounding the first layer; and a third layer, surrounding the second layer, and The first layer and the third layer include the same material, and the second layer includes a material different from the materials of the first layer and the third layer.

17. The display device according to claim 16, wherein: The first layer and the third layer include ZrO x 、SiO x 、HFO x 、BeO、Ta x O y 、Al x O y 、La x O y 、Nb x O y 、TiO x 、CeO x 、MgO、Y x O y and Sr x O y At least one of .

18. The display device according to claim 16, wherein: The first layer and the third layer include AlN, AlGaN, InGaN, SiN x 、AlO x N y 、HfN、ZrN、HfO x N y and ZrO x N y At least one of .

19. The display device according to claim 16, wherein: The first layer has a thickness of 5 nm or less, and the third layer has a thickness of 10 nm or less.

20. The display device according to claim 16, further comprising: an emitting region in which light is emitted from the light emitting element and a non-emitting region surrounding the emitting region; a first alignment electrode disposed between the substrate and the first electrode, the first alignment electrode being electrically connected to the first electrode; a second alignment electrode disposed between the substrate and the second electrode, the second alignment electrode being electrically connected to the second electrode; a first bank located in the non-emitting area, the first bank including an opening corresponding to the emitting area; a second dike located on the first dike; a color conversion layer surrounded by the second bank, the color conversion layer being located above the light emitting element; as well as A color filter is disposed on the color conversion layer.

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