Maximum power point tracking circuit and energy harvesting device

Abstract

The embodiment of the invention discloses a maximum power point tracking circuit and an energy collection device, and the maximum power point tracking circuit comprises a frequency counter which is used for carrying out the statistics of a first switching frequency of a first power switch in a first clock period, and providing the first switching frequency to a controller; the controller is used for comparing the first switching frequency with a second switching frequency of the first power switch in a second clock period, generating a control signal based on a comparison result and transmitting the control signal to the constant switching energy extraction circuit; and the constant switch energy extraction circuit is used for generating a reference voltage signal based on the control of the control signal, comparing the reference voltage signal with an input voltage signal provided by the voltage signal input end, generating a pulse signal based on a comparison result, and transmitting the pulse signal to the control end of the first power switch. According to the maximum power point tracking circuit provided by the embodiment of the invention, the power consumption of the MPPT can be reduced so as to improve the sensitivity of the MPPT.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronic circuit, and particularly relate to a maximum power point tracking circuit and an energy harvesting device. BACKGROUND

[0002] With the development of electronic technology, various electronic devices emerge as the times require. In order to meet the work and operation of various electronic devices, energy harvesting devices are usually needed to harvest energy from external energy sources (such as solar energy, radio frequency energy, light energy or wind energy, etc.) to deliver the harvested energy to the electronic devices to power the electronic devices.

[0003] In the prior art, a maximum power point tracking (MPPT) method is usually used to obtain energy from the energy source to the greatest extent. Among them, the MPPT based on the hill climbing algorithm becomes the mainstream direction of the MPPT method because it is suitable for more scenes. In the MPPT based on the hill climbing algorithm, the voltage and current of the input port of the DC-DC conversion circuit need to be collected to determine the maximum power output to the subsequent DC-DC conversion circuit through the two parameters of voltage and current. In order to detect the voltage and current, an analog circuit is usually used to collect the voltage and current. However, the analog circuit used to collect the voltage and current needs a high static working current, which leads to high power consumption of the MPPT circuit. With the development of electronic products towards low power consumption and high sensitivity, the existing MPPT based on the hill climbing algorithm is not conducive to realizing the working scene of low power consumption and high sensitivity. Therefore, how to reduce the power consumption of the MPPT to improve the sensitivity of the MPPT becomes a problem to be solved. SUMMARY

[0004] Embodiments of the present application provide a maximum power point tracking circuit and an energy harvesting device, which can reduce the power consumption of the MPPT to improve the sensitivity of the MPPT. In order to achieve the above purpose, embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, the embodiments of the present application implement a maximum power point tracking circuit, which comprises a constant switching energy extraction circuit, a frequency counter and a controller; the frequency counter is coupled with a control end of a first power switch in a direct current-direct current (DC-DC) converter and the controller, and is configured to count a first switching frequency of the first power switch in a first clock cycle and provide the first switching frequency to the controller; the controller is coupled with the constant switching energy extraction circuit, and is configured to compare the first switching frequency with a second switching frequency of the first power switch in a second clock cycle, and generate a control signal based on a comparison result and transmit the control signal to the constant switching energy extraction circuit, where the second clock cycle is a previous clock cycle of the first clock cycle; the constant switching energy extraction circuit is coupled with a voltage signal input end of the maximum power point tracking circuit and the control end of the first power switch, and is configured to generate a reference voltage signal based on control of the control signal, compare the reference voltage signal with an input voltage signal provided by the voltage signal input end, and generate a pulse signal based on a comparison result and transmit the pulse signal to the control end of the first power switch, where the input voltage signal is generated based on an external energy source; and in any one of the first clock cycle and the second clock cycle, the first power switch comprises at least one on duration, and a product of each of the at least one on duration and the reference voltage signal is a constant amount.

[0006] The maximum power point tracking circuit provided by the embodiments of the present application sets the constant switching energy extraction circuit, the frequency counter and the controller, uses the constant switching energy extraction circuit to achieve a constant amount of energy obtained by the DC-DC converter in each switching, uses the frequency counter to detect the switching frequency of the power switch in the DC-DC converter to represent the amount of energy obtained from the energy source through the switching frequency of the power switch in the DC-DC converter, and finally the controller adjusts the voltage input to the input end of the DC-DC converter by detecting the switching frequency of the DC-DC converter, thereby achieving maximum power point tracking, that is, achieving optimal energy input to the DC-DC converter. Therefore, the maximum power point tracking circuit and the energy harvesting device provided by the embodiments of the present application can achieve the conversion of the amount of energy represented by the traditional voltage and current into the amount of energy represented by the switching frequency of the power switch by achieving a constant amount of energy obtained by the DC-DC converter in each switching, that is, the embodiments of the present application can achieve the collection of the switching frequency of the power switch through a digital circuit. Compared with the existing MPPT technology based on the hill climbing algorithm which needs to collect voltage and current through an analog circuit, the embodiments of the present application do not need static working current, greatly reduce the power consumption of the MPPT circuit, and are conducive to realizing low-power-consumption and high-sensitivity MPPT.

[0007] In a possible implementation, the controller is specifically configured to: when detecting that the second switching frequency is higher than the first switching frequency, transmit a first control signal to the constant switching energy extraction circuit, the first control signal being used to instruct to increase the reference voltage signal and reduce the on duration of the first power switch.

[0008] In a possible implementation, the controller is specifically configured to: when detecting that the second switching frequency is lower than the first switching frequency, transmit a second control signal to the constant switching energy extraction circuit, the second control signal being used to instruct to reduce the reference voltage signal and increase the on duration of the first power switch.

[0009] In a possible implementation, the constant switching energy extraction circuit comprises a pulse signal generation circuit, a reference voltage signal generation circuit, and a comparator; a first input terminal of the comparator is coupled to an output terminal of the reference voltage signal generation circuit, a second input terminal of the comparator is coupled to a voltage signal input terminal of the maximum power point tracking circuit, and an output terminal of the comparator is coupled to a first control terminal of the pulse signal generation circuit; the reference voltage signal generation circuit generates a reference voltage signal based on the control of the controller and provides the reference voltage signal to the first input terminal of the comparator; the comparator compares the input voltage signal with the reference voltage signal, and when the input voltage signal is greater than or equal to the reference voltage signal, transmits a first signal to the pulse signal generation circuit; the pulse signal generation circuit controls the first power switch to be turned on based on the first signal, and controls the on duration of the first power switch based on the control signal transmitted by the controller.

[0010] In a possible implementation, the pulse signal generation circuit comprises a first capacitor, a charging circuit configured to charge the first capacitor, a discharging circuit configured to discharge the first capacitor, a first transistor, and a comparison circuit; the charging circuit is arranged between a power supply terminal and a first terminal of the first capacitor, a second terminal of the first capacitor is connected to a common ground, and the charging circuit charges the first capacitor based on the first signal; the discharging circuit is arranged between the first terminal of the first capacitor and the common ground, and the discharging circuit discharges the first capacitor based on the control of the control signal and the first signal; the first transistor is arranged between the first terminal of the first capacitor and the common ground, and the first transistor is used to be turned on when the first capacitor is discharged to a first threshold value; and the comparison circuit is used to compare the voltage of the first terminal of the first capacitor with a preset voltage threshold value, and generate a pulse signal based on the comparison result.

[0011] In a possible implementation, the discharging circuit includes a current mirror circuit, at least one group of transistors for mirroring the current mirror circuit, a second transistor arranged between the at least one group of transistors and the common ground; the at least one group of transistors is arranged between the first end of the first capacitor and the second transistor, each group of transistors in the at least one group of transistors includes a third transistor and a fourth transistor, the third transistor and the fourth transistor are coupled in series between the first end of the first capacitor and the second transistor, the third transistor is turned on or turned off based on the control of the controller, and the control end of the fourth transistor is coupled with the current mirror circuit; the first transistor is coupled to the common ground through the second transistor, and the second transistor is turned on or turned off based on the control of the signal transmitted by the comparator.

[0012] In a possible implementation, the charging circuit includes a fifth transistor, the fifth transistor is arranged between the power supply end and the first end of the first capacitor, and the fifth transistor charges the first capacitor based on the control of the first signal.

[0013] In a possible implementation, the comparison circuit includes a sixth transistor, a seventh transistor, an eighth transistor, and an XOR gate; the sixth transistor and the seventh transistor are coupled in series between the power supply end and the control end of the first transistor, the sixth transistor is turned on or turned off based on the control of the signal output by the comparator, and the control end of the seventh transistor is coupled with the first end of the first capacitor; the eighth transistor is coupled between the control end of the first transistor and the common ground, the control end of the eighth transistor is coupled to the first end of the first capacitor; the first input end of the XOR gate is coupled with the control end of the first transistor, the second input end is coupled with the output end of the comparator, and the output end of the XOR gate is coupled with the control end of the first power switch.

[0014] In a possible implementation, the pulse signal generation circuit further includes a compensation circuit, the compensation circuit includes a first AND gate, a ninth transistor, a tenth transistor, a first resistor, and a variable capacitor; the first input end of the first AND gate is coupled with the output end of the XOR gate; the output end of the XOR gate is coupled to the gate of the ninth transistor and the gate of the tenth transistor; the first pole of the ninth transistor is coupled with the power supply end, the second pole of the ninth transistor is coupled with the first pole of the tenth transistor through the first resistor, and the second pole of the tenth transistor is coupled to the common ground; the variable capacitor is coupled between the second pole of the ninth transistor and the common ground, and the second pole of the ninth transistor is coupled with the second input end of the first AND gate; the output end of the first AND gate is coupled with the control end of the first power switch; wherein the ninth transistor and the tenth transistor are different types of transistors.

[0015] In a possible implementation, the reference voltage signal generation circuit includes an output terminal, at least one set of capacitor and gate combination circuit, an eleventh transistor, a third capacitor, a fourth capacitor, a second inverter and a third inverter; any one of the at least one set of capacitor and gate combination circuit includes a second capacitor and a second AND gate, a first input terminal of the second AND gate is configured to input a system clock signal of the maximum power point tracking circuit, a second input terminal of the second AND gate is configured to input a control signal transmitted by the controller, and an output terminal of the second AND gate is coupled to the output terminal through the second capacitor; a first terminal of the eleventh transistor is coupled to the output terminal, and a second terminal of the eleventh transistor is coupled to the common ground; an input terminal of the second inverter is coupled to the first input terminal of the second AND gate, and an output terminal of the second inverter is coupled to a control terminal of the eleventh transistor; an input terminal of the third inverter is coupled to the output terminal of the second inverter, and an output terminal of the third inverter is coupled to the output terminal through the third capacitor; and the fourth capacitor is arranged between the output terminal and the common ground.

[0016] In a second aspect, the embodiments of the present application provide an energy harvesting device, which includes the maximum power point tracking circuit according to the first aspect.

[0017] In a possible implementation, the energy harvesting device further includes a DC-DC converter, the DC-DC converter including an input port, an inductor and a first power switch; the input port of the DC-DC converter is coupled to the energy source; the inductor is coupled between the input port and a first terminal of the first power switch, and a second terminal of the first power switch is coupled to the common ground; the pulse signal output terminal of the maximum power point tracking circuit is coupled to a control terminal of the first power switch.

[0018] In a possible implementation, the DC-DC conversion circuit further includes a second power switch, a fifth capacitor and a resistor; a first terminal of the second power switch is coupled to the first terminal of the first power switch, and a second terminal of the second power switch is coupled to an output port of the DC-DC conversion circuit; the fifth capacitor is coupled between the second terminal of the second power switch and the common ground; and the resistor is coupled between the second terminal of the second power switch and the common ground. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0020] Figure 1 A structural schematic diagram of an energy harvesting circuit in the prior art is provided for the embodiments of the present application;

[0021] Figure 2 A structural schematic diagram of an energy harvesting system provided by an embodiment of the present application;

[0022] Figure 3 A structural schematic diagram of an energy harvesting device provided by an embodiment of the present application;

[0023] Figure 4 An interaction flow chart between components in an energy harvesting device provided by an embodiment of the present application;

[0024] Figure 5 A working timing chart of an energy harvesting device provided by an embodiment of the present application;

[0025] Figure 6 A structural schematic diagram of a constant switch energy extraction circuit provided by an embodiment of the present application;

[0026] Figure 7 A structural schematic diagram of a pulse signal generation circuit in a constant switch energy extraction circuit provided by an embodiment of the present application;

[0027] Figure 8 Another structural schematic diagram of a pulse signal generation circuit in a constant switch energy extraction circuit provided by an embodiment of the present application;

[0028] Figure 9 A timing chart for driving the pulse signal generation circuit shown in Figure 8 to work provided by an embodiment of the present application;

[0029] Figure 10 A structural schematic diagram of a reference voltage signal generation circuit in a constant switch energy extraction circuit provided by an embodiment of the present application;

[0030] Figure 11 Another structural schematic diagram of a pulse signal generation circuit in a constant switch energy extraction circuit provided by an embodiment of the present application;

[0031] Figure 12 A timing chart for driving the pulse signal generation circuit shown in Figure 11 to work provided by an embodiment of the present application. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0033] The term "and / or" in this document is only used to describe associated objects, which means that there can be three relationships, for example, A and / or B can represent three cases: A exists alone, A and B exist together, and B exists alone.

[0034] The terms "first" and "second" and the like in the description of the embodiments of the present application and in the accompanying drawings are used to distinguish different objects, or to distinguish different processing of the same object, and are not used to describe a specific order of the objects.

[0035] In addition, the terms "comprise" and "have" and any variations thereof mentioned in the description of the embodiments of the present application are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but can optionally include other steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0036] It should be noted that in the description of the embodiments of the present application, the words "exemplarily" or "for example" are used to represent as an example, illustration or explanation. Any embodiment or design scheme described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words "exemplarily" or "for example" are intended to present the relevant concept in a specific manner.

[0037] In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0038] Please refer to Figure 1 , Figure 1 is a structural schematic diagram of an energy harvesting circuit of an MPPT in the prior art provided by the embodiments of the present application. As shown in Figure 1The circuit shown includes an energy source and a direct current-direct current (DC-DC) conversion circuit, and the energy source is connected with the DC-DC conversion circuit through a switch. In the MPPT based on the open circuit voltage, the switch between the output end of the energy source and the DC-DC is turned off, the open circuit voltage of the output end of the energy source is detected, the detected voltage is compared with an empirical value (which can also be called an open circuit coefficient), and the impedance of the subsequent DC-DC conversion circuit is adjusted (for example, at least one of the capacitance value, the inductance value and the resistance value is adjusted) according to the comparison result, so that the energy harvesting system reaches the maximum power point. However, since the open circuit coefficient is usually a constant value, when the energy source has time-varying characteristics, in the MPPT based on the open circuit voltage, since the detected voltage needs to be compared with the empirical value and the impedance of the subsequent circuit needs to be adjusted, there is a delay in the circuit, and in the delay time range, the open circuit voltage of the energy source may change, so that the adjusted circuit may not be the maximum power value, and thus the optimal power value cannot be obtained in real time. Therefore, the MPPT based on the open circuit voltage will cause the accuracy of the MPPT to decrease, and the energy obtained from the energy source to decrease. In addition, since the nonlinearity of the radio frequency energy source is very strong, the system open circuit coefficient changes greatly with the input energy, and the MPPT based on the open circuit voltage cannot be applied to the radio frequency energy source.

[0039] Therefore, the industry further proposes to use the MPPT based on the hill climbing algorithm. In the MPPT based on the hill climbing algorithm, the voltage and the current at the input end of the subsequent DC-DC conversion circuit need to be collected to determine the maximum power output to the subsequent DC-DC conversion circuit through the two parameters of voltage and current. In order to detect the voltage and the current, an analog circuit is usually used to collect the voltage and the current. However, the analog circuit used to collect the voltage and the current needs a high static working current, which causes the MPPT circuit to have high power consumption, that is, the MPPT circuit needs to divide part of the energy obtained from the energy source, thereby causing the sensitivity of the subsequent circuit or device to decrease due to insufficient energy. However, with the development of electronic products towards low power consumption and high sensitivity, the existing MPPT based on the hill climbing algorithm is not conducive to realizing the working scene of low power consumption and high sensitivity. For example, the power consumption of a certain energy harvesting chip itself is 5 μF, and due to insufficient environmental energy, the surrounding environmental energy is only 4 μF, which may cause the energy harvesting chip to fail to work normally, that is, the sensitivity of the energy harvesting chip decreases.

[0040] In summary, the MPPT circuit in the prior art has the problems of high power consumption and poor accuracy. Therefore, how to reduce the power consumption of the MPPT and improve the accuracy of the MPPT becomes a problem to be solved.

[0041] The maximum power point tracking circuit and the energy collection device provided by the embodiments of the present application can realize that the energy obtained by the power switch of the DC-DC converter is constant by setting the constant energy packet extraction (CEPE) circuit, the frequency counter and the controller, and the energy obtained by the power switch of the DC-DC converter is constant by using the constant energy packet extraction circuit. The frequency counter is used to detect the switching frequency of the power switch of the DC-DC converter, so as to represent the energy obtained from the energy source by the switching frequency of the power switch of the DC-DC converter. Finally, the controller detects the switching frequency of the DC-DC converter, and adjusts the voltage input to the input end of the DC-DC converter, so as to realize the maximum power point tracking, that is, to realize the input of the optimal energy to the DC-DC converter. Therefore, the maximum power point tracking circuit and the energy collection device provided by the embodiments of the present application can realize the conversion of the energy represented by the traditional voltage and current into the energy represented by the switching frequency of the power switch, that is, the embodiments of the present application can realize the collection of the switching frequency of the power switch by using the digital circuit. Compared with the existing MPPT technology based on the hill climbing algorithm, the embodiments of the present application do not need the static working current, greatly reduce the power consumption of the MPPT circuit, and are beneficial to realize the low-power-consumption and high-sensitivity MPPT. In addition, compared with the existing MPPT based on the open-circuit voltage, the frequency counter counts the frequency of the power switch of the DC-DC converter based on the preset period (for example, the system clock period), and the controller can adjust the voltage input to the DC-DC converter based on the preset period, so as to ensure that the accuracy of the MPPT circuit does not change with time, and improve the accuracy of the MPPT circuit. The maximum power point tracking circuit and the energy collection device provided by the embodiments of the present application will be described in more detail below in combination with the embodiments shown in the drawings. Figures 2-12 The maximum power point tracking circuit and the energy collection device provided by the embodiments of the present application will be described in more detail below in combination with the embodiments shown in the drawings.

[0042] The maximum power point tracking circuit provided by the embodiments of the present application can be applied to the energy collection system. Please refer to Figure 2 , Figure 2 is a structural schematic diagram of the energy collection system 100 provided by the embodiments of the present application. As shown in Figure 2As shown, the energy harvesting system 10 includes an energy harvesting device 10, an energy source 20 and a load 30. The energy source 20 can be an energy harvesting sensor for harvesting direct current, including but not limited to a solar panel, a thermoelectric generator, an intracochlear potential energy; or can be an energy harvesting sensor for harvesting alternating current, including but not limited to a piezoelectric material; in addition, the energy source 20 can also be a radio frequency source for harvesting radio frequency signals, which can include an antenna and an antenna receiver, for example, the antenna is connected to the energy harvesting device 10 through the antenna receiver. The energy source 20 can be connected to the energy harvesting device 10 through wired connection or wireless connection. The energy source 20 is used to transmit voltage to the energy harvesting device 10, and the energy harvesting device 10 charges the load 30 based on the received voltage.

[0043] In the embodiment of the present application, the energy harvesting device 10 can be a chip or a chip set or a circuit board carrying a chip or a chip set, and can also be a module integrated in an electronic device, but is not used to limit the embodiment. The energy harvesting device 10 can include one or more processors, such as a controller for executing a hill climbing algorithm and a frequency counter for frequency collection of power switches in a DC-DC converter. When the one or more processors are integrated in the same chip, the chip is also called a system on a chip (SOC) chip, which can also be called an energy harvesting chip. The DC-DC converter and the like can also be integrated on the energy harvesting chip.

[0044] The load 30 is connected to the output end of the energy harvesting device 10. The load 30 can include but is not limited to: a battery, various processors or other types of devices for driving the operation of terminal equipment, such as a graphics processing unit (GPU), a central processing unit (CPU), an arithmetic accelerator or various digital circuits and analog circuits, etc.; the load 40 can also be various integrated circuit chips, including but not limited to artificial intelligence chips, image processing chips, etc.

[0045] In the embodiment of the present application, the energy harvesting device 10 can be arranged together with the load 30 in the same electronic device, which can include but is not limited to: a mobile phone, a wearable device, an electric toothbrush, a keyboard, a headset, an industrial sensor node, etc. When the energy harvesting device 10 and the load 30 are arranged in the same electronic device, the energy source 20 can be independent of the electronic device, and the energy harvesting device 10 can be connected to the energy source 20 through various standard interfaces such as wired interfaces or wireless interfaces provided on the electronic device.

[0046] Based on Figure 2 As shown in the energy harvesting system 100, please continue to refer toFigure 3 , Figure 3 This embodiment of the present application provides Figure 2 A schematic diagram of the structure of the energy harvesting device 10 is shown. Figure 3 As shown, the energy harvesting device 10 includes an MPPT circuit 11 and a DC-DC converter 12. The MPPT circuit 11 includes a constant switching energy extraction circuit 101, a frequency counter 102 and a controller 103. Figure 3 As shown, the constant switch energy extraction circuit 101 includes multiple control terminals, and two control terminals vc1 and vc2 are schematically shown in the figure. The control terminal vc1 and the control terminal vc2 of the constant switch energy extraction circuit 101 are coupled to the control signal output terminals co1 and co2 of the controller 103 respectively. It can be understood that the constant switch energy extraction circuit 101 may include more or fewer control terminals, and the controller 103 may include more or fewer control signal output terminals, which is not specifically limited in the embodiment of the present application. The constant switch energy extraction circuit 101 also includes a pulse signal output terminal pon, and the DC-DC converter 12 includes an input port vi and a power switch K1. The pulse signal output terminal pon of the constant switch energy extraction circuit 101 is coupled to the control terminal of the power switch K1 of the DC-DC converter 12. In addition, the energy harvesting device 10 includes a voltage input port vin, and the voltage input port vin is connected to Figure 2 The circuit 101 is coupled to an energy source 20 for inputting a voltage from the energy source 20. Furthermore, the constant switching energy extraction circuit 101 includes an input terminal vhi coupled to an external energy source via a voltage input port vin. Furthermore, an input port vi of the DC-DC converter 12 is coupled to the voltage input port vin for inputting a voltage from the external energy source. A frequency counter 102 is coupled to a control terminal of the power switch K1 and an input terminal cin of the controller 103.

[0047] In the embodiment of the present application, the controller 103 can be a general-purpose processor, a dedicated processor, or any other processor. In addition, the controller 103 can also be a programmable logic device. A software program can be installed in the controller 103. The controller 103 can control the constant switch energy extraction circuit 101 by executing the software program. The software program can be, for example, a hill climbing algorithm, so that the constant switch energy extraction circuit 101 transmits an energy pulse signal and a reference voltage signal to the DC-DC converter 12. The constant switch energy extraction circuit 101 can be a digital-analog hybrid circuit, etc., wherein the specific structure of the constant switch energy extraction circuit 101 is described below. Figure 7 、 Figure 8 、 Figure 10 、 Figure 11In the embodiment shown, the frequency counter 102 can be a programmable logic device, that is, the frequency counter 102 can be a digital circuit. The frequency counter 102 can count the switching frequency of the power switch K1 in the DC-DC converter 12 within each clock cycle. Here, the switching frequency of the power switch K1 can be the number of times the power switch K1 switches on and off. The frequency counter 102 can provide the counted switching frequency of the power switch K1 within each clock cycle to the controller 103. The controller 103 can then further control the constant switching energy extraction circuit 101 based on the switching frequency of the power switch K1 within each clock cycle counted by the frequency counter 102 (for example, by reducing the on-time of the pulse signal transmitted to the power switch K1, increasing the reference voltage signal value, or increasing the on-time of the pulse signal transmitted to the power switch K1, and reducing the reference voltage signal value). It should be noted that in the embodiment of the present application, within each clock cycle, the power switch K1 includes at least one pulse signal, that is, has at least one on-time, and the product of each of the at least one on-time and the reference voltage signal is a constant. Specifically, refer to the following formula (1)

[0048]

[0049] Among them, E sw is the energy obtained by the DC-DC converter 12, t on is the on-time of the power switch K1 in the DC-DC converter 12, t Off is the on-time of the power switch K2 in the DC-DC converter 12, V in is the voltage value input to the DC-DC converter 12 , and L is the inductance value of the inductor L1 in the DC-DC converter 12 .

[0050] Based on formula (1), when the conduction time t of the power switch K1 in the DC-DC converter 12 is on Much longer than the turn-off time (i.e. the turn-on time of the power switch K2) t Off When , we have formula (2)

[0051]

[0052] Among them, I peak is the peak current of the inductor L1. In addition, the error Ro between the energy Esw obtained by the DC-DC converter 12 and the energy Ecepe provided to the DC-DC converter 12 by the switching energy extraction circuit 101 is as shown in formula (3):

[0053]

[0054] Vo is the voltage of the output port vo of the DC-DC converter 12, and Vi is the voltage of the input port of the DC-DC converter 12. As can be seen from equation (2), when the on-time t on of the power switch K1 is made to be in a constant value, the DC-DC converter 12 can obtain the same energy every time the power switch K1 is switched on. As can be seen from equation (3), when the on-time t on of the power switch K1 is much longer than the on-time t Off of the power switch K2, the error R sw between the energy E cepe obtained by the DC-DC converter 12 and the energy E O provided by the constant switching energy extraction circuit 101 to the DC-DC converter 12 is very small. Thus, the amount of energy obtained by the DC-DC converter 12 can be determined by the switching frequency of the power switch K1 in each clock cycle. Therefore, the reference voltage signal Vref can be generated in the constant switching energy extraction circuit 101, and the voltage signal Vin input to the voltage input port vin is compared with the reference voltage signal Vref. When the voltage signal Vin input to the voltage input port vin is greater than or equal to the reference voltage signal Vref, the power switch K1 is turned on, so that the voltage signal Vin follows the reference voltage signal Vref. In addition, the controller 103 adjusts the on-time t on of the power switch K1 in the constant switching energy extraction circuit 101 according to the voltage value of the reference voltage signal Vref, so that the on-time t on of the power switch K1 is a constant value, and thus the on-time t on of the power switch K1 is a constant value when the voltage signal Vin input to the DC-DC converter 12 is a constant value.

[0055] Based on the principle of the energy harvesting device 10 described above, the working process of the MPPT circuit 11 provided in the present application is described in detail below by the interaction between the components in the MPPT circuit 11 shown in Figure 4 and the timing shown in Figure 5 . As can be seen from Figure 4 , Figure 4 , the MPPT circuit 11 includes the following flow steps:

[0056] Step 401: During clock cycle T1, the controller 103 sends a control signal C1 to the constant switching energy extraction circuit 101. During this step, when the energy harvesting system 100 is initialized, the controller 103 may send the control signal C1 to the constant switching energy extraction circuit 101 based on pre-set initialization parameters (e.g., setting the reference voltage signal in the constant switching energy extraction circuit 101 to a preset value).

[0057] In step 402, during the aforementioned clock cycle T1, the constant switching energy extraction circuit 101 generates a reference voltage signal Vref1 based on the control signal C1. Furthermore, during clock cycle T1, the constant switching energy extraction circuit 101, based on the control signal C1, compares the generated reference voltage signal Vref1 with the voltage signal Vin obtained from the energy source in real time to detect whether the voltage signal Vin obtained from the energy source is greater than or equal to the reference voltage signal Vref1. When the voltage signal Vin obtained from the energy source is greater than or equal to the reference voltage signal Vref1, a first pulse signal is transmitted to the power switch K1 in the DC-DC converter 12, thereby controlling the power switch K1 to conduct.

[0058] from Figure 5 As can be seen from the timing sequence shown, in clock cycle T1, for the voltage signal Vin with time-varying characteristics, the voltage signal Vin exhibits fluctuations, that is, at certain time points, it is greater than or equal to the reference voltage signal Vref1, and at certain time points, it is less than the reference voltage signal Vref1. At these time points, when the voltage signal Vin is greater than or equal to the reference voltage signal Vref1, the constant switching energy extraction circuit 101 controls the power switch K1 to turn on, wherein the on-time is determined by the controller 103. In other words, the clock cycle T1 includes multiple first pulse signals, Figure 5 Pon is the control timing output by the constant switch energy extraction circuit 101 to the control terminal of the power switch K1.

[0059] In step 403 , the frequency counter 102 counts the switching frequency f1 of the power switch K1 (ie, the number of switching times of the power switch K1 ) within the clock period T1 , and provides the counted switching frequency f1 of the power switch K1 to the controller 103 .

[0060] In step 404, the controller 103 saves the switching frequency f1 and sends a control signal C2 to the constant switching energy extraction circuit 101 during the clock cycle T2. The control signal C2 is used to instruct to increase the reference voltage signal value and reduce the on-time of the pulse signal transmitted to the power switch K1.

[0061] Step 405, at the above clock cycle T2, the constant switching energy extraction circuit 101 generates the reference voltage signal Vref2 based on the control of the control signal C2. In addition, during the clock cycle T2, the constant switching energy extraction circuit 101 compares the generated reference voltage signal Vref2 with the voltage signal Vin obtained from the energy source in real time based on the control of the control signal C2, and detects whether the voltage signal Vin obtained from the energy source is greater than or equal to the reference voltage signal Vref2. When the voltage signal Vin obtained from the energy source is greater than or equal to the reference voltage signal Vref2, the second pulse signal is transmitted to the power switch K1 in the DC-DC converter 12, that is, the power switch K1 is controlled to be turned on.

[0062] From Figure 5 As can be seen from the timing diagram shown, at the clock cycle T2, for the voltage signal Vin with time-varying characteristics, the voltage signal Vin presents fluctuation, that is, at some time points, it is greater than or equal to the reference voltage signal Vref2, and at some time points, it is less than the reference voltage signal Vref2. At the time points greater than or equal to the reference voltage signal Vref2, the constant switching energy extraction circuit 101 controls the power switch K1 to be turned on, and the on duration is determined by the controller 103. That is to say, the clock cycle T2 includes a plurality of second pulse signals.

[0063] Step 406, the frequency counter 102 counts the switching frequency f2 of the power switch K1 during the clock cycle T2, and provides the counted switching frequency f2 of the power switch K1 to the controller 103.

[0064] Step 407, the controller 103 saves the switching frequency f2, and compares the switching frequency f2 with the switching frequency f1. From Figure 5 As can be seen from the timing diagram shown, the number of second pulse signals in the clock cycle T2 is higher than the number of first pulse signals in the clock cycle T1, that is, the switching frequency f2 is higher than the switching frequency f1, then at the clock cycle T3, the controller 103 sends the control signal C3 to the constant switching energy extraction circuit 101. The control signal C3 is used to indicate that the reference voltage signal value is increased, and the on duration of the pulse signal transmitted to the power switch K1 is reduced.

[0065] Step 408, at the above clock cycle T3, the constant switching energy extraction circuit 101 generates the reference voltage signal Vref3 based on the control of the control signal C3. In addition, during the clock cycle T1, the constant switching energy extraction circuit 101 transmits the third pulse signal to the power switch K1 in the DC-DC converter 12 based on the control of the control signal C1. The specific working principle is referred to step 402 or step 405.

[0066] In step 409 , the frequency counter 102 counts the switching frequency f2 of the power switch K1 within the clock period T2 , and provides the counted switching frequency f2 of the power switch K1 to the controller 103 .

[0067] In step 410, the controller 103 stores the switching frequency f3 and compares the switching frequency f3 with the switching frequency f2. Figure 5 As can be seen from the timing sequence shown, the number of the third pulse signal in clock cycle T3 is lower than the number of the first pulse signal in clock cycle T1, that is, the switching frequency f3 is lower than the switching frequency f2. Therefore, in clock cycle T4, the controller 103 sends a control signal C4 to the constant switching energy extraction circuit 101. The control signal C4 is used to instruct to reduce the reference voltage signal value and increase the on-time of the pulse signal transmitted to the power switch K1.

[0068] In the embodiment of the present application, after the MPPT circuit 11 is powered on, by repeatedly executing the steps shown in steps 404 to 410 above, the time-varying signal obtained from the energy source can be tracked in real time to improve the performance of the MPPT circuit.

[0069] Please continue to refer to Figure 3 ,like Figure 3 As shown, the DC-DC converter 12 can be a boost converter circuit. In addition to the input port vi and the power switch K1, the DC-DC converter 12 also includes an inductor L1, a power switch K2, a capacitor Cd1 and a resistor Rd1. Among them, the inductor L1 is coupled between the input port vi and the first end of the power switch K1, and the second end of the power switch K1 is coupled to the common ground Gnd; the first end of the power switch K2 is coupled to the first end of the power switch K1, and the second end of the power switch K2 is coupled to the output port vo of the DC-DC converter; the capacitor Cd1 is coupled between the second end of the power switch K2 and the common ground Gnd; the resistor Rd1 is coupled between the second end of the power switch K2 and the common ground Gnd. Among them, the output port vo of the DC-DC converter is connected to Figure 2 The load 30 shown is coupled to provide energy to the load 30. It should be noted that the control of the power switch K2 in the DC-DC converter 12 provided in the embodiment of the present application can adopt a traditional zero current detection (ZCD) control method. In addition, the power switch K1 and the power switch K2 in the DC-DC converter 12 provided in the embodiment of the present application can both be Nmos transistors or Pmos transistors. For example, the power switch K1 is an Nmos transistor and the power switch K2 is a Pmos transistor.

[0070] based on Figure 3 The energy harvesting device 10 shown, please continue to refer toFigure 6 , Figure 6 This is a structural diagram of the constant switch energy extraction circuit 101 provided in an embodiment of the present application. Figure 6 As shown, the constant switching energy extraction circuit 101 provided in the embodiment of the present application may include a pulse signal generating circuit 1011, a reference voltage signal generating circuit 1012, and a comparator B. The non-inverting input terminal of the comparator B is the input terminal vhi of the constant switching energy extraction circuit 101, and is coupled to the voltage input port vin through the input terminal vhi. The inverting input terminal of the comparator B is coupled to the output terminal vref of the reference voltage signal generating circuit 1012. The output terminal p0 of the comparator B is coupled to the control terminal of the pulse signal generating circuit 1011. Figure 3 The controller 103 shown can control the reference voltage signal generating circuit 1012 to generate a reference voltage signal Vref. The comparator B compares the voltage signal Vin inputted at the input terminal vhi with the reference voltage signal Vref. When the voltage signal inputted at the input terminal vhi is greater than or equal to the reference voltage signal Vref, a control signal P0 is generated and transmitted to the pulse signal generating circuit 1011, so that the pulse signal generating circuit 1011 generates a pulse signal to control the power switch K1 to turn on, thereby making the voltage signal Vin follow the reference voltage signal Vref. The width of the generated pulse signal is controlled by the control signal outputted by the controller 103. The structure of the pulse signal generating circuit 1011 is shown in FIG. Figure 7 、 Figure 8 or Figure 11 As shown in any embodiment. The reference voltage signal generating circuit 1012 can be a digital-to-analog converter. The reference voltage signal generating circuit 1012 can convert the control signal output from the output terminal co1 of the controller 103 (that is, the control signal input from the control terminal vc1 of the constant switching energy extraction circuit 101) into an analog voltage signal. The converted analog voltage signal is the reference voltage signal. In a possible implementation, the structure of the reference voltage signal generating circuit 1012 can be as follows: Figure 10 shown.

[0071] In a possible implementation, the structure of the pulse signal generating circuit 1011 is as follows: Figure 7 As shown. Figure 7In the embodiment, the pulse signal generation circuit 1011 comprises a capacitor C1, a charging circuit, a discharging circuit, a transistor M1 and a comparison circuit. The charging circuit is arranged between a power supply end Vcc and a first end of the capacitor C1, and a node a is formed between the charging circuit and the capacitor C1; a control end of the charging circuit is coupled to an output end p0 of the comparator B. The discharging circuit is arranged between the first end of the capacitor C1 and a common ground Gnd, and the discharging circuit comprises a plurality of control ends, one of the control ends is coupled to the output end p0 of the comparator B, and the remaining control ends can be coupled to a control end vc1 and a control end vc2 of the constant switching energy extraction circuit 101, respectively. The transistor M1 is coupled between the first end (i.e., the node a) of the capacitor C1 and the common ground Gnd, and the transistor M1 can be an NMOS transistor, wherein a drain of the transistor M1 is coupled to the node a, and a source of the transistor M1 is coupled to the common ground Gnd. One input end of the comparison circuit is coupled to the node a, and the other input end is used to input a reference voltage signal Vb, and an output end of the comparison circuit is a pulse signal output end pon of the constant switching energy extraction circuit 101. Based on the circuit structure shown in FIG. 10, in the embodiment, first, in a t1 period, the charging circuit is controlled based on a control signal transmitted by the comparator B to charge the capacitor C1, and the voltage of the node a is raised; then in a t2 period, the discharging circuit is controlled based on the control signal transmitted by the comparator B to discharge the capacitor C1, and when the capacitor C1 is discharged to a preset threshold, the transistor M1 is turned on, and the comparison circuit compares the voltage Va of the node a with the reference voltage signal Vb, and when the voltage Va of the node a is different from the reference voltage signal Vb, the power switch K1 in the DC-DC converter 12 is turned on; when the voltage Va of the node a is the same as the reference voltage signal Vb, the power switch K1 in the DC-DC converter 12 is turned off. Figure 7 Based on the pulse signal generation circuit 1011 shown in FIG. 10, in a possible implementation manner, the structure of the pulse signal generation circuit 1011 can be as shown in FIG. 11. Please refer to

[0072] Based on the pulse signal generation circuit 1011 shown in FIG. 10, in a possible implementation manner, the structure of the pulse signal generation circuit 1011 can be as shown in FIG. 11. Please refer to Figure 7 Figure 8 Based on the pulse signal generation circuit 1011 shown in FIG. 10, in a possible implementation manner, the structure of the pulse signal generation circuit 1011 can be as shown in FIG. 11. Please refer to Figure 8 Figure 8 is a more detailed structure diagram of the pulse signal generation circuit 1011 provided by the embodiment. As shown in FIG. 12, in the pulse signal generation circuit 1011, the charging circuit comprises a transistor M4, the transistor M4 is arranged between a power supply end Vcc and a first end of a capacitor C1, and a gate of the transistor M4 is coupled to an output end p0 of a comparator B. Figure 8

[0073] ​​​The discharge circuit includes a current mirror circuit, at least one set of transistors for mirroring the current in the current mirror circuit, and a transistor M2 disposed between the at least one set of transistors and a common ground Gnd. The current mirror circuit includes a current source Is and a transistor M3, an output terminal of the current source Is is coupled to a drain and a gate of the transistor M3, and a source of the transistor M3 is coupled to the common ground Gnd. The at least one set of transistors can include one set of transistors, two sets of transistors, three sets of transistors, or four sets of transistors, and the like, and the embodiments of the present application are not limited in this regard, and are set based on the needs of the application scenario, Figure 8 In the embodiment shown in FIG. 2, two sets of transistors MA and MB are schematically shown. In a preferred implementation, the at least one set of transistors can include 15 sets of transistors. Each of the two sets of transistors MA and MB is disposed between the first terminal of the capacitor C1 and the transistor M2. That is, one set of transistors MA and one set of transistors MB are connected in parallel. Each of the two sets of transistors MA and MB includes two transistors, and the two transistors in the same set are coupled in series between the first terminal of the capacitor C1 and the transistor M2, Figure 8 In the embodiment shown in FIG. 2, one set of transistors MA includes a transistor MA1 and a transistor MA2, and one set of transistors MB includes a transistor MB1 and a transistor MB2. The drain of the transistor MA1 and the drain of the transistor MB1 are coupled to a node a, the source of the transistor MA1 and the drain of the transistor MA2 are coupled, the source of the transistor MB1 and the drain of the transistor MB2 are coupled, and the source of the transistor MA2 and the source of the transistor MB2 are coupled to the drain of the transistor M2. The gate of the transistor MA1 is coupled to the control terminal vc1 of the constant switching energy extraction circuit 101, the gate of the transistor MB1 is coupled to the control terminal vc2 of the constant switching energy extraction circuit 101, and the gate of the transistor MA2 and the gate of the transistor MB2 are both coupled to the gate of the transistor M3 (i.e., the output terminal of the current mirror circuit). The source of the transistor M2 is coupled to the common ground Gnd, and the gate of the transistor M2 is coupled to the control terminal P0 of the constant switching energy extraction circuit 101. In addition, the source of the transistor M1 is coupled to the drain of the transistor M2 to be coupled to the common ground Gnd through the transistor M2. It should be noted that in the embodiments of the present application, Figure 3 The controller 103 shown in FIG. 2 controls the width of the pulse signal output by the pulse signal output terminal pon by controlling the number of sets of transistors turned on for mirroring the current in the current mirror circuit, that is, the on duration of the power switch K1.

[0074] The comparison circuit includes transistors M5, M6, M7 and an XOR gate H. The transistor M5 and the transistor M6 are coupled in series between the power supply end Vcc and the control end (gate) of the transistor M1, the gate of the transistor M6 is coupled with the first end of the capacitor C1; the transistor M7 is coupled between the control end (gate) of the transistor M1 and the common ground Gnd, the control end (gate) of the transistor M7 is coupled to the first end of the capacitor C1; the first input end of the XOR gate H is coupled with the control end of the transistor M1, the second input end of the XOR gate H is coupled to the output end p0 of the comparator B, and the output end of the XOR gate H is the pulse signal output end pon of the constant switching energy extraction circuit 101, which is coupled with the control end of the power switch K1. Figure 6 The output end p0 of the comparator B is coupled with the gate of the transistor M5 through the inverter F1.

[0075] As shown in the pulse signal generation circuit 1011, Figure 8 the transistors M1, M2 and M7 are NMOS transistors, and the transistors M4, M5 and M6 are PMOS transistors, so that each transistor can be driven based on the control signal output by the output end p0 of the comparator B, and the pulse signal generation circuit 1011 as shown in Figure 8 works to generate a pulse signal provided to the output end pon. Wherein, the output end p0 of the comparator B is coupled with the gate of the transistor M5 through the inverter F1. It should be noted that the type of the transistors M1 to M7 is not specifically limited in the embodiments of the present application, and can be set based on the needs of the application scenario. In addition, based on different types of transistors, the driving signals of each transistor can also be adaptively adjusted.

[0076] Based on the pulse signal generation circuit 1011 as shown in Figure 8 , please refer to Figure 9 , Figure 9 is the working timing of the pulse signal generation circuit 1011 as shown in Figure 8 . Wherein, P0 is the timing signal output by the output end p0 of the comparator B, Va is the timing voltage signal of node a, Vb is the timing voltage signal of node b, and Pon is the timing signal output by the output end pon of the XOR gate H. From Figure 9As can be seen from the working timing shown, when the comparator B outputs a low level signal, the transistor M2 is turned off, a reset operation is performed, the node a is charged to VDD, and the node b is "0"; when the output end p0 of the comparator B outputs a high level signal, the transistor M2 is turned on, at least one of the transistor group MA and the transistor group MB draws electricity from the node a, and after the node a is lowered to (VDD-VTH), the transistor M1 is turned on to make the node a quickly drop to "0". The time from when the comparator B outputs a high level signal to when the node a is lowered to "0" is the on time ton of the power switch K1 in the DC-DC converter 12, and the output value is shown in formula (4).

[0077]

[0078] Wherein, C1 is the capacitance value of the capacitor C1, I BAS is the current value provided by the current loop circuit, V DD is the voltage value provided by the power supply end Vdd, V TH is the on threshold value of the transistor MA1 or MB1; N is the number of groups of transistors used for mirroring the current loop circuit.

[0079] Please continue to refer to Figure 10 , Figure 10 is a structural diagram of a reference voltage signal generation circuit 1012 in the constant switch energy extraction circuit 101 provided by the embodiment of the present application. As Figure 10 shown, the reference voltage signal generation circuit 1012 includes an output end vref, a transistor M8, at least one group of AND gate capacitor combination circuits, a capacitor C2, a capacitor C3, an inverter F2 and an inverter F3; wherein the at least one group of AND gate capacitor combination circuits can include one group, two groups or three groups, etc., which are not limited by the embodiment of the present application. Each group of AND gate capacitor combination circuits includes an AND gate Y1 and a capacitor C, wherein one of the input ends of the AND gate Y1 is coupled to a system clock signal CLK, the other input end is connected with a control end vc1 (or a control end vc2), the output end of the AND gate Y1 is connected with one end of the capacitor C, and the other end of the capacitor C is connected to the output end vref. The drain of the transistor M8 is coupled to the output end vref, and the source of the transistor M8 is coupled to the common ground Gnd. The input end of the inverter F2 is coupled to the system clock signal CLK, and the output end of the inverter F2 is coupled with the control end (gate) of the transistor M8. The input end of the inverter F3 is coupled with the output end of the inverter F2, and the output end of the inverter F3 is coupled to the output port Vref through the capacitor C2. The capacitor C3 is arranged between the output port Vref and the common ground Gnd. As Figure 10The reference voltage signal generating circuit 1012 shown, when CLK is low, all capacitors are reset to ground, the output end vref output reference voltage signal is 0V; when CLK is high, the control signal is high capacitor access power end, the output end vref output reference voltage signal VREF as formula (5)

[0080]

[0081] Combined with formula (4) and formula (5), then formula (6)

[0082]

[0083] The above through Figures 7-9 The embodiment shown, introduced when the DC-DC converter 12 in the power switch K1 on the length ton is much greater than the power switch K2 on the length toff, the structure and driving timing of the pulse signal generating circuit 1011. When the power switch K1 on the length ton does not satisfy the condition that the power switch K2 on the length toff is much greater, even if you can make the product of ton and Vref is constant, it can not be guaranteed that the DC-DC converter 12 can obtain constant energy within each switch, wherein the error Ro between the energy Esw obtained by the DC-DC converter 12 and the energy Eccepe provided by the switch energy extraction circuit 101 to the DC-DC converter 12 is shown in formula (3). From formula (3), when the power switch K1 on the length ton does not satisfy the condition that the power switch K2 on the length toff is much greater, the error Ro between the energy Esw obtained by the DC-DC converter 12 and the energy Eccepe provided by the switch energy extraction circuit 101 to the DC-DC converter 12 is greater. At this time, if a certain multiple of the power switch K2 on the length toff is compensated on the basis of the original power switch K1 on the length ton, the compensation can effectively reduce the error between the actual energy obtained by the DC-DC converter 12 and the theoretical energy. Specifically, the energy Eccepe input by the constant switch energy extraction circuit 101 to the DC-DC converter 12 is referenced to formula (7)

[0084]

[0085] Wherein, Vin is the voltage input port vin input voltage, that is, the voltage of the energy source input, ton is the on time of the power switch K1 in the DC-DC converter 12, toff is the on time of the power switch K2, based on formula (7), the error Ro between the energy Esw obtained by the DC-DC converter 12 and the energy Eccepe provided by the switch energy extraction circuit 101 to the DC-DC converter 12 is shown in formula (8)

[0086]

[0087] In formula (8), VCR is the ratio of the voltage Vo at the output port vo of the DC-DC converter 12 to the voltage Vi at the input port vi. As can be seen from formula (8), when the on duration ton of the power switch K1 does not satisfy the condition of being much greater than the off duration toff of the power switch K2, the error between the energy Esw obtained by the DC-DC converter 12 and the energy Eccepe provided by the switching energy extraction circuit 101 to the DC-DC converter 12 can be reduced by adjusting the value of β. Based on the above principle, please continue to refer to Figure 11 , Figure 11 is another structural schematic diagram of the pulse signal generation circuit 1011 provided by the embodiments of the present application. As shown in the pulse signal generation circuit 1011, Figure 11 when the on duration ton of the power switch K1 in the DC-DC converter 12 is much greater than the off duration toff of the power switch K2, a certain multiple of the off duration toff of the power switch K2 can be compensated on the basis of the on duration ton of the original power switch K1 to reduce the error. As shown in the pulse signal generation circuit 1011, Figure 11 on the basis of the pulse signal generation circuit 1011, Figure 9 the pulse signal generation circuit 1011 further includes a compensation circuit. The compensation circuit includes an AND gate Y2, a transistor M9, a transistor M10, a resistor R2 and a variable capacitor Cd. The first input end of the AND gate Y2 is coupled to the output end pon of the XOR gate H; the output end pon of the XOR gate H is coupled to the gate of the transistor M9 and the gate of the transistor M10; the source of the transistor M9 is coupled to the power supply end Vcc, the drain of the transistor M9 is coupled to the drain of the transistor M10 through the resistor R2, and the source of the transistor M10 is coupled to the common ground Gnd; the coupling position of the transistor M9 and the resistor R2 forms a node c, the variable capacitor Cd is coupled between the node c and the common ground Gnd, and the node c is coupled to the second input end of the AND gate Y2; the output end pon,c of the AND gate Y2 is coupled to the control end of the power switch K1 in the DC-DC converter 12. As shown in the pulse signal generation circuit 1011, Figure 11 the variable capacitor Cd can also be a capacitor array connected in parallel. By controlling the number of capacitors accessed in the pulse signal generation circuit 1011 or adjusting the size of the capacitance value of the variable capacitor, the adjustment of the value of β in formula (7) can be realized, so that the error between the energy obtained by the DC-DC converter 12 and the energy provided by the switching energy extraction circuit 101 to the DC-DC converter 12 can be reduced. It should be noted that the on duration of the power switch K2 in the DC-DC converter 12 (i.e., the off duration toff of the DC-DC converter 12) is realized by ZCD control. Among them, Figure 12 is a diagram of the pulse signal generation circuit 1011Figure 11 the working timing of the pulse signal generating circuit 1011. In Figure 12 the working timing of the pulse signal generating circuit 1011. In Figure 12 the working timing of the pulse signal generating circuit 1011. In

[0088] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A maximum power point tracking circuit, characterized by, The constant switching energy extraction circuit, a frequency counter and a controller are included. The frequency counter is coupled with a control terminal of a first power switch in a direct current-direct current (DC-DC) converter and the controller, and is configured to count a first switching frequency of the first power switch in a first clock cycle and provide the first switching frequency to the controller. The controller is coupled with the constant switching energy extraction circuit, and is configured to compare the first switching frequency with a second switching frequency of the first power switch in a second clock cycle, and generate a control signal based on a comparison result and transmit the control signal to the constant switching energy extraction circuit, where the second clock cycle is a previous clock cycle of the first clock cycle. The constant switching energy extraction circuit is coupled with a voltage signal input terminal of the maximum power point tracking circuit and the control terminal of the first power switch, and is configured to generate a reference voltage signal based on the control of the control signal, compare the reference voltage signal with an input voltage signal provided by the voltage signal input terminal, and generate a pulse signal based on a comparison result and transmit the pulse signal to the control terminal of the first power switch, where the input voltage signal is generated based on an external energy source. In any one of the first clock cycle and the second clock cycle, the first power switch includes at least one on duration, and a product of each of the at least one on duration and the reference voltage signal is a constant amount. The controller is specifically configured to: when detecting that the second switching frequency is higher than the first switching frequency, transmit a first control signal to the constant switching energy extraction circuit, where the first control signal is used to indicate that the reference voltage signal is increased and the on duration of the first power switch is reduced.

2. The maximum power point tracking circuit of claim 1, wherein, The controller is specifically configured to:

3. The maximum power point tracking circuit of claim 1 or 2, characterized in that, When detecting that the second switching frequency is lower than the first switching frequency, transmit a second control signal to the constant switching energy extraction circuit, where the second control signal is used to indicate that the reference voltage signal is reduced and the on duration of the first power switch is increased. The constant switching energy extraction circuit includes a pulse signal generation circuit, a reference voltage signal generation circuit and a comparator.

4. The maximum power point tracking circuit of claim 1, wherein, A first input terminal of the comparator is coupled with an output terminal of the reference voltage signal generation circuit, a second input terminal of the comparator is coupled with the voltage signal input terminal of the maximum power point tracking circuit, and an output terminal of the comparator is coupled with a first control terminal of the pulse signal generation circuit. The reference voltage signal generation circuit generates the reference voltage signal based on the control of the controller and provides the reference voltage signal to the first input terminal of the comparator. The comparator compares the input voltage signal with the reference voltage signal, and transmits a first signal to the pulse signal generation circuit when the input voltage signal is greater than or equal to the reference voltage signal. ​ The pulse signal generation circuit controls the first power switch to be turned on based on the first signal, and controls the on duration of the first power switch based on the control signal transmitted by the controller.

5. The maximum power point tracking circuit of claim 4, wherein, The pulse signal generation circuit comprises a first capacitor, a charging circuit for charging the first capacitor, a discharging circuit for discharging the first capacitor, a first transistor, and a comparison circuit. The charging circuit is arranged between a power supply end and a first end of the first capacitor, a second end of the first capacitor is connected to a common ground, and the charging circuit charges the first capacitor based on the first signal. The discharging circuit is arranged between the first end of the first capacitor and the common ground, and the discharging circuit discharges the first capacitor based on the control of the control signal and the first signal. The first transistor is arranged between the first end of the first capacitor and the common ground, and the first transistor is used to turn on when the first capacitor is discharged to a first threshold value. The comparison circuit is used to compare the voltage of the first end of the first capacitor with a preset voltage threshold, and generate the pulse signal based on the comparison result.

6. The maximum power point tracking circuit of claim 5, wherein, The discharging circuit comprises a current mirror circuit, at least one group of transistors for mirror copying the current mirror circuit, and a second transistor arranged between the at least one group of transistors and the common ground. The at least one group of transistors is arranged between the first end of the first capacitor and the second transistor, each group of transistors in the at least one group of transistors comprises a third transistor and a fourth transistor, the third transistor and the fourth transistor are coupled in series between the first end of the first capacitor and the second transistor, the third transistor is turned on or turned off based on the control of the controller, and the control end of the fourth transistor is coupled with the current mirror circuit. The first transistor is coupled to the common ground through the second transistor, and the second transistor is turned on or turned off based on the control of the signal transmitted by the comparator.

7. The maximum power point tracking circuit of claim 5, wherein, The charging circuit comprises a fifth transistor, the fifth transistor is arranged between the power supply end and the first end of the first capacitor, and the fifth transistor charges the first capacitor based on the control of the first signal.

8. The maximum power point tracking circuit of any of claims 5 to 7, wherein, The comparison circuit comprises a sixth transistor, a seventh transistor, an eighth transistor, and an XOR gate. The sixth transistor and the seventh transistor are coupled in series between the power supply end and the control end of the first transistor, the sixth transistor is turned on or turned off based on the control of the signal output by the comparator, and the control end of the seventh transistor is coupled with the first end of the first capacitor. The eighth transistor is coupled between the control end of the first transistor and the common ground, and the control end of the eighth transistor is coupled to the first end of the first capacitor. The first input end of the XOR gate is coupled with the control end of the first transistor, the second input end is coupled with the output end of the comparator, and the output end of the XOR gate is coupled with the control end of the first power switch.

9. The maximum power point tracking circuit of claim 8, wherein, The pulse signal generation circuit further comprises a compensation circuit, the compensation circuit comprising a first AND gate, a ninth transistor, a tenth transistor, a first resistor and a variable capacitor; a first input terminal of the first AND gate is coupled with an output terminal of the XOR gate; the output terminal of the XOR gate is coupled to a gate of the ninth transistor and a gate of the tenth transistor; a first pole of the ninth transistor is coupled with the power supply terminal, a second pole of the ninth transistor is coupled with a first pole of the tenth transistor through the first resistor, and a second pole of the tenth transistor is coupled to a common ground; the variable capacitor is coupled between the second pole of the ninth transistor and the common ground, and the second pole of the ninth transistor is coupled with a second input terminal of the first AND gate; an output terminal of the first AND gate is coupled with a control terminal of the first power switch; wherein the ninth transistor and the tenth transistor are transistors of different types.

10. The maximum power point tracking circuit of claim 4, wherein, The reference voltage signal generation circuit comprises an output terminal, at least one set of capacitor-AND gate combination circuit, an eleventh transistor, a third capacitor, a fourth capacitor, a second inverter and a third inverter; any one of the at least one set of capacitor-AND gate combination circuit comprises a second capacitor and a second AND gate, a first input terminal of the second AND gate is used for inputting a system clock signal of the maximum power point tracking circuit, a second input terminal of the second AND gate is used for inputting a control signal transmitted by the controller, and an output terminal of the second AND gate is coupled with the output terminal through the second capacitor; a first terminal of the eleventh transistor is coupled to the output terminal, and a second terminal of the eleventh transistor is coupled to a common ground; an input terminal of the second inverter is coupled with a first input terminal of the second AND gate, and an output terminal of the second inverter is coupled with a control terminal of the eleventh transistor; an input terminal of the third inverter is coupled with an output terminal of the second inverter, and an output terminal of the third inverter is coupled to the output terminal through the third capacitor; the fourth capacitor is arranged between the output terminal and the common ground.

11. An energy harvesting device, characterized by, The maximum power point tracking circuit comprises any one of claims 1 to 10.

12. The energy-harvesting device of claim 11, wherein, The energy collection device further comprises a DC-DC converter, the DC-DC converter comprising an input port, an inductor and a first power switch; the input port of the DC-DC converter is coupled with an energy source; the inductor is coupled between the input port and a first terminal of the first power switch, and a second terminal of the first power switch is coupled to a common ground; a pulse signal output terminal of the maximum power point tracking circuit is coupled with a control terminal of the first power switch.

13. The energy-harvesting device of claim 12, wherein, The DC-DC conversion circuit further comprises a second power switch, a fifth capacitor and a resistor; a first terminal of the second power switch is coupled with a first terminal of the first power switch, and a second terminal of the second power switch is coupled with an output port of the DC-DC conversion circuit; the fifth capacitor is coupled between the second terminal of the second power switch and the common ground; the resistor is coupled between the second terminal of the second power switch and the common ground.

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