Memory system, operating method thereof, storage medium, and electronic device

Abstract

The embodiment of the invention provides a memory system, an operation method of the memory system, a computer readable storage medium and electronic equipment. The memory system includes: a memory including a plurality of memory blocks, the memory blocks including a plurality of physical pages; the memory controller is coupled with the memory, and the memory controller is configured to determine the sum of reading times of a physical page adjacent to a first target physical page in a first memory block in the plurality of memory blocks; in response to the fact that the sum of the reading times is larger than or equal to a first threshold value, moving the data stored in the first target physical page to a second storage block in the multiple storage blocks; wherein the second storage block is different from the first storage block.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular, to a memory system and an operating method thereof, a computer readable storage medium, and an electronic device. BACKGROUND

[0002] In recent years, the semiconductor integrated circuit industry has experienced rapid growth. As the semiconductor manufacturing process continues to progress, the feature size of semiconductor devices continues to shrink, and the integration density of memory continues to increase. For example, non-volatile semiconductor memory is widely used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and various other electronic devices. As the development of information, the amount of data used by these devices is also rapidly increasing, which drives larger storage capacity and faster access speed.

[0003] In a read operation of a memory, data information stored in a memory cell can be obtained by applying a read voltage to a selected word line and applying a pass voltage to an unselected word line. However, as the requirement for the performance of the memory is continuously improved, there are still many problems in the execution of the read operation of the memory. SUMMARY

[0004] The present disclosure provides a memory system and an operating method thereof, a computer readable storage medium, and an electronic device.

[0005] In a first aspect, the present disclosure provides a memory system, comprising:

[0006] a memory, the memory comprising a plurality of memory blocks, the memory blocks comprising a plurality of physical pages;

[0007] a memory controller coupled to the memory, the memory controller configured to:

[0008] determine a sum of read times of physical pages adjacent to a first target physical page in a first memory block of the plurality of memory blocks;

[0009] in response to the sum of read times being greater than or equal to a first threshold, move data stored in the first target physical page to a second memory block of the plurality of memory blocks; wherein the second memory block is different from the first memory block.

[0010] In some embodiments, the memory controller is specifically configured to:

[0011] count the read times of the physical pages adjacent to the first target physical page to determine the sum of read times.

[0012] In some embodiments, the memory controller is specifically configured to:

[0013] determining, in response to a read request comprising a logical address, a physical address corresponding to the logical address; wherein the physical address comprises a physical address of the physical page adjacent to the first target physical page;

[0014] reading, in response to the physical address, the physical page adjacent to the first target physical page and counting a number of times of reading the physical page adjacent to the first target physical page.

[0015] In some embodiments, the memory controller comprises a counting circuit configured to:

[0016] counting a number of times of reading the physical page adjacent to the first target physical page to determine the sum of the number of times of reading.

[0017] In some embodiments, the memory controller is specifically configured to:

[0018] counting a number of times of reading the physical page adjacent to the first target physical page within a preset time period to determine the sum of the number of times of reading.

[0019] In some embodiments, the first threshold value of the different first target physical pages in the first storage block is different.

[0020] In some embodiments, the memory controller is further configured to:

[0021] determining a number of times of reading a second target physical page in the first storage block;

[0022] moving data stored in the second target physical page to the second storage block in response to the number of times of reading the second target physical page being greater than or equal to a second threshold value; wherein the second threshold value is less than or equal to the first threshold value.

[0023] In some embodiments, the memory controller is further configured to:

[0024] determining whether the reading for the second target physical page is a single logical page reading;

[0025] moving data stored in the second target physical page to the second storage block in response to the reading for the second target physical page being a single logical page reading and the number of times of reading the second target physical page being greater than or equal to the second threshold value.

[0026] In some embodiments, a number of bits of a storage unit in the second storage block is less than a number of bits of a storage unit in the first storage block.

[0027] In some embodiments, the first storage block comprises two-tier cells, three-tier cells, or four-tier cells; and the second storage block comprises one-tier cells.

[0028] In some embodiments, the memory controller is further configured to:

[0029] update a logical address to physical address mapping table in response to the data being moved to the second storage block.

[0030] In a second aspect, the present disclosure provides an operation method of a memory system, the memory system comprising a memory and a memory controller coupled to the memory; the memory comprising a plurality of storage blocks, the storage blocks comprising a plurality of physical pages; the operation method comprising:

[0031] determining a sum of read times of physical pages adjacent to a first target physical page in a first storage block of the plurality of storage blocks;

[0032] moving data stored in the first target physical page to a second storage block of the plurality of storage blocks in response to the sum of read times being greater than or equal to a first threshold; wherein the second storage block is different from the first storage block.

[0033] In some embodiments, the determining the sum of read times of physical pages adjacent to a first target physical page in a first storage block of the plurality of storage blocks comprises:

[0034] counting the read times of the physical pages adjacent to the first target physical page to determine the sum of read times.

[0035] In some embodiments, the operation method further comprises:

[0036] determining a physical address corresponding to a logical address in response to a read request comprising the logical address; wherein the physical address comprises physical addresses of the physical pages adjacent to the first target physical page;

[0037] reading the physical pages adjacent to the first target physical page in response to the physical address.

[0038] the counting the read times of the physical pages adjacent to the first target physical page comprises:

[0039] counting the read times of the physical pages adjacent to the first target physical page in response to reading the physical pages adjacent to the first target physical page.

[0040] In some embodiments, the first threshold of the first target physical page in the first storage block is different from the first threshold of a different first target physical page in the first storage block.

[0041] In some embodiments, the operation method further includes:

[0042] determining a read count of a second target physical page in the first storage block;

[0043] in response to the read count of the second target physical page being greater than or equal to a second threshold, moving data stored in the second target physical page to the second storage block; wherein the second threshold is less than or equal to the first threshold.

[0044] In some embodiments, the operation method further includes:

[0045] determining whether the read for the second target physical page is a single logical page read;

[0046] the response to the read count of the second target physical page being greater than or equal to a second threshold, moving data stored in the second target physical page to the second storage block, includes:

[0047] in response to the read for the second target physical page being a single logical page read and the read count of the second target physical page being greater than or equal to the second threshold, moving data stored in the second target physical page to the second storage block.

[0048] In some embodiments, the operation method further includes:

[0049] determining the second threshold according to a reference threshold of a read count of a single physical page in the memory; wherein the second threshold is 1 / 5 to 1 / 3 of the reference threshold.

[0050] In some embodiments, the operation method further includes:

[0051] in response to the data being moved to the second storage block, updating a logical address to physical address mapping table.

[0052] In a third aspect, the present disclosure provides a computer readable storage medium having stored thereon executable instructions that, when executed, implement the operation method of any of the above embodiments.

[0053] In a fourth aspect, the present disclosure provides an electronic device, comprising the memory system of any of the above embodiments.

[0054] In the embodiments of the present disclosure, the memory controller is configured to determine a sum of read times of physical pages adjacent to the first target physical page in the first memory block, and then move data stored in the first target physical page to a second memory block in response to the sum of read times being greater than or equal to a first threshold, and the second memory block is different from the first memory block. In this way, the memory controller can reduce the interference on the first target physical page caused by repeatedly reading the adjacent physical pages multiple times, alleviate the phenomenon of threshold voltage offset, reduce the error bit count of reading the first target physical page, and thus improve the reliability of the memory. BRIEF DESCRIPTION OF DRAWINGS

[0055] Figure 1 A schematic diagram of a system with a memory according to an embodiment of the present disclosure;

[0056] Figure 2a A schematic diagram of a memory card according to an embodiment of the present disclosure;

[0057] Figure 2b A schematic diagram of a solid state drive (SSD) according to an embodiment of the present disclosure;

[0058] Figure 3 A schematic diagram of threshold voltage distribution states of memory cells of different levels according to an embodiment of the present disclosure;

[0059] Figure 4 A schematic diagram of physical pages corresponding to a plurality of word lines in a memory block according to an embodiment of the present disclosure;

[0060] Figure 5 A schematic diagram of a memory system according to an embodiment of the present disclosure;

[0061] Figure 6 A schematic diagram of a counting circuit in a memory controller according to an embodiment of the present disclosure;

[0062] Figure 7 A step flowchart of an operation method of a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] In order to facilitate the understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms, and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood, and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0064] In the following description, numerous specific details are given to provide a thorough understanding of the disclosure. However, it will be apparent that the disclosure can be practiced without one or more of the specific details. In some embodiments, well-known structures and techniques are not described in order to avoid obscuring the disclosure. In some embodiments, in order to avoid obscuring the disclosure, some technical features that are well-known in the art are not described; that is, all features of actual embodiments can not be described here, and well-known functions and structures are not described in detail.

[0065] Generally, the terminology can be understood at least in part from usage of the terms in the context in which they are used. For example, the term "one or more" as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in the singular or can be used to describe combinations of features, structures or characteristics, in the plural, both singly and in combination. Likewise, terms such as "a" and "the" can be construed to mean either singular or plural, depending at least in part upon context. Additionally, the term "based on" can be construed to mean "based, at least in part, on," that is, the term "based on" can be construed to mean both "based on" and "based, at least in part, on."

[0066] Unless otherwise defined, the terms used herein are intended to have their ordinary meaning in the art. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0067] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail as follows, however, in addition to these detailed descriptions, the present disclosure can also have other implementation manners.

[0068] Figure 1 A schematic diagram of a system 100 having a memory according to some aspects of the present disclosure is shown. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a memory therein.

[0069] AsFigure 1 As shown in FIG. 1, the system 100 can include a host 108 and a memory system 102 having one or more memories 104 and a memory controller 106. The host 108 can be a processor (e.g., a Central Processing Unit (CPU) or a System on Chip (SoC) (e.g., an Application Processor (AP))) of an electronic device. The host 108 can be configured to send or receive data to or from the memory 104.

[0070] According to some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108, and is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a Secure Digital Memory Card (SD Card), a Compact Flash Card (CF Card), a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment solid state drive or an Embedded Multi Media Card (eMMC), which are used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0071] The memory controller 106 may be configured to control operations of the memory 104, such as read, erase, and write (also known as programming) operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is further configured to process error correction codes (ECC) for data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with a host (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the host 108 through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCIE) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced System Device Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, etc.

[0072] The memory controller 106 and the one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash memory package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown in FIG, the memory controller 106 and the single memory 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association, PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a Multi Media Card (MMC), a Reduced-Size MMC (RS-MMC), a Micro Multi Media Card (MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a Universal Flash Storage (UFS), etc. The memory card 202 may also include a computer that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in FIG. Figure 2b In another example shown in , the memory controller 106 and the plurality of memories 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0073] In the embodiments of the present disclosure, the memory may be a NAND flash memory, but it should be understood that the solution or technology of the present disclosure is not limited to application in NAND flash memory, and can be applied to other types of memory devices, such as Electrically Erasable Programmable Read-Only Memory (EEPROM), NOR flash memory, Phase Change Random Access Memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0074] In embodiments of the present disclosure, each of the storage dies can include one or more arrays of storage cells. One type of storage cell, such as a Single-Level Cell (SLC), can store one bit per cell. Other types of storage cells, such as Multi-Level Cell (MLC), Trinary-Level Cell (TLC), Quad-Level Cell (QLC), and Penta-Level Cell (PLC), can store multiple bits per cell. In some embodiments, each of the memory can include one or more arrays of storage cells, such as an SLC array, an MLC array, a TLC array, a QLC array, or any combination of such arrays of storage cells.

[0075] In some embodiments, as shown in FIG. 1A, an SLC can correspond to two threshold voltage distributions: P0 and P1, where the threshold voltage distribution P0 corresponds to an erased data state; the threshold voltage distribution P1 corresponds to a programmed data state. The threshold voltage of the erased data state corresponding to the threshold voltage distribution P0 is less than the threshold voltage of the programmed data state corresponding to the threshold voltage distribution P1. Thus, a memory cell having a threshold voltage in the threshold voltage distribution P0 is in an erased data state; a memory cell having a threshold voltage in the threshold voltage distribution P1 is in a programmed data state. In some implementations, an SLC type memory cell stores 1 bit of data. Figure 3

[0076] An MLC corresponds to four threshold voltage distributions: P0, P1, P2, and P3, and the threshold voltages increase in order. Again, the threshold voltage distribution P0 corresponds to an erased data state; the threshold voltage distributions P1, P2, and P3 correspond to programmed states. In some implementations, an MLC type memory cell stores 2 bits of data.

[0077] A TLC corresponds to eight threshold voltage distributions: P0, P1, P2, P3, P4, P5, P6, and P7, and the threshold voltages increase in order. Similarly, the threshold voltage distribution P0 corresponds to an erased data state; the threshold voltage distributions P1, P2, P3, P4, P5, P6, and P7 correspond to programmed data states. In some implementations, a TLC type memory cell stores 3 bits of data.

[0078] ​In QLC, it corresponds to sixteen threshold voltage distributions: P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, and P15, and the threshold voltage increases sequentially. Similarly, threshold voltage distribution P0 corresponds to the erased data state; threshold voltage distributions P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, and P15 correspond to the programmed data state. In some embodiments, the QLC type memory cell stores 4 bits of data. Specifically, the 4 bits of data stored in the storage cell in the QLC memory correspond to the data of 4 logical pages, namely, lower page (LP) data, middle page (MP) data, upper page (UP) data, and extra page (XP) data.

[0079] In some embodiments, the memory may include multiple storage blocks. Figure 4 As shown, a memory block may include multiple memory strings (String, ST), a first end of each memory cell string ST is connected to a bit line (Bit Line, BL), a second end is connected to a source line (Source Line, SL), and multiple memory cells M1 to M on the memory cell string ST n The gates are coupled to word lines WL1 to WL n , where all the memory cells coupled to a word line can constitute a physical page in the memory block. When the memory controller performs a read operation on the memory, a read voltage V is applied to the selected word line. read , a pass voltage V is applied to the unselected word lines pass , and the threshold voltage V of the selected memory cell can be determined by sensing the current on the selected bit line. t The size of the voltage V is used to obtain the data information stored in the selected storage unit. pass Greater than the read voltage V read , and each read operation only selects one word line (i.e., read by page), that is, each read operation applies a read voltage V to a selected word line read , while applying the pass voltage V to all other unselected word lines pass . In this way, the larger pass voltage V passThis can cause slight programming (also known as soft programming) to memory cells coupled to unselected word lines. After multiple read operations, the cumulative effect of the slight programming can cause the threshold voltage distribution of memory cells in the memory block to shift (e.g., shift right), ultimately leading to read errors. This phenomenon is known as read disturb (RD). When multiple read operations are performed on the same selected word line (physical page), memory cells coupled to at least one unselected word line adjacent to the selected word line will experience greater read disturb, resulting in a significant increase in the Fail Bit Count (FBC) of the read operation and a decrease in memory reliability. This phenomenon is known as single page read disturb (SPRD). It can be understood that single page read disturb can refer to the read disturbance caused by multiple read operations on the same physical page. For example, the memory controller may receive a read request containing a logical address from outside the memory system (such as a host). The physical address of each physical page in the memory may correspond to one or more logical addresses. In this way, when the logical addresses involved in multiple read requests received by the memory controller are all mapped to the same physical address, the corresponding physical page (a word line) in the memory will be repeatedly read multiple times, thereby causing the occurrence of single-page read interference. In some embodiments, the pass voltage V applied to the unselected word line can be appropriately reduced. pass To alleviate the impact of slight programming accumulation in multiple read operations, however, this method cannot solve the problem of read disturbance from the root.

[0080] like Figure 5 As shown, the present disclosure provides a memory system 30, comprising: a memory 301, wherein the memory 301 comprises a plurality of memory blocks 310, wherein the memory block 310 comprises a plurality of physical pages; a memory controller 302, wherein the memory controller 302 is coupled to the memory 301, and wherein the memory controller 302 is configured to: determine a first memory block 310a in the plurality of memory blocks 310 corresponding to a first target physical page P n The sum of the number of reads of adjacent physical pages; in response to the sum of the number of reads being greater than or equal to a first threshold, the first target physical page P n The data stored in is moved to a second storage block 310b among the plurality of storage blocks 310; wherein the second storage block 310b is different from the first storage block 310a.

[0081] In an embodiment of the present disclosure, a memory system 30 includes a memory 301 and a memory controller 302 coupled to the memory 301. The memory 301 may include multiple memory blocks 310, each memory block 310 may include multiple physical pages, each of which corresponds one-to-one to multiple word lines, and each physical page includes all memory cells coupled to a corresponding word line. The memory 301 may be NAND flash memory, electrically erasable programmable read-only memory, NOR flash memory, phase-change random access memory, magnetic RAM, resistive RAM, ferroelectric RAM, etc. Here, the memory 301 is described as NAND flash memory. The memory controller 302 may be implemented using hardware (e.g., logic circuits), software, firmware, or a combination of hardware, software, and firmware. Examples of logic circuits include dedicated hardwired logic circuits (e.g., one or more state machine logic circuits), programmable logic circuits (e.g., field programmable gate arrays (FPGAs) and programmable logic arrays (PLAs), etc.). In some embodiments, the logic circuits of the memory controller 302 are designed to execute some form of program code, such as memory firmware (e.g., an embedded processor, an embedded controller, etc.).

[0082] The memory controller 302 can determine the physical address of the first target physical page P in the first storage block 310a by counting the number of read operations performed on each physical page or analyzing the physical address corresponding to the read command received from an external device (such as a host). n The sum of the number of reads of adjacent physical pages. It can be understood that if the first target physical page P n Corresponding to the first word line or the last word line in the first memory block 310a, the first target physical page P n There can be only one adjacent physical page; if the first target physical page P n Corresponding to the word lines located in the middle portion of the first memory block 310a, that is, corresponding to the word lines other than the first word line and the last word line, the first target physical page P n There can be two adjacent physical pages (P n+1 and P n-1 ).

[0083] The memory controller 302 may also respond to the first target physical page P n If the sum of the number of reads of adjacent physical pages is greater than or equal to a first threshold, the first target physical page P n The data stored in the first memory block 310a is moved to the second memory block 310b, where the second memory block 310b and the first memory block 310a are two different memory blocks. In other words, in order to prevent or reduce the repeated reading of adjacent word lines (such as WL n+1 and WL n-1 ) memory cells coupled to the word line WLn The slight programming caused by the coupled storage unit eventually leads to a read error, and a first threshold value can be set to represent an upper limit of the total number of read disturbances suffered by the storage unit in the first target physical page P n . If the sum of the read times of the physical pages adjacent to the first target physical page P n is greater than or equal to the first threshold value, data migration can be triggered, that is, the memory controller 302 moves the data stored in the first target physical page P n to other open storage blocks (such as the second storage block 310b), where the open storage block refers to a storage block in which only part of the physical pages are written with data, and other physical pages are not written with data. It should be noted that the first threshold value can be determined according to the actual test results of the memory product, or a reference value can be provided by the designer. In this disclosure, the memory controller 302 moves the data stored in the first target physical page P n to the second storage block 310b, which can be achieved by first reading the data stored in the first target physical page P n , and then writing the read data to the second storage block 310b. That is, the process of "data migration" in this disclosure can temporarily not erase the data stored in the first target physical page P n , and after the "data migration" is completed, the data stored in the first target physical page P n becomes invalid data, so the memory controller 302 can erase the invalid data stored in the first target physical page P n in subsequent operations (such as garbage collection operations).

[0084] In this way, the memory controller 302 can reduce the interference caused by repeatedly reading adjacent physical pages on the first target physical page P n , alleviate the threshold voltage offset phenomenon, reduce the error bit count of reading the first target physical page P n , and thus improve the reliability of the memory.

[0085] In some embodiments, the number of bits of the storage unit in the second storage block 310b is less than the number of bits of the storage unit in the first storage block 310a.

[0086] In the embodiments of the present disclosure, the performance of the storage unit in terms of read interference resistance, read speed, data retention capability, etc. decreases as the number of storage unit levels increases, that is, the performance of SLC, MLC, TLC, QLC decreases in turn. In this way, the number of bits (i.e., the number of levels) of the storage unit in the second storage block 310b can be less than the number of bits (i.e., the number of levels) of the storage unit in the first storage block 310a, that is, the number of bits (i.e., the number of levels) of the storage unit in the first target physical page P nIn a case where the sum of the read times of the adjacent physical pages is greater than or equal to a first threshold value, the data stored in the first target physical page P n to the second storage block 310b with better read interference resistance, read speed, and data retention capability, thereby reducing the problem of frequent read retries caused by read errors, reducing the refresh frequency of the storage block, improving the performance of the memory system in subsequent read operations, and improving the data reliability of the memory system in some complex use scenarios. For example, if the storage unit in the first storage block 310a is QLC, the storage unit in the second storage block 310b can be TLC, MLC, or SLC; if the storage unit in the first storage block 310a is TLC, the storage unit in the second storage block 310b can be MLC or SLC; and if the storage unit in the first storage block 310a is MLC, the storage unit in the second storage block 310b can be SLC.

[0087] In some embodiments, the first storage block 310a includes two-layer cells, three-layer cells, or four-layer cells; and the second storage block 310b includes single-layer cells.

[0088] In the embodiments of the present disclosure, each storage block 310 in the memory 301 can include a type of storage unit (such as one of SLC, MLC, TLC, and QLC). For example, the first storage block 310a can be a storage block composed of MLC, TLC, or QLC, and the second storage block 310b can be a storage block composed of SLC. Since the read interference resistance of SLC is stronger than that of MLC, TLC, and QLC, SLC can withstand more read interference times of a single page, and moving the data stored in the first target physical page P n to the second storage block 310b can effectively reduce the problem of frequent read retries caused by read errors, and can also reduce the refresh frequency of the storage block. Furthermore, since the read speed of SLC is faster than that of MLC, TLC, and QLC, moving the data stored in the first target physical page P n to the second storage block 310b can improve the performance of the memory system in subsequent read operations on the data stored in the original first target physical page P n . In addition, since SLC has better data retention capability than MLC, TLC, and QLC, moving the data stored in the first target physical page P n to the second storage block 310b can also improve the data reliability of the memory system in some complex use scenarios.

[0089] In some embodiments, the memory controller 302 is specifically configured to count the number of times of reading the first target physical page P n count the number of times of reading the adjacent physical pages to determine the sum of the number of times of reading.

[0090] In the embodiments of the present disclosure, the memory controller 302 can include a processor, which includes but is not limited to a central processing unit (CPU), a field programmable gate array, a programmable logic array, an application specific integrated circuit (ASIC), etc. The processor in the memory controller 302 can count the number of times of reading the first target physical page P n count the number of times of reading the adjacent physical pages to determine the sum of the number of times of reading. n count the number of times of reading the adjacent physical pages to determine the sum of the number of times of reading. It should be noted that the processor in the memory controller 302 can count the number of times of reading all the physical pages in the first memory block 310a, and determine the sum of the number of times of reading the adjacent physical pages for each physical page respectively. It can be understood that if the first target physical page P n is the first physical page in the first memory block 310a, the processor in the memory controller 302 can count the number of times of reading the second physical page as the sum of the number of times of reading. n is the last physical page in the first memory block 310a, the processor in the memory controller 302 can count the number of times of reading the second-to-last physical page as the sum of the number of times of reading. n is a physical page in the middle part of the first memory block 310a (such as P n ), the processor in the memory controller 302 can count the number of times of reading the physical pages P n+1 and P n-1 , and take the sum of the two as the sum of the number of times of reading.

[0091] In some embodiments, in order to more accurately determine the influence of the read disturbance on the first target physical page P n , the memory controller 302 can further determine the sum of the number of times of reading the physical pages P n+2 , P n+1 , P n-1 and P n-2 , and take the sum of the number of times of reading the physical pages P n+2 , P n+1 , P n-1 and P n-2When the sum of the number of reads is greater than or equal to a preset threshold, the first target physical page P n The data stored in the first target physical page P is moved to the second storage block 310b which has better anti-read disturbance capability, reading speed and data retention capability. In other words, the memory controller 302 can also count the data stored in the first target physical page P within a certain range. n The number of reads of all physical pages of the first target physical page P is calculated more accurately. n Whether the read interference has reached the upper limit. It can be understood that compared with the physical page P n+1 and P n-1 , physical page P n+2 and P n-2 For the first target physical page P n The effect of read interference is smaller, so the memory controller 302 can determine the sum of the number of reads in the physical page P n+2 and P n-2 The number of reads is multiplied by a coefficient less than 1, thereby accurately measuring the proximity to the first target physical page P n For example, the sum X of the above read times can be determined by the following formula:

[0092] X=X n+1 +X n-1 +μ(X n+2 +X n-2 )

[0093] Where X is the sum of the number of reads, X n+1 、X n-1 、X n+2 and X n-2 Physical page P n+1 、P n-1 、P n+2 and P n-2 The number of reads of the physical page P is , μ is the influence coefficient and μ is less than 1. In some embodiments, the memory controller 302 can also determine the physical page P n+3 and P n-3 The number of reads is based on the physical page P n+1 、P n-1 、P n+2 、P n-2 、P n+3 and P n-3 The sum of the above reading times is determined by the number of readings, so as to more accurately evaluate the first target physical page P n Whether the read interference has reached the upper limit. It should be noted that X here may not be an integer, and X is only used to measure the first target physical page P nThe degree of read disturbance does not represent the actual sum of read times of multiple adjacent physical pages.

[0094] In some embodiments, the memory controller 302 is specifically configured to: in response to a read request including a logical address, determine the physical address corresponding to the logical address; wherein the physical address includes the physical address of the physical page adjacent to the first target physical page; in response to the physical address, read the physical page adjacent to the first target physical page, and count the number of reads of the physical page adjacent to the first target physical page.

[0095] In an embodiment of the present disclosure, the memory controller 302 can determine the physical address corresponding to the logical address in response to a read request including a logical address from outside the memory system 30 (such as a host). Exemplarily, the memory controller 302 may include a Flash Translation Layer (FTL), which can be used to convert the logical address received by the memory controller 302 into a corresponding physical address based on a mapping (Mapping) of the logical address to the physical address. The Flash Translation Layer can be implemented by executing a corresponding firmware algorithm through the hardware circuit of the memory controller 302. Here, the physical address determined by the memory controller 302 according to the logical address in the read request may include the physical address of at least one physical page adjacent to the first target physical page (that is, the physical address corresponding to one or two physical pages adjacent to the first target physical page). Then, the memory controller 302 can read the physical pages corresponding to these physical addresses in response to the physical address converted from the logical address, that is, read at least one physical page adjacent to the first target physical page, and count the number of reads of at least one physical page adjacent to the first target physical page. That is, the multiple physical addresses corresponding to the multiple logical addresses in the read request may hit the physical page adjacent to the first target physical page P n One or two adjacent physical pages (such as physical page P n+1 and / or P n-1 ), no matter whether one or two adjacent physical pages are hit, the memory controller 302 counts the number of reads of the corresponding physical page.

[0096] In some embodiments, as Figure 6 As shown, the memory controller 302 includes a counting circuit, which is configured to count the number of times the physical pages adjacent to the first target physical page are read to determine the sum of the number of times.

[0097] In the embodiments of the present disclosure, the processor 330 in the memory controller 302 can be coupled to the host 40 through the host interface 340, and the processor 330 can also be coupled to the memory 301 through the memory interface 350. The memory controller 302 further includes a cache 360 coupled to the processor 330, and the cache 360 can be used to cache a partial logical address to physical address (L2P) mapping table and executable instructions, etc. The memory controller 302 can further include a counting circuit 320, which can be part of the logic circuit in the processor 330 of the memory controller 302, and the counting circuit 320 can be composed of a series of flip-flops and logic gate circuits. The counting circuit 320 can count the number of read operations on the physical pages adjacent to the first target physical page, so as to determine the sum of the number of read operations.

[0098] In some embodiments, the counting circuit can also be other logic circuits outside the processor 330 in the memory controller 302. In other embodiments, the memory controller 302 can also implement counting of the number of read operations on each physical page in the form of executing firmware.

[0099] In some embodiments, the memory controller 302 is specifically configured to count the number of read operations on the physical pages adjacent to the first target physical page within a preset time period, so as to determine the sum of the number of read operations.

[0100] In the embodiments of the present disclosure, the memory controller 302 can count the number of read operations on the physical pages adjacent to the first target physical page within a preset time period, so as to determine the sum of the number of read operations. Here, the preset time period can be determined according to the actual test results of the memory product, or a reference value provided by the designer, and the preset time period can also be the refresh period of the first memory block. In this way, the memory controller 302 can respond to the frequently read adjacent physical pages within the preset time period, move the data stored in the first target physical page affected by the read interference, so as to alleviate the phenomenon of threshold voltage shift, reduce the error bit count of reading the first target physical page, and thus improve the reliability of the memory.

[0101] It should be noted that the present disclosure can also set the size of the period threshold based on the length of the preset time period, and the period threshold is smaller than the first threshold described above. The memory controller 302 can also move the data stored in the first target physical page to the second memory block in response to the sum of the number of read operations on the physical pages adjacent to the first target physical page within the preset time period being greater than or equal to the period threshold. In this way, the memory controller 302 can solve the problem of read errors of the first target physical page caused by repeated reading of adjacent physical pages in advance.

[0102] In some embodiments, the memory controller 302 can also determine the physical address corresponding to the logical address in response to the read request including the logical address, and directly increase the read count of the corresponding physical page according to the physical address, instead of increasing the read count after completing the read operation on the physical page. In this way, the working efficiency of the memory controller can be further improved.

[0103] In some embodiments, the first threshold of the different first target physical pages in the first storage block is different.

[0104] In the embodiments of the present disclosure, due to the influence of manufacturing process or external environmental factors, the physical characteristics of each physical page itself can be different, and thus the anti-read interference capability of each physical page can also be different. Therefore, different first thresholds can be set for different first target physical pages in the first storage block, so as to more accurately evaluate whether the read interference suffered by different first target physical pages reaches the upper limit.

[0105] In some embodiments, the memory controller 302 is further configured to: determine a read count of a second target physical page in the first storage block 310a; and in response to the read count of the second target physical page being greater than or equal to a second threshold, move the data stored in the second target physical page to the second storage block 310b; wherein the second threshold is less than or equal to the first threshold.

[0106] In the embodiments of the present disclosure, the memory controller 302 can also move the data stored in the second target physical page to the second storage block 310b in response to the read count of the second target physical page being greater than or equal to the second threshold. That is, the read count threshold (i.e., the second threshold) can also be set for the physical page (i.e., the second target physical page) that is the source of read interference, and the data of the physical page that is the source of read interference due to frequent reading can be moved, so as to prevent the read interference on the adjacent physical page caused by repeatedly reading the physical page. It can be understood that since the read interference suffered by any one physical page (the second target physical page) is caused by one or two adjacent physical pages, the second threshold can be less than or equal to the first threshold. For example, for the physical page (the second target physical page) corresponding to the first word line or the last word line in the storage block, the second threshold can be equal to the first threshold, and for the physical page (the second target physical page) corresponding to the word line other than the first word line and the last word line in the storage block, the second threshold can be less than the first threshold.

[0107] In some embodiments, the memory controller 302 is further configured to determine whether the read for the second target physical page is a single logical page read; and in response to the read for the second target physical page being a single logical page read and the number of reads for the second target physical page being greater than or equal to the second threshold, move the data stored in the second target physical page to the second storage block.

[0108] In embodiments of the present disclosure, the memory controller 302 can further determine whether the multiple read operations for the second target physical page are single logical page reads based on multiple read requests including logical addresses from outside the memory system 30 (e.g., a host). In the case that the read for the second target physical page is a single logical page read and the number of reads for the second target physical page is greater than or equal to the second threshold, the memory controller 302 can move the data stored in the second target physical page to the second storage block 310b. In this way, the read errors of the memory system 30 in the single page read interference scenario can be reduced, thereby improving the reliability of the memory system 30.

[0109] In some embodiments, the memory controller 302 is further configured to update the logical address to physical address mapping table in response to the data being moved to the second storage block.

[0110] In embodiments of the present disclosure, after the memory controller 302 moves the data stored in the first target physical page and / or the second target physical page to the second storage block 310b, the memory controller 302 can update the logical address to physical address mapping table using the flash translation layer, thereby updating the L2P mapping relationship of the data originally stored in the first target physical page and / or the second target physical page.

[0111] As shown in FIG. 1, Figure 7 The present disclosure provides an operating method of a memory system, the memory system including a memory and a memory controller coupled to the memory; the memory including a plurality of storage blocks, the storage blocks including a plurality of physical pages; the operating method including the steps of:

[0112] Step S10, determining a sum of numbers of reads of physical pages adjacent to a first target physical page in a first storage block of the plurality of storage blocks;

[0113] Step S20, in response to the sum of numbers of reads being greater than or equal to a first threshold, moving data stored in the first target physical page to a second storage block of the plurality of storage blocks; wherein the second storage block is different from the first storage block.

[0114] It should be understood that the steps shown in Figure 7 the steps shown in FIG. 1 are not exclusive and other steps can be performed before, after, or between any of the steps shown.

[0115] In the embodiments of the present disclosure, with reference to Figure 5 The number of times of reading operations performed on each physical page can be counted, or the physical addresses corresponding to the read commands received from an external device (such as a host) can be analyzed, to determine the first target physical page P n The sum of the number of times of reading operations performed on the adjacent physical pages. It can be understood that if the first target physical page P n corresponds to the first word line or the last word line in the first memory block, then the first target physical page P n may have only one adjacent physical page; if the first target physical page P n corresponds to a word line in the middle part of the first memory block, i.e., a word line other than the first word line and the last word line, then the first target physical page P n may have two adjacent physical pages (P n+1 and P n-1 ).

[0116] Then, in response to the sum of the number of times of reading operations performed on the physical pages adjacent to the first target physical page P n being greater than or equal to a first threshold value, the data stored in the first target physical page P n is moved to a second memory block, where the second memory block is different from the first memory block. That is, in order to prevent or reduce read errors caused by repeated reading of the memory cells coupled to the adjacent word lines (such as WL n+1 and WL n-1 ) and the accumulation of slight programming of the memory cells coupled to the word line WL n , a first threshold value representing an upper limit of the total number of times of read interference suffered by the memory cells in the first target physical page can be set. If the sum of the number of times of reading operations performed on the physical pages adjacent to the first target physical page is greater than or equal to the first threshold value, data migration can be triggered, i.e., the data stored in the first target physical page is moved to another open memory block (such as the second memory block), where the open memory block refers to a memory block in which only part of the physical pages are written with data, and the other physical pages are not written with data. It should be noted that the first threshold value can be determined according to the actual test results of the memory product, or a reference value can be provided by the designer.

[0117] In this way, the interference on the first target physical page caused by repeated reading of the adjacent physical pages can be reduced, the phenomenon of threshold voltage shift can be alleviated, the error bit count of reading the first target physical page can be reduced, and the reliability of the memory can be improved.

[0118] In some embodiments, the determining the sum of the read times of the physical pages adjacent to the first target physical page in the first storage block of the plurality of storage blocks comprises counting the read times of the physical pages adjacent to the first target physical page to determine the sum of the read times.

[0119] In some embodiments, the operation method further comprises: in response to a read request comprising a logical address, determining a physical address corresponding to the logical address; wherein the physical address comprises a physical address of the physical page adjacent to the first target physical page; in response to the physical address, reading the physical page adjacent to the first target physical page; and the counting the read times of the physical pages adjacent to the first target physical page comprises: in response to reading the physical page adjacent to the first target physical page, counting the read times of the physical pages adjacent to the first target physical page.

[0120] In some embodiments, the first threshold value is different for different first target physical pages in the first storage block.

[0121] In some embodiments, the operation method further comprises: determining a read time of a second target physical page in the first storage block; and in response to the read time of the second target physical page being greater than or equal to a second threshold value, moving data stored in the second target physical page to the second storage block; wherein the second threshold value is less than or equal to the first threshold value.

[0122] In some embodiments, the operation method further comprises: determining a read time of a second target physical page in the first storage block; and in response to the read time of the second target physical page being greater than or equal to a second threshold value, moving data stored in the second target physical page to the second storage block; wherein the second threshold value is less than or equal to the first threshold value.

[0123] In some embodiments, the operation method further comprises: determining the second threshold value according to a reference threshold value of the read times of a single physical page in the memory; wherein the second threshold value is 1 / 5 to 1 / 3 of the reference threshold value.

[0124] In the embodiments of the present disclosure, the second threshold value can be determined according to a reference threshold value of the read times of a single physical page. The reference threshold value can be determined according to actual test results of a memory product, or a reference value can be provided by a designer, a manufacturer, or an industry standard (such as a read threshold value specified by a spec of a NAND in a single-page read interference scenario). Preferably, the second threshold value can be 1 / 5 to 1 / 3 of the reference threshold value.

[0125] In some embodiments, the operation method further includes: updating a logical address to physical address mapping table in response to the data moving to the second storage block.

[0126] The present disclosure provides a computer readable storage medium having stored thereon executable instructions that, when executed, implement the operation method of any of the above embodiments. Exemplarily, the executable instructions can be stored in the memory 301 or the cache of the memory controller 302, and can be executed by the processor in the memory controller. The executable instructions can also be referred to as firmware.

[0127] The present disclosure provides an electronic device, comprising the memory system of any of the above embodiments.

[0128] In the embodiments of the present disclosure, the electronic device can correspond to the system 100 as shown in the above Figure 1 The system 100 in the embodiments shown can be understood as above, and will not be described here again.

[0129] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial number of the above embodiments of the present disclosure is only for description, not representing the advantages and disadvantages of the embodiments.

[0130] The above only describes the preferred embodiments of the present disclosure, and does not limit the patent scope of the present disclosure, and any equivalent structural transformation made according to the disclosure content of the present disclosure and the contents of the drawings, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory system, characterized by, The memory system comprises a memory and a memory controller coupled to the memory; the memory comprises a plurality of memory blocks, and each memory block comprises a plurality of physical pages; the memory controller is configured to: determine a sum of read times of the physical pages adjacent to a first target physical page in a first memory block of the plurality of memory blocks; in response to the sum of read times being greater than or equal to a first threshold, move data stored in the first target physical page to a second memory block of the plurality of memory blocks; wherein the second memory block is different from the first memory block. The memory controller is specifically configured to: count the read times of the physical pages adjacent to the first target physical page to determine the sum of read times.

2. The memory system of claim 1, wherein, The memory controller is specifically configured to: in response to a read request comprising a logical address, determine a physical address corresponding to the logical address; wherein the physical address comprises physical addresses of the physical pages adjacent to the first target physical page; 3. The memory system of claim 2, wherein, in response to the physical address, read the physical pages adjacent to the first target physical page and count the read times of the physical pages adjacent to the first target physical page. The memory controller comprises a counting circuit configured to: count the read times of the physical pages adjacent to the first target physical page to determine the sum of read times.

4. The memory system of claim 2, wherein, The memory controller is specifically configured to: count the read times of the physical pages adjacent to the first target physical page within a preset time period to determine the sum of read times.

5. The memory system of claim 2, wherein, The first threshold of the different first target physical page in the first memory block is different. The memory controller is further configured to:

6. The memory system of claim 1, wherein, determine a read time of a second target physical page in the first memory block; 7. The memory system of claim 1, wherein, in response to the read time of the second target physical page being greater than or equal to a second threshold, move data stored in the second target physical page to the second memory block; wherein the second threshold is less than or equal to the first threshold. The memory controller is further configured to: determine whether the read for the second target physical page is a single logical page read; 8. The memory system of claim 7, wherein, in response to the read for the second target physical page being a single logical page read and the read time of the second target physical page being greater than or equal to the second threshold, move data stored in the second target physical page to the second memory block. The number of bits of a storage unit in the second memory block is less than the number of bits of a storage unit in the first memory block. The first memory block comprises two-layer cells, three-layer cells, or four-layer cells; and the second memory block comprises single-layer cells.

9. The memory system of claim 1, wherein, The memory controller is further configured to:

10. The memory system of claim 1, wherein, in response to the data being moved to the second memory block, update a logical address to physical address mapping table.

11. The memory system of claim 1, wherein, The memory system comprises a memory and a memory controller coupled to the memory; the memory comprises a plurality of memory blocks, and each memory block comprises a plurality of physical pages; the memory controller is configured to: determine a sum of read times of the physical pages adjacent to a first target physical page in a first memory block of the plurality of memory blocks; 12. An operating method of a memory system, characterized by, in response to the sum of read times being greater than or equal to a first threshold, move data stored in the first target physical page to a second memory block of the plurality of memory blocks; wherein the second memory block is different from the first memory block. ​ In response to the sum of the read times being greater than or equal to a first threshold, move data stored in the first target physical page to a second storage block of the plurality of storage blocks; wherein the second storage block is different from the first storage block.

13. The method of operation of claim 12, wherein, The determining the sum of the read times of the physical pages adjacent to the first target physical page in the first storage block of the plurality of storage blocks comprises: counting the read times of the physical pages adjacent to the first target physical page to determine the sum of the read times.

14. The method of claim 13, wherein, The operation method further comprises: in response to a read request comprising a logical address, determining a physical address corresponding to the logical address; wherein the physical address comprises a physical address of the physical pages adjacent to the first target physical page; in response to the physical address, reading the physical pages adjacent to the first target physical page; The counting the read times of the physical pages adjacent to the first target physical page comprises: in response to reading the physical pages adjacent to the first target physical page, counting the read times of the physical pages adjacent to the first target physical page.

15. The method of claim 12, wherein, The first threshold of the different first target physical pages in the first storage block is different.

16. The method of claim 12, wherein, The operation method further comprises: determining the read times of a second target physical page in the first storage block; in response to the read times of the second target physical page being greater than or equal to a second threshold, moving data stored in the second target physical page to the second storage block; wherein the second threshold is less than or equal to the first threshold.

17. The method of operation of claim 16, wherein, The operation method further comprises: determining whether the read for the second target physical page is a single logical page read; The moving the data stored in the second target physical page to the second storage block in response to the read times of the second target physical page being greater than or equal to a second threshold comprises: in response to the read for the second target physical page being a single logical page read and the read times of the second target physical page being greater than or equal to the second threshold, moving the data stored in the second target physical page to the second storage block.

18. The method of claim 16, wherein, The operation method further comprises: determining the second threshold according to a reference threshold of the read times of a single physical page in the memory; wherein the second threshold is 1 / 5 to 1 / 3 of the reference threshold.

19. The method of claim 12, wherein, The operation method further comprises: in response to the data being moved to the second storage block, updating a logical address to physical address mapping table.

20. A computer-readable storage medium, characterized in that, The computer readable storage medium has stored thereon executable instructions that, when executed by a processor, implement the operation method of any one of claims 12 to 19.

21. An electronic device, comprising: comprises: The memory system of any one of claims 1 to 11.

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