An efficient memory management method and system based on an SOC chip

Abstract

The application relates to the technical field of SOC chips, and discloses an efficient memory management method and system based on an SOC chip, which comprehensively analyzes the internal physical structure of the chip, constructs a complete topology graph, and calculates access delay distribution. The application monitors the memory access behavior of each processing core in real time, executes dynamic memory partitioning according to the access characteristics and the physical topology structure, and allocates the optimal access area to the processing core. When the access hot spot is detected, a data migration mechanism is triggered to copy the hot spot data to a relatively close memory area. The application reorganizes the memory address space by adopting a topology-aware address mapping algorithm, establishes a multi-level cache cooperation mechanism, and dynamically adjusts the working mode of the memory controller according to the application type. Through load balancing monitoring and periodic memory reorganization, the application effectively reduces the memory access delay, improves the bandwidth utilization, and optimizes the overall memory access performance of the SOC chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of SOC chips, and particularly relates to a high-efficiency memory management method and system based on an SOC chip. BACKGROUND

[0002] At present, with the popularity of intelligent devices and complex applications, the system based on an SOC (System on Chip) chip has higher requirements for memory management efficiency, which is directly related to the overall system performance and the quality of user experience. The traditional memory management method often adopts a unified strategy and fails to fully consider the complex physical topology structure inside the SOC chip, resulting in obvious performance bottlenecks in data-intensive application scenarios. The current method usually ignores the physical distance difference between the processing core and the memory controller, making the data transmission path long and causing unnecessary signal delay, especially when multiple cores work cooperatively.

[0003] In the prior art, the memory access delay in the SOC chip architecture is positively correlated with the data transmission distance, and this physical characteristic makes the location distribution of the memory controller a key factor affecting the system performance. When the processing core needs to access the memory region with a far physical location, the signal transmission delay is significantly increased, thereby causing the processing efficiency to decrease. The delay problem caused by the physical distance further causes the memory bandwidth allocation to be uneven, because the system tends to frequently access the memory region with a short physical distance, causing some memory banks to be overloaded while other regions are idle, and the overall memory resources cannot be fully utilized.

[0004] In addition, different application scenarios have completely different requirements for memory access modes, and the unified memory partition strategy and fixed address mapping algorithm are difficult to adapt to such diversity. The centralized storage of hot data further aggravates the problem of uneven memory access, especially in data-intensive applications, which is prone to form memory access hotspots and cause local congestion.

[0005] Therefore, how to establish an intelligent data flow path according to the physical topology structure of the SOC chip, optimize the memory partition and address mapping strategy for different application scenarios, and realize the balanced distribution of hot data has become a key problem to improve the memory management efficiency of the SOC chip. SUMMARY

[0006] The present application provides a high-efficiency memory management method and system based on an SOC chip to improve the memory management efficiency of the SOC chip.

[0007] In a first aspect, to solve the above technical problems, the present application provides a high-efficiency memory management method based on an SOC chip, comprising:

[0008] acquire a physical distance matrix between each processing core and memory controller of the SOC chip, construct a physical topology structure of the SOC chip, and acquire memory access behavior characteristics of each application program, and allocate optimal memory access regions for each processing core according to the memory access behavior characteristics and the physical topology structure;

[0009] If it is detected that the access frequency of one of the processing cores to the optimal memory region exceeds a preset frequency threshold, a data migration mechanism is triggered to reorganize the memory address space and establish a multi-level cache coordination mechanism.

[0010] The working load and queue depth of each memory controller are detected in real time, and when it is detected that the load of one of the memory controllers exceeds a load threshold, the memory request distribution strategy is dynamically adjusted to redirect part of the access requests to the memory controller with lighter load.

[0011] According to the relationship between the memory access heat distribution map and the physical topology structure, a periodic memory reorganization operation is performed to integrate the memory fragmentation that occurs in a long-running system, and the data storage location is rearranged so that data blocks with similar access frequencies are stored in adjacent memory regions.

[0012] Preferably, the acquisition of the physical distance matrix between each processing core and memory controller of the SOC chip, and the construction of the physical topology structure of the SOC chip, comprises:

[0013] The coordinate information of each processing core and memory controller of the SOC chip is extracted, a topology-aware scanning algorithm is used to grid the physical layout of the SOC chip, each grid unit is scanned and the accurate physical positions of each processing core and memory controller are recorded.

[0014] The physical distance between any two processing cores and between a processing core and a memory controller is calculated according to the coordinate information, and the calculation result is generated as a distance matrix.

[0015] According to the distance matrix and the internal transmission rate parameters of the SOC chip, the theoretical access delay data between each pair of processing core and memory region is calculated, and the theoretical access delay data is processed in layers and analyzed for data path optimization.

[0016] The high-delay hot spot region and the low-delay region are identified, the difference between the actual measured delay and the theoretically calculated delay is compared, and an optimal data access path recommendation table is generated.

[0017] Preferably, the acquisition of the memory access behavior characteristics of each application program comprises:

[0018] Receiving memory access request information initiated by each processing core, the memory access request information including request initiation timestamp, target memory address range, request data block size, and read-write type;

[0019] According to the memory access request information, performing segmented processing according to a preset time window, calculating the total number of accesses to each memory region and the cumulative data transmission amount in each time window, and obtaining a memory region heat index;

[0020] Analyzing the address continuity and periodicity characteristics in the memory access request information, judging the access mode type, if the addresses of continuous multiple accesses present fixed step growth, it is determined as a sequential access mode; if the access addresses present regular repetition and similar interval time, it is determined as a cyclic access mode; if the access address distribution is random and irregular, it is determined as a random access mode;

[0021] According to the access mode type and application program running state information, establishing an application program memory access behavior mapping relationship, and constructing an application program memory access behavior portrait database.

[0022] Preferably, the memory access behavior characteristics of each application program are obtained, and according to the memory access behavior characteristics and the physical topology structure, the optimal memory access region is allocated for each processing core, including:

[0023] Real-time collection of memory access request frequency and target address distribution of each processing core, recording of access heat index of each memory region, time window statistical analysis of access request, and obtaining of memory access behavior characteristics of each application program according to access frequency, data block size, and access mode characteristics;

[0024] According to the memory access behavior characteristics and the physical topology structure, the physical memory space is divided into multiple regions with different access priorities, the memory page where the frequently accessed hot data is marked, and the optimal memory access region is allocated for each processing core.

[0025] Preferably, the memory access behavior characteristics of each application program are obtained, and according to the memory access behavior characteristics and the physical topology structure, the optimal memory access region is allocated for each processing core, including:

[0026] Receiving memory access request information issued by each processing core, the memory access request information including target memory address and access timestamp;

[0027] According to the memory access request information, calculating the access frequency of each memory page in a preset time window, if the access frequency exceeds a high frequency threshold, marking as a hot data page, and obtaining memory page heat marking information;

[0028] obtaining a physical topology diagram, calculating a physical distance matrix between the processing core and each memory region, generating a distance weight factor according to the physical distance matrix, and obtaining a weighted distance table;

[0029] measuring bandwidth usage of the processing core, calculating a bandwidth fluctuation index and a delay sensitivity index, and classifying access characteristics of the processing core according to the bandwidth fluctuation index and the delay sensitivity index;

[0030] performing dynamic partitioning of memory regions, and migrating the hot data page to a memory region with the minimum weighted distance from the corresponding processing core according to the heat label information, the weighted distance table, and the access characteristic classification.

[0031] Preferably, the data migration mechanism is triggered to reorganize the memory address space and establish a multi-level cache cooperation mechanism, including:

[0032] triggering the data migration mechanism to copy the hot data from a distant memory region to a memory region closer to the processing core, and updating the corresponding physical address pointer in the memory mapping table;

[0033] reorganizing the memory address space to map the virtual address to the physical address, and allocating the data blocks accessed continuously in physically adjacent memory regions closer to the processing core;

[0034] establishing a multi-level cache cooperation mechanism to add an intermediate cache layer between the processing core and the distant memory controller, predictively caching the historical access data, and loading the accessible data to the cache closer to the processing core according to the memory access behavior characteristics.

[0035] Preferably, the memory access behavior characteristics of each application are obtained, and the optimal memory access region for each processing core is allocated according to the memory access behavior characteristics and the physical topology, including:

[0036] real-time collection of memory access request frequency and target address distribution of each processing core, recording of access heat index of each memory region, time window statistical analysis of access requests, and obtaining of memory access behavior characteristics of each application according to access frequency, data block size, and access mode characteristics;

[0037] dividing the physical memory space into multiple regions with different access priorities according to the memory access behavior characteristics and the physical topology, marking the memory page where the frequently accessed hot data is located, and allocating the optimal memory access region for each processing core.

[0038] Preferably, the data migration mechanism includes:

[0039] receiving monitoring data of memory access frequency in the processing core from the hardware performance counter, the monitoring data including access frequency statistics of different memory regions by each processing core;

[0040] determining whether the access frequency of the processing core exceeds a preset frequency threshold according to the monitoring data, and triggering an access pattern recognition procedure to generate high-frequency access memory region identification information if the access frequency exceeds the preset frequency threshold;

[0041] receiving the high-frequency access memory region identification information through a memory controller, scanning data blocks stored in the high-frequency access memory region, identifying a data page with the highest access heat, and calculating physical distance values between the processing core and each candidate target memory region to determine a nearest available memory region to the processing core as a data migration target position;

[0042] starting a data replication process to perform a hot data physical replication operation from a remote memory region to the data migration target position, updating a physical address mapping relationship in a page table entry through a memory management unit, modifying a virtual address to physical address conversion table entry, and obtaining an optimized memory access path configuration.

[0043] Preferably, the multi-level cache coordination mechanism includes:

[0044] obtaining physical distance measurement data between the processing core and the memory controller;

[0045] if the physical distance exceeds a preset distance threshold, establishing a three-level cache architecture between the processing core and a remote memory controller, the three-level cache architecture including storage space configuration parameters of each level of cache;

[0046] monitoring a historical access sequence of the processing core according to the storage space configuration parameters, and analyzing access pattern features of the historical access sequence using a time window sliding algorithm;

[0047] if a continuous access frequency exceeds a preset frequency threshold, calculating a data prediction weight value;

[0048] training a prediction model according to the data prediction weight value, triggering a preloading mechanism if the data prediction weight value is greater than a preset prediction threshold, migrating predicted high-weight data to a cache layer closest to the processing core through a load balancing scheduler to obtain a pre-cache data set;

[0049] real-time monitoring a hit rate of the pre-cache data set in each level of cache, and dynamically adjusting a distribution of the pre-cache data set among the cache layers according to a bandwidth utilization rate if a hit rate of one level of cache is lower than a preset hit rate threshold.

[0050] Preferably, the memory access hotness distribution map and the physical topology structure are related to perform periodic memory reorganization operations to integrate the memory fragmentation in long-running systems, rearrange the data storage location, and make the data blocks with similar access frequencies stored in adjacent memory areas in physical location.

[0051] The memory access monitoring module continuously collects read and write operation records of each memory address, and if the access frequency of one memory page exceeds the preset frequency threshold in a continuous monitoring period, the memory page is marked as a hot page and the access hotness value is recorded.

[0052] The memory fragmentation detection algorithm is used to scan the memory access hotness distribution map to determine whether there are memory blocks with access frequency difference exceeding the preset difference in adjacent physical address range. If there are adjacent memory blocks with unmatched access frequency, the fragmented area is identified and the physical address list is obtained.

[0053] According to the access frequency data of the fragmented area, the data blocks are re-grouped. If the access frequency difference between two data blocks is less than the preset similarity threshold, they are classified into the same reorganization group and the target storage location is determined.

[0054] The memory page migration mechanism is used to perform physical location adjustment of data blocks according to the data migration mapping relationship, and the data block copying and original address space release are completed through atomic operation.

[0055] In a second aspect, the application provides an efficient memory management system based on a SOC chip, comprising:

[0056] The allocation module is used to obtain the physical distance matrix between each processing core and the memory controller of the SOC chip, construct the physical topology structure of the SOC chip, and obtain the memory access behavior characteristics of each application program. According to the memory access behavior characteristics and the physical topology structure, the optimal memory access area is allocated to each processing core.

[0057] The processing module is used to trigger the data migration mechanism, reorganize the memory address space, and establish a multi-level cache cooperation mechanism if it is detected that the access frequency of one of the processing cores to the optimal memory area exceeds the preset frequency threshold.

[0058] The directional module is used to detect the workload and queue depth of each memory controller in real time. When it is detected that the load of one of the memory controllers exceeds the load threshold, the memory request distribution strategy is dynamically adjusted, and part of the access requests are redirected to the memory controller with lighter load.

[0059] The integration module is used for performing a periodic memory reorganization operation according to a relationship between a memory access heat distribution map and a physical topology structure, integrating memory fragments in a long-time running system, and rearranging data storage positions so that data blocks with similar access frequencies are stored in memory areas with adjacent physical positions.

[0060] Compared with the prior art, the application provides a topology-aware SOC chip memory access optimization method and system, which comprehensively analyzes the internal physical structure of a chip, constructs a complete topology map and calculates access delay distribution. The application monitors memory access behaviors of each processing core in real time, performs dynamic memory partitioning according to access characteristics and a physical topology structure, and allocates optimal access areas for the processing cores. When detecting an access hotspot, a data migration mechanism is triggered to copy hotspot data to a memory area that is relatively close. The application uses a topology-aware address mapping algorithm to reorganize a memory address space, establishes a multi-level cache cooperation mechanism, and dynamically adjusts a memory controller working mode according to an application type. Through load balancing monitoring and periodic memory reorganization, the application effectively reduces memory access delay, improves bandwidth utilization, and optimizes overall memory access performance of the SOC chip. BRIEF DESCRIPTION OF DRAWINGS

[0061] Figure 1 is a high-efficiency memory management method flowchart based on an SOC chip provided by the first embodiment of the application;

[0062] Figure 2 is a high-efficiency memory management system structure schematic diagram based on an SOC chip provided by the second embodiment of the application. DETAILED DESCRIPTION

[0063] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the application.

[0064] With reference to Figure 1 The first embodiment of the application provides a high-efficiency memory management method flowchart based on an SOC chip, including the following steps:

[0065] S11, a physical distance matrix between each processing core of an SOC chip and a memory controller is obtained, a physical topology structure of the SOC chip is constructed, memory access behavior characteristics of each application program are obtained, and optimal memory access areas are allocated for the processing cores according to the memory access behavior characteristics and the physical topology structure;

[0066] S12, if the access frequency of one of the processing cores to the optimal memory region exceeds a preset frequency threshold, triggering a data migration mechanism, reorganizing the memory address space, and establishing a multi-level cache coordination mechanism;

[0067] S13, real-time detection of the workload and queue depth of each memory controller, and when the load of one of the memory controllers exceeds a load threshold, dynamically adjusting the memory request distribution strategy and redirecting part of the access requests to the memory controller with lighter load;

[0068] S14, according to the relationship between the memory access heat map and the physical topology structure, performing periodic memory reorganization operation, integrating the memory fragmentation in the long-running system, and rearranging the data storage location to make the data blocks with similar access frequency stored in the memory regions with adjacent physical locations.

[0069] In step S11, the physical distance matrix between each processing core and memory controller of the SOC chip is obtained, the physical topology structure of the SOC chip is constructed, and the memory access behavior characteristics of each application program are obtained. According to the memory access behavior characteristics and the physical topology structure, the optimal memory access region is allocated to each processing core.

[0070] Preferably, the physical distance matrix between each processing core and memory controller of the SOC chip is obtained, and the physical topology structure of the SOC chip is constructed, comprising:

[0071] The coordinate information of each processing core and memory controller of the SOC chip is extracted, the topology-aware scanning algorithm is used to grid the physical layout of the SOC chip, each grid unit is scanned and the accurate physical position of each processing core and memory controller is recorded;

[0072] The physical distance between any two processing cores and between the processing core and the memory controller is calculated according to the coordinate information, and the calculation result is generated as a distance matrix;

[0073] According to the distance matrix and the internal transmission rate parameter of the SOC chip, the theoretical access delay data between each pair of processing core and memory region is calculated, and the theoretical access delay data is processed in layers and analyzed for data path optimization;

[0074] The high-delay hot spot region and the low-delay region are identified, and the difference between the actual measured delay and the theoretically calculated delay is compared to generate an optimal data access path recommendation table.

[0075] For example, in chip design, the physical layout of processing cores and memory controllers has a significant impact on system performance. The topology-aware scanning algorithm can effectively grid the physical layout of the chip, facilitating accurate positioning of each component.

[0076] In an embodiment, assume a multi-core processor chip contains 16 processing cores and 4 memory controllers. By the topology-aware scanning algorithm, the chip can be divided into 8x8 grid cells, each cell size is 0.5mmx0.5mm. After scanning, the processing core coordinates are obtained as (1, 2), (1, 6), (3, 3), etc., and the memory controller coordinates are (0, 0), (0, 7), (7, 0), (7, 7).

[0077] Specifically, based on the coordinate information, the physical distance between any two points can be calculated.

[0078] It should be noted that, in combination with the signal transmission rate parameter (such as a transmission delay of 0.1 ns per millimeter), the physical distance can be converted into access delay. For example, the theoretical access delay of P1 to M1 is 1.5mmx0.1ns / mm=0.15ns. These delay data can be processed in layers, such as 0-0.2ns for a low-delay layer, 0.2-0.5ns for a medium-delay layer, and 0.5ns or more for a high-delay layer.

[0079] Exemplarily, by analysis, a high-delay hotspot area can be identified, such as the processing core P12 located at (6, 6) to the nearest memory controller, the distance is 5 grid cells, and the delay is 0.5ns, becoming a hotspot to be optimized. P2 located at (1, 1) to M1 has only 1 grid cell, and the delay is only 0.1ns, belonging to a low-delay area.

[0080] Preferably, by comparing the actual measured delay (such as 0.65ns of P12 to M3) with the theoretically calculated delay (0.5ns), congestion points or unreasonable wiring areas can be found, and then an optimal data access path recommendation table can be generated to guide the application program to preferentially use low-delay paths, thereby improving the overall system performance.

[0081] Preferably, the memory access behavior characteristics of each application program are obtained, including:

[0082] Receiving memory access request information initiated by each processing core, the memory access request information including a request initiation timestamp, a target memory address range, a request data block size, and a read-write type;

[0083] According to the memory access request information, segment processing is performed according to a preset time window, the total number of accesses to each memory region and the cumulative data transmission amount in each time window are calculated, and a memory region heat index is obtained;

[0084] The address continuity and periodicity characteristics in the memory access request information are analyzed, and a type of access mode is determined. If the addresses of continuous multiple accesses present a fixed step growth, the access mode is determined as a sequential access mode. If the access addresses present regular repetition and similar interval time, the access mode is determined as a cyclic access mode. If the access addresses are randomly distributed and have no regularity, the access mode is determined as a random access mode.

[0085] According to the type of access mode and the application program running state information, a mapping relationship between an application program and a memory access behavior is established, and a memory access behavior portrait database of the application program is constructed.

[0086] In an embodiment, a memory access monitoring system can capture memory requests initiated by each processing core in a SOC chip in real time.

[0087] For example, when the processing core P3 initiates a read request for the memory address 0x8000-0x8FFF at the timestamp T1=10:15:30.125, and the data block size is 4 KB, the system records this complete request information.

[0088] Specifically, the system uses a 10 ms time window for segmentation processing, and calculates an access heat index for each memory region. Assuming that in a certain 10 ms window, the memory region A is accessed 120 times, and the cumulative transmission data amount is 480 KB, while the memory region B is accessed only 15 times, and the transmission data is 60 KB, then the heat index of the A region is obviously higher than that of the B region, and the A region can be marked as a “hot region”.

[0089] It should be noted that the access mode recognition is realized by analyzing the address continuity and periodicity characteristics.

[0090] For example, when the system detects that the processing core P5 continuously issues 10 memory requests, and the target addresses are 0x1000, 0x1100, 0x1200..., which present a fixed step growth of 0x100, the system determines that the access mode is a sequential access mode. When the access sequence of the processing core P8 is 0x2000, 0x5000, 0x2000, 0x5000, and the time interval is about 5 ms, the system recognizes that the access mode is a cyclic access mode. For the request with random address distribution issued by the processing core P12, the system determines that the access mode is a random access mode.

[0091] Exemplarily, when a graphics processing application is running, the system can observe that the processing cores P1-P4 mainly present a sequential access mode, and access the memory regions C and D. When a matrix calculation application is running, the processing cores P5-P8 present a cyclic access mode, and mainly access the memory regions A and B. The system establishes a mapping relationship between the application program and the memory access behavior according to this, and forms a memory access behavior portrait of the application program.

[0092] Preferably, the memory access behavior characteristics of each application are obtained, and optimal memory access regions are allocated to the processing cores according to the memory access behavior characteristics and the physical topology structure, including:

[0093] The memory access request frequency and target address distribution of each processing core are collected in real time, the access heat index of each memory region is recorded, time window statistical analysis is performed on the access requests, and the memory access behavior characteristics of each application are obtained according to the access frequency, data block size, and access mode characteristics;

[0094] According to the memory access behavior characteristics and the physical topology structure, the physical memory space is divided into multiple regions with different access priorities, the memory pages where the frequently accessed hot data are marked, and optimal memory access regions are allocated to each processing core.

[0095] Preferably, the memory access behavior characteristics of each application are obtained, and optimal memory access regions are allocated to the processing cores according to the memory access behavior characteristics and the physical topology structure, including:

[0096] The memory access request information sent by each processing core is received, and the memory access request information includes target memory address and access timestamp;

[0097] The access frequency of each memory page in a preset time window is calculated according to the memory access request information, and if the access frequency exceeds a high frequency threshold, the memory page is marked as a hot data page to obtain memory page heat marking information;

[0098] A physical topology structure diagram is obtained, a physical distance matrix between the processing cores and each memory region is calculated, a distance weight factor is generated according to the physical distance matrix, and a weighted distance table is obtained;

[0099] The bandwidth usage of the processing cores is measured, a bandwidth fluctuation index and a delay sensitivity index are calculated, and the processing cores are classified according to the access characteristics according to the bandwidth fluctuation index and the delay sensitivity index;

[0100] Dynamic partitioning of the memory region is performed, and the hot data pages are migrated to the memory region with the smallest weighted distance from the corresponding processing core according to the heat marking information, the weighted distance table, and the access characteristic classification.

[0101] In one embodiment, the memory access monitoring system optimizes data distribution by receiving memory requests sent by the processing cores.

[0102] Specifically, when the system captures the access request of address 0x4000 sent by processing core C1 at time T=15:20:45.632, the timestamp and target address information of the request are recorded, and the request is classified into the current 50ms time window for statistical analysis.

[0103] It is to be noted that the system obtains the physical topology of the chip and calculates the physical distance between each processing core and the memory region.

[0104] In a possible implementation, the system measures the bandwidth usage of the processing core. For example, the bandwidth usage of the processing core C3 in the last 10 time windows is 45%, 48%, 46%, 47%, 45%, 70%, 72%, 45%, 46%, and 47%, respectively, and the bandwidth fluctuation index is calculated to be 0.18 (standard deviation / average value). At the same time, by measuring the influence of the access delay change on the performance, the delay sensitivity index of C3 is obtained to be 0.75 (high sensitivity). The system classifies C3 as a “high delay sensitivity” processing core accordingly. Finally, the system performs the dynamic partitioning operation of the memory region. When it is found that the hot data page MP1 is mainly accessed by the “high delay sensitivity” processing core C3, and the weighted distance between C3 and the memory region M1 is the smallest (0.9), the system migrates MP1 to the M1 region to ensure that C3 can access the frequently used data with the lowest delay.

[0105] In step S12, if the access frequency of one of the processing cores to the optimal memory region exceeds a preset frequency threshold, a data migration mechanism is triggered, the memory address space is reorganized, and a multi-level cache coordination mechanism is established.

[0106] The data migration mechanism is triggered, the memory address space is reorganized, and the multi-level cache coordination mechanism is established, including:

[0107] The data migration mechanism is triggered, the hot data is copied from a distant memory region to a memory region closer to the processing core, and the corresponding physical address pointer in the memory mapping table is updated;

[0108] The memory address space is reorganized, the virtual address is mapped to the physical address, and the data blocks that are continuously accessed are allocated in the memory region that is physically adjacent and closer to the processing core;

[0109] The multi-level cache coordination mechanism is established, an intermediate cache layer is added between the processing core and the distant memory controller, the historical access data is predictively cached, and the accessible data is loaded into the cache closer to the processing core according to the memory access behavior characteristics.

[0110] For example, the hardware performance counter, as an important component of the modern processor, can monitor the memory access behavior of each processing core in real time.

[0111] Exemplarily, in a certain multi-core processor system, performance counter PMC0 is responsible for counting the number of accesses to a DDR4 memory region by a processing core, and PMC1 monitors the access frequency to a high-bandwidth memory (HBM). When the number of accesses to a memory region Zone_A by a processing core Core0 reaches 12000 times per second in a continuous monitoring period, the system compares this data with a preset frequency threshold of 10000 times per second.

[0112] In an embodiment, the access pattern recognition program uses a sliding window mechanism to analyze the access frequency trend.

[0113] Specifically, the system sets a time window of 200 milliseconds, and when it is detected that the access frequency of a processing core Core2 to a memory address range 0x10000000-0x1000FFFF exceeds the threshold in three consecutive windows, a high-frequency access identifier HotZone_ID_0x1000 is immediately generated, and the identification information is transmitted to the memory controller for subsequent processing.

[0114] It should be noted that after the memory controller receives the high-frequency access region identifier, a special scanning engine is started to perform fine-grained analysis on the target memory region.

[0115] For example, when the scanning engine detects that a 4KB data page Page_0x1000 has been accessed 8500 times in the last 500 milliseconds, while Page_0x1001 in the same region has been accessed only 1200 times, the system will mark Page_0x1000 as the highest heat data page and give priority to migration operations.

[0116] Exemplarily, the physical distance calculation module determines the relative position relationship between each memory region and the processing core according to the NUMA topology. In a certain server system, the processing core Core3 is located in Socket0, and the physical distance to the local memory region LocalMem_0 is 1 memory hop, the distance to the remote memory region RemoteMem_1 is 2 hops, and the distance to RemoteMem_2 is 3 hops. The system calculates the expected access delay values as 80 nanoseconds, 150 nanoseconds and 220 nanoseconds respectively.

[0117] In an embodiment, the data replication process uses an asynchronous replication mechanism to avoid blocking normal memory access operations.

[0118] Specifically, when the system decides to migrate the hot data page from RemoteMem_2 to LocalMem_0, the copy engine first allocates a memory space of the same size at the target location, and then performs data transmission in units of 64 bytes. During the entire copying process, the original data page remains accessible, and the page table update operation is performed only after the copying is completed and the data integrity is verified.

[0119] The trigger data migration mechanism comprises:

[0120] The monitoring data of the memory access frequency of the processing core sent by the hardware performance counter comprises statistical information of the access frequency of each processing core to different memory regions;

[0121] According to the monitoring data, it is determined whether the access frequency of the processing core exceeds a preset frequency threshold, and if so, a high-frequency access memory region identification information is generated by the access pattern recognition program;

[0122] The high-frequency access memory region identification information is received by the memory controller, and the data blocks stored in the high-frequency access memory region are scanned to identify the data page with the highest access heat, and the physical distance value between the processing core and each candidate target memory region is calculated to determine the nearest available memory region to the processing core as the data migration target position;

[0123] A data copy process is started to perform a hot data physical copy operation from a remote memory region to the data migration target position, and the physical address mapping relationship in the page table entry is updated by the memory management unit to modify the virtual address to physical address conversion table entry to obtain an optimized memory access path configuration.

[0124] For example, the hardware topology discovery interface obtains the physical connection relationship between the processing core and the memory controller by scanning the system bus architecture.

[0125] For example, in a four-way processor system, the distance between CPU0 and local memory controller MC0 is 10 nanoseconds, and the distances between CPU0 and remote memory controllers MC1, MC2 and MC3 are 40 nanoseconds, 50 nanoseconds and 45 nanoseconds, respectively. The distance measurement algorithm calculates a delay matrix based on the NUMA topology information, sorts the memory controllers according to the delay values to generate a priority table, and MC0 has the highest priority, followed by MC1. The virtual address access pattern detector identifies the continuous access pattern by monitoring the memory access instruction sequence.

[0126] Specifically, when detecting that the application sequentially reads data in the range of virtual address 0x10000000 to 0x10001000, the system determines that it is a continuous access mode. At this time, the address mapping scheduler selects MC0 with the smallest delay from the priority table as the target memory controller. The memory region allocator divides the continuous address space in the physical memory managed by MC0.

[0127] In an embodiment, for large block continuous data access, the system uses 2MB large page mapping instead of traditional 4KB small page, reducing the number of page table entries and TBL miss rate. The topology-aware address mapping table records the mapping relationship of virtual address 0x10000000 to physical address 0x80000000, while marking the corresponding memory controller identifier MC0. The virtual address conversion operation is completed by querying the topology-aware address mapping table.

[0128] It should be noted that the system also supports a dynamic adjustment mechanism. When detecting a change in access mode, the address mapping scheduler re-evaluates the memory controller selection strategy to ensure that the mapping relationship is always optimally matched with the current access mode and hardware topology.

[0129] The establishment of the multi-level cache coordination mechanism includes:

[0130] Obtain physical distance measurement data between the processing core and the memory controller;

[0131] If the physical distance exceeds a preset distance threshold, a three-level cache architecture is established between the processing core and the remote memory controller, and the three-level cache architecture includes storage space configuration parameters of each level of cache;

[0132] According to the storage space configuration parameters, monitor the historical access sequence of the processing core, and analyze the access mode characteristics of the historical access sequence using a time window sliding algorithm;

[0133] If the continuous access frequency exceeds a preset frequency threshold, a data prediction weight value is calculated;

[0134] According to the data prediction weight value, a prediction model is trained. If the data prediction weight value is greater than a preset prediction threshold, a preloading mechanism is triggered, and predicted high-weight data is migrated to the cache layer closest to the processing core through a load balancing scheduler to obtain a pre-cache data set;

[0135] The hit rate of the pre-cache data set in each level of cache is monitored in real time. If the hit rate of one level of cache is lower than a preset hit rate threshold, the distribution of the pre-cache data set among the cache layers is dynamically adjusted according to the bandwidth utilization rate.

[0136] Among the technical field of SOC (System on Chip) chips, the data prediction weight value generally refers to a parameter used to quantify the influence degree of different input data on the prediction result in a data-driven algorithm or a hardware acceleration module.

[0137] In an embodiment, physical distance measurement data is obtained through a hardware performance counter, and when the delay between the processing core and the memory controller exceeds 200 nanoseconds, the system automatically triggers the establishment of a three-level cache architecture.

[0138] Specifically, the first-level cache is configured with a capacity of 32KB, the second-level cache is set to 256KB, and the third-level cache is expanded to 8MB. Different association degrees are configured for each level of cache to optimize storage efficiency.

[0139] For example, the time window sliding algorithm sets the window size to 1000 access operations and the sliding step to 100 operations. The system monitoring found that when a certain application program continuously accesses array elements, the access frequency reaches 10,000 times per second, far exceeding the preset threshold of 5,000 times. At this time, the algorithm analyzes the spatial locality characteristics of the access sequence and identifies that the sequential access mode accounts for 85% and the random access accounts for only 15%.

[0140] In a possible implementation, the data prediction weight value is calculated through three dimensions of access frequency, time interval, and data size. When a certain data block is accessed more than 50 times within the last 100 milliseconds and the access interval shows a regular decreasing trend, its prediction weight value can reach 0.9, exceeding the preset threshold of 0.7. The prediction model is trained based on historical access patterns and can predict the data address range that may be accessed in advance.

[0141] Specifically, after the preloading mechanism is triggered, the load balancing scheduler evaluates the current load status of each cache layer. When the utilization rate of the first-level cache reaches 80%, the system allocates part of the predicted data to the second-level cache to ensure that critical data can still be kept at the nearest distance. The pre-cached data set usually contains continuous 4KB to 64KB data blocks, and the block size is dynamically adjusted according to application characteristics.

[0142] For example, real-time monitoring shows that the first-level cache hit rate has dropped from the expected 95% to 75%, which is lower than the preset threshold of 80%. At this time, the system analysis finds that the bandwidth utilization rate of the second-level cache is only 40%, leaving room for optimization. The dynamic adjustment mechanism promotes the data with high access frequency from the third-level cache to the second-level cache, while sinking the data with low access frequency, rebalancing the data distribution of each level.

[0143] It should be noted that this multi-level cache management strategy can significantly reduce the average access delay, especially when dealing with large-scale data sets. Through intelligent prediction and dynamic adjustment, the overall performance of the system can be improved by more than 30%, while reducing the bandwidth waste caused by long-distance memory access.

[0144] In step S13, the workload and queue depth of each memory controller are detected in real time, and when it is detected that the load of one of the memory controllers exceeds the load threshold, the memory request distribution strategy is dynamically adjusted, and part of the access requests are redirected to the memory controller with lighter load.

[0145] Before step S13, it also includes: dynamically adjusting the working mode of the memory controller according to the application type and the memory access mode, and allocating higher memory bandwidth to data-intensive applications.

[0146] Obtain the memory access mode characteristic value carrying the application type identifier, the memory access mode characteristic value is generated by the application monitoring agent at runtime; query the preset working mode mapping table according to the memory access mode characteristic value, if the application type identifier belongs to data-intensive application, the memory controller configuration module determines the corresponding high-performance working mode parameter; the high-performance working mode parameter is processed by using a dynamic weight algorithm, and the memory bandwidth allocator calculates the memory bandwidth quota proportion of the data-intensive application according to the processing result; receive the memory access request queue carrying the priority weight value and the timestamp information, and the load balancing scheduler monitors the current load state of each memory controller according to the memory bandwidth quota proportion, and distributes high-priority requests to the memory controller with lower load for execution.

[0147] For example, the load monitoring agent collects the real-time running state data of each memory controller through a periodic scanning mechanism.

[0148] In one embodiment, the monitoring agent samples the state of 16 memory controllers in the system every 10 milliseconds to generate load state information containing controller numbers MC001 to MC016 and corresponding queue depth values.

[0149] Specifically, when the to-be-processed request queue of a certain memory controller accumulates 72 entries, the monitoring agent immediately encapsulates this state information as a data packet and transmits it to the load management module. The load threshold table is pre-configured with queue depth critical values in different working modes.

[0150] For example, the queue depth threshold is set to 64 entries in the standard working mode, the threshold is adjusted to 96 entries in the high-performance mode, and the threshold is reduced to 32 entries in the energy-saving mode.

[0151] In one possible implementation, the system automatically triggers the redirection mechanism when the received load status information shows that the queue depth of the controller MC005 reaches 78 entries, exceeding the 64-entry threshold of the current standard mode. Upon receiving the redirection trigger instruction, the request distribution scheduler immediately initiates the alternative controller screening algorithm.

[0152] Specifically, the scheduler scans the current load status of the remaining 15 memory controllers and identifies a candidate controller with a queue depth lower than 32 entries and an available bandwidth capacity exceeding 8 GB per second.

[0153] In one embodiment, the controller MC012 has a current queue depth of only 28 entries and an available bandwidth capacity of 12 GB per second, and is selected as the optimal redirection target. The scheduler then generates a set of access instructions containing the new controller identifier MC012 and the corresponding redirection address 0x2A000000. The cross-access coordinator is responsible for establishing the mapping relationship between the original access address and the target controller.

[0154] For example, memory access requests originally pointing to the address space 0x1F000000 to 0x1F0FFFFF of the controller MC005 need to be remapped to the address space 0x2A000000 to 0x2A0FFFFF of the controller MC012.

[0155] In one possible implementation, the coordinator maintains a dynamic mapping table recording the source address range, target address range, and effective timestamp of each redirection operation.

[0156] It should be noted that the cross-controller access path mapping mechanism also includes access permission verification and data consistency guarantee functions. When establishing a new mapping relationship, the coordinator checks whether the target controller has the permission to handle a specific data type and ensures that there is no data loss or access conflict during the redirection process.

[0157] Specifically, the system assigns a unique session identifier to each mapping relationship for tracking and managing the entire redirection life cycle, ensuring the reliability and transparency of load balancing operations.

[0158] In step S14, according to the relationship between the memory access heat distribution map and the physical topology structure, periodic memory reorganization operations are performed to integrate memory fragments that appear in long-running systems, rearrange data storage locations, and store data blocks with similar access frequencies in memory areas with adjacent physical locations.

[0159] The periodic memory reorganization operation is performed according to the relationship between the memory access heat distribution map and the physical topology structure, the memory fragmentation in a long-time running system is integrated, the data storage positions are rearranged, and the data blocks with similar access frequencies are stored in the memory areas with adjacent physical positions, including:

[0160] The read-write operation records of each memory address are continuously collected by the memory access monitoring module, if the access times of one memory page in a continuous monitoring period exceed the preset number threshold, the memory page is marked as a hot page and the access heat value is recorded, the physical memory topology structure information is obtained to obtain a memory access heat distribution map;

[0161] The memory fragmentation detection algorithm is used to scan the memory access heat distribution map, whether there are memory blocks with access frequency difference exceeding the preset difference in the adjacent physical address range is judged, if there are adjacent memory blocks with unmatched access frequencies, the fragmentation area is identified and the physical address list is obtained;

[0162] According to the access frequency data of the fragmentation area, the data blocks are re-grouped, if the access frequency difference of two data blocks is less than the preset similarity threshold, the data blocks are classified into the same reorganization group and the target storage position is determined;

[0163] The memory page migration mechanism is used to perform physical position adjustment of the data blocks according to the data migration mapping relationship, and the data block copying and original address space release are completed through atomic operation.

[0164] For example, the memory access monitoring module realizes real-time tracking of read-write operations of memory addresses through hardware performance counters or software probe technology.

[0165] For example, in a database system, the monitoring module collects memory access data every 100 milliseconds, when a 4KB memory page is accessed more than 1000 times in 10 continuous monitoring periods, the system marks it as a hot page and records the access heat value as a high frequency level. By obtaining the topology structure information of NUMA node, memory controller and physical memory, the system can construct a complete memory access heat distribution map, which can directly show the access intensity of each memory area.

[0166] In one embodiment, the memory fragmentation detection algorithm uses a sliding window mechanism to scan the heat distribution map and detect the access frequency difference in the adjacent 64KB physical address range.

[0167] Specifically, when the access frequency difference of adjacent memory blocks exceeds the preset 500 access difference, the system identifies the area as a fragmentation area.

[0168] For example, the memory block at address 0x1000000 is accessed 2000 times, while the adjacent memory block at 0x1010000 is accessed only 200 times, with a difference of 1800 times, far exceeding the preset threshold, and thus is marked as a fragmentation area and recorded in the physical address list.

[0169] It can be understood that the data block regrouping process is optimized based on the similarity of access frequency. When the difference in access frequency of two data blocks is less than the similarity threshold of 100 times, the system classifies them into the same regrouping group.

[0170] For example, two data blocks with access frequencies of 1950 and 1880 times respectively have a difference of only 70 times, meeting the similarity requirement, and thus are assigned to the high-frequency access group and determined to have the local memory of NUMA node 0 as the target storage location. This grouping strategy can significantly improve the locality of memory access and reduce cross-node access delay.

[0171] In a possible implementation, the memory page migration mechanism uses the copy-on-write technology to perform data block physical location adjustment. The system first allocates a new memory page at the target location, and then completes the complete copy of the data block through an atomic operation to ensure data consistency. During the migration process, the original address space is temporarily kept in a read-only state, and the release operation of the original address space is performed after the data verification at the new address is completed.

[0172] For example, a hot data block with an access frequency of 1800 times is migrated from a remote NUMA node to a local node, and the entire migration process takes about 2 milliseconds, but can bring a 30% reduction in access delay.

[0173] It should be noted that this memory optimization mechanism can bring significant technical effects. By eliminating memory fragmentation and optimizing data layout, the memory access efficiency of the system can be improved by 25% to 40%, while reducing memory bandwidth waste and cache invalidation rate. In particular, in a large-scale data processing scenario, the optimized memory layout can better utilize the hardware prefetch mechanism, further improving the overall system performance.

[0174] In addition, the HBM is a new type of CPU / GPU memory chip, which realizes a large capacity and a high bit width DDR combined array by stacking a plurality of DDR chips together and packaging on the GPU. The topology-aware modeling and dynamic memory optimization provided by the application can also be applied to the integration scene of the HBM (high bandwidth memory) and the SOC, and can be deeply combined with the advanced packaging technology to bring significant advantages. For example, by storing the hot data nearby, the transmission delay of the interposer in the access path of the HBM is reduced; the dynamic load balancing avoids the overload of a single HBM controller, and fully develops the parallel bandwidth of multiple banks (such as 6.4Gbps / pin of HBM3). At the same time, the topology model can guide the packaging wiring optimization, such as preferentially shortening the high-delay path.

[0175] In summary, the application discloses a topology-aware SOC chip memory access optimization method, which comprehensively analyzes the internal physical structure of the chip, constructs a complete topology graph and calculates the access delay distribution. The application monitors the memory access behavior of each processing core in real time, performs dynamic memory partitioning according to the access characteristics and physical topology structure, and allocates the optimal access area for the processing core. When the access hot spot is detected, the data migration mechanism is triggered to copy the hot data to the memory area close to the hot spot. The application uses a topology-aware address mapping algorithm to reorganize the memory address space, establishes a multi-level cache cooperation mechanism, and dynamically adjusts the working mode of the memory controller according to the application type. Through load balancing monitoring and periodic memory reorganization, the application effectively reduces the memory access delay, improves the bandwidth utilization, and optimizes the overall memory access performance of the SOC chip.

[0176] Reference Figure 2 The second embodiment of the application provides a high-efficiency memory management system structure diagram based on an SOC chip, which comprises:

[0177] The allocation module 201 is configured to obtain a physical distance matrix between each processing core of the SOC chip and the memory controller, construct a physical topology structure of the SOC chip, and obtain memory access behavior characteristics of each application program, and allocate an optimal memory access area for each processing core according to the memory access behavior characteristics and the physical topology structure.

[0178] The processing module 202 is configured to trigger a data migration mechanism, reorganize the memory address space, and establish a multi-level cache cooperation mechanism if it is detected that the access frequency of one of the processing cores to the optimal memory area exceeds a preset frequency threshold.

[0179] The orientation module 203 is configured to detect the working load and queue depth of each memory controller in real time, and dynamically adjust the memory request distribution strategy when it is detected that the load of one of the memory controllers exceeds a load threshold, so as to redirect part of the access requests to the memory controller with lighter load.

[0180] The integration module 204 is configured to perform a periodic memory reorganization operation according to the relationship between the memory access heat map and the physical topology structure, to integrate and rearrange the data storage positions of the memory fragmentation in a long-time running system, so that the data blocks with similar access frequencies are stored in the memory regions with adjacent physical positions.

[0181] It should be noted that the SOC chip-based efficient memory management system provided by the embodiments of the present application is used to perform all the process steps of the SOC chip-based efficient memory management method provided by the above embodiments, and the working principles and advantages of the two are one-to-one corresponding, thus not being described again.

[0182] The embodiments of the present application further provide an electronic device. The electronic device comprises a processor, a memory, and a computer program stored in the memory and executable on the processor, for example, a SOC chip-based efficient memory management program. The processor implements the steps in the above various SOC chip-based efficient memory management method embodiments when executing the computer program, for example Figure 1 The processor implements the functions of the modules / units in the above various device embodiments when executing the computer program, for example, the first acquisition module.

[0183] For example, the computer program can be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete the present application. The one or more modules / units can be a series of computer program instruction segments capable of completing a specific function, which are used to describe the execution process of the computer program in the electronic device.

[0184] The electronic device can be a desktop computer, a notebook computer, a palm computer, a smart tablet and the like. The electronic device can include, but is not limited to, a processor, a memory. Those skilled in the art can understand that the above components are only examples of the electronic device, and do not constitute a limitation on the electronic device, and can include more or fewer components than the above, or combine certain components, or different components, for example, the electronic device can also include an input / output device, a network access device, a bus and the like.

[0185] The processor can be a central processing unit (CPU), and can also be other general-purpose processors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The processor is a control center of the electronic device, and connects various parts of the electronic device through various interfaces and lines.

[0186] The memory can be used to store the computer program and / or modules, and the processor realizes various functions of the electronic device by running or executing the computer program and / or modules stored in the memory, and calling data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application program required by a function (such as a sound playing function, an image playing function, etc.), etc.; and the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), etc. In addition, the memory can include a high-speed random access memory, and can also include a nonvolatile memory, for example, a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other volatile solid-state memory device.

[0187] The modules / units integrated in the electronic device, if realized in the form of software function units and sold or used as independent products, can be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the above-mentioned embodiment methods can also be completed by a computer program instructing related hardware, and the computer program can be stored in a computer readable storage medium. The computer program can implement the steps of each method embodiment when executed by a processor. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or some intermediate forms, etc. The computer readable medium can include any entity or device, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. that can carry the computer program code. It should be noted that the contents included in the computer readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction, for example, in some jurisdictions, according to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.

[0188] It should be noted that the above-described device embodiments are only schematic, and the units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment. In addition, the connection relationship between the modules in the device embodiment provided by the present application indicates that there is a communication connection between them, which can be realized as one or more communication buses or signal lines. Those skilled in the art can understand and implement it without creative labor.

[0189] The above-described specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above-described specific embodiments are only for the specific embodiments of the present application and are not used to limit the protection scope of the present application. It is particularly pointed out that any modification, equivalent replacement, improvement, etc. made by those skilled in the art within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A high-efficiency memory management method based on a SOC chip, characterized in that, include: Obtain the physical distance matrix between each processing core of the SOC chip and the memory controller, construct the physical topology of the SOC chip, obtain the memory access behavior characteristics of each application, and allocate the optimal memory access region for each processing core based on the memory access behavior characteristics and the physical topology. If it is detected that the access frequency of one of the processing cores to the optimal memory region exceeds a preset frequency threshold, a data migration mechanism is triggered to reorganize the memory address space and establish a multi-level cache coordination mechanism. The workload and queue depth of each memory controller are monitored in real time. When the load of one of the memory controllers exceeds the load threshold, the memory request distribution strategy is dynamically adjusted to redirect some access requests to the memory controller with a lighter load. Based on the relationship between the memory access heat distribution map and the physical topology, periodic memory reorganization operations are performed to integrate memory fragments that appear in long-running systems, rearrange data storage locations, and concentrate data blocks with similar access frequencies in physically adjacent memory regions. The acquisition of memory access behavior characteristics of each application includes: Receive memory access request information initiated by each processing core. The memory access request information includes the request initiation timestamp, target memory address range, requested data block size, and read / write type. Based on the memory access request information, the memory region is segmented according to a preset time window. The total number of times each memory region is accessed and the cumulative data transfer volume are calculated within each time window to obtain the memory region heat index. Analyze the address continuity and periodicity characteristics in the memory access request information to determine the access mode type. If the addresses accessed multiple times in a row show a fixed step size increase, it is determined to be a sequential access mode; if the access addresses show regular repetition and the interval time is similar, it is determined to be a circular access mode; if the access addresses are randomly distributed and have no pattern, it is determined to be a random access mode. Based on the access mode type and application running status information, establish a mapping relationship between application memory access behavior and construct an application memory access behavior profile database; The step of allocating optimal memory access regions to each processing core based on the memory access behavior characteristics and the physical topology includes: Receive memory access request information from each processing core, wherein the memory access request information includes the target memory address and access timestamp; The access frequency of each memory page within a preset time window is calculated based on the memory access request information. If the access frequency exceeds the high frequency threshold, it is marked as a hot data page, and memory page hotness marking information is obtained. Obtain the physical topology diagram, calculate the physical distance matrix between the processing core and each memory region, generate distance weight factors based on the physical distance matrix, and obtain a weighted distance table; Measure the bandwidth usage of the processing core, calculate the bandwidth fluctuation index and latency sensitivity index, and classify the access characteristics of the processing core based on the bandwidth fluctuation index and latency sensitivity index; Dynamic partitioning of memory regions is performed. Based on the heat labeling information, the weighted distance table, and the access characteristic classification, the hot data pages are migrated to the memory region with the smallest weighted distance to the corresponding processing core.

2. The high-efficiency memory management method based on a SOC chip according to claim 1, characterized in that, The process of obtaining the physical distance matrix between each processing core of the SOC chip and the memory controller, and constructing the physical topology of the SOC chip, includes: The coordinate information of each processing core and memory controller of the SOC chip is extracted. The topology-aware scanning algorithm is used to divide the physical layout of the SOC chip into a grid, and each grid cell is scanned and the precise physical location of each processing core and memory controller is recorded. Calculate the physical distance between any two processing cores and between a processing core and a memory controller based on the coordinate information, and generate a distance matrix from the calculation results; Based on the distance matrix and the internal transmission rate parameters of the SOC chip, the theoretical access latency data between each pair of processing cores and memory regions is calculated, and the theoretical access latency data is processed in layers and data path optimization analysis is performed. High-latency hotspots and low-latency areas are identified, and the difference between actual measured latency and theoretical calculated latency is compared to generate an optimal data access path recommendation table.

3. The high-efficiency memory management method based on a SOC chip according to claim 2, characterized in that, The process of acquiring memory access behavior characteristics of each application and allocating optimal memory access regions to each processing core based on these characteristics and the physical topology includes: Real-time collection of memory access request frequency and target address distribution of each processing core, recording of access heat index of each memory region, time window statistical analysis of access requests, and acquisition of memory access behavior characteristics of each application based on access frequency, data block size and access pattern characteristics. Based on the memory access behavior characteristics and physical topology, the physical memory space is divided into multiple regions with different access priorities. Memory pages containing frequently accessed hot data are marked, and the optimal memory access region is allocated to each processing core.

4. The high-efficiency memory management method based on a SOC chip according to claim 1, characterized in that, The triggered data migration mechanism reorganizes the memory address space and establishes a multi-level cache coordination mechanism, including: The data migration mechanism is triggered to copy hot data from a distant memory region to a memory region closer to the processing core, and the corresponding physical address pointer in the memory mapping table is updated. The memory address space is reorganized, virtual addresses are mapped to physical addresses, and consecutively accessed data blocks are allocated in physically adjacent memory regions that are close to the processing core. A multi-level cache collaboration mechanism is established, and an intermediate cache layer is added between the processing core and the remote memory controller to perform predictive caching of historical access data. Based on the memory access behavior characteristics, accessible data is loaded into the cache closer to the processing core.

5. The high-efficiency memory management method based on a SOC chip according to claim 4, characterized in that, The data migration triggering mechanism includes: The system receives monitoring data on the memory access frequency of the processing cores from the hardware performance counter. The monitoring data includes statistical information on the number of times each processing core accesses different memory regions. Based on the monitoring data, it is determined whether the access frequency of the processing core exceeds a preset frequency threshold. If it does, the access pattern recognition program is triggered to generate high-frequency access memory region identification information. The memory controller receives the identification information of the high-frequency access memory region, scans the data blocks stored in the high-frequency access memory region, identifies the data page with the highest access frequency, calculates the physical distance between the processing core and each candidate target memory region, and determines the available memory region closest to the processing core as the data migration target location. The data copying process is initiated to perform physical copying of hot data from a distant memory region to the data migration target location. The physical address mapping relationship in the page table is updated through the memory management unit, and the virtual address to physical address translation table entry is modified to obtain the optimized memory access path configuration.

6. The high-efficiency memory management method based on a SOC chip according to claim 5, characterized in that, The establishment of a multi-level cache coordination mechanism includes: Obtain the physical distance measurement data between the processing core and the memory controller; If the physical distance exceeds a preset distance threshold, a three-level cache architecture is established between the processing core and the remote memory controller. The three-level cache architecture includes storage space configuration parameters for each level of cache. Based on the storage space configuration parameters, the historical access sequence of the processing core is monitored, and the access pattern characteristics of the historical access sequence are analyzed using a time window sliding algorithm. If the frequency of continuous access exceeds the preset frequency threshold, the data prediction weight value is calculated. The prediction model is trained based on the predicted weight values ​​of the data. If the predicted weight values ​​of the data are greater than the preset prediction threshold, the preloading mechanism is triggered. The high-weight predicted data is migrated to the cache layer closest to the processing core through the load balancer scheduler to obtain a pre-cached data set. The hit rate of the pre-cached data set in each level of cache is monitored in real time. If the hit rate of the first-level cache is lower than the preset hit rate threshold, the distribution of the pre-cached data set in each cache level is dynamically adjusted according to the bandwidth utilization.

7. The high-efficiency memory management method based on SOC chip according to claim 1, characterized in that, The process of performing periodic memory reorganization based on the relationship between memory access frequency distribution maps and physical topology consolidates memory fragments that occur in long-running systems, rearranges data storage locations, and concentrates data blocks with similar access frequencies in physically adjacent memory regions. This includes: The memory access monitoring module continuously collects read and write operation records of each memory address. If the number of accesses to a memory page exceeds the preset threshold within a continuous monitoring period, it is marked as a hot page and the access heat value is recorded. After obtaining the physical memory topology information, a memory access heat distribution map is obtained. The memory access heat distribution map is scanned using a memory fragmentation detection algorithm to determine whether there are memory blocks with access frequency differences exceeding a preset value within the range of adjacent physical addresses. If there are adjacent memory blocks with mismatched access frequencies, they are identified as fragmented regions and a list of physical addresses is obtained. Data blocks are regrouped based on the access frequency data of the fragmented regions. If the difference in access frequency between two data blocks is less than a preset similarity threshold, they are classified into the same regrouping group and the target storage location is determined. The memory page migration mechanism is used to adjust the physical location of data blocks according to the data migration mapping relationship, and the data block copying and original address space release are completed through atomic operations.

8. A high-efficiency memory management system based on a SOC chip, characterized in that, A method for implementing an efficient memory management method based on a SOC chip as described in any one of claims 1 to 7, comprising: The allocation module is used to obtain the physical distance matrix between each processing core of the SOC chip and the memory controller, construct the physical topology of the SOC chip, obtain the memory access behavior characteristics of each application, and allocate the optimal memory access area to each processing core according to the memory access behavior characteristics and the physical topology. The processing module is used to trigger a data migration mechanism, reorganize the memory address space, and establish a multi-level cache coordination mechanism if it detects that the access frequency of one of the processing cores to the optimal memory region exceeds a preset frequency threshold. The redirection module is used to detect the workload and queue depth of each memory controller in real time. When it is detected that the load of one of the memory controllers exceeds the load threshold, the memory request distribution strategy is dynamically adjusted to redirect some access requests to the memory controller with a lighter load. The integration module is used to perform periodic memory reorganization operations based on the relationship between the memory access heat map and the physical topology. It integrates memory fragments that appear in long-running systems, rearranges the data storage locations, and concentrates data blocks with similar access frequencies in physically adjacent memory regions.

Images