Gate driving circuit, display panel and display panel driving method

Abstract

The invention relates to a gate driving circuit, a display panel and a display panel driving method, the gate driving circuit comprises multiple levels of cascaded gate driving units, and the Nth level of gate driving unit comprises a pull-down maintenance module comprising at least one phase inverter; the pull-down module comprises a first transistor and a second transistor, the first transistor and the second transistor are connected in series between a first node of the Nth-level gate driving unit and a first low-potential signal line, a gate of the second transistor is electrically connected to an output end of a phase inverter of the (N-x) th-level gate driving unit, N and x are positive integers, and N is greater than x; when the first node of the (N-x) th-level gate driving unit is in a high potential period, the second transistor is in a closed state, so that the first node of the Nth-level gate driving unit does not leak electricity through the first transistor. According to the invention, the first node of the Nth-level gate driving unit does not leak electricity through the first transistor, and a new transistor does not need to be designed for electricity leakage prevention.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate driving circuit, a display panel and a display panel driving method. BACKGROUND

[0002] The array substrate gate driving circuit (Gate-driver On Array, GOA) is a driving mode that integrates the gate driving circuit on the array substrate of the display panel and realizes the row-by-row output of the gate scanning signal by using the thin film transistor (Thin Film Transistor, TFT). The gate driving circuit includes multiple cascaded gate driving units. Taking the Nth gate driving unit as an example, the Q point of the Nth gate driving unit is a point of the gate of the related thin film transistor for controlling the high potential of the gate scanning signal G(N), and the stability of the Q point voltage determines the stability of the gate scanning signal G(N), wherein N is a positive integer.

[0003] In the related art, in order to realize high response and high refresh rate of the display panel, the common method is to reduce the channel width of the thin film transistor or to use the low temperature poly-silicon (Low Temperature Poly-silicon, LTPS) and indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) type thin film transistors. However, the above design or material selection is easy to cause the Q point of the thin film transistor to leak seriously in the off state, thereby affecting the stage transmission of the gate driving circuit. Moreover, in the related art, in order to design the anti-leakage structure, a new thin film transistor needs to be introduced in the gate driving unit, and in order to reduce the influence of the anti-leakage structure on the charging and discharging of the gate driving unit, the size of the introduced thin film transistor is relatively large, which is not conducive to the design of the narrow frame display panel. Therefore, how to optimize the design of the Q point anti-leakage structure is a problem to be solved. SUMMARY

[0004] Therefore, the present application provides a gate driving circuit, a display panel and a display panel driving method, which can make the second transistor in the off state during the first node of the N-xth gate driving unit is at high potential, thereby increasing the difficulty of leakage between the first node of the Nth gate driving unit and the first low potential line, and the second transistor of the present application itself is part of the gate driving unit in the related art, without the need to add a new transistor for anti-leakage design, which is conducive to the design of the narrow frame display panel.

[0005] According to an aspect of the present application, a gate drive circuit is provided, which comprises a plurality of cascaded gate drive units, an Nth gate drive unit comprising: a pull-down maintaining module comprising at least one inverter; a pull-down module comprising a first transistor and a second transistor, the first transistor and the second transistor being connected in series between a first node of the Nth gate drive unit and a first low potential signal line, and a gate of the second transistor being electrically connected to an output terminal of the inverter of an N-xth gate drive unit, N and x being positive integers and N being greater than x; wherein during a period when the first node of the N-xth gate drive unit is at a high potential, the second transistor is in an off state, so that the first node of the Nth gate drive unit does not leak through the first transistor.

[0006] According to another aspect of the present application, a display panel is provided, which comprises the gate drive circuit.

[0007] According to another aspect of the present application, a display panel driving method is provided, which is applied to the gate drive circuit, and comprises: at a first time, controlling the first node of the N-xth gate drive unit to be at a high potential, so that the second transistor of the Nth gate drive unit is off, and the first node of the Nth gate drive unit is limited to leak through the first transistor; and at a second time, controlling the first node of the N-xth gate drive unit to be at a low potential, so that the first node of the Nth gate drive unit is pulled down through the first transistor.

[0008] By connecting the first transistor and the second transistor in series between the first node of the Nth gate drive unit and the first low potential signal line, and electrically connecting the second transistor to the pull-down maintaining module of the N-xth gate drive unit, the present application can make the second transistor in an off state during a period when the first node of the N-xth gate drive unit is at a high potential, thereby increasing the difficulty of leakage between the first node of the Nth gate drive unit and the first low potential signal line, and the second transistor of the present application itself is part of the gate drive unit in the related art, and no new transistor needs to be designed to prevent leakage, which is conducive to the design of a narrow frame of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A schematic diagram of an Nth gate drive unit in the related art is shown.

[0010] Figure 2 A schematic diagram of an Nth gate drive unit in an embodiment of the present application is shown.

[0011] Figure 3 A timing diagram showing the operation of an N-1th gate drive unit and an Nth gate drive unit in an embodiment of the present application is shown.

[0012] Figure 4 A schematic diagram showing signal simulation of the Nth-stage gate drive unit of the embodiment of the present application.

[0013] Figure 5 A flow chart showing the display panel driving method of the embodiment of the present application. DETAILED DESCRIPTION

[0014] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The technical solutions described below are only used to explain and illustrate the idea of the present application, and should not be regarded as limiting the protection scope of the present application.

[0015] In addition, the terms “first”, “second” and similar words do not represent any order, number or importance, but are only used to distinguish different technical features. The term “multiple” and similar words represent two or more, unless otherwise explicitly limited.

[0016] Figure 1 A schematic diagram showing the Nth-stage gate drive unit of the related art. As shown in Figure 1 The Nth-stage gate drive unit in the related art includes a series of thin film transistors T4x, which includes transistors T41, T42, T43 and T44. The Q point is connected to the first low voltage signal line VSSQ through the series of thin film transistors T4x, and is connected to the gate scanning signal G(N) through the transistor T11. Both the series of thin film transistors T4x and the transistor T11 can become a leakage channel of the Q point.

[0017] In the related art, in order to design a leakage prevention structure, a new thin film transistor needs to be introduced in the gate drive unit, and in order to reduce the influence of the leakage prevention structure on the charging and discharging of the gate drive unit, the size of the introduced thin film transistor is relatively large, which is not conducive to the design of a narrow frame display panel.

[0018] Therefore, the application provides a gate drive circuit, which comprises a plurality of cascaded gate drive units, and an Nth gate drive unit comprises a pull-down maintaining module comprising at least one inverter, and a pull-down module comprising a first transistor and a second transistor, wherein the first transistor and the second transistor are connected in series between a first node of the Nth gate drive unit and a first low potential signal line, and a gate of the second transistor is electrically connected to an output terminal of the inverter of an N-xth gate drive unit, N and x are positive integers, and N is greater than x; during a high potential period of the first node of the N-xth gate drive unit, the second transistor is in an off state, so that the first node of the Nth gate drive unit does not leak through the first transistor.

[0019] By connecting the first transistor and the second transistor in series between the first node of the Nth gate drive unit and the first low potential signal line, and electrically connecting the second transistor to the pull-down maintaining module of the N-xth gate drive unit, the application can make the second transistor in the off state during the high potential period of the first node of the N-xth gate drive unit, thereby increasing the difficulty of leakage between the first node of the Nth gate drive unit and the first low potential line, and the second transistor itself is part of the gate drive unit in the related art, without the need to design a new transistor for leakage prevention, which is conducive to the design of a narrow frame of a display panel.

[0020] In an embodiment, the gate drive circuit is an array substrate gate drive circuit integrated on an array substrate of a display panel. The display panel comprises a display area and a non-display area. The display area comprises a pixel unit array in which a plurality of pixels are arranged in rows and columns, and the non-display area comprises the gate drive circuit. The gate drive circuit is electrically connected to the pixel unit array. The gate drive circuit comprises a plurality of cascaded gate drive units.

[0021] In an embodiment, the plurality of gate drive units can be connected to each other in a level transmission mode. Part of the output of a previous gate drive unit can be used as part of the input of a next gate drive unit. Each gate drive unit can output a corresponding row scanning signal for scanning the pixel units in a corresponding row of the pixel unit array.

[0022] Figure 2 A schematic diagram of an Nth gate drive unit of an embodiment of the application is shown. As shown in Figure 2 the circuit diagram of Figure 2 may be a circuit diagram of an Nth gate drive unit of the gate drive circuit, and N is a positive integer. The specific structure of the gate drive unit of the application will be specifically described below. Figure 2

[0023] ​In an embodiment, the pull-down maintaining module of the Nth-stage gate drive unit comprises a first inverter electrically connected to the second node of the Nth-stage gate drive unit, wherein a gate of the first transistor is electrically connected to a first control signal end ST(N+y) of an N+yth-stage gate drive unit, one of a source and a drain of the first transistor is electrically connected to the first node, and the other of the source and the drain of the first transistor is electrically connected to a first node of an N-xth-stage gate drive unit, y is a positive integer; a gate of the second transistor is electrically connected to a third node P(N-x) of the N-xth-stage gate drive unit, one of a source and a drain of the second transistor is electrically connected to the first node of the N-xth-stage gate drive unit, and the other of the source and the drain of the second transistor is electrically connected to the first low-voltage signal line.

[0024] The pull-down maintaining module of the Nth-stage gate drive unit comprises a second inverter electrically connected to the third node of the Nth-stage gate drive unit, and the pull-down module of the Nth-stage gate drive unit further comprises: a third transistor, a gate of the third transistor is electrically connected to the second node of the N-xth-stage gate drive unit, one of a source and a drain of the third transistor is electrically connected to the first node of the N-xth-stage gate drive unit, and the other of the source and the drain of the third transistor is electrically connected to the first low-voltage signal line.

[0025] Optionally, x is 1 and y is 6 in the application.

[0026] Please refer to Figure 2 The Nth-stage gate drive unit comprises a pull-down module 1, and the pull-down module 1 comprises a first transistor T41, a second transistor T42 and a third transistor T43.

[0027] A gate of the first transistor T41 is electrically connected to a first control signal end ST(N+6) of an N+6th-stage gate drive unit, one of a source and a drain of the first transistor T41 is electrically connected to the first node Q, and the other of the source and the drain of the first transistor T41 is electrically connected to a first node Q(N-1) of an N-1th-stage gate drive unit.

[0028] A gate of the second transistor T42 is electrically connected to a third node P(N-1) of the N-1th-stage gate drive unit, one of a source and a drain of the second transistor T42 is electrically connected to the first node Q(N-1) of the N-1th-stage gate drive unit, and the other of the source and the drain of the second transistor T42 is electrically connected to the first low-voltage signal line VSSQ.

[0029] The gate of the third transistor T43 is electrically connected to a second node K(N-1) of the N-1th gate drive unit, one of the source and the drain of the third transistor T43 is electrically connected to a first node Q(N-1) of the N-1th gate drive unit, and the other of the source and the drain of the third transistor T43 is electrically connected to the first low-voltage signal line VSSQ.

[0030] In an embodiment, the Nth gate drive unit further comprises a pull-down maintaining module, the pull-down maintaining module comprises at least one pull-down component, and the pull-down component is electrically connected to an inverter. Figure 2 For example, the pull-down maintaining module can comprise a first pull-down component 22 and a second pull-down component 24, and the first pull-down component 22 and the second pull-down component 24 are respectively electrically connected to an inverter.

[0031] The first pull-down component 22 comprises a fourth transistor T32, the gate of the fourth transistor T32 is electrically connected to a second node K, and the second node K is electrically connected to a first inverter 21. One of the source and the drain of the fourth transistor is electrically connected to a second low-voltage signal line VSSG, and the other of the source and the drain of the fourth transistor is electrically connected to a gate signal output end G(N) of the Nth gate drive unit.

[0032] The second pull-down component 24 comprises a fifth transistor T33, the gate of the fifth transistor T33 is electrically connected to a third node P, and the third node P is electrically connected to a second inverter 23. One of the source and the drain of the fifth transistor is electrically connected to a second low-voltage signal line VSSG, and the other of the source and the drain of the fifth transistor is electrically connected to a gate signal output end G(N) of the Nth gate drive unit.

[0033] In an embodiment, the Nth gate drive unit further comprises a pull-up module 3, the pull-up module 3 comprises a sixth transistor T21, the gate of the sixth transistor T21 is electrically connected to the first node Q, one of the source and the drain of the sixth transistor T21 is electrically connected to a scanning signal output end G(N) of the Nth gate drive unit, and the other of the source and the drain of the sixth transistor T21 is electrically connected to a clock signal end CK(N).

[0034] The pull-up module further comprises a coupling capacitor Cbt, a first end of the coupling capacitor is electrically connected to the gate of the sixth transistor T21, and a second end of the coupling capacitor Cbt is electrically connected to a gate signal output end G(N) of the Nth gate drive unit.

[0035] In an embodiment, the Nth stage gate drive unit further comprises a stage transmission module 4, the stage transmission module 4 comprising a seventh transistor T22, a gate of the seventh transistor T22 being electrically connected to the first node Q, one of a source and a drain of the seventh transistor T22 being electrically connected to a first control signal terminal ST(N) of the Nth stage gate drive unit, the other of the source and the drain of the seventh transistor T22 being electrically connected to a clock signal terminal CK(N).

[0036] In an embodiment, the Nth stage gate drive unit further comprises a pull-up control module 5, the pull-up control module 5 comprising an eighth transistor T11. A gate of the eighth transistor T11 is electrically connected to a first control signal terminal ST(N-4) of an (N-4)th stage gate drive unit, one of a source and a drain of the eighth transistor T11 is electrically connected to the first node Q, the other of the source and the drain of the eighth transistor T11 is electrically connected to a gate signal output terminal G(N-4) of the (N-4)th stage gate drive unit.

[0037] In an embodiment, the pull-down maintaining module comprises at least one of the inverters. Figure 2 For example, the pull-down maintaining module can comprise a first inverter 21 and a second inverter 23, the first inverter being electrically connected to the first pull-down component 22, the second inverter being electrically connected to the second pull-down component 24.

[0038] In an embodiment, the first inverter 21 comprises a ninth transistor T51, a tenth transistor T52, an eleventh transistor T53 and a twelfth transistor T54.

[0039] A gate of the ninth transistor T51 is electrically connected to a second control signal terminal LC1 of the Nth stage gate drive unit, one of a source and a drain of the ninth transistor T51 is electrically connected to the second control signal terminal LC1.

[0040] A gate of the tenth transistor T52 is electrically connected to the first node Q of the Nth stage gate drive unit, one of a source and a drain of the tenth transistor T52 is electrically connected to the first low voltage signal line VSSQ, the other of the source and the drain of the tenth transistor T52 is electrically connected to the other of the source and the drain of the ninth transistor T51.

[0041] A gate of the eleventh transistor T53 is electrically connected to the other of the source and the drain of the ninth transistor T51, one of a source and a drain of the eleventh transistor T53 is electrically connected to a second node K of the Nth stage gate drive unit, the other of the source and the drain of the eleventh transistor T53 is electrically connected to the second control signal terminal LC1 of the Nth stage gate drive unit.

[0042] One of the source and drain of the twelfth transistor T54 is electrically connected to the first node Q of the Nth stage gate drive unit, and the other of the source and drain of the twelfth transistor T54 is electrically connected to the first low voltage signal line VSSQ.

[0043] In an embodiment, the second inverter 23 includes a thirteenth transistor T61, a fourteenth transistor T62, a fifteenth transistor T63, and a sixteenth transistor T64.

[0044] The gate of the thirteenth transistor T61 is electrically connected to the third control signal end LC2 of the Nth stage gate drive unit, and one of the source and drain of the thirteenth transistor T61 is electrically connected to the third control signal end LC2.

[0045] The gate of the fourteenth transistor T62 is electrically connected to the first node Q of the Nth stage gate drive unit, one of the source and drain of the fourteenth transistor T62 is electrically connected to the first low voltage signal line VSSQ, and the other of the source and drain of the fourteenth transistor T62 is electrically connected to the other of the source and drain of the thirteenth transistor T61.

[0046] The gate of the fifteenth transistor T63 is electrically connected to the other of the source and drain of the thirteenth transistor T61, one of the source and drain of the fifteenth transistor T63 is electrically connected to the third node P of the Nth stage gate drive unit, and the other of the source and drain of the fifteenth transistor T63 is electrically connected to the third control signal end LC2 of the Nth stage gate drive unit.

[0047] The gate of the sixteenth transistor T64 is electrically connected to the first node Q of the Nth stage gate drive unit, one of the source and drain of the sixteenth transistor T64 is electrically connected to the first low voltage signal line VSSQ, and the other of the source and drain of the sixteenth transistor T64 is electrically connected to the third node P of the Nth stage gate drive unit.

[0048] In an embodiment, the Nth stage gate drive unit further includes a reset module 6, and the reset module 6 includes a seventeenth transistor T44. The gate of the seventeenth transistor T44 is electrically connected to a reset signal end Reset, one of the source and drain of the seventeenth transistor T44 is electrically connected to the first low voltage signal line VSSQ, and the other of the source and drain of the seventeenth transistor T44 is electrically connected to the first node Q of the Nth stage gate drive unit.

[0049] Figure 3The timing chart showing the working of the Nth-1 stage gate drive unit and the Nth stage gate drive unit of the embodiments of the present application is shown in FIG. 6. As shown in FIG. 6, when the first node Q(N) of the Nth stage gate drive unit is at high potential, the second node K(N-1) and the third node P(N-1) of the Nth-1 stage gate drive unit, to which the two inverters of the Nth-1 stage gate drive unit are electrically connected respectively, are both at low potential. At this time, the second transistor T42 and the third transistor T43 are in the off state, thereby limiting the leakage of the first node Q of the Nth-1 stage gate drive unit through the first transistor T41. Figure 3

[0050] Specifically, referring to FIG. 6, Figure 3 At t1, the first node Q(N-1) of the Nth-1 stage gate drive unit becomes the first high potential, at this time, the sixth transistor T21 and the seventh transistor T22 of the Nth-1 stage gate drive unit are both in the on state. Since the clock signal end CK(N-1) of the Nth-1 stage gate drive unit becomes the low potential, at this time, the gate signal output end G(N-1) and the first control signal end ST(N-1) of the Nth-1 stage gate drive unit are also both at the low potential. Since the potential of the second node and the potential of the third node are both opposite to the potential of the first node, the second node K(N-1) and the third node P(N-1) of the Nth-1 stage gate drive unit also become the low potential.

[0051] At t1, the first node Q of the Nth stage gate drive unit is at the low potential, the clock signal end CK(N)(N) of the Nth stage gate drive unit is at the high potential, since the sixth transistor T21 of the Nth stage gate drive unit is in the off state, the gate signal output end G(N) of the Nth stage gate drive unit is still at the low potential. Since the second node K(N-1) and the third node P(N-1) of the Nth-1 stage gate drive unit also become the low potential, the gate of the second transistor T42 and the gate of the third transistor T43 of the Nth stage gate drive unit are also at the low potential, the second transistor T42 and the third transistor T43 of the Nth stage gate drive unit are in the off state, thereby limiting the leakage of the first node Q of the Nth stage gate drive unit through the first transistor T41.

[0052] ​At the moment t2, the clock signal end CK(N-1) of the N-1th gate drive unit, the first node Q(N-1) of the N-1th gate drive unit and the gate signal output end G(N-1) of the N-1th gate drive unit remain unchanged, the clock signal end CK(N)(N) of the Nth gate drive unit changes from high potential to low potential, the first node Q(N) of the Nth gate drive unit becomes the first high potential, at this moment the sixth transistor T21 of the Nth gate drive unit is in the open state, but due to the low potential of the clock signal end CK(N)(N), the gate signal output end G(N) of the Nth gate drive unit is still low potential.

[0053] At the moment t3, the clock signal end CK(N-1) of the N-1th gate drive unit changes from low potential to high potential, due to the coupling effect of the coupling capacitor Cbt of the N-1th gate drive unit, the first node Q(N-1) of the N-1th gate drive unit is further coupled to the second high potential which is greater than the first high potential. The clock signal end CK(N)(N) of the Nth gate drive unit, the first node Q(N) of the Nth gate drive unit and the gate signal output end G(N) of the Nth gate drive unit remain unchanged.

[0054] At the moment t4, the clock signal end CK(N)(N) of the Nth gate drive unit changes from low potential to high potential, at this moment the gate signal output end G(N) of the Nth gate drive unit changes to high potential and starts to output the Nth gate signal because the sixth transistor T21 of the Nth gate drive unit is in the open state. Due to the coupling effect of the coupling capacitor Cbt of the Nth gate drive unit, the first node Q(N) of the Nth gate drive unit is further coupled to the second high potential.

[0055] At the moment t5, the clock signal end CK(N-1) of the N-1th gate drive unit changes from high potential to low potential, at this moment the first node Q(N-1) of the N-1th gate drive unit starts to pull down because the sixth transistor T21 and the seventh transistor T22 of the N-1th gate drive unit are in the open state, and the gate signal output end G(N) of the N-1th gate drive unit is low potential.

[0056] At the moment t6, the clock signal end CK(N)(N) of the Nth gate drive unit changes from high potential to low potential, at this moment the first node Q(N) of the Nth gate drive unit starts to pull down because the sixth transistor T21 and the seventh transistor T22 of the Nth gate drive unit are in the open state, and the gate signal output end G(N) of the Nth gate drive unit changes to low potential.

[0057] At the t7 moment, the first node Q(N-1) of the N-1th gate drive unit is pulled low to a low potential. Since the potential of the second node and the potential of the third node are both opposite to the potential of the first node, the second node K(N-1) and the third node P(N-1) of the N-1th gate drive unit are both high potentials. At this time, the gate of the second transistor T42 and the gate of the third transistor T43 of the Nth gate drive unit are both high potentials, and the second transistor T42 and the third transistor T43 of the Nth gate drive unit are in an open state, so that the first node Q of the Nth gate drive unit can be electrically connected to the first low voltage signal line VSSQ through the first transistor T41, to ensure that the first node Q of the Nth gate drive unit can be pulled down to the first low voltage through the first transistor T41.

[0058] Figure 4 A schematic diagram of signal simulation of the Nth gate drive unit of the embodiment of the application is shown. As shown in Figure 4 , the voltage waveform simulation results of the Q(N) point and the K / P(N-1) point of the Nth gate drive unit designed by the application are shown in Figure 4 . When the Q(N) point is a high potential, the K / P(N-1) point is at a low potential, which can effectively close T42 / T43, realize Q point anti-leakage, and the ΔQ and leakage current are smaller, so as to improve the Q point voltage, realize faster rising and pull-down of the G(N) signal. At the same time, the K / P(N-1) point voltage rises to a high potential before being pulled down by T41, one of T42 and T43 is opened, and the pull-down function of T41 to the Q point is ensured to be unaffected. In addition, T42 and T43 are connected to the Q point of the previous stage gate drive unit, and can maintain the original pull-down maintenance function in a high potential state.

[0059] Figure 5 A flow chart of the display panel driving method of the embodiment of the application is shown. As shown in Figure 5 , the display panel driving method is applied to the gate drive circuit, and the display panel driving method comprises:

[0060] Step S1: at a first moment, the first node of the N-xth gate drive unit is controlled to be a high potential, so that the second transistor of the Nth gate drive unit is closed, and the leakage of the first node of the Nth gate drive unit through the first transistor is limited.

[0061] The first moment is the t1 moment.

[0062] Step S2: at a second moment, the first node of the N-xth gate drive unit is controlled to be a low potential, so that the first node of the Nth gate drive unit is pulled down through the first transistor.

[0063] The second time point is t7. The gate drive circuit can include a processor, and the display panel driving method can be executed by the processor. For specific details of the display panel driving method, refer to the description of the structure of the gate drive unit and Figure 3

[0064] In summary, by connecting the first transistor and the second transistor in series between the first node of the Nth gate drive unit and the first low potential signal line, and electrically connecting the second transistor to the pull-down maintaining module of the N-xth gate drive unit, the second transistor can be in an off state during the first node of the N-xth gate drive unit is at a high potential, thereby increasing the difficulty of leakage between the first node of the Nth gate drive unit and the first low potential line, and the second transistor itself is part of the gate drive unit in the related art, without the need to design a new transistor to prevent leakage, which is conducive to the design of a narrow frame of the display panel.

[0065] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0066] The present application can have other various embodiments. Those skilled in the art can make various corresponding changes and modifications according to the present application without departing from the spirit and essential characteristics of the present application, and these corresponding changes and modifications shall all fall within the protection scope of the claims attached to the present application.​

Claims

1. A gate drive circuit characterized by comprising: The gate drive circuit comprises a plurality of cascaded gate drive units, an Nth gate drive unit comprising: a pull-down maintaining module comprising at least one inverter; a pull-down module comprising a first transistor and a second transistor, the first transistor and the second transistor being connected in series between a first node of the Nth gate drive unit and a first low-voltage signal line, and a gate of the second transistor being electrically connected to an output terminal of the inverter of an N-xth gate drive unit, N and x being positive integers and N being greater than x; wherein during a high-voltage period of the first node of the N-xth gate drive unit, the second transistor is in a closed state, so that the first node of the Nth gate drive unit does not leak through the first transistor.

2. The gate drive circuit according to claim 1, characterized by The pull-down maintaining module of the Nth gate drive unit comprises a first inverter, the first inverter being electrically connected to a second node of the Nth gate drive unit, wherein a gate of the first transistor is electrically connected to a first control signal terminal ST(N+y) of an N+yth gate drive unit, one of a source and a drain of the first transistor is electrically connected to the first node, and the other of the source and the drain of the first transistor is electrically connected to the first node of the N-xth gate drive unit, y being a positive integer; a gate of the second transistor is electrically connected to a third node of the N-xth gate drive unit, one of a source and a drain of the second transistor is electrically connected to the first node of the N-xth gate drive unit, and the other of the source and the drain of the second transistor is electrically connected to the first low-voltage signal line.

3. The gate drive circuit according to claim 2, characterized by The pull-down maintaining module of the Nth gate drive unit comprises a second inverter, the second inverter being electrically connected to a third node of the Nth gate drive unit, and the pull-down module of the Nth gate drive unit further comprises: a third transistor, a gate of the third transistor being electrically connected to the second node of the N-xth gate drive unit, one of a source and a drain of the third transistor being electrically connected to the first node of the N-xth gate drive unit, and the other of the source and the drain of the third transistor being electrically connected to the first low-voltage signal line.

4. The gate drive circuit according to claim 3, characterized by The pull-down maintaining module of the Nth gate drive unit comprises a first pull-down component, the first pull-down component being electrically connected to the first inverter, and the first pull-down component comprises: a fourth transistor, a gate of the fourth transistor being electrically connected to the second node, one of a source and a drain of the fourth transistor being electrically connected to a second low-voltage signal line, and the other of the source and the drain of the fourth transistor being electrically connected to a gate signal output terminal of the Nth gate drive unit.

5. The gate drive circuit according to claim 4, characterized in that The pull-down maintaining module of the Nth gate drive unit comprises a second pull-down component, the second pull-down component being electrically connected to the second inverter, and the second pull-down component comprises: A fifth transistor, a gate of the fifth transistor is electrically connected to the third node, one of a source and a drain of the fifth transistor is electrically connected to the second low-voltage signal line, and the other of the source and the drain of the fifth transistor is electrically connected to the gate signal output end of the Nth-stage gate drive unit.

6. The gate drive circuit according to claim 5, characterized by The Nth-stage gate drive unit further includes a pull-up module and a stage transmission module, wherein The pull-up module includes a sixth transistor, a gate of the sixth transistor is electrically connected to the first node of the Nth-stage gate drive unit, one of a source and a drain of the sixth transistor is electrically connected to the scan signal output end of the Nth-stage gate drive unit, and the other of the source and the drain of the sixth transistor is electrically connected to the clock signal end; The stage transmission module includes a seventh transistor, a gate of the seventh transistor is electrically connected to the first node of the Nth-stage gate drive unit, one of a source and a drain of the seventh transistor is electrically connected to the first control signal end ST(N) of the Nth-stage gate drive unit, and the other of the source and the drain of the seventh transistor is electrically connected to the clock signal end.

7. The gate drive circuit according to claim 3, wherein The first inverter and the second inverter work alternately, wherein, at the same time, one of the second transistor and the third transistor is in an open state, and the other of the second transistor and the third transistor is in a closed state.

8. The gate drive circuit according to claim 3, characterized by One of the second transistor and the third transistor is opened earlier than the first transistor, so as to avoid the second node and the third node of the Nth-x stage gate drive unit from competing.

9. A display panel, characterized by, The display panel includes the gate drive circuit according to any one of claims 1-8.

10. A display panel driving method, comprising: The display panel driving method is applied to the gate drive circuit according to any one of claims 1-8, and the display panel driving method includes: At a first time, the first node of the Nth-x stage gate drive unit is controlled to be high, so as to make the second transistor of the Nth-stage gate drive unit closed and limit the first node of the Nth-stage gate drive unit from leaking through the first transistor; At a second time, the first node of the Nth-x stage gate drive unit is controlled to be low, so as to make the first node of the Nth-stage gate drive unit pulled down through the first transistor.

Images