Memory device

Abstract

A memory device includes: a first bit cell group including a first plurality of bit cells; and a first peripheral circuit group configured to write data to the first plurality of bit cells and read data from the first plurality of bit cells, where the first peripheral circuit group includes a first type transistor and a second type transistor of a different type from the first type transistor, and where the first peripheral circuit group is configured to write data to the first plurality of bit cells and read data from the first plurality of bit cells. The first peripheral circuit group includes a first switching cell including one of a first type transistor and a second type transistor, and a plurality of first standard cells adjacent to each other in a first direction.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0054310, filed on April 23, 2024, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2025-0040184, filed on March 28, 2025, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a memory device. BACKGROUND

[0003] A memory device is a storage device that can record data and read the data when needed. The memory device can include a non-volatile memory (NVM) in which stored data does not disappear even if power is not supplied, and a volatile memory (VM) in which stored data is destroyed when power is not supplied. Meanwhile, as electronic devices such as electronic portable devices become smaller, memory devices mounted on the electronic devices also gradually become smaller and lighter. As the memory device size shrinks, various researches are being conducted to integrate more circuits in a limited space. SUMMARY

[0004] Some embodiments according to the present disclosure attempt to provide a memory device that efficiently utilizes an area.

[0005] Some embodiments according to the present disclosure seek to provide a memory device that improves a voltage drop (IR drop) with respect to a standard cell in a memory device.

[0006] Some embodiments of the present disclosure provide a memory device including a first bit cell group including a first plurality of bit cells, and a first peripheral circuit group configured to write data to and read data from the first plurality of bit cells, wherein the first peripheral circuit group includes a first type transistor and a second type transistor different from the first type transistor, and wherein the first peripheral circuit group includes a first switch cell including one of the first type transistor and the second type transistor, and a plurality of first standard cells adjacent to each other in a first direction.

[0007] Some embodiments of the present disclosure provide a memory device, comprising: a bit cell group comprising a plurality of bit cells; and a peripheral circuit group, wherein a width of the peripheral circuit group in a first direction is equal to a width of the bit cell group in the first direction, wherein the peripheral circuit group is aligned with the bit cell group in a second direction perpendicular to the first direction, and wherein the peripheral circuit group comprises: a plurality of power rails spaced apart from each other in the first direction and extending in the second direction, a plurality of first active regions between a first power rail and a second power rail among the plurality of power rails, wherein the plurality of first active regions are spaced apart from each other in the first direction and extend in the second direction, and comprise a first transistor and a second transistor of a different type than the first transistor, wherein the first transistor and the second transistor are electrically connected to a first bit cell and a second bit cell among the plurality of bit cells, respectively, a plurality of second active regions between a third power rail and a fourth power rail among the plurality of power rails, wherein the plurality of second active regions are spaced apart from each other in the first direction and extend in the second direction, and comprise a third transistor and a fourth transistor of a different type than the third transistor, wherein the third transistor and the fourth transistor are electrically connected to a third bit cell and a fourth bit cell among the plurality of bit cells, respectively, and a third active region between the second power rail and the third power rail, wherein the second power rail and the third power rail are adjacent to each other, wherein the third active region is spaced apart from the second power rail and the third power rail by a same distance in the first direction and extends in the second direction, and wherein the third active region comprises a fifth transistor.

[0008] Some embodiments of the present disclosure provide a memory device, comprising: a plurality of bit cells having a first width in a first direction; a plurality of standard cells having a second width different from the first width in the first direction, wherein the plurality of standard cells are electrically connected to the plurality of bit cells by bit lines, wherein the plurality of standard cells comprise a plurality of active regions, wherein each of the plurality of active regions comprises a first type transistor and a second type transistor different from the first type transistor, wherein a height of each active region of the plurality of active regions in the first direction is based on a width of the respective active region of the plurality of active regions in the first direction, and wherein the plurality of standard cells are aligned in the first direction; and a non-standardized cell aligned with the plurality of standard cells in the first direction and having a height equal to a difference between a length of the first width and a length of the second width. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A block diagram of a memory device is shown in accordance with some embodiments.

[0010] Figure 2 A layout diagram of a memory device is shown in accordance with some embodiments.

[0011] Figure 3 A circuit diagram showing a bitcell of a semiconductor device according to some embodiments of the disclosure is shown.

[0012] Figure 4 A layout diagram of a semiconductor device according to comparative embodiments is shown.

[0013] Figure 5 A layout diagram of a standard cell of a peripheral circuit group is shown.

[0014] Figure 6 A diagram showing a switch cell among the standard cells in a peripheral circuit group according to comparative embodiments is shown.

[0015] Figure 7 A diagram showing a switch cell among the standard cells in a peripheral circuit group according to comparative embodiments is shown.

[0016] Figure 8 A layout diagram of a semiconductor device according to some embodiments is shown.

[0017] Figure 9 A layout diagram of a standard cell of a peripheral circuit group according to some embodiments is shown.

[0018] Figure 10 A cross-sectional view of a standard cell and a switch cell according to some embodiments is shown.

[0019] Figure 11 A layout diagram of a memory device according to some embodiments is shown.

[0020] Figure 12 A layout diagram of a memory device according to some embodiments is shown.

[0021] Figure 13 A layout diagram of a memory device according to some embodiments is shown.

[0022] Figure 14 A layout diagram of a memory device according to some embodiments is shown.

[0023] Figure 15 A block diagram showing a computing system that fabricates a memory device according to some embodiments is shown.

[0024] Figure 16 A layout diagram of a memory device according to some embodiments is shown.

[0025] Figure 17 A layout diagram of a memory device according to some embodiments is shown. DETAILED DESCRIPTION

[0026] In the following detailed description, certain embodiments of the disclosure have been illustrated and described by way of example only. As will be realized by those skilled in the art, the described embodiments are merely examples and are not intended to limit the scope of the disclosure in any way.

[0027] It is understood that the embodiments described herein are intended to implement various features of the disclosure. These are of course merely examples and are not intended to be limiting. For example, the dimensions of the components are not limited to the ranges or values disclosed and can vary according to process conditions and / or desired device properties. Further, in the following description, the formation of a first structure on or over a second structure can include embodiments in which the first structure and the second structure are formed in direct contact, and embodiments in which additional structures can be formed between the first structure and the second structure such that the first structure and the second structure are not in direct contact. For simplicity and clarity, various structures are depicted in different scales.

[0028] Further, for ease of description, spatial relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, can be used herein to describe the relationship of one element or structure to another element or structure as shown in the drawings. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the drawings. For example, if the device in the drawings is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0029] The accompanying drawings and description are thus to be regarded as illustrative in nature and not restrictive. Throughout the specification, like reference numerals will be understood to refer to like elements every where they occur.

[0030] Further, unless expressly identified as an "explicitly recited limitation" no single feature or group of features should be inherently considered a discretionary disclosure. Expressions such as "one" or "the" as used herein not only include the singular form but also include the plural form unless explicitly stated otherwise. Terms including ordinal numbers, such as first, second, etc., will only be used to describe various components and not be construed as limiting those components. Such terms can be used for the purpose of distinguishing one constituent element from another constituent element.

[0031] It will be understood that when an element (such as a layer, film, region, or substrate) is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The term "and / or" includes any and all combinations of one or more of the associated listed items. The term "connected" herein can be used to indicate physical and / or electrical connections, and can mean directly or indirectly connected.

[0032] Figure 1 A block diagram of a memory device is shown in accordance with some embodiments.

[0033] Referring to Figure 1 The memory device 100 can receive a command CMD, an address ADDR, a clock CLK, and write data DATA_IN, and can output read data DATA_OUT. For example, the memory device 100 can receive a command CMD indicating a write (hereinafter can be referred to as a write command), an address (hereinafter can be referred to as a write address), and write data DATA_IN, and the write data DATA_IN can be stored in a region of the memory cell block 110 corresponding to the address. Additionally, the memory device 100 can receive a command (CMD) indicating a read (hereinafter can be referred to as a read command) and an address (hereinafter can be referred to as a read address), and can externally output read data DATA_OUT stored in a region of the memory cell block 110 corresponding to the address.

[0034] The memory cell block 110 can include a plurality of bit cells 120. Each of the bit cells 120 can be connected to one of a plurality of word lines WL and connected to at least one of a plurality of bit lines BL.

[0035] The row driver 140 can be connected to the memory cell block 110 through the word lines WL. The row driver 140 can activate one of the word lines WL based on a row address ROW. Accordingly, among the memory cells, a memory cell connected to the activated word line can be selected. That is, the row driver 140 can select any one of the word lines WL.

[0036] The control block 150 can receive the command CMD, the address ADDR, and the clock CLK, and can generate the row address ROW, the column address COL, the first control signal CTR1, and the second control signal CTR2. For example, the control block 150 can identify a read command by decoding the command CMD, and can generate the row address ROW, the column address COL, and the first control signal CTR1 to read the read data DATA_OUT from the memory cell block 110. Also, the control block 150 can identify a write command by decoding the command CMD, and can generate the row address ROW, the column address COL, and the second control signal CTR2 to write the write data DATA_IN in the memory cell block 110.

[0037] The input / output block 130 can include a bit line pre-charge circuit 131, a column driver 132, a read circuit 133, and a write circuit 134.

[0038] The bit line pre-charge circuit 131 can be connected to the memory cell block 110 through the bit line BL. The bit line pre-charge circuit 131 can pre-charge the bit line BL. The bit line BL can include a bit line connected to opposite ends of the memory cell and a bit line bar complementary to the bit line.

[0039] The column driver 132 can be connected to the bit line pre-charge circuit 131 through the bit line BL. The column driver 132 can select at least one bit line among the bit lines BL based on the column address COL. When at least one bit line is selected among the bit lines BL, a bit cell 120 connected to the selected bit line among the bit cells 120 can be selected. The at least one bit line can include a first bit line BL1 and a second bit line BL2 complementary to the first bit line BL1. The first bit line BL1 and the second bit line BL2 can be connected to opposite ends of the bit cells 120 of the memory cell block 110. The connection relationship between the bit cells 120 and the first bit line BL1 and the second bit line BL2 will be described later with reference to FIG. 2. Figure 3 The connection relationship between the bit cells 120 and the first bit line BL1 and the second bit line BL2 will be described later with reference to FIG. 2.

[0040] The read circuit 133 can detect a current and / or a voltage received through the bit line BL during a read operation, can identify a value connected to an activated word line (i.e., a value stored in the bit cell 120), and can output the read data DATA_OUT based on the identified value. The read circuit 133 can be connected to the column driver 132 through at least one bit line among the bit lines BL. The at least one bit line can include the first bit line BL1 and the second bit line BL2. The read circuit 133 can receive the first control signal CTR1 from the control block 150. The read circuit 133 can include a sense amplifier.

[0041] The write circuit 134 can apply a current and / or a voltage to the bit line BL based on the write data DATA IN during a write operation, and can write a value to the selected bit cell 120 connected to the activated word line. The write circuit 134 can be connected to the column driver 132 through at least one bit line among the bit lines BL. The at least one bit line can include a first bit line BL1 and a second bit line BL2. The write circuit 134 can receive a second control signal CTR2 from the control block 150.

[0042] Figure 2 A layout diagram of a memory device according to some embodiments is shown.

[0043] The memory device 100 can include a memory cell block 110, an input / output (I / O) block 130, a row driver 140, and a control block 150. The memory cell block 110 can include a plurality of bit cells 120 each accessed by a word line and a bit line. In some embodiments, the bit cells 120 can be volatile memory cells such as static random access memory (SRAM), dynamic random access memory (DRAM), etc. Embodiments of the present disclosure will be mainly described with reference to SRAM cells, but the present disclosure is not limited thereto.

[0044] Referring to Figure 2 The row driver 140 can be positioned adjacent to the memory cell block 110 in a first direction X. The row driver 140 can be positioned between the memory cell blocks 110 in the first direction X. The row driver 140 can access the bit cells 120 by the word line. The input / output block 130 can be positioned adjacent to the memory cell block 110 in a second direction Y perpendicular to the first direction X. The input / output block 130 can perform a write operation or a read operation. The control block 150 can be positioned adjacent to the input / output block 130 in the first direction X and adjacent to the row driver 140 in the second direction Y. The control block 150 can be positioned between the input / output blocks 130 in the first direction X. The input / output block 130 can transmit a signal to perform the write operation or the read operation.

[0045] Hereinafter, the input / output block 130, the row driver 140, and the control block 150 of the memory device 100 except for the memory cell block 110 can be referred to as a peripheral circuit. The peripheral circuit can include a plurality of standard cells. The standard cell as a unit of layout can be designed to perform a pre-defined function. The standard cell can refer to a standardized cell having a predetermined size, and can be provided from a cell library. In some embodiments, the bit cells of the memory cell block 110 of the memory device 100 can form a plurality of bit cell groups, and the plurality of standard cells of the peripheral circuit can form a plurality of peripheral circuit groups.

[0046] In some embodiments, the standard cell of the peripheral circuit group can write data to or read data from the bit cell of the memory cell block 110. The peripheral circuit group can include a switching cell. For example, the switching cell can perform a power gating operation of selectively providing a power supply voltage to the standard cell. In some embodiments, the switching cell can be implemented with a P-type transistor or an N-type transistor. Later, reference will be made to Figure 4 A bit cell group and a peripheral circuit group are described.

[0047] Figure 3 A circuit diagram for describing a bit cell of a semiconductor device according to some embodiments of the disclosure is shown. The bit cell 120 can be included in the memory cell block 110 of Figure 1 and Figure 2 and can refer to the bit cell 120 of Figure 1 and Figure 2 Here, the bit cell 120 can be an SRAM bit cell, but the disclosure is not limited thereto.

[0048] Referring to Figure 3 , the bit cell 120 can include a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass transistor PA1, and a second pass transistor PA2. The first pull-up transistor PU1 and the second pull-up transistor PU2 are P-type transistors, and the first pull-down transistor PD1, the second pull-down transistor PD2, and the first pass transistor PA1 and the second pass transistor PA2 can be N-type transistors, but the disclosure is not limited thereto.

[0049] The first pull-up transistor PU1 and the first pull-down transistor PD1 can constitute a first inverter IV1. The gates of the first pull-up transistor PU1 and the first pull-down transistor PD1 can be connected to each other. The gates of the first pull-up transistor PU1 and the first pull-down transistor PD1 connected to each other can correspond to an input terminal of the first inverter IV1. A first node N1 can correspond to an output terminal of the first inverter IV1.

[0050] The second pull-up transistor PU2 and the second pull-down transistor PD2 can constitute a second inverter IV2. The gates of the second pull-up transistor PU2 and the second pull-down transistor PD2 can be connected to each other. The gates of the second pull-up transistor PU2 and the second pull-down transistor PD2 connected to each other can correspond to an input terminal of the second inverter IV2. A second node N2 can correspond to an output terminal of the second inverter IV2.

[0051] The first inverter IV1 and the second inverter IV2 can be combined to form a latch structure. The gates of the first pull-up transistor PU1 and the first pull-down transistor PD1 can be electrically connected to the second node N2, and the gates of the second pull-up transistor PU2 and the second pull-down transistor PD2 can be electrically connected to the first node N1. That is, the input terminal of the first inverter IV1 can be connected to the output terminal of the second inverter IV2, and the input terminal of the second inverter IV2 can be connected to the output terminal of the first inverter IV1.

[0052] The source and the drain of the first pass transistor PA1 can be connected to the first node N1 and the first bit line BL1, respectively. The source and the drain of the second pass transistor PA2 can be connected to the second node N2 and the second bit line BL2, respectively. The second bit line BL2 can be complementary to the first bit line BL1. The gates of the first pass transistor PA1 and the second pass transistor PA2 can be electrically connected to the bit line WL.

[0053] In the bit cell 120, when the potential of the word line WL reaches the first level (e.g., logic high), the first pass transistor PA1 and the second pass transistor PA2 can be turned on, and the signals of the bit line BL and the complementary bit line BLB can be transmitted to the first inverter IV1 and the second inverter IV2, respectively, to be operated in order to write or read data.

[0054] Figure 4 A layout diagram of a semiconductor device according to a comparative embodiment is shown. Specifically, Figure 4 is a description of a bit cell group BG included in the memory device 100 in an X-Y plane and a peripheral circuit group PG corresponding to the bit cell group BG and included in a peripheral circuit. The bit cell group BG and the peripheral circuit group PG can be repeatedly arranged a plurality of times along a first direction X, but for the simplicity of description, one bit cell group BG and one peripheral circuit group PG are shown here.

[0055] Referring to Figure 4 , the bit cell group BG can include a predetermined number of bit cells arranged adjacently in the first direction X. For example, the bit cell group BG can include four bit cells 121, 122, 123, and 124, but the number of bit cells included in the bit cell group is not limited thereto. The bit cells 121, 122, 123, and 124 can be electrically connected to standard cells arranged in the peripheral circuit group PG (e.g., standard cells in which circuits constituting Figure 1 and Figure 2 the input / output block 130 are implemented) through bit lines and complementary bit lines.

[0056] The peripheral circuit group PG can include a predetermined number of standard cells SC arranged adjacently in the first direction X. The standard cell SC can include a logic cell such as a switching cell or an inverter. The standard cell, which is a unit of layout, can be designed to include a complementary metal-oxide semiconductor (CMOS) transistor including a P-type transistor and an N-type transistor. The standard cells arranged in the peripheral circuit group PG can implement a peripheral circuit that writes data to a bit cell or reads data from a bit cell.

[0057] The peripheral circuit group PG can correspond to the bit cell group BG. That is, the peripheral circuit group PG and the bit cell group BG can be aligned with each other in the second direction Y and have the same width in the first direction X. In Figure 4 In the embodiment, four bit cells 121, 122, 123, and 124 of the bit cell group BG are shown to correspond to six standard cells SC of the peripheral circuit group PG, but the ratio between the number of bit cells and the number of standard cells is not limited thereto and can be modified in various ways.

[0058] Meanwhile, the peripheral circuit group PG can include standard cells having different heights in order to increase integration of the standard cells positioned in a predetermined region corresponding to the bit cell group BG. Here, the height of a standard cell can refer to the length of the standard cell in the X-axis direction. For example, a first standard cell SC1 can have a first height H1, and a second standard cell SC2 can have a second height H2. In this case, the first height H1 can be greater than the second height H2. The height of a standard cell can vary according to the driving force or driving power of the standard cell. Among the standard cells, the height of a standard cell requiring a relatively large driving force or driving power can be greater than the height of a standard cell requiring a relatively small driving force or driving power. For example, the first height H1 corresponds to a first driving force or a first driving power, the second height H2 corresponds to a second driving force or a second driving power, and the first driving force or the first driving power can be greater than the second driving force or the second driving power. In Figure 4 In the embodiment, the peripheral circuit group PG is shown to include standard cells having two different heights, but the present disclosure is not limited thereto and the peripheral circuit group PG can include standard cells having three or more different heights. The internal structure of a standard cell 200 included in the peripheral circuit group PG will be described with reference to Figure 5 The internal structure of a standard cell 200 included in the peripheral circuit group PG will be described with reference to

[0059] Figure 5 A layout diagram of a standard cell of the peripheral circuit group is shown.

[0060] Referring to Figure 5The peripheral circuit group can include first standard cells SC1 of a first height H1 and second standard cells SC2 of a second height H2. A plurality of power rails (e.g., first to third power rails PR1 to PR3) that supply voltages to the standard cells can be positioned at the boundary (shown as M1) of each standard cell 200. The first to third power rails PR1 to PR3 can be formed as conductive patterns extending in the second direction Y and can be arranged to be spaced apart from each other in the first direction X. A power voltage and a ground voltage can be applied to the power rails. For example, a power voltage can be applied to the first and third power rails PR1 and PR3, and a ground voltage at a level lower than the power voltage can be applied to the second power rail PR2. Each standard cell can receive the power voltage and the ground voltage through the power rails.

[0061] The standard cells 200 can include a plurality of active regions (or active areas) extending in the second direction Y and spaced apart from each other in the first direction X. The first and second standard cells SC1 and SC2 can each include two active regions. The height of the standard cells 200 can be determined by the width of the active regions included in the standard cells in the first direction X. For example, the width W1 of the active regions included in the first standard cell SC1 in the first direction X is greater than the width W2 of the active regions included in the second standard cell SC2 in the first direction X, and thus the first height H1 of the first standard cell SC1 can be greater than the second height H2 of the second standard cell SC2.

[0062] An active pattern formed in the active regions can cross a gate line to form a transistor. For example, an N-type transistor can be formed in an active region formed on a substrate, and a P-type transistor can be formed in an active region formed in an n-well (shown as NWELL in FIG. 1) doped with an N-type impurity. The n-well can be formed across different standard cells. For example, one n-well can be formed across the first and second standard cells SC1 and SC2, but the n-well can be formed in different shapes according to the arrangement and number of transistors. Figure 7

[0063] ​Meanwhile, as described above, the peripheral circuit group PG and the bit cell group BG can have the same width in the first direction to facilitate integration of the standard cells SC in the peripheral circuit group PG, and the height of the standard cells designed as CMOS transistors can vary according to driving power of the standard cells SC. However, the height of some of the standard cells can be determined to be greater than the height due to driving force or driving power required by the standard cells, in order to maintain the same width of the peripheral circuit group PG and the bit cell group BG in the first direction. For example, assuming that a first driving force or a first driving power is greater than a second driving force or a second driving power, and the first standard cell SCI requires the second driving force or the second driving power, although the first standard cell SCI can be implemented with a second height H2, the first standard cell SCI having a first height HI corresponding to the first driving force or the first driving power can be positioned to maintain the same width of the peripheral circuit group PG and the bit cell group BG in the first direction.

[0064] The active pattern formed in the active region within the standard cell can be formed in various shapes. For example, the standard cell can be formed as a gate-all-around (GAA) transistor in which a nanowire on the active region is surrounded by a gate line, a plurality of nanosheets can be stacked on the active region, and the gate line can be formed as a multi-bridge channel (MBC) transistor surrounding the nanosheets. In this case, the maximum size of the nanowire or the nanosheet is predetermined, so the size of the transistor can not be adjusted beyond the maximum size of the nanowire or the nanosheet. That is, the width of the active region can not be increased beyond the maximum size of the nanowire or the nanosheet. However, there is a problem that although the maximum size of the transistor is fixed, some space in some of the standard cells is wasted as a blank space by increasing the height of some of the standard cells to maintain the same width of the peripheral circuit group PG and the bit cell group BG in the first direction X.

[0065] There is also a problem of wasting space within the standard cell in the standard cell implemented as a switching cell. Next, the problem will be described later with reference to Figure 6 and Figure 7 .

[0066] Figure 6 and Figure 7 a diagram for describing a switching cell among the standard cells in the peripheral circuit group according to a comparative embodiment is shown. Specifically, Figure 6 a circuit diagram for describing the switching cell is shown, and Figure 7 a layout diagram of the switching cell is shown.

[0067] Referring to Figure 6The standard cell in the peripheral circuit group of the memory device 100 can include a switching cell 210 and a logic cell 230. Here, the switching cell 210 is a power gating cell, and hereinafter, the operation of the switching cell 210 is shown and described as being implemented with P-type transistors, but the present disclosure is not limited thereto, and the switching cell 210 can be implemented with N-type transistors.

[0068] The switching cell 210 can receive a first voltage RVDD from the outside (e.g., an external source), and can output a second voltage VVDD based on an enable signal EN. The switching cell 210 can operate as a power gating cell by selectively outputting the second voltage VVDD based on the enable signal EN. The voltage levels of the first voltage RVDD and the second voltage VVDD can be the same. The switching cell 210 can provide the second voltage VVDD to the logic cell 230. The CMOS transistor 240 in the logic cell 230 can receive the second voltage VVDD from the switching cell 210, and can receive a ground voltage GND from the outside.

[0069] Meanwhile, according to the comparative example, the standard cell within the peripheral circuit group of the memory device 100 can be designed as a CMOS transistor. Accordingly, the switching cell 210 can include a P-type transistor 211 and an N-type transistor 213. However, since the operation of the switching cell 210 can be implemented with only the P-type transistor 211, the area of the N-type transistor 213 within the switching cell 210 can exist as a dummy area (or dummy region).

[0070] Referring to Figure 7 The switching cell 210 in the peripheral circuit group according to the comparative example can include a P-type transistor 211 and an N-type transistor 213, and the area of the N-type transistor within the switching cell 210 can exist as a dummy area. In other words, there is a problem that the space within the switching cell 210 comparable to the size of the N-type transistor is wasted.

[0071] According to some embodiments, the height of the standard cell in the peripheral circuit group is determined according to the driving force or driving power of the standard cell, and the P-type transistor or the N-type transistor can be positioned in the remaining area within the peripheral circuit group. According to some embodiments, the peripheral circuit group can include a switching cell designed with only the P-type transistor or the N-type transistor.

[0072] Figure 8 A layout diagram of a semiconductor device according to some embodiments is shown. Specifically, the peripheral circuit group PG according to some embodiments can include a standard cell SC1' having a height determined according to the driving force or driving power of the standard cell, and a switching cell designed with only the P-type transistor or the N-type transistor.

[0073] In some embodiments, the peripheral circuit group PG may include a first standard cell SC1′ of a third height H1′ and a second standard cell SC2 of a second height H2 according to a driving force or driving power. The first standard cell SC1′ according to some embodiments indicates a first standard cell SC2 of a third height H1′ and a second standard cell SC2 of a second height H2. Figure 4 The first standard cell SC1 of the comparative embodiment has a height determined according to the driving force or driving power required for the first standard cell SC1. For example, assuming that a third driving force or third driving power is required for the first standard cell SC1', the first standard cell SC1' may have a third height H1' determined according to the third driving force or third driving power required for the first standard cell SC1'. Therefore, the width of the bit cells 821, 822, 823, 824 in the first direction X may be different from the width of the standard cell SC in the first direction X. The length of the width of the bit cells 821, 822, 823, 824 in the first direction X may be longer than the length of the width of the standard cell SC in the first direction X. That is, depending on the driving force or driving power, the peripheral circuit group PG according to some embodiments may include the first standard cell SC1' having the third height H1' and the second standard cell SC2 having the second height H2, thereby obtaining as much remaining space as the fourth height H0. The fourth height H0 may be equal to a difference between the length of the width of the bit cells 821 , 822 , 823 , 824 in the first direction X and the length of the width of the standard cell SC in the first direction X.

[0074] The peripheral circuit group PG according to some embodiments may include a P-type transistor or an N-type transistor. The peripheral circuit group PG according to some embodiments may include a switch unit SW designed only with a P-type transistor or an N-type transistor. The peripheral circuit group PG may position a plurality of standard cells having a height determined according to a driving force or a driving power, and may position only a separate P-type transistor or an N-type transistor in the remaining space obtained. In some embodiments, the fourth height H0 may be a minimum height for realizing a P-type transistor or an N-type transistor. That is, the minimum height H0 for positioning a P-type transistor or an N-type transistor in the peripheral circuit group PG may be ensured by determining the height of the standard cell SC according to the driving force or the driving power of the standard cell SC in the peripheral circuit group PG. Figure 8 , the P-type transistor or N-type transistor implemented as the switch unit SW is shown as being positioned between the standard cells in the peripheral circuit group PG, but the present disclosure is not limited thereto, and the P-type transistor or N-type transistor implemented as the switch unit SW may be positioned at the edge of the peripheral circuit group PG.

[0075] In some embodiments, the peripheral circuit group PG can obtain a space larger than the fourth height H0 as a remaining space after determining the height of the standard cell SC in the peripheral circuit group PG according to the driving force or driving power of the standard cell SC. For example, the peripheral circuit group PG can obtain a space larger than an integer multiple of the fourth height H0 by determining the height of the standard cell SC according to the driving force or driving power of the standard cell SC in the peripheral circuit group PG. In some embodiments, the plurality of switching cells SW can be positioned in the remaining space after determining the height of the standard cell SC. For example, the peripheral circuit group PG can position the switching cell SW in a plurality of positions in which the switching cell SW is needed. The peripheral circuit group PG can position the switching cell SW implemented only with a P-type transistor or an N-type transistor at a position in which the switching cell SW is needed. The memory device 800 according to some embodiments can obtain a remaining space by determining the height of the standard cell SC according to the driving force or driving power of the standard cell SC, and the area of the memory device 800 can be efficiently utilized by positioning only the P-type transistor or the N-type transistor as the switching cell SW at a position in which the switching cell SW is needed. Additionally, when the switching cell SW operates as a power gating cell, there is an advantage of improving voltage drop (IR drop) for the standard cell within the peripheral circuit group PG.

[0076] The memory device 800 including the bit cells 821, 822, 823, 824 according to some embodiments can increase the number of standard cells implemented as logic cells by optimizing the size of the standard cell included in the peripheral circuit group PG corresponding to the bit cell group BG, thereby efficiently utilizing the area of the memory device 800. The internal structure of the standard cell 900 included in the peripheral circuit group PG according to some embodiments of the disclosure will be described with reference to FIG. 9. Figure 9 The internal structure of the standard cell 900 included in the peripheral circuit group PG according to some embodiments of the disclosure will be described with reference to FIG. 9.

[0077] Figure 9 A layout diagram of a standard cell of a peripheral circuit group according to some embodiments is illustrated. Meanwhile, a description that is repetitive with the description of the layout diagram according to Figure 4 will be omitted here.

[0078] In some embodiments, the peripheral circuit group can include first standard cells SC1' of a third height H1' and switch cells SW positioned between the first standard cells SC1'. At the boundary of the first standard cells SC1', first to fourth power rails PR1 to PR4 extending in a second direction Y and spaced apart from each other in a first direction X can be positioned to supply a power voltage and a ground voltage to the standard cells. The first standard cells SC1' can include a plurality of active regions extending in the second direction Y and spaced apart from each other in the first direction X. N-type transistors can be formed in the active regions formed on a substrate, and P-type transistors can be formed in the active regions formed in an n-hydrazine doped with an N-type impurity. Here, the third height H1' of the first standard cells SC1' can be a height determined according to a driving force or driving power of the first standard cells SC1'.

[0079] In some embodiments, the peripheral circuit group can include P-type transistors implemented as switch cells SW positioned in a remaining space obtained by optimizing the height of the standard cells. The switch cells SW can include an active region extending in the second direction Y. The active region of the switch cells SW can be positioned at an equal distance d from the power rails PR2 and PR3 positioned adjacent to the switch cells SW. In Figure 9 In the middle, the distance d is shown as a distance from the center of the power rails PR2 and PR3 to the edge of the active region, but the disclosure is not limited thereto, and the distance d can be based on various points, such as from the center of the power rails PR2 and PR3 to the center of the active region.

[0080] In some embodiments, the switch cells SW can share the n-hydrazine with the adjacent first standard cells SC1'. The switch cells SW can share the power rails PR2 and PR3 with the adjacent first standard cells SC1'. For example, at least one of the power rails PR2 and PR3 can be a power rail supplying a power voltage. The switch cells SW can output a second voltage VVDD to at least one of the power rails PR2 and PR3 based on a first voltage RVDD and an enable signal EN received from the outside.

[0081] Meanwhile, unlike Figure 8 and Figure 9 , the standard cells of various heights can be arranged around the switch cells SW, and the n-hydrazine can be formed in various shapes according to the arrangement and type of the switch cells and the standard cells.

[0082] Figure 10 A cross-sectional view of a standard cell and a switch cell according to some embodiments is illustrated. Specifically, Figure 10 A cross-sectional view taken along line A-A' in Figure 9 is illustrated, showing an example in which a nanosheet is formed as an active pattern in an active region. However, the memory device according to the disclosure is not limited thereto.

[0083] Referring to Figure 10 In some embodiments, a plurality of active regions FA extending in the second direction Y can be formed on the substrate SUB, and a nanosheet stacked structure in which a plurality of nanosheets N1, N2, and N3 are stacked can be formed on each of upper portions of the active regions FA.

[0084] The plurality of active regions FA on the substrate SUB can be formed in an n-well NWELL formed within the substrate SUB. Trenches 1010 defining the active regions FA can be formed between the active regions FA. The active regions FA can be separated from each other by the trenches 1010.

[0085] In some embodiments, nanosheets N1, N2, and N3 can be formed on top of each of the active regions FA. The nanosheets N1, N2, and N3 can be arranged to be spaced apart from the active regions FA in the second direction Y. Each of the nanosheets N1, N2, and N3 can extend on the active regions FA in the first direction X. Each of the nanosheets N1, N2, and N3 can be stacked one by one on the active regions FA and can serve as a channel of a transistor. For example, if N-type impurities are doped in the nanosheets N1, N2, and N3, a P-type transistor can be formed, and if P-type impurities are doped, an N-type transistor can be formed. Meanwhile, here, three nanosheets N1, N2, and N3 are shown to form a nanosheet stacked structure, but the disclosure is not limited thereto. Further, here, the planar shape of the nanosheets N1, N2, and N3 can be shown to have an approximate quadrangular shape, but the disclosure is not limited thereto, and the nanosheets N1, N2, and N3 can have various planar shapes according to the planar shape of the active regions FA and the planar shape of the gates GI and GL. The nanosheets N1, N2, and N3 can be made of silicon (Si), germanium (Ge), or silicon-germanium (SiGe), and can also be made of InGaAs, InAs, GaSb, InSb, or a combination thereof.

[0086] The gates GI and GL can be formed to surround at least a portion of the nanosheets N1, N2, and N3. For example, the gates GI and GL can include a gate line GL surrounding the nanosheets N1, N2, and N3 and a gate insulating film GI formed between the nanosheets N1, N2, and N3 and the gate line GL.

[0087] An interlayer insulating layer 1020 can be disposed on the gate line GL, and the gate line GL can be connected to power rails PR2 and PR3 of the first metal layer through a gate contact and a gate via (not shown) formed to extend through the interlayer insulating layer.

[0088] Referring to Figure 9 , the nanosheet stacked structure in which a plurality of nanosheets N1, N2, and N3 are stacked can be formed on each of upper portions of the active regions FA. Figure 10The P-type transistor in the center among the transistors shown in the center can be a switch cell SW. That is, unlike other standard cells designed with CMOS transistors, the switch cell SW is implemented with a P-type transistor, which has an advantage of optimizing the area of the memory device.

[0089] Figures 11 to 13 A layout diagram of a memory device according to some embodiments is shown.

[0090] Referring to Figure 11 The memory device 800 can include a first bit cell group BG1 and a second bit cell group BG2 including a predetermined number of bit cells arranged adjacently in a first direction X. For example, each of the first bit cell group BG1 and the second bit cell group BG2 arranged adjacently to each other in the first direction X can include a plurality of bit cells arranged adjacently to each other in the first direction X.

[0091] The memory device 800 can include a first peripheral circuit group PG1 and a second peripheral circuit group PG2 including a predetermined number of standard cells arranged adjacently in the first direction X and a second direction Y. For example, each of the first peripheral circuit group PG1 and the second peripheral circuit group PG2 arranged adjacently to each other in the first direction X can include a plurality of standard cells arranged adjacently in the first direction X and the second direction Y.

[0092] The first peripheral circuit group PG1 can correspond to the first bit cell group BG1, and the second peripheral circuit group PG2 can correspond to the second bit cell group BG2. The first peripheral circuit group PG1 and the first bit cell group BG1 can be aligned to each other in the second direction Y and can have the same width in the first direction X. The second peripheral circuit group PG2 and the second bit cell group BG2 can be aligned to each other in the second direction Y and can have the same width in the first direction X.

[0093] In some embodiments, the first and second peripheral circuit groups PG1 and PG2 can include P-type transistors TR1 and / or N-type transistors TR2. The first and second peripheral circuit groups PG1 and PG2 can include P-type transistors TR1 and / or N-type transistors TR2 aligned in the second direction Y positioned at a boundary between the first and second peripheral circuit groups PG1 and PG2. Here, one peripheral circuit group is shown to include transistors of different types, but one peripheral circuit group can include transistors of the same type. For example, the first peripheral circuit group PG1 can include P-type transistors TR1 aligned in the second direction Y at an interface with the second peripheral circuit group PG2, and the second peripheral circuit group PG2 can include N-type transistors TR2 aligned in the second direction Y at an interface with the first peripheral circuit group PG1. In some embodiments, at an interface where the first and second peripheral circuit groups PG1 and PG2 face each other, the types of transistors included in the first and second peripheral circuit groups PG1 and PG2 can be different from each other.

[0094] Referring to Figure 12 , the first and second bit cell groups BG1 and BG2 can include a plurality of bit cells, and the first and second peripheral circuit groups PG1 and PG2 can include a plurality of standard cells having different heights arranged in a plurality of rows. For example, the first peripheral circuit group PG1 can include standard cells of a first height Ha, standard cells of a second height Hb, and standard cells of a third height Hc, and the standard cells of the second peripheral circuit group PG2 can be arranged in a manner that the standard cells of the first peripheral circuit group PG1 are flipped with respect to the second direction Y. However, the arrangement of the standard cells in each peripheral circuit group is not limited thereto.

[0095] In some embodiments, the first and second peripheral circuit groups PG1 and PG2 can include P-type transistors TR1 and / or N-type transistors TR2 positioned at an interface. The P-type transistors TR1 and N-type transistors TR2 positioned at a boundary between the first and second peripheral circuit groups PG1 and PG2 can form one CMOS transistor by aligning the first and second peripheral circuit groups PG1 and PG2 adjacent to each other. Specifically, when the first and second peripheral circuit groups PG1 and PG2 are adjacently aligned in the first direction X, the P-type transistors TR1 and N-type transistors TR2 positioned at a boundary between the first and second peripheral circuit groups PG1 and PG2 can form one CMOS transistor. This allows to additionally implement a standard cell designed as a CMOS transistor without increasing the area of the memory device, increasing the integration of the standard cells in the memory device, thereby achieving an additional area improvement. This will be described with reference to Figure 13An internal structure of the transistor 810 positioned at a boundary between the first peripheral circuit group PG1 and the second peripheral circuit group PG2 is described.

[0096] Referring to Figure 13 The first transistor 811 and the second transistor 813 of the first peripheral circuit group PG1 and the first transistor 814 and the second transistor 812 of the second peripheral circuit group PG2 can be arranged adjacent to each other in the first direction X. Here, the first transistors 811 and 814 can be P-type transistors, and the second transistors 812 and 813 can be N-type transistors, but the present disclosure is not limited thereto. For example, the transistors 811 and 813 positioned in the first peripheral circuit group PG1 are P-type transistors, and the transistors 812 and 814 positioned in the second peripheral circuit group PG2 are N-type transistors. The first transistor 811 of the first peripheral circuit group PG1 can share the first power rail PR1 with an adjacent standard cell in the first peripheral circuit group PG1. Here, a power voltage can be applied to the first power rail PR1. The second transistor 813 of the first peripheral circuit group PG1 can share the third power rail PR3 with an adjacent standard cell in the first peripheral circuit group PG1. Here, a ground voltage can be applied to the third power rail PR3. The second transistor 812 in the second peripheral circuit group PG2 can share the second power rail PR2 with an adjacent standard cell in the second peripheral circuit group PG2. Here, a ground voltage can be applied to the second power rail PR2. The first transistor 814 in the second peripheral circuit group PG2 can share the fourth power rail PR4 with an adjacent standard cell in the second peripheral circuit group PG2. Here, a power voltage can be applied to the fourth power rail PR4.

[0097] In some embodiments, the first transistor 811 of the first peripheral circuit group PG1 and the second transistor 812 of the second peripheral circuit group PG2 are positioned adjacent to each other in the first direction X such that the first transistor 811 and the second transistor 812 can form a standard cell as a single CMOS transistor. In addition, the second transistor 813 of the first peripheral circuit group PG1 and the first transistor 814 of the second peripheral circuit group PG2 are positioned adjacent to each other in the first direction X such that the second transistor 813 and the first transistor 814 can form a standard cell as a single CMOS transistor.

[0098] Figure 14 A layout diagram of a memory device according to some embodiments is shown.

[0099] In some embodiments, the peripheral circuit groups PG3 and PG4 can have different widths in the first direction X than the bit cell groups BG3 and BG4. As described above in Figures 11 to 13In some embodiments described in the detailed description, in which the peripheral circuit groups are adjacently aligned to additionally form some of the standard cells, the peripheral circuit groups can also include P-type transistors and N-type transistors at the interface with another peripheral circuit group.

[0100] Referring to Figure 14 , the peripheral circuit groups PG3 and PG4 can be aligned with the bit cell groups BG3 and BG4 in the second direction Y. The third peripheral circuit group PG3 can correspond to the third bit cell group BG3, and the fourth peripheral circuit group PG4 can correspond to the fourth bit cell group BG4. The peripheral circuit groups PG3 and PG4 can include a plurality of standard cells arranged in a plurality of rows, and at least one of the rows can include P-type transistors and N-type transistors at the interface with another peripheral circuit group. For example, the third peripheral circuit group PG3 can include P-type transistors and N-type transistors in a first row in the interface with the fourth peripheral circuit group PG4, and the fourth peripheral circuit group PG4 can include P-type transistors and N-type transistors in a second row at the interface with the third peripheral circuit group PG3. Thus, by aligning the third peripheral circuit group PG3 and the fourth peripheral circuit group PG4 adjacent to each other, the standard cells can be additionally formed as CMOS transistors.

[0101] Figure 15 A block diagram illustrating a computing system that fabricates a memory device according to some embodiments is shown. At least a portion of the steps for fabricating a memory device according to embodiments of the present disclosure can be performed in the computing system 1500.

[0102] Referring to Figure 15 , the computing system 1500 can be a stationary computing system such as a desktop computer, a workstation, or a server, or a portable computing system such as a laptop computer. The computing system 1500 includes a processor 1510, input / output devices 1520, a network interface 1530, random access memory (RAM) 1540, read-only memory (ROM) 1550, and storage 1560. The processor 1510, the input / output devices 1520, the network interface 1530, the RAM 1540, the ROM 1550, and the storage 1560 can communicate with each other through a bus 1570.

[0103] The processor 1510 can be referred to as a processing unit and can include at least one core capable of executing any instruction set (such as, for example, in a microprocessor, an application processor (AP), a digital signal processor (DSP), or a graphics processor (GPU)). For example, the processor 1510 can access a memory (i.e., the RAM 1540 or the ROM 1550) through the bus 1570 and can execute instructions stored in the RAM 1540 or the ROM 1550.

[0104] The RAM 1540 can store the program 1541 or at least a portion of the program 1541 for manufacturing a memory device according to some embodiments of the disclosure. For example, the program 1541 can include semiconductor design tools such as logic synthesis tools and place and route (P&R) tools.

[0105] The program 1541 can cause the processor 1510 to perform at least a portion of the operations for manufacturing a memory device of Figures 8 to 13 For example, the operations for manufacturing a memory device of Figures 8 to 13 may include performing logic synthesis from register transfer level (RTL) data written in a hardware description language (HDL) or arranging and interconnecting standard cells. That is, the program 1541 can include a plurality of instructions executable by the processor 1510, and the instructions included in the program 1541 can cause the processor 1510 to perform at least a portion of the operations for manufacturing a memory device of Figures 8 to 13

[0106] The storage 1560 can not lose stored data even if power supplied to the computing system 1500 is cut off. For example, the storage 1560 can include a non-volatile memory device or a storage medium such as a magnetic tape, an optical disc, or a magnetic disc. The storage 1560 can store the program 1541 according to some embodiments of the disclosure, and the program 1541 or at least a portion of the program 1541 can be loaded into the RAM 1540 from the storage 1560 before the program 1541 is executed by the processor 1510. Alternatively, the storage 1560 can store a file written in a program language, and the program 1541 or at least a portion of the program 1541 generated from the file by a compiler or the like can be loaded into the RAM 1540.

[0107] The storage 1560 can store a database (DB) 1561, and the database 1561 can include information required to design a semiconductor device. For example, the database 1561 can include a cell library of standard cells of Figures 8 to 13 The cell library can include information related to logic cells included in a peripheral circuit group. For example, the cell library can include functional information, characteristic information, layout information, etc. of logic cells. Additionally, the storage 1560 can store data to be processed by the processor 1510 or data processed by the processor 1510.

[0108] The output / output device 1520 can include an input device such as a keyboard and a pointing device, and can include an output device such as a display device or a printer. The network interface 1530 can provide access to a network external to the computing system 1500.

[0109] Figure 16 A layout diagram of a memory device according to some embodiments is illustrated.​

[0110] As described above with reference to Figure 4 and Figure 5 To maintain the same width of the peripheral circuit group PG and the bit cell group BG in the first direction X, the height of some of the standard cells SC can be greater than the height determined due to the driving force required for the standard cell. Alternatively, to maintain the same width of the peripheral circuit group PG and the bit cell group BG including the standard cells in the first direction X, the area of the bit cells 1621, 1622, 1623, 1624 (e.g., the length of the width of the bit cells 1621, 1622, 1623, 1624 in the first direction X) can need to vary. This can result in an increase in the area of the memory device 1600.

[0111] In some embodiments, the bit cell group BG of the memory device 1600 can include the bit cells 1621, 1622, 1623, 1624. In Figure 16 , the peripheral circuit group PG is shown to include standard cells of various normalized heights (e.g., H1’, H2) according to driving force, but is not limited thereto, the peripheral circuit group PG can include standard cells of the same height. In some embodiments, the bit cell group BG of the memory device 1600 can include the bit cells 1621, 1622, 1623, 1624, and the peripheral circuit group PG can have a remaining space equal to the height Hn. That is, the width of the bit cells 1621, 1622, 1623, 1624 in the first direction X and the width of the standard cells SC in the first direction X can be different. The length of the width of the bit cells 1621, 1622, 1623, 1624 in the first direction X can be longer than the length of the width of the standard cells SC in the first direction X. Here, the height Hn can be equal to the difference between the length of the width of the bit cells 1621, 1622, 1623, 1624 in the first direction X and the length of the width of the standard cells SC in the first direction X. Accordingly, the peripheral circuit group PG can have a remaining space equal to the height Hn.

[0112] In some embodiments, the peripheral circuit group PG can include a tap cell (TC) of height Hn. The tap cell (TC) according to some embodiments can be a non-standardized cell, wherein the size of the non-standardized cell can not be predetermined. The tap cell can provide well tapping by connecting an n-well within the tap cell to a power voltage and connecting a p-well within the tap cell to a ground voltage to prevent a latch-up effect of the standard cell. The tap cell TC can be implemented in different heights to maintain the same width of the peripheral circuit group PG and the bit cell group BG in the first direction X, i.e., the height Hn of the tap cell TC can vary according to the length of the remaining space in the first direction X. Additionally, the peripheral circuit group PG can also include a plurality of tap cells (TC) according to the length of the remaining space in the first direction X. In Figure 16 In some embodiments, the tap cell (TC) is shown to be disposed between the standard cells within the peripheral circuit group (PG), but is not limited thereto, and the tap cell (TC) can be disposed at an edge of the peripheral circuit group (PG).

[0113] Figure 17 is a layout diagram of a memory device according to some embodiments.

[0114] In some embodiments, the memory device 1700 can include a first bit cell group BG1 and a second bit cell group BG2 including a predetermined number of bit cells arranged adjacently in the first direction X. For example, each of the first bit cell group BG1 and the second bit cell group BG2 arranged adjacently to each other in the first direction X can include a plurality of bit cells arranged adjacently to each other in the first direction X.

[0115] The memory device 1700 can include a first peripheral circuit group PG1 and a second peripheral circuit group PG2 including a predetermined number of standard cells arranged adjacently in the first direction X and the second direction Y. For example, each of the first peripheral circuit group PG1 and the second peripheral circuit group PG2 arranged adjacently to each other in the first direction X can include a plurality of standard cells arranged adjacently in the first direction X and the second direction Y.

[0116] Referring to Figure 17The first and second bit cell groups BG1 and BG2 can include a plurality of bit cells, and the first and second peripheral circuit groups PG1 and PG2 can include a plurality of standard cells having different heights arranged in a plurality of rows. For example, the first peripheral circuit group PG1 can include standard cells of a first height Ha, a second height Hb, a third height Hc, and a fourth height Hd, and the standard cells of the second peripheral circuit group PG2 can be arranged in a manner in which the standard cells of the first peripheral circuit group PG1 are flipped with respect to the second direction Y. However, the arrangement of the standard cells in each peripheral circuit group is not limited thereto.

[0117] In some embodiments, the width of the bit cells BITCELL in the first and second bit cell groups BG1 and BG2 in the first direction X and the width of the standard cells in the first and second peripheral circuit groups PG1 and PG2 in the first direction X can be different. The length of the width of the bit cells in the first direction X can be longer than the length of the width of the standard cells in the first direction X. The difference between the length of the width of the bit cells in the first direction X and the length of the width of the standard cells in the first direction X can be equal to the height Hn. Accordingly, the first and second peripheral circuit groups PG1 and PG2 can have a remaining space equal to the height Hn.

[0118] In some embodiments, the first and second peripheral circuit groups PG1 and PG2 can include the tap cells TC1, TC2 at the boundary bd. Here, the height Hn of the tap cells TC1, TC2 can vary according to the height of the remaining portion of the remaining space. In addition, the first and second peripheral circuit groups PG1 and PG2 can further include the tap cells at the boundary bd according to the height of the remaining space.

[0119] As described above, embodiments are disclosed in the drawings and the specification. In this specification, embodiments have been described using specific terminology to describe the technical idea of the present disclosure, but this is only for the purpose of describing the technical idea of the present disclosure, and is not intended to limit the meaning or scope of the present disclosure as set forth in the patent claims. Therefore, those of ordinary skill in the art will understand that various modifications and other equivalent embodiments of the present disclosure are possible. Accordingly, the true technical protection scope of the present disclosure must be determined based on the technical spirit of the appended claims.

Claims

1. A memory device comprising: a first group of bit cells comprising a first plurality of bit cells; and a first group of peripheral circuits configured to write data to and read data from the first plurality of bit cells, wherein the first group of peripheral circuits comprises a first type of transistor and a second type of transistor different from the first type of transistor, and wherein the first group of peripheral circuits comprises a first switch cell comprising one of the first type of transistor and the second type of transistor and a plurality of first standard cells adjacent to each other in a first direction.

2. The memory device of claim 1, further comprising: a plurality of power rails on a boundary of the plurality of first standard cells, wherein the plurality of power rails are configured to extend in a second direction perpendicular to the first direction, and wherein the plurality of power rails are configured to apply a first power voltage and a second power voltage different from the first power voltage to each of the plurality of first standard cells, and the first switch cell is between a first power rail and a second power rail among the plurality of power rails, wherein the first power rail and the second power rail are adjacent to each other.

3. The memory device of claim 2, wherein, the first switch cell is configured to receive a power voltage from an external source and send the power voltage as the first power voltage to at least one of the first power rail and the second power rail.

4. The memory device of claim 1, further comprising: a second group of bit cells comprising a second plurality of bit cells; and a second group of peripheral circuits configured to write data to and read data from the second plurality of bit cells, wherein the second group of peripheral circuits comprises a second switch cell comprising one of the first type of transistor and the second type of transistor and a plurality of second standard cells comprising the first type of transistor and the second type of transistor, and wherein the second group of peripheral circuits is adjacent to the first group of peripheral circuits in the first direction.

5. The memory device of claim 4, wherein, the first switch cell and the second switch cell are adjacent to a boundary between the first group of peripheral circuits and the second group of peripheral circuits.

6. The memory device of claim 5, wherein, the types of transistors of the first switch cell and the second switch cell are different from each other.

7. The memory device of any one of claims 1-6, wherein, the first type of transistor and the second type of transistor are gate-all-around transistors.

8. The memory device of claim 7, wherein, the gate-all-around transistors are multi-bridge-channel transistors.

9. The memory device of any one of claims 1-6, wherein, the first plurality of bit cells are static random access memory cells.

10. The memory device of any one of claims 1-6, wherein, the first type of transistor is a P-type transistor, and wherein the second type of transistor is an N-type transistor.

11. The memory device of any one of claims 1-6, wherein, the first group of peripheral circuits is aligned with the first group of bit cells in a second direction perpendicular to the first direction, and wherein a width of the first group of peripheral circuits in the first direction is equal to a width of the first group of bit cells in the first direction.

12. A memory device comprising: a group of bit cells comprising a plurality of bit cells; and a group of peripheral circuits, wherein a width of the group of peripheral circuits in a first direction is equal to a width of the group of bit cells in the first direction, wherein the group of peripheral circuits is aligned with the group of bit cells in a second direction perpendicular to the first direction, and wherein the group of peripheral circuits comprises: a plurality of power rails spaced apart from each other in a first direction and extending in a second direction, a plurality of first active regions between a first power rail and a second power rail among the plurality of power rails, wherein the plurality of first active regions are spaced apart from each other in the first direction and extend in the second direction, and include a first transistor and a second transistor having a different type from the first transistor, wherein the first transistor and the second transistor are electrically connected to a first bit cell and a second bit cell among the plurality of bit cells, respectively, a plurality of second active regions between a third power rail and a fourth power rail among the plurality of power rails, wherein the plurality of second active regions are spaced apart from each other in the first direction and extend in the second direction, and include a third transistor and a fourth transistor having a different type from the third transistor, wherein the third transistor and the fourth transistor are electrically connected to a third bit cell and a fourth bit cell among the plurality of bit cells, respectively, and a third active region between the second power rail and the third power rail, wherein the second power rail and the third power rail are adjacent to each other, wherein the third active region is spaced apart from the second power rail and the third power rail by the same distance in the first direction and extends in the second direction, and wherein the third active region includes a fifth transistor.

13. The memory device of claim 12, further comprising: a plurality of fourth active regions between a fifth power rail and a sixth power rail among the plurality of power rails, wherein the plurality of fourth active regions are spaced apart from each other in the first direction and extend in the second direction, and include a sixth transistor and a seventh transistor having a different type from the sixth transistor, wherein the sixth transistor and the seventh transistor are electrically connected to a sixth bit cell and a seventh bit cell among the plurality of bit cells, respectively; a plurality of fifth active regions between a seventh power rail and an eighth power rail among the plurality of power rails, wherein the plurality of fifth active regions are spaced apart from each other in the first direction and extend in the second direction, and include an eighth transistor and a ninth transistor having a different type from the eighth transistor, wherein the eighth transistor and the ninth transistor are electrically connected to an eighth bit cell and a ninth bit cell among the plurality of bit cells, respectively; and a sixth active region between the sixth power rail and the seventh power rail, wherein the sixth power rail and the seventh power rail are adjacent to each other, wherein the sixth active region is spaced apart from the sixth power rail and the seventh power rail by the same distance in the first direction, and wherein the sixth active region includes a tenth transistor.

14. The memory device of claim 12 or 13, wherein, The fifth transistor is configured to receive a power voltage from an external source, and transmit a first power voltage having a same voltage level as the power voltage to at least one of the second power rail and the third power rail.

15. The memory device of claim 14, wherein, The second power rail is configured to apply the first power voltage to the first transistor.

16. The memory device of claim 12 or 13, wherein, The fifth transistor is a P-type transistor.

17. The memory device of claim 12 or 13, wherein, The plurality of bit cells are static random access memory cells.

18. A memory device, comprising: a plurality of bit cells having a first width in a first direction; a plurality of standard cells having a second width different from the first width in the first direction, wherein the plurality of standard cells are electrically connected to the plurality of bit cells by bit lines, wherein the plurality of standard cells include a plurality of active areas, wherein each of the plurality of active areas includes a first type of transistor and a second type of transistor different from the first type of transistor, wherein a height of the plurality of standard cells is determined by a width of a respective active area of the plurality of active areas in the first direction, and wherein the plurality of standard cells are aligned in the first direction; and a non-standardized cell aligned in the first direction with the plurality of standard cells and having a height equal to a difference between a length of the first width and a length of the second width.

19. The memory device of claim 18, wherein, a first standard cell and a second standard cell of the plurality of standard cells have different heights in the first direction.

20. The memory device of claim 18 or 19, wherein, the non-standardized cell is a tap cell or a switch cell including a first active area including one of the first type of transistor and the second type of transistor.

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