Semiconductor package and related manufacturing method

Abstract

A method includes providing a first lead frame panel including a plurality of first lead frames, the first lead frames including a plurality of first die pads plated with a first plating material. The method further includes providing a second lead frame panel separate from the first lead frame panel and including a plurality of second lead frames including a plurality of second die pads plated with a second plating material, the second plating material being different from the first plating material. The method further includes mechanically connecting the first leadframe panel with the second leadframe panel to form a combined leadframe panel. The method further includes mounting a plurality of first semiconductor chips of a first type on the first lead frame panel. The method further includes mounting a plurality of second semiconductor chips of a second type different from the first type on a second lead frame panel.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor packages and related methods of manufacture. BACKGROUND

[0002] Semiconductor packages can include different types of semiconductor chips that can be mounted on one or more package lead frames. The lead frames can take different designs and can be made of different materials. Integrating various semiconductor chips into the same package can be challenging, and in some cases, different lead frame surfaces can be required to properly mount the semiconductor chips. This can require expensive plating techniques, thereby substantially increasing the overall package cost. In view of the foregoing, it can be desirable to provide a simple and cost-effective method to manufacture a superior performing semiconductor package. SUMMARY

[0003] One aspect of the present disclosure relates to a method. The method includes the steps of providing a first lead frame panel including a plurality of first lead frames, wherein the first lead frames include a plurality of first die pads plated with a first plating material. The method also includes the steps of providing a second lead frame panel separate from the first lead frame panel and including a plurality of second lead frames, wherein the second lead frames include a plurality of second die pads plated with a second plating material different from the first plating material. The method also includes the step of mechanically connecting the first lead frame panel with the second lead frame panel to form a combined lead frame panel. The method also includes the step of mounting a plurality of first semiconductor chips of a first type on the first lead frame panel. The method also includes the step of mounting a plurality of second semiconductor chips of a second type different from the first type on the second lead frame panel.

[0004] Another aspect of the present disclosure relates to a semiconductor package. The semiconductor package includes a first lead frame including a first die pad plated with a first plating material and a second lead frame including a second die pad plated with a second plating material different from the first plating material. The semiconductor package also includes a first semiconductor chip of a first type mounted on the first lead frame and a second semiconductor chip of a second type different from the first type mounted on the second lead frame. BRIEF DESCRIPTION OF DRAWINGS

[0005] The methods and devices according to the present disclosure are described in more detail below based on the drawings. The elements in the figures are not necessarily drawn to scale relative to each other. Like reference numerals can denote corresponding similar parts. Technical features of the various illustrated examples can be combined unless they are mutually exclusive, and / or can be selectively omitted if not described as essential.

[0006] Figure 1 A flowchart of a method according to the present disclosure is shown.

[0007] Figures 2A to 2H A method according to the present disclosure is shown schematically.

[0008] Figures 3A to 3C A leadframe panel that can be used in a method according to the present disclosure is shown schematically.

[0009] Figure 4 A side cross-sectional view of a semiconductor package 400 according to the present disclosure is shown schematically. DETAILED DESCRIPTION

[0010] In the following detailed description, reference is made to the accompanying drawings, which illustrate exemplary aspects of the present disclosure by way of illustration. In this regard, directional terminology, such as "top," "bottom," "front," "back," etc., can be used with reference to the orientation of the described drawings. Because components of the described devices can be positioned in a number of different orientations, the directional terminology can be used for purposes of explanation without limiting the concepts of the present disclosure. Other aspects can be utilized and structural or logical changes can be made without departing from the concepts of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the concepts of the present disclosure are defined by the appended claims.

[0011] Reference is now made to Figure 1 , a flowchart of a method according to the present disclosure is shown. The method is described in general terms in order to qualitatively illustrate various aspects of the present disclosure. The method can be used to manufacture a semiconductor package according to the present disclosure, such as the semiconductor package 400 described later Figure 4 . It should be appreciated that the method can include other aspects. For example, the method can be extended by any aspect described in connection with the method of Figures 2A to 2H or any other example described herein.

[0012] In step 2, a first leadframe panel comprising a plurality of first leadframes can be provided. The first leadframes can comprise a plurality of first die pads plated with a first plating material. In step 4, a second leadframe panel separate from the first leadframe panel and comprising a plurality of second leadframes can be provided. The second leadframes can comprise a plurality of second die pads plated with a second plating material, which is different from the first plating material. In step 6, the first leadframe panel can be mechanically connected with the second leadframe panel to form a combined leadframe panel. In step 8, a plurality of first semiconductor chips of a first type can be mounted on the first leadframe panel. In step 10, a plurality of second semiconductor chips of a second type, which is different from the first type, can be mounted on the second leadframe panel.

[0013] It should be noted that the above steps do not necessarily have to be performed in the given order, but their order can at least partially be exchanged if technically feasible. As one example, the steps 8 of mounting the first semiconductor chips on the first leadframe panel and 10 of mounting the second semiconductor chips on the second leadframe panel can be performed before or after the step 6 of mechanically connecting the first leadframe panel with the second leadframe panel to form a combined leadframe panel.

[0014] Reference is now made to Figures 2A to 2H , which describes a further method according to the present disclosure. Figures 2A to 2H The method of Figure 1 may at least partially be seen as a more detailed version of the previously described method of Figures 2A to 2H For example, the method of Figure 4 may be used for manufacturing the semiconductor package 400 of

[0015] In Figure 2A , a first leadframe panel 12A comprising a plurality of individual first leadframes 14A can be provided. For example, the step of Figure 2A may correspond to the step 2 of Figure 1 The first leadframes 14A can comprise a plurality of first die pads 16A. In the shown example, the first leadframe panel 12A can comprise a first peripheral frame 18A, wherein a plurality of rows of first die pads 16A can be connected to opposite sides of the first peripheral frame 18A and spaced apart by a first gap 20A. For example, each row of first die pads 16A can extend along a y-direction. The number of first die pads 16A in each individual leadframe 14A can depend on the type of semiconductor package to be manufactured. In the shown case, each individual leadframe 14A can comprise a single first die pad 16A. However, in other cases, the individual leadframes 14A can comprise two or even more first die pads 16A.

[0016] It is noted that, Figures 2A to 2H The method of the first leadframe panel 12A can correspond to batch processing, wherein a plurality of leadframes and semiconductor chips can be processed in a single batch, rather than processing each leadframe and semiconductor chip individually. Thus, the first leadframe panel 12A can comprise a large number of individual leadframes 14A, e.g. tens to hundreds. In a non-limiting and purely exemplary example, the first leadframe panel 12A can have 25 rows, with 5 individual first leadframes 14A per row, i.e. a total of 125 individual first leadframes 14A.

[0017] The first die pad 16A can be plated with a first plating material, which can depend on the type of semiconductor chip to be mounted on the first die pad 16A and / or the material of the electrical connection element to be connected to the first die pad 16A, for example. The electrical connection element can comprise or can correspond to at least one of a wire, a ribbon, a clip, etc., for example. For the sake of simplicity, the present specification can refer to a wire as the electrical connection element in particular. However, it is to be understood that the wire described herein in connection with the particular examples can be replaced by a different type of electrical connection element, e.g. a ribbon, a clip, etc. In other words, the examples described herein are not limited to electrical connection elements in the form of a wire. The first plating material can comprise or can correspond to at least one of Ni, NiP, NiNiP, Cu or Ag, for example. In one case, the first die pad 16A can be completely plated with the first plating material. In other cases, only a portion of the respective first die pad 16A can be plated with the first plating material, while another portion of the die pad can remain un-plated.

[0018] The first leadframe 14A can further comprise a plurality of first leads (or pins or lead fingers) 22A, which can be mechanically and / or electrically connected to the associated first die pad 16A or not. The number of first leads 22A in each individual first leadframe 14A can depend on the type of semiconductor package to be manufactured. In the illustrated case, each individual first leadframe 14A can comprise a plurality of first leads 22A arranged to the right of the respective first die pad 16A. However, in other cases, the number and arrangement of first leads 22A for an individual first leadframe 14A can be different.

[0019] The first leads 22A can be plated with a third plating material (note that the second plating material will be described later in connection with the second leadframe 14B). The third plating material can depend on the type of electrical connection element to be connected to the first leads 22A, for example. The third plating material can comprise or can correspond to at least one of Au, Ag, Cu, Ni, NiP, NiNiP, etc., for example. In one case, the first leads 22A can be completely plated with the third plating material. In other cases, only a portion of the first leads 22A can be plated with the third plating material, while another portion of the first leads 22A can remain un-plated. Figure 2BA third plating material can be deposited on the first lead 22A, for example, depending on the material of the wire that can be connected to the first lead 22A. For example, the third plating material can comprise or correspond to at least one of Ni, NiP, NiNiP, Cu, or Ag. In one example, the third plating material on the first lead 22A can be different from the first plating material on the first die pad 16A. In another example, the first plating material and the third plating material can be the same.

[0020] The first leadframe panel 12A can comprise a core on which the first plating material of the first die pad 16A and / or the third plating material of the first lead 22A can have been deposited. The core of the first leadframe panel 12A can comprise a first core material. For example, the first core material can comprise or can be made of Cu or a Cu alloy.

[0021] In Figure 2B , a second leadframe panel 12B comprising a plurality of individual second leadframes 14B can be provided. For example, Figure 2B The steps of Figure 1 correspond to step 4 of the method of. The second leadframe 14B can comprise a plurality of second die pads 16B. In the shown example, the second leadframe panel 12B can comprise a second peripheral frame 18B, wherein a plurality of rows of second die pads 16B can be connected to opposite sides of the second peripheral frame 18B and be spaced apart by a second gap 20B. For example, each row of second die pads 16B can extend along the y-direction. The number of second die pads 16B in each individual second leadframe 14B can depend on the type of semiconductor package to be manufactured. In the shown case, each individual second leadframe 14B can comprise two second die pads 16B. However, in other cases, the individual second leadframes 14B can comprise only one or even more than two second die pads 16B.

[0022] The second die pads 16B can be plated with a second plating material, which can depend, for example, on the type of semiconductor chip to be mounted on the second die pads 16B and / or the material of the wire to be connected to the second die pads 16B. For example, the second plating material can comprise at least one of Cu or Ag. Additionally or alternatively, the second leadframe 14B can be a pre-plated frame (PPF) or a micro pre-plated frame (mPPF). In one case, the second die pads 16B can be completely plated with the second plating material. In other cases, only a portion of the respective second die pad 16B can be plated with the second plating material, while another portion of the die pad can remain un-plated.

[0023] The second leadframe 14B can further include a plurality of second leads 22B, which can be mechanically and / or electrically connected to the associated second die pads 16B or not. The number of second leads 22B in each individual second leadframe 14B can depend on the type of semiconductor package to be manufactured. In the illustrated case, each individual second leadframe 14B can include a plurality of second leads 22B arranged to the left of the respective second die pad 16B. However, in other cases, the number and arrangement of second leads 22B for an individual second leadframe 14B can be different.

[0024] The second leads 22B can be plated with a fourth plating material, which can depend on the material of the wires that can be connected to the second leads 22B, for example. For example, the fourth plating material can include or can correspond to at least one of Cu or Ag. In one example, the fourth plating material on the second leads 22B can be different from the second plating material on the second die pads 16B. In another example, the fourth plating material and the second plating material can be the same.

[0025] The second leadframe panel 12B can include a core, on which the second plating material of the second die pads 16B and / or the fourth plating material of the second leads 22B can have been deposited. The core of the second leadframe panel 12B can include a second core material. In particular, the second core material of the second leadframe panel 12B can be different from the first core material of the first leadframe panel 12A. For example, the second core material can include or can be made of Al or an Al alloy.

[0026] In Figure 2C , a plurality of first semiconductor chips 24A of a first type can be mounted on the first leadframe panel 12A. For example, Figure 2C , the steps of Figure 1 Step 8 of the method of FIG. 1. In the illustrated example, the first semiconductor chips 24A can be mounted on the first die pads 16A. However, in other examples, the first semiconductor chips 24A can be at least partially mounted on the first leads 22A. In the illustrated, non-limiting case, a single first semiconductor chip 24A can be mounted on each first die pad 16A. However, it is to be understood that the number and arrangement of second semiconductor chips 24B can depend on the type of semiconductor package to be manufactured and can be different in other examples.

[0027] Typically, the semiconductor chips described herein can be made of elemental semiconductor materials (e.g., Si) or of wide bandgap semiconductor materials or compound semiconductor materials (e.g., SiC, GaN, SiGe, GaAs). The semiconductor chip can be of any type and can include an integrated circuit with active electronic components and / or passive electronic components. The integrated circuit can be designed as a logic integrated circuit, an analog integrated circuit, a mixed-signal integrated circuit, a power integrated circuit, a memory circuit, an integrated passive device, etc. Please note that throughout this specification, the terms "chip," "semiconductor chip," "bare die," and "semiconductor bare die" can be used interchangeably.

[0028] In particular, the first semiconductor chip 24A can be a power semiconductor chip. In this context, the term "power semiconductor chip" can refer to a semiconductor chip that provides at least one of a high voltage blocking capability or a high current carrying capability. The power semiconductor chip can be configured to be used for a high current with a maximum current value of several amperes (e.g., 10A) or a maximum current value of up to or exceeding 100A. Similarly, the voltage associated with such a current value can have a value of several volts to tens of volts or hundreds of volts or even several thousand volts, for example, about 1200V, about 1600V, about 2400V, etc. The power semiconductor chip can be used for any type of power application, such as a MOSFET (metal oxide semiconductor field effect transistor), a half-bridge circuit, a power module including a gate driver, etc. For example, the power chip can include a power device or can be a part of a power device, such as a power MOSFET, a LV (low voltage) power MOSFET, a power IGBT (insulated gate bipolar transistor), a power diode, a super junction power MOSFET, etc.

[0029] The first semiconductor chip 24A can be mounted on the first lead frame panel 12A based on a process or technology specifically configured for mounting power semiconductor chips to a lead frame or a die pad. For example, the first semiconductor chip 24A can be mounted on the first lead frame panel 12A based on at least one of a diffusion soldering process, a soft soldering process, a preform soldering process, a sintering process, or a solder paste process.

[0030] After the first semiconductor chip 24A has been mounted on the first lead frame panel 12A, Figure 2C Further steps are performed in the context of FIG. 1 , which are not explicitly shown for simplicity. For example, the first semiconductor chip 24A can be electrically coupled to the first leadframe panel 12A via a first electrical connection element. More specifically, the first semiconductor chip 24A can be electrically coupled to at least one of the first die pad 16A or the first lead 22A. For example, the first electrical connection element can include or correspond to a first wire comprising a first wire material.

[0031] The properties of the first wires and the employed wire bonding process can be specifically adapted to the type of the first semiconductor chips 24A and to the properties of the first and third plating materials that can be arranged on the first die pads 16A and the first leads 22A, respectively. For example, the first wire material can comprise Al or an Al alloy. The electrical coupling of the first semiconductor chips 24A to the first lead frame panel 12A via the first wires can be based on a wedge bonding process.

[0032] In Figure 2D , a plurality of second semiconductor chips 24B of a second type different from the first type can be mounted on the second lead frame panel 12B. For example, Figure 2D the steps can correspond to Figure 1 step 10 of the method 10. In the illustrated example, the second semiconductor chips 24B can be mounted on the second die pads 16B. However, in other examples, the second semiconductor chips 24B can be at least partially mounted on the second leads 22B. In the illustrated non-limiting case, a single second semiconductor chip 24B can be mounted on each of the second die pads 16B. However, it is to be understood that the number and arrangement of the second semiconductor chips 24B can depend on the type of semiconductor package to be manufactured and can differ in other examples.

[0033] In particular, the second semiconductor chips 24B can be at least one of a logic semiconductor chip or a driver semiconductor chip. For example, the logic semiconductor chip or the driver semiconductor chip can be configured to drive and / or control one or more power semiconductor chips, e.g., via a gate terminal of a power transistor chip. Thus, some logic semiconductor chips can be referred to as driver semiconductor chips (or drivers) or control semiconductor chips (or controllers). In particular, in the manufactured semiconductor package, the logic or driver semiconductor chips 24B can be configured to control or drive one or more power semiconductor chips 24A.

[0034] The second semiconductor chips 24B can be mounted on the second lead frame panel 12B based on a process or technique specifically configured for mounting logic or driver semiconductor chips to lead frames or die pads. For example, the second semiconductor chips 24B can be mounted on the second lead frame panel 12B based on at least one of a die bonding process, a die attach film process, or a sintering process. In particular, since the first semiconductor chips 24A and the second semiconductor chips 24B can be of different types, the mounting of the first semiconductor chips 24A on the first lead frame panel 12A and the mounting of the second semiconductor chips 24B on the second lead frame panel 12B can be based on different processes.

[0035] After the second semiconductor chip 24B has been mounted on the second leadframe panel 12B, further steps can be performed in the context of Figure 2D For the sake of simplicity, these steps are not explicitly shown. For example, the second semiconductor chip 24B can be electrically coupled to the second leadframe panel 12B via second electrical connection elements. More particularly, the second semiconductor chip 24B can be electrically coupled to at least one of the second die pads 16B or the second leads 22B. For example, the second electrical connection elements can comprise or can correspond to second wires comprising a second wire material being different from the first wire material of the first wires.

[0036] The properties of the second wires and the employed wire bonding process can be particularly adapted to the type of the second semiconductor chip 24B and to the properties of the second plating material and the fourth plating material which can be arranged on the second die pads 16B and the second leads 22B, respectively. For example, the second wire material can comprise Cu or a Cu alloy. Further, electrically coupling the second semiconductor chip 24B to the second leadframe panel 12B via the second wires can be based on a ball bonding process. In particular, since the first semiconductor chip 24A and the second semiconductor chip 24B can be of different types, electrically coupling the first semiconductor chip 24A to the first leadframe panel 12A via the first wires and electrically coupling the second semiconductor chip 24B to the second leadframe panel 12B via the second wires can be based on different processes.

[0037] In Figure 2E The first leadframe panel 12A and the second leadframe panel 12B can be mechanically connected to form a combined leadframe panel 26. For example, Figure 2E The steps of Figure 1 may correspond to step 6 of Figure 2E Any suitable process or technique can be used to connect the leadframe panels 12A and 12B. For example, mechanically connecting the first leadframe panel 12A and the second leadframe panel 12B to form the combined leadframe panel 26 can comprise at least one of clamping, gluing or soldering. From the example of Figure 2E It can be seen that in the combined leadframe panel 26, the rows of the first die pads 16A of the first leadframe panel 12A can be arranged at the second gaps 20B of the second leadframe panel 12B, while the rows of the second die pads 16B of the second leadframe panel 12B can be arranged at the first gaps 20A of the first leadframe panel 12A.

[0038] In one embodiment, first lead frame panel 12A and second lead frame panel 12B may be aligned with each other such that first peripheral frame 18A and second peripheral frame 18B overlap when viewed in the z-direction. After alignment, first peripheral frame 18A and second peripheral frame 18B may be attached to each other based on at least one of clamping, gluing, or welding. In other words, the mechanical connection between first lead frame panel 12A and second lead frame panel 12B may only include the mechanical connection between first peripheral frame 18A and second peripheral frame 18B, and first individual lead frame 14A of first lead frame panel 12A may not necessarily be connected to second individual lead frame 14B of second lead frame panel 12B.

[0039] exist Figures 2A to 2H In the example, Figure 2C The first semiconductor chip 24A is mounted on the first lead frame panel 12A as shown and Figure 2D The illustrated mounting of the second semiconductor chip 24B on the second lead frame panel 12B can be performed before mechanically connecting the first lead frame panel 12A to the second lead frame panel 12B to form the combined lead frame panel 26. In this case, the mounting of the first semiconductor chip 24A and the second semiconductor chip 24B can be performed separately in different production lines. However, it should be understood that in other examples, the first lead frame panel 12A and the second lead frame panel 12B can be connected to form the combined lead frame panel 26 first, and then the first semiconductor chip 24A and the second semiconductor chip 24B can be mounted at corresponding positions on the combined lead frame panel 26.

[0040] In a similar manner, electrically coupling the first semiconductor chip 24A to the first leadframe panel 12A via the first wire and electrically coupling the second semiconductor chip 24B to the second leadframe panel 12B via the second wire can be performed before mechanically connecting the first leadframe panel 12A and the second leadframe panel 12B to form the combined leadframe panel 26. In this case, electrically coupling the semiconductor chips 24A and 24B to the leadframe panels 12A and 12B can be performed separately in different production lines. However, it should be understood that in other examples, the first leadframe panel 12A and the second leadframe panel 12B can be connected to form the combined leadframe panel 26 first, and then the first semiconductor chip 24A and the second semiconductor chip 24B can be electrically coupled to corresponding locations on the combined leadframe panel 26 via corresponding wires.

[0041] exist Figure 2EIn another optional step, at least one of the first semiconductor chips 24A can be electrically coupled to at least one of the second semiconductor chips 24B via one or more electrical connection elements, such as, for example, at least one of a wire, a ribbon, a clip, etc. In this context, at least one of a wire connection process, a clip attachment, etc. can be performed. In particular, an electrical coupling can be provided between the first semiconductor chip 24A and the second semiconductor chip 24B to be included in the same semiconductor package to be manufactured. Figure 4 One example for such a semiconductor package and electrical connections between a first semiconductor chip 24A and a second semiconductor chip 24B are shown and discussed.

[0042] Figure 2F Shows that when viewed in the y direction Figure 2E 2. The combined lead frame panel 26 includes two lead frame panels 12A and 12B. In the example shown, the two lead frame panels 12A and 12B can have different thicknesses, particularly when measured in the z-direction. In particular, the first thickness of the first lead frame panel 12A can be greater than the second thickness of the second lead frame panel 12B. If the first semiconductor chip 24A is a power semiconductor chip, the greater first thickness of the first lead frame panel 12A can increase heat dissipation and allow for high current transmission. If the second semiconductor chip 24B corresponds to a logic and / or driver semiconductor chip, the smaller second thickness of the second lead frame panel 12B can provide for more refined signal routing.

[0043] Figure 2G It shows that when viewed in the x-direction, Figure 2E A side cross-sectional view of the combined lead frame panel 26 relative to section AA'. Figure 2F and Figure 2G As can be seen from the example of , the first lead frame panel 12A and the second lead frame panel 12B (particularly the first die pad 16A and the second die pad 16B) can be arranged at different heights relative to the z-direction in the combined lead frame panel 26 (the first lead frame panel 12A can be arranged below the second lead frame panel 12B). Figure 2G It can be further seen that due to the different heights of the lead frame panels 12A and 12B, a free or vacant area or space 28 can be provided below the second die pad 16B of the first lead frame panel 12B, the function of which will be described later.

[0044] exist Figure 2H In the embodiment of the present invention, an encapsulation process may be performed, wherein the first semiconductor chip 24A, the second semiconductor chip 24B, and the combined lead frame panel 26 may be at least partially encapsulated in an encapsulation material 30. For example, Figure 1 The method can be achieved through Figure 2HThe encapsulation material 30 may include or be made of at least one of the following materials: epoxy, filled epoxy, glass-filled epoxy, imide, thermoplastic, thermosetting polymer, polymer blend, laminate, molding compound, etc. Various techniques may be used to encapsulate the component in the encapsulation material 30, such as at least one of compression molding, injection molding, powder molding, liquid molding, mirror molding, lamination, etc.

[0045] In the example shown, a plurality of strips (or bands) of encapsulation material 30 can be formed, wherein each strip can encapsulate a row of first die pads 16A and an adjacent row of second die pads 16B. In the illustrated case, the strips of encapsulation material 30 can extend along the y-direction between the peripheral frames 18A and 18B. The peripheral frames 18A and 18B can remain uncovered by the encapsulation material 30.

[0046] Back to Figure 2G As shown in the side view of FIG, after the encapsulation process is performed, the bottom main surface of the first leadframe panel 12A (opposite to the upper main surface on which the first semiconductor chip 24A can be mounted) can remain uncovered by the encapsulation material 30. In contrast, the bottom main surface of the second leadframe panel 12B (opposite to the upper main surface on which the second semiconductor chip 24B can be mounted) can be covered by the encapsulation material 30. In other words, the previously vacant area 28 can be filled with the encapsulation material 30. As a result, the second leadframe panel 12B can be electrically isolated by the dielectric encapsulation material 30. In this way, a defined isolation thickness can be provided for the covered second leadframe 14B and the second semiconductor chip 24B arranged on the second leadframe 14B by selecting a corresponding thickness of the first leadframe panel 12A.

[0047] It should be understood that Figures 2A to 2H The method may include other steps that are not explicitly described for the sake of simplicity. In an exemplary further step, the semiconductor chips 24A, 24B embedded in the encapsulation material 30 and the combined lead frame panel 26 may be singulated into a plurality of semiconductor packages. In this context, as Figure 2H The strips of encapsulation material 30 shown can be separated from each other by cutting or dicing the arrangement along the y-direction between the strips. In addition, each separate strip of encapsulation material 30 can be separated into multiple semiconductor packages by cutting or dicing the corresponding strip along the x-direction.

[0048] For example, singulated semiconductor packages can include separate first lead frames 14A including first die pads 16A plated with a first plating material and separate second lead frames 14B including second die pads 16B plated with a second plating material. First semiconductor chips 24A of a first type can be mounted on the first lead frames 14A and second semiconductor chips 24B of a second type can be mounted on the second lead frames 14B. Note that later examples will be described in connection with Figure 4 more detailed examples of semiconductor packages 400 (which can be manufactured by the methods of Figure 1 and Figures 2A to 2H ) according to the present disclosure are shown and described.

[0049] Figure 1 and Figures 2A to 2H The methods of Figures 3A to 3C The methods of Figures 3A to 3C The lead frame panels of Figures 2A to 2H may include some or all of the features of the lead frame panels of

[0050] Figure 3A The first lead frame panel 12A shown in

[0051] As described in Figure 3BThe illustrated second leadframe panel 12B can include only one type of individual second leadframes 14B. The individual second leadframes 14B can include a plurality of second die pads 16B which can be arranged in rows that connect to opposite sides of a second peripheral frame 18B. In the illustrated example, the individual second leadframes 14B do not necessarily include leads. The rows of second die pads 16B can be spaced apart by a second gap 20B. Similar to the previous example, the second die pads 16B can be plated with a second plating material that is different than the first plating material.

[0052] Figure 3C A combined leadframe panel 26 is shown that can be formed by mechanically connecting Figure 3A and 3B the first leadframe panel 12A and the second leadframe panel 12B. In the combined leadframe panel 26, the rows of second die pads 16B of the second leadframe panel 12B can be arranged at the first gap 20A of the first leadframe panel 12A. Similar to the example of Figures 2A to 2H , semiconductor chips can be mounted to the leadframe panels 12A and 12B and electrically coupled to the individual leadframes as previously discussed in connection with Figure 2C and 2D . In a further step, the semiconductor chips and the combined leadframe panel 26 can be encapsulated and singulated to obtain a plurality of semiconductor packages. In this context, the singulation process can for example include cutting or scribing along the second gap 20A' as illustrated by the dashed line in Figure 3C . For example, the singulated semiconductor packages can include one first type of first die pads 16A, one second type of first die pads 16A' and one second die pad 16B.

[0053] In one more specific and non-limiting example, Figure 3CThe leadframe panel 26 of the combination of FIG. 1 can be used to manufacture semiconductor packages comprising three semiconductor chips, which can be electrically interconnected to form a half-bridge circuit. Here, each manufactured semiconductor package can comprise a first power semiconductor chip and a second power semiconductor chip, e.g., which can correspond to a low-side switch and a high-side switch of a half-bridge circuit, respectively. The two power semiconductor chips can be mounted on the first die pads 16A and 16A’ obtained from the first leadframe panel 12A. Further, the manufactured semiconductor package can comprise a logic semiconductor chip, which can be configured to control and / or drive at least one of the first power semiconductor chip and the second power semiconductor chip. The logic semiconductor chip can be mounted on the second die pad 16B obtained from the second leadframe panel 12B. In particular, the logic semiconductor chip can comprise a driver circuit configured to drive the high-side switch and the low-side switch of the half-bridge circuit.

[0054] Reference is now made to Figure 4 , which schematically illustrates a side cross-sectional view of a semiconductor package 400 according to the present disclosure. For example, the semiconductor package 400 can be manufactured based on one of the previously described methods according to the present disclosure. Thus, the comments made in connection with any one of Figures 1 to 3A to Figure 3C also apply to the example of Figure 4 .

[0055] The semiconductor package 400 can comprise a first leadframe 14A comprising first die pads 16A, which can be (in particular completely) plated with a first plating material 32A. For example, the first leadframe 14A (or more particularly the core of the first leadframe 14A) can comprise or be made of Cu or a Cu alloy, and the first plating material 32A can comprise or be made of NiNiP or Ni. Further, the semiconductor package 400 can comprise a second leadframe 14B comprising second die pads 16B, which can be (in particular completely) plated with a second plating material 32B different from the first plating material 32A. For example, the second leadframe 14B (or more particularly the core of the second leadframe 14B) can comprise or be made of Cu or a Cu alloy, and the second plating material 32B can comprise or be made of Ag or Cu. In the illustrated example, for the sake of simplicity, possible leads of the leadframes 14A and 14B are not shown.

[0056] A first semiconductor die 24A of a first type can be mounted on the first leadframe 14A (or more particularly on the first die pad 16A). Further, a second semiconductor die 24B of a second type different from the first type can be mounted on the second leadframe 14B (or more particularly on the second die pad 16B). The first semiconductor die 24A can include a backside metallization 34 and can be mounted on the first leadframe 14A via the backside metallization 34. The backside metallization 34 can be composed of a metal stack including different metals configured to enable proper electrical and / or mechanical contact between the first leadframe 14A and the first semiconductor die 24A. For example, the backside metallization 34 can include or can correspond to at least one of a multi-layer backside metallization, a copper backside metallization, a silver backside metallization, etc.

[0057] In a similar manner, the second semiconductor die 24B can be mounted on the second leadframe 14B via a backside portion or material 36 thereof. In one example, the backside material 36 of the second semiconductor die 24B can include or can correspond to a non-metallic material such as bare silicon, silicon oxide, etc. In the illustrated example, the backside material 36 can be attached to the second leadframe plating 32B via a die attach material 38 such as an adhesive. In another example, the backside material 36 can include or can correspond to a backside metallization similar to the backside metallization 34 of the first semiconductor die 24A.

[0058] The first semiconductor die 24A can include at least one first contact pad 42A which can be arranged on a top surface of the first semiconductor die 24A. For example, the first contact pad 42A can include or can be made of Al(Si)Cu. In a similar manner, the second semiconductor die 24B can include at least one second contact pad 42B which can be arranged on a top surface of the second semiconductor die 24B. For example, the second contact pad 42B can include or can be made of at least one of PdAu or Cu.

[0059] The semiconductor package 400 can comprise at least one first electrical connection element 40A electrically coupling the first semiconductor chip 24A with the first leadframe 14A. In the illustrated example, the first electrical connection element 40A can comprise or can correspond to a first wire 40A comprising a first wire material. In other examples, the first wire 40A can be replaced by another type of electrical connection element, such as a ribbon, a clip, etc., depending on the application under consideration. In particular, the first wire 40A can be in direct contact with the first contact pad 42A and with the first plated material 32A of the first die pad 16A. Alternatively or additionally, the first wire 40A can be in direct contact with the first contact pad 42A and with a third plated material of a first lead (not shown) of the first leadframe 14A.

[0060] Furthermore, the semiconductor package 400 can comprise at least one second electrical connection element 40B. In the illustrated example, the second electrical connection element 40B can comprise or can correspond to a second wire 40B comprising a second wire material different from the first wire material. In other examples, the second wire 40B can be replaced by another type of electrical connection element, such as a ribbon, a clip, etc., depending on the application under consideration. For example, the second wire 40B can electrically couple the second semiconductor chip 24B with the second leadframe 14B. In particular, the second wire 40B can be in direct contact with the second contact pad 42B and with the second plated material 32B of the second die pad 16B. Alternatively or additionally, the second wire 40B can be in direct contact with the second contact pad 42B and with a fourth plated material of a second lead (not shown) of the second leadframe 14B. Furthermore, the second wire 40B can electrically couple the second semiconductor chip 24B with the first semiconductor chip 24A. In particular, the second wire 40B can be in direct contact with the second contact pad 42B of the second semiconductor chip 24B and with the first contact pad 42A of the first semiconductor chip 24A. It is to be noted that in other examples, one or more wires 40B can be replaced by another type of electrical connection element, such as a ribbon, a clip, etc., depending on the application under consideration.

[0061] It is to be understood that the components of the semiconductor package 400 can be made of different materials and can be processed based on various technologies. In this context, four exemplary scenarios are listed below. In each scenario, the first semiconductor chip 24A can be a power semiconductor chip, while the second semiconductor chip 24B can be a driver or logic semiconductor chip.

[0062] In a first scenario, the first semiconductor chip 24A can be attached to the first leadframe 14A (or the first die pad 16A) via its backside metallization 34 based on a diffusion soldering process. The first lead 40A can be made of Al and can be connected based on a wedge-wedge connection process. The first leadframe plating 32A can be NiP or Ni located on the die pad 16A and on the lead connection area. The second semiconductor chip 24B can be attached to the second leadframe 14B (or the second die pad 16B) via its silicon backside 36 using Ag paste. The second lead 40B can be made of Cu or Au and can be connected based on a ball soldering process. In case of Au ball soldering, the second leadframe plating 32B can be Ag or the second leadframe 14B can be a micro pre-plated frame (μPPF). In case of Cu ball soldering, the second leadframe plating 32B can be Cu or Ag or the second leadframe 14B can be a micro pre-plated frame (μPPF).

[0063] In a second scenario, the first semiconductor chip 24A can be attached to the first leadframe 14A (or the first die pad 16A) via its backside metallization 34 based on a diffusion soldering process. The first lead 40A can be made of Cu and can be connected based on a wedge-wedge connection process. The first leadframe plating 32A can be NiP or Ni located on the die pad 16A and Cu located on the lead connection area. The second semiconductor chip 24B can be attached to the second leadframe 14B (or the second die pad 16B) via its silicon backside 36 using Ag paste. The second lead 40B can be made of Cu or Au and can be connected based on a ball soldering process. In case of Au ball soldering, the second leadframe plating 32B can be made of Ag or the second leadframe 14B can be a micro pre-plated frame (μPPF). In case of Cu ball soldering, the second leadframe plating 32B can be made of Cu or Ag or the second leadframe 14B can be a micro pre-plated frame (μPPF).

[0064] In a third scenario, the first semiconductor chip 24A can be attached to the first leadframe 14A (or the first die pad 16A) via the 4-layer backside metallization 34 based on a solder paste process. The first lead 40A can be made of Al and can be connected based on a wedge-wedge connection process. The first leadframe plating 32A can be bare Cu or Ag on the die pad 16A and NiP or Ni on the lead connection area. The second semiconductor chip 24B can be attached to the second leadframe 14B (or the second die pad 16B) via its silicon backside 36 using an Ag paste. The second lead 40B can be made of Cu or Au and can be connected based on a ball bonding process. In case of Au ball bonding, the second leadframe plating 32B can be made of Ag or the second leadframe 14B can be a micro pre-plated frame (μPPF). In case of Cu ball bonding, the second leadframe plating 32B can be made of Cu or Ag or the second leadframe 14B can be a micro pre-plated frame (μPPF).

[0065] In a fourth scenario, the first semiconductor chip 24A can be attached to the first leadframe 14A (or the first die pad 16A) via the 4-layer backside metallization 34 based on a solder paste process. The first lead 40A can be made of Cu and can be connected based on a wedge-wedge connection process. The first leadframe plating 32A can be Cu or Ag on the die pad 16A and the lead connection area. The second semiconductor chip 24B can be attached to the second leadframe 14B (or the second die pad 16B) via its silicon backside 36 using an Ag paste. The second lead 40B can be made of Cu or Au and can be connected based on a ball bonding process. In case of Au ball bonding, the second leadframe plating 32B can be made of Ag or the second leadframe 14B can be a micro pre-plated frame (μPPF). In case of Cu ball bonding, the second leadframe plating 32B can be made of Cu or Ag or the second leadframe 14B can be a micro pre-plated frame (μPPF).

[0066] The concepts according to the present disclosure described herein can be advantageous over conventional concepts in different ways as described below. In this regard, the following comments are not to be seen as conclusive.

[0067] The concepts described herein can provide for using leadframes with different thicknesses in the same semiconductor package. In particular, no costly processes such as selective etching are required in this regard. The possibility of a semiconductor package with thick leadframes for power semiconductor chips and thin leadframes for logic or driver semiconductor chips can be beneficial for implementing SIPs (systems in package). In this regard, thick leadframes can provide for heat dissipation as well as proper transmission of high currents, while thin leadframes can provide for fine signal routing.

[0068] The concepts described herein can provide semiconductor packages including exposed die pads and non-exposed die pads having a certain isolation thickness. In this regard, complex and costly isolation concepts (e.g., TIM sheets, foils) are not necessarily required.

[0069] The concepts described herein can provide cost-effective approaches to use different lead frames and different plating materials in the same semiconductor package. For example, a first lead frame can be a copper lead frame having a first plating material, while a second lead frame can be an aluminum lead frame having a second plating material different from the first plating material.

[0070] The concepts described herein can enable cost-effective integration of various semiconductor chips using lead frames having different plating materials into the same package. In particular, each of the included lead frames can be made as a fully plated lead frame, thus eliminating the need for partial plating. The proposed concepts do not necessarily require expensive plating techniques (e.g., partial plating) that can substantially increase the overall package cost.

[0071] Example

[0072] In the following, methods and semiconductor packages according to the present disclosure are described by way of example.

[0073] Example 1 is a method comprising: providing a first lead frame panel comprising a plurality of first lead frames, wherein the first lead frames comprise a plurality of first die pads plated with a first plating material; providing a second lead frame panel separate from the first lead frame panel and comprising a plurality of second lead frames, wherein the second lead frames comprise a plurality of second die pads plated with a second plating material different from the first plating material; mechanically connecting the first lead frame panel and the second lead frame panel to form a combined lead frame panel; mounting a plurality of first semiconductor chips of a first type on the first lead frame panel; and mounting a plurality of second semiconductor chips of a second type different from the first type on the second lead frame panel.

[0074] Example 2 is the method according to example 1, wherein: the first lead frames further comprise a plurality of first leads plated with a third plating material, and / or the second lead frames further comprise a plurality of second leads plated with a fourth plating material.

[0075] Example 3 is the method according to example 2, wherein: the third plating material is different from the first plating material, and / or the fourth plating material is different from the second plating material.

[0076] Example 4 is the method according to example 2, wherein: the first plating material is the same as the third plating material, and / or the second plating material is the same as the fourth plating material.

[0077] Example 5 is the method according to one of the preceding examples, wherein: the first die pad is completely plated with the first plating material, and the second die pad is completely plated with the second plating material.

[0078] Example 6 is the method according to one of the preceding examples, wherein: the first plating material comprises at least one of Ni, NiP, NiNiP, Cu, Ag, the second plating material comprises at least one of Cu, Ag, and / or the second leadframe panel is a pre-plated frame (PPF) or a micro pre-plated frame (μPPF).

[0079] Example 7 is the method according to one of the preceding examples, wherein: the first semiconductor chip is a power semiconductor chip, and the second semiconductor chip is at least one of a logic semiconductor chip or a driver semiconductor chip.

[0080] Example 8 is the method according to one of the preceding examples, wherein: the first leadframe panel has a first thickness, and the second leadframe panel has a second thickness that is smaller than the first thickness.

[0081] Example 9 is the method according to one of the preceding examples, wherein: mounting the first semiconductor chip on the first leadframe panel and mounting the second semiconductor chip on the second leadframe panel are based on different processes.

[0082] Example 10 is the method according to one of the preceding examples, wherein: mounting the first semiconductor chip on the first leadframe panel is based on at least one of a diffusion soldering process, a soft soldering process, a pre-form soldering process, a sintering process, or a solder paste process, and mounting the second semiconductor chip on the second leadframe panel is based on at least one of a gluing process, a die attach film process, a soldering process, a soft soldering process, or a sintering process.

[0083] Example 11 is the method according to one of the preceding examples, wherein: mounting the first semiconductor chip on the first leadframe panel and mounting the second semiconductor chip on the second leadframe panel are performed before mechanically connecting the first leadframe panel with the second leadframe panel.

[0084] Example 12 is the method according to one of the preceding examples, wherein: mounting the first semiconductor chip on the first leadframe panel and mounting the second semiconductor chip on the second leadframe panel are performed in different production lines.

[0085] Example 13 is the method of one of the preceding examples, wherein: the first leadframe panel includes a first peripheral frame and a plurality of rows of first die pads, wherein the rows of first die pads are connected to opposite sides of the first peripheral frame and are spaced apart by first gaps; the second leadframe panel includes a second peripheral frame and a plurality of rows of second die pads, wherein the rows of second die pads are connected to opposite sides of the second peripheral frame and are spaced apart by second gaps; in the combined leadframe panel, the rows of first die pads of the first leadframe panel are disposed at the second gaps of the second leadframe panel, and the rows of second die pads of the second leadframe panel are disposed at the first gaps of the first leadframe panel.

[0086] Example 14 is the method of one of the preceding examples, wherein the first die pads and the second die pads are disposed at different heights in the combined leadframe panel.

[0087] Example 15 is the method of one of the preceding examples, further comprising: performing an encapsulation process, wherein the first semiconductor chips, the second semiconductor chips, and the combined leadframe panel are at least partially encapsulated in an encapsulation material, and singulating the encapsulated semiconductor chips and the combined leadframe panel into a plurality of semiconductor packages.

[0088] Example 16 is the method of Example 15, wherein: the singulated semiconductor packages include first leadframes comprising the first die pads plated with a first plating material and second leadframes comprising the second die pads plated with a second plating material; the first semiconductor chips of the first type are mounted on the first leadframes; and the second semiconductor chips of the second type are mounted on the second leadframes.

[0089] Example 17 is the method of Example 15 or 16, wherein: the first semiconductor chips are mounted on a first major surface of the first leadframe panel, the second semiconductor chips are mounted on a second major surface of the second leadframe panel, after performing the encapsulation process, a major surface of the first leadframe panel opposite the first major surface is not covered by the encapsulation material, and a major surface of the second leadframe panel opposite the second major surface is covered by the encapsulation material.

[0090] Example 18 is the method of one of the preceding examples, further comprising: electrically coupling the first semiconductor chips to the first leadframe panel via first electrical connection elements, the first electrical connection elements comprising a first electrical connection element material; and electrically coupling the second semiconductor chips to the second leadframe panel via second electrical connection elements, the second electrical connection elements comprising a second electrical connection element material different from the first electrical connection element material.

[0091] Example 19 is the method of example 18, wherein: the first electrical connection element comprises a first wire, the first wire comprising a first wire material, the second electrical connection element comprises a second wire, the second wire comprising a second wire material.

[0092] Example 20 is the method of example 19, wherein: the first electrical connection element material comprises Al, the second electrical connection element material comprises Cu.

[0093] Example 21 is the method of example 19 or 20, wherein electrically coupling the first semiconductor chip to the first leadframe panel via the first electrical connection element and electrically coupling the second semiconductor chip to the second leadframe panel via the second electrical connection element are based on different processes.

[0094] Example 22 is the method of one of examples 19 to 21, wherein: electrically coupling the first semiconductor chip to the first leadframe panel via the first electrical connection element is based on a wedge bonding process, electrically coupling the second semiconductor chip to the second leadframe panel via the second electrical connection element is based on a ball bonding process.

[0095] Example 23 is the method of one of the preceding examples, wherein mechanically connecting the first leadframe panel with the second leadframe panel to form a combined leadframe panel comprises at least one of clamping, gluing, or soldering.

[0096] Example 24 is the method of one of the preceding examples, wherein: a core of the first leadframe panel comprises a first core material, a core of the second leadframe panel comprises a second core material different from the first core material.

[0097] Example 25 is the method of example 24, wherein: the first core material comprises Cu, the second core material comprises Al.

[0098] Example 26 is a semiconductor package comprising: a first leadframe comprising first die pads plated with a first plating material; a second leadframe comprising second die pads plated with a second plating material, the second plating material being different from the first plating material; a first semiconductor chip of a first type mounted on the first leadframe; and a second semiconductor chip of a second type different from the first type mounted on the second leadframe.

[0099] Example 27 is the semiconductor package of example 26, wherein: the first semiconductor chip comprises a backside metallization and is mounted on the first leadframe via the backside metallization, the second semiconductor chip is mounted on the second leadframe via a backside thereof formed of a non-metallic material.

[0100] Example 28 is the semiconductor package of example 26 or 27, wherein: the first semiconductor chip is a power semiconductor chip, and the second semiconductor chip is at least one of a logic semiconductor chip or a driver semiconductor chip.

[0101] Example 29 is the semiconductor package of one of examples 26 to 28, further comprising: a first electrical connecting element comprising a first electrical connecting element material and electrically coupling the first semiconductor chip with the first leadframe; and a second electrical connecting element comprising a second electrical connecting element material different from the first electrical connecting element material and electrically coupling the second semiconductor chip with the second leadframe.

[0102] Example 30 is the semiconductor package of example 29, wherein: the first electrical connecting element comprises a first wire comprising a first wire material, and the second electrical connecting element comprises a second wire comprising a second wire material.

[0103] Example 31 is the semiconductor package of one of examples 26 to 30, wherein: the first die pad is completely plated with a first plating material, and the second die pad is completely plated with a second plating material.

[0104] As employed in this specification, the terms "connected," "coupled," "electrically connected," and / or "electrically coupled" can not necessarily mean that elements are directly connected or coupled together. Intervening elements can be present.

[0105] Further, the words "on," "over," and the like in reference to a material layer can be used herein to mean that the material layer can be "directly" on (e.g., formed, deposited, etc. on) the surface, e.g., in direct contact with the surface. The words "on," "over," and the like in reference to a material layer can also be used herein to mean that the material layer can be "indirectly" on (e.g., formed, deposited, etc. on) the surface, with one or more additional layers being disposed between the material layer and the surface.

[0106] Further, the terms "have," "comprise," "contain," "hold," or their variants in the context of the specific embodiments or claims herein are used in the sense of open inclusion, that is, in the sense of "including, but not limited to." That is, as used herein, the terms "have," "comprise," "contain," "hold," "including," and the like are open-ended terms that indicate the presence of the stated element or feature, but do not exclude the presence of additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0107] Furthermore, the word “exemplary” is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the word exemplary is intended to present concepts in a concrete manner. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or”. That is, unless specified otherwise, or clear from context, “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then “X employs A or B” is satisfied under any of the foregoing instances. Moreover, articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Additionally, at least one of A and B or like phrases should be construed to mean A or B or both A and B unless otherwise indicated or clear from context to be directed to a singular form.

[0108] Described herein are devices and methods for manufacturing devices. Comments made in connection with a described device can also hold true for a corresponding method, and vice versa. For example, if a device is described as including certain components, a corresponding method can include steps for providing those components, even if such steps are not explicitly described or shown.

[0109] While the present disclosure has been shown and described with reference to one or more implementations, those skilled in the art will understand that other equivalents and modifications in the disclosure can occur based on a reading and understanding of the description of the application and the accompanying drawings. The present disclosure includes all such modifications and equivalents. The disclosure is limited only as described by the following claims and their equivalents. In particular, with respect to the various functions performed by the above described components (e.g., elements, resources, etc.), the terms used to describe those components are intended to correspond, in appropriate context, to any component which performs the function described for that component, such as functional equivalents (i.e., that functionally equivalent), even though other structure can be structurally equivalent in some respects. Furthermore, although particular features of the present disclosure can have been disclosed with respect to only one of multiple implementations, such features can be combined with one or more other features of the other implementations as can be desired and advantageous for any given or particular application.

Claims

1. A method comprising: providing a first leadframe panel (12A) comprising a plurality of first leadframes (14A), wherein the first leadframes (14A) comprise a plurality of first die pads (16A) plated with a first plating material (32A); providing a second leadframe panel (12B) separate from the first leadframe panel (12A) and comprising a plurality of second leadframes (14B), wherein the second leadframes (14B) comprise a plurality of second die pads (16B) plated with a second plating material (32B) different from the first plating material (32A); mechanically connecting the first leadframe panel (12A) with the second leadframe panel (12B) to form a combined leadframe panel (26); mounting a plurality of first semiconductor chips (24A) of a first type on the first leadframe panel (12A); and mounting a plurality of second semiconductor chips (24B) of a second type different from the first type on the second leadframe panel (12B).

2. The method according to claim 1, wherein: the first leadframes (14A) further comprise a plurality of first leads (22A) plated with a third plating material, and / or the second leadframes (14B) further comprise a plurality of second leads (22B) plated with a fourth plating material.

3. The method according to claim 2, wherein: the third plating material is different from the first plating material (32A), and / or the fourth plating material is different from the second plating material (32B).

4. The method according to claim 2, wherein: the first plating material (32A) is the same as the third plating material, and / or the second plating material (32B) is the same as the fourth plating material.

5. The method according to any of the preceding claims, wherein: the first die pads (16A) are completely plated with the first plating material (32A), and the second die pads (16B) are completely plated with the second plating material (32B).

6. The method according to any of the preceding claims, wherein: the first plating material (32A) comprises at least one of Ni, NiP, NiNiP, Cu, Ag, and the second plating material (32B) comprises at least one of Cu, Ag, and / or the second leadframe panel (12B) is a pre-plated frame (PPF) or a micro pre-plated frame (μPPF).

7. The method according to any of the preceding claims, wherein: the first semiconductor chips (24A) are power semiconductor chips, and the second semiconductor chips (24B) are at least one of logic semiconductor chips or driver semiconductor chips.

8. The method according to any of the preceding claims, wherein: the first leadframe panel (12A) has a first thickness, and the second leadframe panel (12B) has a second thickness smaller than the first thickness.

9. The method of any of the preceding claims, wherein, Mounting the first semiconductor chip (24A) on the first leadframe panel (12A) and mounting the second semiconductor chip (24B) on the second leadframe panel (12B) are based on different processes.

10. The method of any of the preceding claims, wherein: mounting the first semiconductor chip (24A) on the first leadframe panel (12A) is based on at least one of a diffusion bonding process, a solder bonding process, a preform bonding process, a sintering process, or a solder paste process; and mounting the second semiconductor chip (24B) on the second leadframe panel (12B) is based on at least one of a die attach film process, a soldering process, a solder bonding process, or a sintering process.

11. The method of any of the preceding claims, wherein: mounting the first semiconductor chip (24A) on the first leadframe panel (12A) and mounting the second semiconductor chip (24B) on the second leadframe panel (12B) are performed prior to mechanically connecting the first leadframe panel (12A) with the second leadframe panel (12B).

12. The method of any of the preceding claims, wherein: mounting the first semiconductor chip (24A) on the first leadframe panel (12A) and mounting the second semiconductor chip (24B) on the second leadframe panel (12B) are performed in different production lines.

13. The method of any of the preceding claims, wherein: the first leadframe panel (12A) comprises a first peripheral frame (18A) and a plurality of rows of first die pads (16A), the rows of first die pads (16A) being connected to opposite sides of the first peripheral frame (18A) and being spaced apart by first gaps (20A); the second leadframe panel (12B) comprises a second peripheral frame (18B) and a plurality of rows of second die pads (16B), the rows of second die pads (16B) being connected to opposite sides of the second peripheral frame (18B) and being spaced apart by second gaps (20B); and in the combined leadframe panel (26), the rows of first die pads (16A) of the first leadframe panel (12A) are arranged at the second gaps (20B) of the second leadframe panel (12B), and the rows of second die pads (16B) of the second leadframe panel (12B) are arranged at the first gaps (20A) of the first leadframe panel (12A).

14. The method of any of the preceding claims, wherein, The first die pads (16A) and the second die pads (16B) are arranged at different heights in the combined leadframe panel (26).

15. The method of any of the preceding claims, wherein, The method further comprises: performing an encapsulation process, the first semiconductor chip (24A), the second semiconductor chip (24B), and the combined leadframe panel (26) being at least partially encapsulated in an encapsulation material (30), and singulating the encapsulated semiconductor chips (24A, 24B) and the combined leadframe panel (26) into a plurality of semiconductor packages.

16. The method of claim 15, wherein: The singulated semiconductor package includes a first leadframe (14A) including a first die pad (16A) plated with a first plating material (32A) and a second leadframe (14B) including a second die pad (16B) plated with a second plating material (32B); a first semiconductor chip (24A) of a first type is mounted on the first leadframe (14A); and a second semiconductor chip (24B) of a second type is mounted on the second leadframe (14B).

17. The method of claim 15 or 16, wherein: the first semiconductor chip (24A) is mounted on a first major surface of the first leadframe panel (12A), the second semiconductor chip (24B) is mounted on a second major surface of the second leadframe panel (12B), and after performing the encapsulation process, a major surface of the first leadframe panel (12A) opposite the first major surface is not covered by the encapsulation material (30), and a major surface of the second leadframe panel (12B) opposite the second major surface is covered by the encapsulation material (30).

18. The method of any one of the preceding claims, wherein, The method further includes: electrically coupling the first semiconductor chip (24A) to the first leadframe panel (12A) via first electrical connection elements (40A), the first electrical connection elements (40A) comprising a first electrical connection element material, and electrically coupling the second semiconductor chip (24B) to the second leadframe panel (12B) via second electrical connection elements (40B), the second electrical connection elements (40B) comprising a second electrical connection element material different from the first electrical connection element material.

19. The method of claim 18, wherein: the first electrical connection elements (40A) comprise first wires (40A) comprising a first wire material, the second electrical connection elements (40B) comprise second wires (40B) comprising a second wire material.

20. The method of claim 19, wherein: the first electrical connection element material comprises Al, and the second electrical connection element material comprises Cu.

21. The method of claim 19 or 20, wherein, Electrically coupling the first semiconductor chip (24A) to the first leadframe panel (12A) via first electrical connection elements (40A) and electrically coupling the second semiconductor chip (24B) to the second leadframe panel (12B) via second electrical connection elements (40B) is based on different processes.

22. The method of any one of claims 19 to 21, wherein: electrically coupling the first semiconductor chip (24A) to the first leadframe panel (12A) via first electrical connection elements (40A) is based on a wedge bonding process; and electrically coupling the second semiconductor chip (24B) to the second leadframe panel (12B) via second electrical connection elements (40B) is based on a ball bonding process.

23. The method of any one of the preceding claims, wherein, Mechanically connecting the first leadframe panel (12A) with the second leadframe panel (12B) to form the combined leadframe panel (26) includes at least one of clamping, gluing, or soldering.

24. The method of any of the preceding claims, wherein: the core of the first leadframe panel (12A) includes a first core material, and the core of the second leadframe panel (12B) includes a second core material different from the first core material.

25. The method of claim 24, wherein: the first core material includes Cu, and the second core material includes Al.

26. A semiconductor package, comprising: a first leadframe (14A) including first die pads (16A) plated with a first plating material (32A); a second leadframe (14B) including second die pads (16B) plated with a second plating material (32B) different from the first plating material (32A); a first semiconductor chip (24A) of a first type mounted on the first leadframe (14A); and a second semiconductor chip (24B) of a second type different from the first type mounted on the second leadframe (14B).

27. The semiconductor package of claim 26, wherein: the first semiconductor chip (24A) includes a backside metallization (34) and is mounted on the first leadframe (14A) via the backside metallization (34); and the second semiconductor chip (24B) is mounted on the second leadframe (14B) via a backside thereof formed of a non-metallic material (36).

28. The semiconductor package of claim 26 or 27, wherein: the first semiconductor chip (24A) is a power semiconductor chip, and the second semiconductor chip (24B) is at least one of a logic semiconductor chip or a driver semiconductor chip.

29. The semiconductor package of any one of claims 26-28, wherein, the package further includes: a first electrical connection element (40A) including a first electrical connection element material and electrically coupling the first semiconductor chip (24A) with the first leadframe (14A); and a second electrical connection element (40B) including a second electrical connection element material different from the first electrical connection element material and electrically coupling the second semiconductor chip (24B) with the second leadframe (14B).

30. The semiconductor package of claim 29, wherein: the first electrical connection element (40A) includes a first wire (40A) including a first wire material; the second electrical connection element (40B) includes a second wire (40B) including a second wire material.

31. The semiconductor package of any of claims 26 to 30, wherein: the first die pads (16A) are completely plated with the first plating material (32A); the second die pads (16B) are completely plated with the second plating material.

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