Semiconductor chip with bond pad made of nanowires

Abstract

A method for forming a semiconductor package includes providing a semiconductor chip containing a bond pad located on a top surface of the semiconductor chip, providing a carrier including a chip mounting pad and a landing pad, mounting the semiconductor chip onto the chip mounting pad with the bond pad facing away from the carrier, and attaching an electrical connecting element between the bond pad and the landing pad, wherein the bond pad is formed from nanowires.

Description

TECHNICAL AREA

[0001] The present invention relates to a semiconductor package, in particular a semiconductor package with a semiconductor chip having a bond pad made of nanowires, and a method for manufacturing the same. background

[0002] In the field of semiconductor devices, metallization layers are widely used to create interconnects between devices and to fabricate bond pads. In power devices, thicker metallization layers are required to accommodate the high currents and heat associated with their operation. Increasing the thickness of a metallization layer on a semiconductor chip presents several design challenges. Specifically, with increasing metallization thickness, the risk of delamination from the substrate, cracking, and wafer warping increases. Furthermore, it is desirable to use copper interconnects to accommodate the high currents and heat associated with power device operation.However, copper fasteners can damage the bond pads due to the hardness of the material and the force required to achieve attachment. Therefore, there is a need to improve the durability of metallization layers in semiconductor devices. Brief description

[0003] A method for manufacturing a semiconductor package is disclosed. According to one embodiment, the method comprises providing a semiconductor chip comprising a bond pad arranged on a top surface of the semiconductor chip, providing a carrier comprising a chip mounting pad and a landing pad, mounting the semiconductor chip onto the chip mounting pad, the bond pad facing away from the carrier, and attaching an electrical connection element between the bond pad and the landing pad, the bond pad being formed from nanowires.

[0004] A semiconductor package is disclosed. According to one embodiment, the semiconductor package comprises a carrier including a chip mounting pad and a landing pad chip, a semiconductor chip including a bond pad arranged on a top side of the semiconductor chip and mounted on the chip mounting pad, the bond pad facing away from the carrier, and an electrical connecting element attached between the bond pad and the landing pad, the bond pad being formed from nanowires. Brief description of the characters

[0005] The elements in the drawings are not necessarily to scale. Identical reference numerals denote corresponding similar parts. The features of the various illustrated embodiments can be combined, provided they are not mutually exclusive. Embodiments are shown in the drawings and are described in detail in the following description. Fig. Figure 1 illustrates an arrangement for manufacturing a semiconductor package according to one embodiment. Fig. Figure 2 illustrates an arrangement for manufacturing a semiconductor package according to one embodiment. Fig. Figure 3 illustrates an arrangement for manufacturing a semiconductor package according to one embodiment. Detailed description

[0006] Embodiments of a semiconductor package and a corresponding method for manufacturing the semiconductor package are disclosed herein. The semiconductor package comprises a semiconductor chip mounted on a substrate, e.g., a power electronics substrate, PCB, conductor frame, etc. The semiconductor chip includes a bond pad located on a top surface of the semiconductor chip facing away from the substrate. An electrical connection element, e.g., bond wire, clip, tape, etc., is used to establish an electrical connection between the bond pad and a landing pad of the substrate. Advantageously, the bond pad of the semiconductor chip is made of nanowires. The nanowire bond pad configuration enables improved current capacity and heat dissipation while avoiding some of the disadvantages of conventional metallization layers at increased thickness values.Due to the compressibility and elasticity of the bond pad structure, wafer bending and cracking are reduced compared to conventional metallization layers. Furthermore, thick and / or hard bonding elements, such as copper bond wires, can be used with a pressure-based fastening technique, thus reducing the risk of bond pad cracking.

[0007] With reference to Fig. Document 1 comprises a method for manufacturing a semiconductor package, comprising providing a semiconductor chip 100 which includes a bond pad 102 arranged on a top surface 104 of the semiconductor chip 100. According to one embodiment, the semiconductor chip 100 is a power device. The term "power device" refers to a discrete semiconductor chip 100 that is dimensioned to accept voltages and / or currents associated with power applications, e.g., voltages of at least 100 V (volts), at least 600 V, at least 1200 V or more, and / or dimensioned to accept currents of at least 1 A (ampere), at least 10 A, at least 50 A, at least 100 A or more. Power devices include power transistors, e.g., MOSFETs, HEMTs, IGBTs, etc., thyristors, and diodes. The bond pad 102 is configured as a point of electrical contact with one of the terminals of the device integrated into the semiconductor chip 100.According to one embodiment, the bond pad 102 is configured as a load terminal, i.e., a terminal that accepts the load current of the device. For example, the bond pad 102 can correspond to a source or drain terminal in the case of a MOSFET, a collector or emitter terminal in the case of an IGBT, an anode or cathode in the case of a diode, etc. The semiconductor chip 100 can be configured as a so-called vertical device, wherein the load terminals of the semiconductor chip 100 are provided on opposite main and back faces of the semiconductor chip 100, and the semiconductor chip 100 is configured to conduct in a direction perpendicular to the main and back faces. Fig. Figure 1 shows an example of a vertical device configuration, wherein the semiconductor chip 100 includes a second bond pad 106 arranged on a bottom surface that may correspond to the opposite side of the source or drain terminal in the case of a MOSFET, the collector or emitter terminal in the case of an IGBT, the anode or cathode in the case of a diode, etc. In another embodiment, the semiconductor chip 100 may be configured as a so-called lateral device, wherein each of the terminals of the semiconductor chip 100 is provided on a single main surface of the semiconductor chip 100, and the semiconductor chip 100 is configured to conduct in a direction parallel to this main surface. The semiconductor chip 100 may include additional bond pads arranged on the top surface 104 of the semiconductor chip 100, which are arranged in Fig. 1 are not visible. For example, the semiconductor chip 100 may include an additional bond pad located on the top surface 104, which is configured as a control terminal (e.g., a gate terminal) in the case of a transistor device.

[0008] The method for manufacturing a semiconductor package includes providing a carrier 108 comprising a chip mounting pad 110 and a landing pad 112. In general, the carrier 108 can be any structure that accommodates the mounting of one or more electronic devices (e.g., chips, passives, etc.) and enables electrical communication between the mounted devices and the carrier 108 and / or with an external device. According to the illustrated embodiment, the carrier 108 is configured as a power electronics substrate, which refers to an electronics carrier configured to accommodate one or more power devices and provide a thermally conductive heat dissipation path for these devices. Examples of power electronics substrates include DBC (Direct Bonded Copper), IMS (Insulated Metal), or AMB (Active Metal Brazed) substrates.The power electronics substrate comprises an upper metallization layer 114, a lower metallization layer 116, and an insulating substrate 118 located between the upper and lower metallization layers 114 and 116. The insulating substrate 118 is made of a thermally conductive and electrically insulating material, such as a ceramic. The upper and lower metallization layers 114 and 116 are made of conductive metals, including, for example, Cu, Ni, Ag, Au, Pd, Pt, and alloys thereof. In the illustrated embodiment, the chip mounting pad 110 and the landing pad 112 correspond to structured parts of the upper metallization layer 114. In another embodiment, the carrier 108 is configured as a PCB (printed circuit board). In this case, the support 108 can comprise an electrically insulating substrate made of laminate materials such as FR-4, FR-5, CEM-4, bismaleimide trazine (BT) resin, etc.The chip mounting pad 110 and the landing pad 112 can correspond to structured parts of an upper metallization layer arranged on the electrically insulating substrate. In another embodiment, the carrier 108 is configured as a conductor frame and can therefore be free of an electrically insulating substrate. An example of such an embodiment is described below with reference to [reference to figure]. Fig. 3 described.

[0009] The method for forming the semiconductor package comprises mounting the semiconductor chip 100 onto the chip mounting pad 110, with the top surface 104 and the bond pad 102 facing away from the carrier 108 being arranged on it. The semiconductor chip 100 can be mounted using any type of fastening technique, e.g., solder, sintering compound, adhesive, tape, etc. In the case of a vertical device, the semiconductor chip 100 can be mounted such that the second bond pad 102 is electrically connected to the chip mounting pad 110, e.g., by a solder or sintered connection.

[0010] The process for manufacturing the semiconductor package includes attaching an electrical connector 120 between the bond pad 102 and the landing pad 112. The electrical connector 120 is an electrically conductive structure that forms an electrical connection between the bond pad 102 and the landing pad 112. The electrical connector 120 can be made of electrically conductive metals, including, for example, Cu, Ni, Ag, Au, Pd, Pt, and alloys thereof. The electrical connector 120 can be attached to the bond pad 102 using one of the following: mechanical pressure or adhesive, such as solder, sintering compound, etc.

[0011] In the illustrated embodiment, the electrical connector 120 is configured as a bond wire. This bond wire can be a relatively thick bond wire configured for power applications. For example, the bond wire can have a diameter of at least 5 µm, at least 10 µm, at least 25 µm, at least 50 µm, at least 100 µm, at least 250 µm, at least 500 µm, or more. Separately or in combination, this bond wire can be a copper bond wire. As used herein, a copper bond wire refers to a bond wire formed of pure copper or an alloy comprising at least 90% copper by mass. An electrical connector 120 configured as a bond wire can be attached to the bond pad 102 and the landing pad 112 using any type of wire bonding technique, e.g., B. wedge bonding, wedge-wedge bonding, ball bonding, wedge-ball bonding, laser welding, etc., can be fastened.These wire bonding techniques may involve the application of ultrasonic or laser energy and / or mechanical pressure to attach the electrical connecting element 120 to the bond pad 102.

[0012] In other embodiments, the electrical connecting element 120 can be configured as a metal clip or a connecting strip. A metal clip refers to a relatively rigid structure formed from a flat sheet. Metal clips typically exhibit high current-carrying capacity and / or heat dissipation compared to bond wires. A connecting strip refers to a connecting structure with a flattened cross-sectional base and a width that exceeds its thickness. Connecting strips also offer relatively high current-carrying capacity and / or heat dissipation compared to bond wires, while being mechanically more flexible than metal clips, thus facilitating easier handling by machine tools.

[0013] The semiconductor chip 100 is configured such that the bond pad 102 is formed from nanowires 122. Nanowires 122 refer to strands or material in the form of a wire, i.e., an elongated and generally round element, with a thickness measured along a cross-section of the wire in the nanometer range, e.g., between 10 nm and 2,000 nm. The description that the bond pad 102 is formed from nanowires 122 means that nanowires 122 are present throughout the entire volume of the bond pad 102. Furthermore, the bond pad 102 is free of homogeneous metal regions, e.g., regions of elemental metals or alloys thereof formed by conventional metallization techniques such as plating, sputtering, etc. As explained in more detail below, the nanowires 122 can be arranged loosely without an intermediate material separating them, or alternatively, they can be arranged with an intermediate material connecting them together.

[0014] The nanowires 122 are formed from an electrically conductive metal, e.g., Cu, Co, Ni, Pt, Au, Ag, and alloys thereof. The end-to-end length of the nanowires 122 can, for example, range from 500 nm to 100 µm. Each of the nanowires 122 in the group forming the bond pad 102 can have the same or substantially the same length. The nanowires 122 can be formed, for example, by processes such as CVD (chemical vapor deposition), suspension, electrochemical deposition, VLS (vapor liquid solid) growth, and ionic web technology.

[0015] In the embodiment of Fig. In this arrangement, the bond pad 102 is not an intermediate material between each of the nanowires 122. The nanowires 122 are loosely arranged, with the surrounding environment separating them. The nanowires 122 can be arranged in a lawn-like pattern, extending mainly perpendicular to the top surface 104 of the semiconductor chip 100. Thus, the thickness of the bond pad 102 can be approximately equal to the length of the nanowires 122. Generally, the thickness of the bond pad 102 can range from 500 nm to 100 µm. The nanowires 122 in this arrangement are not necessarily exactly perpendicular and can therefore cross each other. For example, the nanowires 122 can be loosely intertwined and / or woven together.

[0016] Advantageously, a bond pad 102 formed from nanowires 122 allows for greater thicknesses without the disadvantages of solid metal structures, such as delamination, wafer bending, cracking, etc. The nanowire structure results in increased elasticity and deformability compared to bond pads made of solid metal structures. This reduces the stress on the semiconductor chip 100 compared to corresponding solid metal structures under thermal pressure. In embodiments, the bond pad 102 is at least 2 µm thick, at least 5 µm thick, at least 10 µm thick, or at least 25 µm thick. Whether used separately or in combination, the ratio between the thickness of the bond pad 102 and the thickness of the semiconductor chip 100 is at least 60%.

[0017] Another advantage of a bond pad 102 formed from nanowires 122 is that it can be combined with electrical connectors 120 made of a relatively hard material and / or electrical connectors 120 that are attached using significant amounts of mechanical pressure without risk of cracking the bond pad 102. The compressibility of the bond pad 102 absorbs pressure and allows it to conform to the contours of a hard electrical connector 120 that is applied with mechanical pressure, e.g., from a wire bonding process. In general, copper-based electrical connectors 120 are preferred over other metals, such as aluminum-based electrical connectors 120, in power electronics applications.However, the high hardness of copper compared to other metals necessitates increased mechanical pressure to achieve a secure bond using a pressure-based fastening technique, such as wire bonding. In embodiments, the electrical bonding element 120 is a copper bonding wire that is at least 1 µm thick, at least 2 µm thick, at least 5 µm thick, at least 10 µm thick, at least 25 µm thick, at least 50 µm thick, at least 100 µm thick, at least 250 µm thick, or at least 500 µm thick. Either separately or in combination, the ratio between the thickness of the bond pad 102 and the thickness of the electrical bonding element 120 configured as a copper bonding wire is at least 10%. Either separately or in combination, the electrical bonding element 120 can be a copper bonding wire attached to the bond pad 102 using a technique involving mechanical pressure, e.g., wire bonding. B. Wedge bonding, wedge-wedge bonding, ball bonding, wedge-ball bonding, etc.

[0018] After completing the steps for manufacturing the semiconductor package as described above, further processing steps can be performed to complete the semiconductor package. These processing steps can include encapsulation steps, which form an electrically insulating encapsulation material around the assembly comprising the carrier 108 and the semiconductor chip 100. The completed semiconductor package can be a so-called power module. In this case, the carrier 108 can be arranged within a package and (optionally) attached to a base plate. This package can be filled with a potting compound, such as silicone gel, which is cured by a curing process.

[0019] With reference to Fig. 2. A semiconductor package is formed according to another embodiment. In the embodiment of Fig. 2 The bond pad 102 is formed from a group of nanowires 122 that are sintered together. Thus, in contrast to the previously described embodiment of Fig. 1 the space between the nanowires 122 is filled with sintered material which acts as a binder and forms a monolithic structure with a compressed arrangement of the nanowires 122.

[0020] The bond pad 102 can be formed according to the following technique. First, the nanowires 122 can be formed on the top surface 104 of the semiconductor chip 100 without an intermediate material between each of the nanowires 122, e.g., in a lawn-like arrangement similar to that described above. The end-to-end length of the nanowires 122 can, for example, be in the range of 500 nm to 100 µm. Subsequently, a sintering paste is applied to the nanowires 122. In general, the sintering paste can be any type of paste suitable for sintering and may contain, for example, Ag, Au, Cu, etc. A sintering process is then carried out, which increases the ambient temperature but keeps it below the melting point of the metal forming the nanowires 122. Optionally, mechanical pressure can also be applied at this stage.This process induces a reaction whereby the particles from the nanowires 122 diffuse into the sintering paste, thereby densifying and reducing the porosity of the structure. The thickness of the bond pad 102 can be reduced by, for example, 25% to 75% through the sintering process. In embodiments, the bond pad 102, formed from a group of sintered nanowires 122, can have a thickness between 1 µm and 12 µm. Although denser than the previously described embodiment, the bond pad 102 formed from a group of sintered nanowires 122 is still compressible, thus making it possible to achieve the advantages described above with regard to thickness and the reduction of wafer bending.Furthermore, the Bondpad 102, which is formed from a group of nanowires 122, is well suited for a pressure-based fastening process, such as the wire bonding process described above, where the sintered structure adapts to and bonds with the bond wire. Accordingly, the Bondpad 102 can be used in combination with the fasteners and fastening techniques described above, while providing the same advantages regarding the thickness, composition, and fastening technique of the fasteners as described above.

[0021] According to one embodiment, mounting the semiconductor chip 100 onto the chip mounting pad 110 includes a sintering process. This sintering process simultaneously bonds the semiconductor chip 100 to the chip mounting pad 110 and connects the group of nanowires 122. That is, a single processing step is used to both mount the semiconductor chip 100 and create the bond wire structure, which comprises sintered nanowires 122. The sintering paste used to mount the semiconductor chip 100 onto the chip mounting pad 110 can optionally be the same as the sintering paste used to sinter the nanowires 122.In any case, a common tempering step can be carried out, which induces a sintering reaction to fuse a bottom bond pad 102 of the semiconductor chip 100 with the chip mounting pad 110 and to fuse the nanowires 122 with the sintering paste in the bond pad 102, which is located on the top 104 of the semiconductor chip 100.

[0022] With reference to Fig. 3. A semiconductor package is formed according to another embodiment. The semiconductor package comprises a bond pad 102 formed from a group of nanowires 122. The bond pad 102 can have any of the configurations described above. Thus, the bond pad 102 can have no intermediate material between each of the nanowires 122, e.g., as described with reference to Fig. 1 described, or can be formed from a group of nanowires 122 that are sintered together, e.g. as described with reference to Fig. 3 described.

[0023] In the embodiment of Fig. In Figure 3, the support 108 is configured as a conductor frame. This conductor frame can be formed from electrically conductive metals such as copper, aluminum, nickel, silver, palladium, gold, etc., and alloys thereof. The conductor frame can include a core metal area formed from one or more of the aforementioned electrically conductive metals and can optionally include one or more coatings applied to the core metal area to enhance the surface properties of the conductor frame, such as protective coatings, adhesive coatings, or corrosion-resistant coatings. The conductor frame can be formed from a sheet of metal of uniform thickness, processed using metalworking techniques such as punching, bending, cutting, etching, etc.

[0024] In the embodiment of Fig. 3. The chip mounting pad 110 and the landing pad 112 correspond to separate sections of the conductor frame. The conductor frame may additionally include a circumferential ring (not shown) that supports the chip mounting pad 110 and the landing pad 112 in front of the encapsulation, which is finally separated in a trim step. The landing pad 112 may be connected to one or more leads that protrude from a package body and form externally accessible package terminals.

[0025] After forming the in Fig.In the housing arrangement shown in Figure 3, an encapsulation process can be performed on the arrangement to form a housing body made of electrically insulating encapsulation material that encapsulates the semiconductor chip 100, while allowing housing contacts or leads to be accessible from the outside of the housing body. The electrically insulating encapsulation material used to form the housing body can be a plastic material made from an organic resin such as an epoxy resin.

[0026] Although the present revelation is not limited to this, the following numbered examples illustrate one or more aspects of the revelation.

[0027] Example 1. Method for manufacturing a semiconductor package, wherein the method comprises: providing a semiconductor chip comprising a bond pad arranged on a top surface of the semiconductor chip; providing a carrier comprising a chip mounting pad and a landing pad; mounting the semiconductor chip onto the chip mounting pad, the bond pad facing away from the carrier; and attaching an electrical connecting element between the bond pad and the landing pad, the bond pad being formed from nanowires.

[0028] Example 2. Method according to Example 1, wherein the bond pad is formed from a group of nanowires that are sintered together.

[0029] Example 3. Method according to Example 1 or 2, wherein the mounting of the semiconductor chip on the chip mounting pad includes a sintering process, and wherein the sintering process simultaneously attaches the semiconductor chip to the chip mounting pad and connects the group of nanowires together.

[0030] Example 4. Method according to one of Examples 1 to 3, wherein the bond pad has no intermediate material between each of the nanowires.

[0031] Example 5. Method according to one of Examples 1 to 4, wherein the electrical connecting element is a bond wire.

[0032] Example 6. Method according to Example 5, wherein the bond wire is a copper bond wire that is at least 2 µm thick.

[0033] Example 7. Method according to Example 5 or 6, wherein the fastening of the electrical connecting element comprises fastening the bond wire to the bond pad using mechanical pressure.

[0034] Example 8. Method according to one of Examples 1 to 7, wherein the semiconductor chip is a power transistor chip, and wherein the bond pad is a load terminal of the power transistor chip.

[0035] Example 9. Method according to one of Examples 1 to 8, wherein the bond pad is at least 2 µm thick.

[0036] Example 10. Semiconductor package comprising: a support comprising a chip mounting pad and a landing pad; a semiconductor chip comprising a bond pad located on a top side of the semiconductor chip and mounted on the chip mounting pad, the bond pad facing away from the support; and an electrical connecting element attached between the bond pad and the landing pad, the bond pad being formed from nanowires.

[0037] Example 11. Semiconductor package according to Example 10, wherein the bond pad is formed from a group of nanowires that are sintered together.

[0038] Example 12. Semiconductor package according to Example 10 or 11, wherein the bond pad has no intermediate material between each of the nanowires.

[0039] Example 13. Semiconductor package according to one of Examples 10 to 12, wherein the electrical connecting element is a bond wire.

[0040] Example 14. Semiconductor package according to Example 13, wherein the bond wire is a copper bond wire that is at least 2 µm thick.

[0041] Example 15. Semiconductor package according to one of Examples 10 to 14, wherein the semiconductor chip is a power transistor chip, and wherein the bond pad is a load terminal of the power transistor chip.

[0042] Example 16. Semiconductor package according to one of Examples 10 to 15, wherein the bond pad is at least 5 µm thick.

[0043] Example 17. Semiconductor package according to one of Examples 10 to 15, wherein the bond pad is at least 2 µm thick.

[0044] Example 18. Semiconductor package according to one of Examples 10 to 17, wherein the carrier is a power electronics carrier.

[0045] Example 19. Semiconductor package according to one of Examples 10 to 17, wherein the support is a conductor frame.

[0046] Spatially relative terms such as "below," "under," "lower," "above," "upper," and the like are used to simplify the description and to explain the positioning of one element relative to another. These terms are intended to encompass various orientations of the device in addition to those shown in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe different elements, areas, sections, etc., and are not intended to be restrictive. The same terms refer to the same elements throughout the description.

[0047] As used herein, the terms "have," "contain," "include," and the like are open terms that indicate the presence of specified elements or features but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and the singular unless the context clearly indicates otherwise.

[0048] Although the present revelation is not limited to this, the following numbered examples illustrate one or more aspects of the revelation.

[0049] Considering the above range of variations and applications, it is understood that the present invention is not limited by the foregoing description or by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims

[1] Method for manufacturing a semiconductor package, the method comprising: Providing a semiconductor chip (100) comprising a bond pad (102) arranged on a top surface (104) of the semiconductor chip (100); Providing a carrier (108) comprising a chip attachment pad (110) and a landing pad (112); Mounting the semiconductor chip (100) onto the chip mounting pad (110), wherein the bond pad (102) faces away from the carrier (108); and Attaching an electrical connecting element (120) between the bond pad (102) and the landing pad (112), wherein the bond pad (102) is formed from nanowires (122). [2] Method according to claim 1, wherein the bond pad (102) is formed from a group of nanowires (122) which are sintered together. [3] Method according to claim 1 or 2, wherein the mounting of the semiconductor chip (100) on the chip mounting pad (110) comprises a sintering process, and wherein the sintering process simultaneously attaches the semiconductor chip (100) to the chip mounting pad (110) and connects the group of nanowires (122) together. [4] Method according to any one of claims 1 to 3, wherein the bond pad (102) has no intermediate material between each of the nanowires (122). [5] Method according to any one of claims 1 to 4, wherein the electrical connecting element (120) is a bond wire, in particular wherein the bond wire is a copper bond wire that is at least 2 µm thick. [6] Method according to claim 5, wherein the fastening of the electrical connecting element (120) comprises fastening the bond wire to the bond pad (102) using mechanical pressure. [7] Method according to any one of claims 1 to 6, wherein the semiconductor chip (100) is a power transistor chip, and wherein the bond pad (102) is a load terminal of the power transistor chip and / or wherein the bond pad (102) is at least 2 µm thick. [8] Semiconductor packages, comprising: a carrier (108) comprising a chip mounting pad (110) and a landing pad (112); a semiconductor chip (100) comprising a bond pad (102) arranged on a top side (104) of the semiconductor chip (100) and mounted on the chip mounting pad (110), the bond pad (102) facing away from the carrier (108); and an electrical connecting element (120) that is attached between the bond pad (102) and the landing pad (112), wherein the bond pad (102) is formed from nanowires (122). [9] Semiconductor housing according to claim 8, wherein the bond pad (102) is formed from a group of nanowires (122) which are sintered together. [10] Semiconductor package according to claim 8 or 9, wherein the bond pad (102) has no intermediate material between each of the nanowires (122). [11] Semiconductor housing according to any one of claims 8 to 10, wherein the electrical connecting element (120) is a bond wire, in particular wherein the bond wire is a copper bond wire that is at least 2 µm thick. [12] Semiconductor package according to any one of claims 8 to 11, wherein the semiconductor chip (100) is a power transistor chip, and wherein the bond pad (102) is a load terminal of the power transistor chip. [13] Semiconductor package according to any one of claims 8 to 12, wherein the bond pad (102) is at least 5 µm thick, in particular at least 2 µm thick. [14] Semiconductor housing according to any one of claims 8 to 13, wherein the carrier (108) is a power electronics carrier or a conductor frame.

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