Semiconductor package
By using a mixture of fillers of different particle sizes and a multi-layer material layer design in semiconductor packaging, the packaging reliability and cost issues under high-density stacking are solved, achieving higher packaging reliability and lower production costs.
Patent Information
- Application Number
- CN202410473944.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-18
- Publication Date
- 2025-10-24
AI Technical Summary
In the case of high-density stacking, the reliability and performance of existing semiconductor packaging technology are limited by the mismatch of thermal expansion coefficients between chips and the reduction of CTE of material layers, which leads to problems such as stratification. In addition, the traditional method of increasing the filler filling rate is costly.
The first and second types of fillers with different average particle sizes are mixed in a non-conductive substrate to form a material layer. The large-particle filler promotes the flow of small-particle fillers, thereby improving the filling rate and uniformity. Combined with the third material layer coating, the CTE and viscosity are optimized and the cost is reduced.
The packaging reliability of the package body is improved, the risk of delamination is reduced, and the production cost is reduced, while maintaining good light transmittance and electrical connection stability.
Smart Images
Figure CN120834084A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a semiconductor package. BACKGROUND
[0002] 3D stacking technology is to stack multiple chips vertically together, and to realize communication and connection between chips through silicon interconnection and packaging technology. Taking high-band memory (HBM) as an example, it includes multiple layers of vertically stacked DRAM dies, and each layer of die is connected with a logic chip through a through-silicon via (TSV) technology. The 3D integration technology makes it possible to package 8, 12 or even more layers of dies in a small volume space, thereby obtaining smaller size, higher bandwidth and higher reliability. SUMMARY
[0003] Embodiments of the present disclosure provide a semiconductor package with higher reliability and performance.
[0004] The problems to be solved by the technical spirits of the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.
[0005] According to an example embodiment of the present disclosure, a semiconductor package includes: a first semiconductor chip; a second semiconductor chip disposed on the first semiconductor chip; and a first material layer disposed between the first semiconductor chip and the second semiconductor chip, wherein the first material layer includes a non-conductive substrate and a first type of filler and a second type of filler distributed in the non-conductive substrate, and the average particle size of the first type of filler is different from the average particle size of the second type of filler.
[0006] In an example embodiment, the first type of filler does not contain a metal element, the second type of filler contains a metal element, and the average particle size of the first type of filler is greater than the average particle size of the second type of filler.
[0007] In an example embodiment, the average particle size of the first type of filler is 2-5 times the average particle size of the second type of filler.
[0008] In an example embodiment, the volume fraction of the first type of filler in the non-conductive substrate is greater than the volume fraction of the second type of filler in the non-conductive substrate.
[0009] In an example embodiment, the volume ratio of the first type of filler to the second type of filler ranges from 2 to 4.5.
[0010] In an example embodiment, a third material layer is further included, the third material layer is disposed on the first semiconductor chip, the third material layer includes a base material and a third type of filler distributed in the base material, the third type of filler has an average particle size greater than the average particle size of the first type of filler and the average particle size of the second type of filler, and the volume percentage of the third type of filler in the base material of the third material layer is less than the sum of the volume percentages of the first type of filler and the second type of filler in the non-conductive base material of the first material layer.
[0011] In an example embodiment, the third material layer has a first contact surface with the first material layer, and a second contact surface with the second semiconductor chip, the first contact surface has a surface area greater than the surface area of the second contact surface.
[0012] In an example embodiment, the third material layer is further disposed on the first material layer, and the first material layer has a portion not covered by the third material layer.
[0013] In an example embodiment, a third semiconductor chip is further included, the third semiconductor chip is disposed on the second semiconductor chip, the first material layer is not disposed between the third semiconductor chip and the second semiconductor chip, and the first material layer is disposed on a surface of the third semiconductor chip away from the second semiconductor chip.
[0014] In an example embodiment, a second material layer is disposed between the third semiconductor chip and the second semiconductor chip, the second material layer has the first type of filler distributed therein.
[0015] In an example embodiment, the third semiconductor chip and the second semiconductor chip are electrically connected through direct bonding.
[0016] In an example embodiment, the first material layer further has a conductive structure electrically connecting the first semiconductor chip and the second semiconductor chip, and the first material layer at least surrounds part of the conductive structure.
[0017] In an example embodiment, the conductive structure includes a first contact pad connected to the first semiconductor chip, a second contact pad connected to the second semiconductor chip, and an intermediate interconnection structure connecting the first contact pad and the second contact pad, and the first material layer surrounds the intermediate interconnection structure.
[0018] According to another example embodiment of the present disclosure, a semiconductor package includes:
[0019] a core chip disposed on the buffer chip; a first material layer at least partially surrounding the buffer chip and the core chip; wherein the first material layer includes a non-conductive base material and a first type of filler and a second type of filler distributed in the non-conductive base material, the first type of filler has an average particle size different from the average particle size of the second type of filler. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0021] Figure 1 is a cross-sectional view of a semiconductor package provided by an embodiment of the present disclosure;
[0022] Figure 2A is a schematic structural diagram of a first material layer provided by an embodiment of the present disclosure;
[0023] Figure 2B is a schematic structural diagram of another first material layer provided in an embodiment of the present disclosure;
[0024] Figure 3 is a schematic diagram of a semiconductor package provided by an embodiment of the present disclosure;
[0025] Figure 4A is a schematic diagram of a semiconductor package provided by an embodiment of the present disclosure;
[0026] Figure 4B is a schematic diagram of a semiconductor package provided by an embodiment of the present disclosure;
[0027] Figure 5A is a schematic diagram of a semiconductor package provided by an embodiment of the present disclosure;
[0028] Figure 5B is a schematic diagram of a semiconductor package provided by an embodiment of the present disclosure;
[0029] Figure 5C is a schematic diagram of a semiconductor package provided by an embodiment of the present disclosure;
[0030] Figure 6 is a schematic diagram of a semiconductor package provided by an embodiment of the present disclosure;
[0031] Figure 7A is a schematic diagram of a semiconductor package provided by the present disclosure;
[0032] Figure 7B is a schematic diagram of a semiconductor package provided by the present disclosure;
[0033] Figure 8A is a schematic diagram of a semiconductor package provided by the present disclosure;
[0034] Figure 8B is a schematic diagram of a semiconductor package provided by the present disclosure;
[0035] Figure 9is a schematic diagram of a semiconductor package provided by the present disclosure.
[0036] The above drawings illustrate specific embodiments of the present disclosure, which will be described in more detail below. These drawings and the accompanying description are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure for those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION
[0037] The following will provide a clear and complete description of the technical solutions in the embodiments of the present disclosure, in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are intended solely to illustrate the relevant disclosure and are not intended to limit the disclosure. It should also be noted that, for ease of description, only relevant portions are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure relates. The terms used herein are for the purpose of describing the embodiments of the present disclosure only and are not intended to limit the present disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments, but it should be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, and third" in the embodiments of the present disclosure are used solely to distinguish similar objects and do not represent a specific ordering of the objects. It should be understood that "first, second, and third" can be interchanged with each other in a specific order or sequential order, where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described.
[0038] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
[0039] In one embodiment of the present disclosure, see Figure 1 , Figure 1 A cross-sectional view of a semiconductor package is provided. The semiconductor package 10 includes a first semiconductor chip 30 and a second semiconductor chip 20 located on the first semiconductor chip 30. A first material layer 40 is arranged between the first semiconductor chip 30 and the second semiconductor chip 20. The first material layer 40 is used to achieve a fixed connection between the first semiconductor chip 30 and the second semiconductor chip 20.
[0040] In some embodiments, the first semiconductor chip 30 has a surface opposite to the second semiconductor chip 20, and the first material layer 40 can be first arranged in the form of a thin film on this surface opposite to the first semiconductor chip 30 and the second semiconductor chip 20, thereby achieving a fixed connection between the first semiconductor chip 30 and the second semiconductor chip 20.
[0041] In some embodiments, the second semiconductor chip 20 has a surface opposite to the first semiconductor chip 30, and the first material layer 40 can be first arranged on the surface of the second semiconductor chip 20 opposite to the first semiconductor chip 30 in the form of a film, so as to realize the fixed connection between the first semiconductor chip 30 and the second semiconductor chip 20.
[0042] In some embodiments, the first semiconductor chip 30 and the second semiconductor chip 20 are both provided with a part of the first material layer 40 on the surface opposite to each other, and the fixed connection between the first semiconductor chip 30 and the second semiconductor chip 20 is realized through the part of the first material layer 40 on the first semiconductor chip 30 and the part of the first material layer 40 on the second semiconductor chip 20.
[0043] In some embodiments, the first semiconductor chip 30 and the second semiconductor chip 20 can be one of the following: gate array, cell base array, embedded array, structured ASIC, FPGA, CPLD, CPU, MPU, MCU, logic IC, AP, driver IC, RF chip, CMOS image sensor, and the like, and can also be a storage chip represented by DRAM and NANA, and the present disclosure is not limited thereto.
[0044] In some embodiments, the first semiconductor chip 30 and the second semiconductor chip 20 can be the same, for example, the first semiconductor chip 30 and the second semiconductor chip 20 are both storage chips or logic chips.
[0045] In some embodiments, the first semiconductor chip 30 and the second semiconductor chip 20 can also be different, for example, the first semiconductor chip 30 is a logic chip, and the second semiconductor chip is a storage chip.
[0046] In some embodiments, referring to Figure 2A and Figure 2B , the first material layer 40 includes a substrate 41, which can be a sealing material for bonding the first semiconductor chip 30 and the second semiconductor chip to each other, such as a non-conductive material such as silicon-based material, thermosetting material, thermoplastic material, UV-curable material, and the like, in addition to which, the substrate 41 also contains additives such as hardener, polymer, flux (soldering flux) and the like, which assist the first material layer 40 to realize the sealing and bonding effect, which will not be described here.
[0047] The first material layer 40 also includes a first filler 42 and a second filler 43 distributed in the substrate 41. The first filler 42 and the second filler 43 are relatively uniformly distributed in the substrate 41, and the first filler 42 and the second filler 43 are mainly used to control the coefficient of thermal expansion (CTE), viscosity, Young's modulus and other properties of the first material layer 40.
[0048] In some embodiments, the first filler 42 and the second filler 43 have different particle size distributions.
[0049] In some embodiments, referring to Figure 2A , the average particle size of the first filler 42 is greater than the average particle size of the second filler 43, and the first filler 42 includes a type of particles with substantially the same geometric structure, such as circular or approximately circular, and the particle size of these particles can be normally distributed; the second filler 43 includes particles 430a, particles 431a and particles 432a, and the geometric structures of the particles 430a, the particles 431a and the particles 432a can be the same or different, for example, the particles 430a, the particles 431a and the particles 432a can have a geometric structure of non-circular or irregular structure, and in some embodiments, the particle sizes of the three particles 430a, 431a and 432a are not normally distributed, that is, the average particle sizes of the particles 430a, 431a and 432a are different from each other.
[0050] In some embodiments, the average particle size of the first filler 42 is about 2-5 times the average particle size of the second filler, and in other some embodiments, the average particle size of the first filler 42 is about 2.5-3 times or 3-3.5 times the average particle size of the second filler.
[0051] In some embodiments, referring to Figure 2B , the average particle size of the first filler 42 is less than the average particle size of the second filler 43. The first filler 42 includes a type of particles with substantially the same geometric structure, such as circular or elliptical, ellipsoidal, etc., and the particle size of these particles can be normally distributed; the second filler 43 includes particles 430b, particles 431b and particles 432b, and the geometric structures of the particles 430b, the particles 431b and the particles 432b can be the same or different, for example, the particles 430b, the particles 431b and the particles 432b can have a geometric structure of non-circular or irregular structure, such as: planar, that is, flake, irregular or prismatic, etc., and in some embodiments, the particle sizes of the three particles 430b, 431b and 432b are not normally distributed, that is, the average particle sizes of the particles 430b, 431b and 432b are different from each other.
[0052] In some embodiments, the average particle size of the second type of filler 42 is about 2-5 times, in other embodiments, about 2.5-3 times, or about 3-3.5 times the average particle size of the first type of filler.
[0053] In these embodiments, by using the first type of filler and the second type of filler with different average particle sizes, the first material layer has better performance in terms of coefficient of thermal expansion (CTE), viscosity, Young's modulus, etc. than a material using the same type of filler. As the packaging volume is further miniaturized, the distance between chips becomes smaller, and the density of the electrical connection part between chips is further increased, the requirements for the CTE, viscosity, Young's modulus, etc. of the fixed material layer between chips are higher. Generally, as the ratio of fillers in the material layer increases, the CTE of the material layer will decrease, which will help to improve the packaging reliability of the package, reduce the risk of delamination, etc. The traditional way to increase the filler filling rate is to reduce the particle size of the filler. However, reducing the particle size, especially for fillers with regular geometric structures at small particle sizes, will increase the production cost. Therefore, in these embodiments of the present disclosure, two types of fillers with different particle sizes are used together. The large-particle-size filler drives the small-particle-size filler to flow in the substrate, improving the uniformity of the small-particle-size filler. The small-particle-size filler can be distributed in the gaps formed by the large-particle-size filler, increasing the filling rate of the filler and improving the CTE of the material layer. At the same time, the use of fillers with different particle sizes can not require the filler to have a regular geometric structure, which can further reduce the cost.
[0054] In some embodiments, the first type of filler 42 and the second type of filler 43 can each be one or more of inorganic fillers, such as silicon dioxide, aluminum oxide, aluminum nitride, boron nitride, silicon nitride, silicon carbide, magnesium oxide, zinc oxide, etc. In some embodiments, the first type of filler 42 can be a silicon-containing inorganic filler such as silicon dioxide, silicon nitride, silicon carbide, etc., preferably spherical silicon dioxide; and the second type of filler 43 can be a composite filler containing metal elements such as aluminum oxide, aluminum nitride, boron nitride, magnesium oxide, zinc oxide, etc., preferably magnesium oxide, zinc oxide, and aluminum nitride.
[0055] In some embodiments, by using the second type of filler containing metal elements, the thermal conductivity of the first material layer can be effectively increased; in some embodiments, by using the second type of filler containing metal elements with smaller particle size, the thermal conductivity of the first material layer can be increased and the CTE of the first material layer can be reduced at the same time.
[0056] In some embodiments, the volume fraction of the first type of filler 42 in the substrate 41 is greater than the volume fraction of the second type of filler 43 in the substrate 41.
[0057] In some embodiments, the volume ratio of the first type of filler 42 to the second type of filler 43 ranges from 2 to 4.5, for example, the volume ratio of the two can be 2 to 3 or 3 to 4.
[0058] In these embodiments, by setting the volume proportion of the first type of filler in the substrate to be greater than the volume proportion of the second type of filler in the substrate, it can be ensured that the first type of filler pushes the second type of filler to flow in the substrate during the flow of the first type of filler in the substrate, thereby improving the uniformity of the distribution of the filler with irregular geometry in the substrate.
[0059] In some embodiments, the use of the second type of filler with relatively small volume proportion in combination with the first type of filler with higher volume ratio and better surface morphology can reduce the risk of the light transmittance of the first material layer being reduced due to the increased scattering of light transmitted through the substrate by the second type of filler with irregular geometry, which will make it difficult for the recognition of the pattern or position displayed by the camera when the first semiconductor chip and the second semiconductor chip are soldered and aligned.
[0060] In some embodiments, referring to Figure 3 The chip area of the first semiconductor chip 30 is greater than the chip area of the second semiconductor chip 20, and the first material layer 40 between the first semiconductor chip 30 and the second semiconductor chip 20 does not completely cover the surface of the first semiconductor chip 30. In these embodiments, the semiconductor package 10 further comprises a third material layer 50 located on the first semiconductor chip 30, and the third material layer 50 covers the second semiconductor chip 20 and the first material layer 40 to further enhance the sealing effect of the first semiconductor chip 30 and the second semiconductor chip 20.
[0061] In some embodiments, the third material layer 50 comprises a substrate 51 and a filler 52 distributed in the substrate 51. The third material layer 50 can be an insulating layer such as a silicon material or an epoxy material, the substrate 51 can be the same or different material as the substrate 41 of the first material layer 40, specifically, it can be a material that can be combined with the first semiconductor chip and the second semiconductor chip after being treated by light, heat and / or pressure, etc., for example, an insulating material with sealing performance such as silicon material or epoxy resin, in some embodiments, the filler 52 can be one or more mixtures of silicon dioxide, aluminum oxide, aluminum nitride, boron nitride, silicon nitride, silicon carbide, magnesium oxide, zinc oxide, etc.
[0062] In some embodiments, the particulate material of the filler 52 can include any suitable particle geometry, for example, but not limited to, spherical, elliptical, ellipsoidal, and planar (i.e., flaky, irregular, or prismatic), etc., and the flatness particle size of these particles is greater than the average particle size of the fillers 42 and 43 in the first material layer 40.
[0063] In some embodiments, the volume percentage of the filler 52 in the substrate 51 is less than the sum of the volume percentages of the filler 42 and the filler 43 in the non-conductive substrate 41. For example, in some embodiments, the volume percentage of the filler 52 in the substrate 51 is 20% to 60%, preferably 35%, 40% or 50%. The total volume percentage of the filler 42 and the filler 43 in the non-conductive substrate 41 is 35% to 70%, preferably 45%, 50% or 60%. In other embodiments, the volume percentage of the filler 52 in the substrate 51 is not less than 50% to 80% of the volume percentage of the filler 42 and the filler 43 in the non-conductive substrate 41. For example, in some embodiments, the total volume percentage of the filler 42 and the filler 43 in the non-conductive substrate 41 is 50% to 80%, then the volume percentage of the filler 52 in the substrate 51 is not less than 25% to 40%.
[0064] In some embodiments, the third material layer 50 can be filled by molding, reflow or other filling means after the first semiconductor chip 30 and the second semiconductor chip 20 are sealed by the first material layer 40, to cover the second semiconductor chip 20, the first material layer 40 and the exposed surface of the first semiconductor chip 30, forming a sealed package 10.
[0065] In these embodiments, by setting the third material layer with larger average filler particle size and smaller filler volume percentage to cover the first material layer and the parts of the first semiconductor chip and the second semiconductor chip not covered by the first material layer, on the one hand, the difference in filler particle size can increase the packaging stability of the entire package at a lower cost; on the other hand, the difference in filler volume percentage can balance the CTE imbalance between the various components during the sealing process. Prevent delamination between the first material layer, the third material layer and the semiconductor chip due to the large CTE difference between them during the heat treatment of the first material layer and the third material layer, affecting the reliability of the package.
[0066] To make the content of the present disclosure clearer, further description is made below in combination with the process of forming a semiconductor package.
[0067] In some embodiments, the semiconductor package 10 is formed by the following steps:
[0068] S11, respectively providing a first type of filler and a second type of filler, mixing the first type of filler and the second type of filler into a non-conductive substrate, and mixing the first type of filler and the second type of filler uniformly in the non-conductive substrate by stirring or other means and solidifying to form a thin film of the first material layer.
[0069] S13, a wafer is provided, and one side of the thin film first material layer is attached to the surface of the wafer. In some embodiments, the surface of the wafer to which the first material layer is attached is provided with contacts for transmitting signals or power, which pass through the surface of the first material into the first material layer and do not protrude from the first material layer. In some embodiments, the wafer can be a wafer containing multiple dies, or a single die or other bearing structure, such as a carrier wafer.
[0070] S15, another wafer is provided, the wafer with the first material layer is flipped over, the other side of the first material layer is attached to one surface of the other wafer, and a hot pressing process is performed to fix the two wafers together via the first material layer. In some embodiments, the surface of the other wafer is provided with contacts for transmitting signals or power, and after the two wafers are attached, the contacts on the respective surfaces are combined with each other, and the first material layer surrounds the contacts combined with each other to achieve insulation between adjacent contacts.
[0071] In some embodiments, the wafer provided in S15 can be a wafer containing multiple dies, or a single die or other bearing structure, such as a carrier wafer.
[0072] In some embodiments, the wafer in S13 is a wafer containing multiple dies, and when this wafer is flipped over in S15, a cutting process is performed on the wafer with the first material layer to form multiple second semiconductor chips separated from each other; the wafer provided in S15 is a single die, i.e., a first semiconductor chip.
[0073] In some embodiments, the wafer in S13 is a wafer containing multiple dies, and when this wafer is flipped over in S15, a cutting process is performed on the wafer with the first material layer to form multiple second semiconductor chips separated from each other; the wafer provided in S15 is a wafer containing multiple dies, and after the step of S15 is completed, a singulation step is further performed, i.e., the other wafer provided in S15 is divided into multiple first semiconductor chips, i.e., the second semiconductor chips are attached first to the wafer containing the first semiconductor chips, and then the first semiconductor chips are separated, thereby obtaining a package combining the first semiconductor chips and the second semiconductor chips.
[0074] In these embodiments, the first semiconductor chips and the second semiconductor chips can be chips with different areas.
[0075] In some embodiments, the first material layer can also be formed on the first semiconductor chips or the wafer containing the first semiconductor chips first, and then attached between the second semiconductor chips or the wafer containing the second semiconductor chips via the first material layer.
[0076] The formation of the package of the present disclosure is not limited to this, and will not be described here.
[0077] In some embodiments, since the first material layer is formed on the first semiconductor chip or the second semiconductor chip first, the thermal compression bonding (TCB) process adopted in the process of bonding the first semiconductor chip and the second semiconductor chip involves temperature rising and falling and pressure changing, in which the first material layer has a certain flowability at a temperature lower than the hardening temperature of the first material layer, so as to realize the encapsulation of the first semiconductor chip and the second semiconductor chip, and then the first material layer is hardened at the hardening temperature of the first material layer. In this process, the first material layer has a part that overflows the first semiconductor chip or the second semiconductor chip. In the prior art, considering the problem of CTE mismatch between the chip and the material bonding the chip, more material overflowing to the surface of the chip not in direct contact with the chip is prevented by controlling the bonding pressure in the TCB process. However, for the sealing effect of the chip, more overflowing material can effectively ensure that there is enough amount of insulating sealing material between the dense contacts between the chip and the chip, and the first material layer provided by the embodiments of the present disclosure can well solve the CTE problem in the case of more overflow, and better packaging reliability is obtained.
[0078] Continuing to refer to Figure 4A and Figure 4B , Figure 4A illustrates a structure schematic diagram of the package 10 formed by the first material layer formed on the first semiconductor chip first. Since the first material layer 40 has been formed on the first semiconductor chip 30 before the first semiconductor chip 30 and the second semiconductor chip 20 are combined, the third material layer 50 formed after the combination of the first semiconductor chip 30 and the second semiconductor chip 20 has a first contact surface directly abutting the first material layer 40, and the second semiconductor chip 20 has a surface not covered by the first material layer 40. In some embodiments, the sidewall of the second semiconductor chip 20 can also be partially covered by the first material layer 40, that is, the part of the first material layer 40 at the outer periphery of the second semiconductor chip 20 has a protruding part, and the protruding part can encapsulate part of the sidewall surface of the second semiconductor chip 20.
[0079] In some embodiments, the third material layer 50 has a second contact surface directly contacting the second semiconductor chip 20, and the surface area of the first contact surface is greater than that of the second contact surface.
[0080] In some embodiments, as shown in Figure 4A , the first material layer 40 can have an edge not covered by the third material layer 50.
[0081] Continuing to refer to Figure 4B , Figure 4BThe first material layer 40 is formed on the package 10 formed by the second semiconductor chip 20. Since the first material layer 40 is formed on the second semiconductor chip 20 before the first semiconductor chip 30 and the second semiconductor chip 20 are combined, the first material layer 40 has a portion that overflows the second semiconductor chip 20 during the TCB process of combining the first semiconductor chip 30 and the second semiconductor chip 20. The third material layer 50 formed after the first material layer 40 has a first contact surface directly abutting the first material layer 40 and a third contact surface directly abutting the first semiconductor chip 30. The second semiconductor chip 20 has a surface that is not covered by the first material layer 40. In some embodiments, the sidewall of the second semiconductor chip 20 can also be partially covered by the first material layer 40, i.e., the first material layer 40 has a protruding portion at the periphery of the second semiconductor chip 20, and the protruding portion can cover part of the sidewall surface of the second semiconductor chip 20.
[0082] In some embodiments, the third material layer 50 has a second contact surface directly contacting the second semiconductor chip 20, and the surface area of the first contact surface is greater than that of the second contact surface.
[0083] In some embodiments, the surface area of the third contact surface is less than that of the first contact surface.
[0084] In these embodiments, since the CTEs of the provided first material layer and the third material layer are closer, the direct contact area between the first material layer and the third material layer is greater than the direct contact area between the third material layer and the second semiconductor chip after the heat pressing process, and thus the package formed has better packaging reliability.
[0085] In some embodiments, referring to Figure 5A , Figure 5B and Figure 5C , the semiconductor package 10 further includes a plurality of third semiconductor chips 21 disposed on the second semiconductor chip 20. The third semiconductor chip 21 closest to the second semiconductor chip 20 is directly abutted against the second semiconductor chip 20, and the first material layer 40 is disposed on the surface of the third semiconductor chip 21 that is not abutted against the second semiconductor chip 20. The number of third semiconductor chips 21 can be 3 or more, such as 7, 11, etc. The number of third semiconductor chips 21 in the present disclosure is 3 as an example, but is not limited thereto. The third semiconductor chips 21 can be the same type or different type of chips as the second semiconductor chip 20. For example, the third semiconductor chips 21 and the second semiconductor chip 20 are both memory chips.
[0086] In some embodiments, referring to Figure 5AThe first material layer 40 is used to adhere the second semiconductor chip 20 and the third semiconductor chip 21. The first material layer 40 is also used to adhere the third semiconductor chips 21. The third semiconductor chips 21 are further coated by the third material layer 50. In some embodiments, the first material layer partially covers the surface of the second semiconductor chip and the third semiconductor chip. In other words, the third material layer 50 also covers the periphery of the first material layer 40. In these embodiments, the stress caused by the multiple thermal compression processes is effectively balanced by the overlapping use of the first material layer and the third material layer, and the packaging reliability is improved.
[0087] In some embodiments, as shown in FIG. 2, the second semiconductor chip 20 and the third semiconductor chip 21 are directly bonded to each other without the use of the first material layer. For example, the second semiconductor chip 20 and the third semiconductor chip 21 are bonded to each other by fusion bonding or hybrid bonding. Figure 5B In some embodiments, as shown in FIG. 2, the second semiconductor chip 20 and the third semiconductor chip 21 are directly bonded to each other without the use of the first material layer. For example, the second semiconductor chip 20 and the third semiconductor chip 21 are bonded to each other by fusion bonding or hybrid bonding. Figure 5B In some embodiments, as shown in FIG. 2, the second semiconductor chip 20 and the third semiconductor chip 21 are directly bonded to each other without the use of the first material layer. For example, the second semiconductor chip 20 and the third semiconductor chip 21 are bonded to each other by fusion bonding or hybrid bonding.
[0088] In some embodiments, as shown in FIG. 2, the second semiconductor chip 20 and the third semiconductor chip 21 are directly bonded to each other without the use of the first material layer. For example, the second semiconductor chip 20 and the third semiconductor chip 21 are bonded to each other by fusion bonding or hybrid bonding. Figure 5C In some embodiments, as shown in FIG. 2, the second semiconductor chip 20 and the third semiconductor chip 21 are directly bonded to each other without the use of the first material layer. For example, the second semiconductor chip 20 and the third semiconductor chip 21 are bonded to each other by fusion bonding or hybrid bonding. Figure 5CThe third semiconductor chips are adhered to each other by the second material layer 60. The third material layer 50 covers the second semiconductor chip 20 and the outer periphery of each third semiconductor chip 21, and the outer periphery of the first material layer 40 and the second material layer 60 is also covered by the third material layer 50. In these embodiments, the cost can be further reduced by using the second material layer to replace part of the first material layer.
[0089] The present disclosure also provides a package 10, which in some embodiments, as shown in Figure 6 , includes a first semiconductor chip 30, a second semiconductor chip 20, a plurality of third semiconductor chips 21, and a conductive structure 70 connecting the chips. The first semiconductor chip 30 and the second semiconductor chip 20 are adhered to each other by a first material layer 40, the second semiconductor chip 20 and the third semiconductor chips 21 are adhered to each other by the first material layer 40, and each of the third semiconductor chips 21 are adhered to each other by the first material layer 40. A third material layer 50 covers the space between the chips that is not covered by the first material layer 40.
[0090] In some embodiments, the chips can also be adhered to each other by a second material layer, and the positions of the first material layer and the third material layer can be set in the manner described above, which is not particularly limited herein.
[0091] Continuing to refer to Figure 6 , in some embodiments, the conductive structure 70 includes a contact pad 701 disposed on the surface of the first semiconductor chip 30, the contact pad 701 is connected to the circuit structure in the first semiconductor chip 20, the conductive structure 70 further includes a contact pad 703 disposed in the surface dielectric layer 202 of the second semiconductor chip 20 and an intermediate interconnection structure 702 connecting the contact pad 703 and the contact pad 701, the contact pad 703 is connected to the circuit structure in the second semiconductor chip 20. In these embodiments, the first material layer 40 covers the intermediate interconnection structure 702, and the contact pad 703 and the contact pad 701 are not covered by the first material layer 40.
[0092] In some embodiments, the first contact pad 701 and the second contact pad 703 can be a metal or an alloy such as copper (Cu), nickel (Ni), tungsten (W), aluminum (Al), etc.
[0093] In some embodiments, the intermediate interconnection structure 702 can be a solder containing one or more of tin (Sn), titanium (Ti), vanadium (V), antimony (Sb), lead (Pb), tungsten (W), chromium (Cr), copper (Cu), nickel (Ni), aluminum (Al), palladium (Pd), silver (Ag), and gold (Au).
[0094] Continuing to refer to Figure 6In some embodiments, the surface of the first semiconductor chip 30 is provided with a dielectric layer 301, and the contact pad 701 is disposed in the dielectric layer 301; the opposite surfaces of the second semiconductor chip 20 are respectively provided with a dielectric layer 201 and a dielectric layer 202, the contact pad 703 is disposed in the dielectric layer 202, and the contact pad 705 is disposed in the dielectric layer 201, the contact pad 703 and the contact pad 705 are interconnected through the interconnection via 704 disposed in the second semiconductor chip 20, so as to realize the electrical connection between the first semiconductor chip 30 and the second semiconductor chip 20. The other surface of the first semiconductor chip 30 is also provided with the solder ball 302, which is used for interconnecting the first semiconductor chip 30 and other structures, such as a silicon interposer, a PCB circuit board, etc.
[0095] The beneficial effects of these embodiments will be further illustrated below. Figure 7A- Figure 7B and Figure 8A- Figure 8B The beneficial effects of these embodiments will be further illustrated below.
[0096] Figure 7A and Figure 7B are schematic diagrams of some embodiments of the present disclosure. As shown in Figure 7A , before the chip 30' and the chip 20' are attached, the first material layer 40' is disposed on the chip 20'; the contact pad 701' is disposed in the dielectric layer 301' on the surface of the chip 30', and has a part protruding from the surface of the chip 30'; the contact pad 703' is disposed in the dielectric layer 202' on the surface of the chip 20', and has a part protruding from the surface of the chip 20'. The intermediate interconnection structure 702' is formed on the contact pad 703', and is covered by the first material layer 40'. As shown in Figure 7B , under the action of the thermal compression bonding equipment, the chip 30' and the chip 20' are interconnected through the first material layer 40', and the intermediate interconnection structure 702' is connected to the contact pad 701'. During the thermal compression process, the intermediate interconnection structure 702' will deform more relative to the contact pad 701' and the contact pad 703', forming an interface protruding from the contact pad 701' and the contact pad 703', and the deformed interface and the part of the interface of each contact pad will be disposed in the first material layer 40', which causes the force of the intermediate interconnection structure 702' extruding the first material layer 40' during the deformation process to simultaneously extrude the first material layer 40' on the surface of each contact pad, as shown by the black arrows in Figure 7B . This leads to the risk of peeling off the first material layer 40' from the surface of each contact pad, thereby reducing the packaging reliability.
[0097] Figure 8A- Figure 8B are schematic diagrams of some embodiments of the present disclosure. As shown in Figure 6 , the local enlarged view of the A area in Figure 8AAs shown, before bonding, the contact pads 701 of the first semiconductor chip 30 and the contact pads 703 of the second semiconductor chip 20 are respectively arranged in the dielectric layer 202 and the dielectric layer 301. The first material layer 40 is formed on the surface of the dielectric layer 202 of the second semiconductor chip 20 and covers the intermediate interconnection structure 702 formed on the contact pads 703. Figure 8B As shown, under the action of the hot pressing bonding equipment, since the contact pads 701 and 703 are arranged in the dielectric layer on the surface of each chip and do not contact the first material layer 40, the sealing effect of the contact pads 701 and 703 will not be affected during the deformation of the intermediate interconnect structure 702, thereby avoiding the risk of large deformation of the intermediate interconnect structure 702; in addition, the first material layer 40 in the embodiment of the present disclosure adopts a composite filler with a lower CTE, which can also effectively resist the deformation of the intermediate interconnect structure 702, prevent the sealing problem caused by the interface between the first material layer 40 and the intermediate interconnect structure 702 becoming more complicated, and prevent short circuits between adjacent intermediate interconnect structures 702.
[0098] The description of the above beneficial effects is merely a presentation of one of the technical effects of the embodiments of the present disclosure and does not constitute any limitation to the technical solutions of these embodiments.
[0099] In some embodiments, as Figure 6 As shown, the first material layer 40 can be first set on the second semiconductor chip 20, and then the first third semiconductor chip 21 can be stacked on the second semiconductor chip 20; then the first material layer 40 can be set on a surface of the first third semiconductor chip 21 away from the second semiconductor chip 20, and then the second third semiconductor chip 21 can be stacked on the surface of the first third semiconductor chip 21 containing the first material layer, and so on, to achieve stacking of multiple third semiconductor chips 21.
[0100] In some embodiments, the first material layer 40 can be first set on a surface of the first third semiconductor chip 21 facing the second semiconductor chip 20, and then this surface is bonded toward the second semiconductor chip 20 to achieve bonding between the second semiconductor chip 20 and the first third semiconductor chip 21; then the first material layer 40 is set on one surface of the second third semiconductor chip 21, and this surface is bonded toward the surface of the first third semiconductor chip 21 away from the second semiconductor chip 20 to achieve bonding between the first third semiconductor chip 21 and the second semiconductor chip 21, and so on, to achieve stacking between multiple third semiconductor chips 21.
[0101] In some embodiments, after the first semiconductor chip 30, the second semiconductor chip 20, and the plurality of third semiconductor chips 21 are stacked, the third material layer 50 is simultaneously formed around the chip stack and the periphery of each first material layer 40 through a one-step injection molding process. In some embodiments, the third material layer 50 may also be coated around the chip stack using other methods known to those skilled in the art, which will not be further described here.
[0102] In some embodiments, the package 10 further includes interconnect structures connecting the second semiconductor chip 20 and the third semiconductor chip 21, and interconnect structures connecting the third semiconductor chips 21. These interconnect structures may employ the same interconnect structures as the first semiconductor chip 30 and the second semiconductor chip 20. In other embodiments, other chip interconnection methods that are understandable to those skilled in the art may also be employed, which will not be described in detail herein.
[0103] Some embodiments of the present disclosure further provide another semiconductor package 10, see Figure 9 , including a buffer chip 11, a core chip 12 arranged on the buffer chip 11, and a first material layer 40 that surrounds both the buffer chip 11 and the core chip 12. The first material layer 40 is the first material layer 40 used in the above embodiments.
[0104] To make the contents of the semiconductor package 10 clearer, the process of forming the semiconductor package 10 is further described below.
[0105] In some embodiments, forming the semiconductor package 10 includes the following steps:
[0106] S21 , providing a first type of filler and a second type of filler respectively, mixing the first type of filler and the second type of filler into a non-conductive base material, and uniformly mixing the first type of filler and the second type of filler in the non-conductive base material by stirring or the like, to obtain a first material layer 40 .
[0107] S23, providing a buffer chip 11 and a core chip 12, wherein contacts arranged at intervals are provided on the surfaces of the buffer chip 11 and the core chip 12, and the contacts of the buffer chip 11 and the core chip 12 are matched one by one to complete pre-bonding.
[0108] S25 , filling the first material layer 40 into the gap between the pre-bonded buffer chip 11 and the core chip 12 through a reflow filling process, and then performing a curing process to complete the bonding between the buffer chip 11 and the core chip 12 .
[0109] The first material layer 40 formed through the above steps will cover both the buffer chip 11 and the core chip 12 . Since the prepared first material layer 40 has a lower CTE and better thermal conductivity, the package formed in these embodiments exhibits good performance.
[0110] In some embodiments, the core chip 12 can be a stack of multiple core chips, and the first material layer 40 simultaneously coats the stack. In some embodiments, the buffer chip 11 can be a logic chip, such as a gate array, a cell base array, an embedded array, a structured application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a central processing unit (CPU), a micro processing unit (MPU), a micro controller unit (MCU), a logic IC, an application processor (AP), a driver IC, an RF chip, a CMOS image sensor, and the like. The core chip 12 can be a memory chip, such as a DRAM, which is not described herein.
[0111] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the embodiments of the present disclosure, and therefore the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.
Claims
1. A semiconductor package comprising: a first semiconductor chip; a second semiconductor chip disposed on the first semiconductor chip; a first material layer disposed between the first semiconductor chip and the second semiconductor chip; wherein the first material layer comprises a non-conductive substrate and a first type of filler and a second type of filler distributed in the non-conductive substrate, the first type of filler having an average particle size different from that of the second type of filler.
2. The semiconductor package of claim 1, wherein, The first type of filler contains no metal element, the second type of filler contains a metal element, and the average particle size of the first type of filler is greater than that of the second type of filler.
3. The semiconductor package of claim 2, wherein, The average particle size of the first type of filler is 2-3 times that of the second type of filler.
4. The semiconductor package of claim 1, wherein, The volume fraction of the first type of filler in the non-conductive substrate is greater than that of the second type of filler in the non-conductive substrate.
5. The semiconductor package of claim 4, wherein, The volume ratio of the first type of filler to the second type of filler ranges from 2 to 4.
5.
6. The semiconductor package of claim 1, wherein, Further comprising a third material layer disposed on the first semiconductor chip, the third material layer comprising a substrate and a third type of filler distributed in the substrate, the third type of filler having an average particle size greater than that of the first type of filler and that of the second type of filler.
7. The semiconductor package of claim 6, wherein, The third material layer has a first contact surface with the first material layer, and a second contact surface with the second semiconductor chip, the first contact surface having a surface area greater than that of the second contact surface.
8. The semiconductor package of claim 6, wherein, The third material layer is also disposed on the first material layer, and the first material layer has a portion not covered by the third material layer.
9. The semiconductor package of claim 1, wherein, Further comprising a third semiconductor chip disposed on the second semiconductor chip, the third semiconductor chip being free of the first material layer between the third semiconductor chip and the second semiconductor chip, and the third semiconductor chip being disposed with the first material layer away from a surface of the second semiconductor chip.
10. The semiconductor package of claim 9, wherein, The third semiconductor chip and the second semiconductor chip are electrically connected by direct bonding.
11. The semiconductor package of claim 9, wherein, The first material layer further comprises an electrically conductive structure electrically connecting the first semiconductor chip and the second semiconductor chip, and the first material layer at least surrounds part of the electrically conductive structure.
12. The semiconductor package of claim 1, wherein, The electrically conductive structure comprises a first contact pad connected to the first semiconductor chip, a second contact pad connected to the second semiconductor chip, and an intermediate interconnection structure connecting the first contact pad and the second contact pad, and the first material layer surrounds the intermediate interconnection structure.
13. The semiconductor package of claim 12, wherein, 14.A semiconductor package comprising: a buffer chip; a core chip disposed on the buffer chip; a first material layer at least partially surrounding the buffer chip and the core chip; wherein The first material layer includes a non-conductive substrate and a first type of filler and a second type of filler distributed in the non-conductive substrate, the average particle size of the first type of filler being different from the average particle size of the second type of filler.