Semiconductor device

Abstract

A semiconductor device (10) is provided with a component-embedded substrate (20). The component-embedded substrate (20) has: a substrate (25); a first semiconductor element (31); a second semiconductor element (32) arranged with the first semiconductor element (31) at a distance from each other in a direction orthogonal to the thickness direction (DT) of the substrate (25); a first heat dissipation member (61) connected to the first semiconductor element (31) in the thickness direction (DT); a second heat dissipation member (62) connected to the second semiconductor element (32) in the thickness direction (DT); and a thermal interference suppression member (65) that is disposed between the first heat dissipation member (61) and the second heat dissipation member (62) and dissipates heat. This makes it possible to provide a semiconductor device in which thermal interference between adjacent semiconductor elements is suppressed.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device. BACKGROUND

[0002] In the past, as described in Patent Document 1, an electronic device provided with a component-embedded substrate, a capacitor, and a first heat dissipation member is known. The capacitor is provided on one of the two faces of the component-embedded substrate in the thickness direction, i.e., a first face. The first heat dissipation member is provided on the other of the two faces of the component-embedded substrate in the thickness direction, i.e., a second face, which is opposite the first face. Further, the component-embedded substrate is provided with a semiconductor element and a second heat dissipation member. The semiconductor element is embedded in the component-embedded substrate and is arranged at intervals in a direction orthogonal to the thickness direction of the component-embedded substrate. The second heat dissipation member is embedded in the component-embedded substrate, is provided between the capacitor and the first heat dissipation member, and is arranged at intervals in a direction orthogonal to the thickness direction of the component-embedded substrate.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENT

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-097157 SUMMARY

[0006] In the electronic device described in Patent Document 1, when the capacitor generates heat, the heat is conducted to the first heat dissipation member via the second heat dissipation member, and the conduction of the heat to the first heat dissipation member is facilitated by the second heat dissipation member, so the heat dissipation of the capacitor is facilitated. However, not only the capacitor generates heat, but also the semiconductor elements generate heat, and since the second heat dissipation members connected to the semiconductor elements are arranged at intervals in a direction orthogonal to the thickness direction of the component-embedded substrate, the heat of the semiconductor elements easily conducts to the adjacent semiconductor elements. Thus, it is easy for the heat of the semiconductor elements adjacent to each other to interfere with each other. Therefore, it is easy for the semiconductor elements to be damaged.

[0007] An object of the present disclosure is to provide a semiconductor device that suppresses heat interference between semiconductor elements adjacent to each other.

[0008] According to one embodiment of the present disclosure, a semiconductor device has a component-embedded substrate, the component-embedded substrate having: a substrate; a first semiconductor element embedded in the substrate; a second semiconductor element embedded in the substrate and arranged at intervals with the first semiconductor element in a direction orthogonal to a thickness direction of the substrate; a first heat dissipation member embedded in the substrate and connected to the first semiconductor element in the thickness direction; a second heat dissipation member embedded in the substrate and connected to the second semiconductor element in the thickness direction; and a heat interference suppression member embedded in the substrate and disposed between the first heat dissipation member and the second heat dissipation member to dissipate heat.

[0009] Thus, the heat conducted from the first semiconductor element to the first heat dissipation member is conducted to the heat interference suppression member. Further, the heat conducted to the heat interference suppression member is dissipated to the outside of the component-embedded substrate. Therefore, the heat conducted from the first semiconductor element to the first heat dissipation member is difficult to be conducted to the second heat dissipation member and the second semiconductor element. Furthermore, the heat conducted from the second semiconductor element to the second heat dissipation member is conducted to the heat interference suppression member. Further, the heat conducted to the heat interference suppression member is dissipated to the outside of the component-embedded substrate. Therefore, the heat conducted from the second semiconductor element to the second heat dissipation member is difficult to be conducted to the first heat dissipation member and the first semiconductor element.

[0010] Thus, the heat interference between the first semiconductor element and the second semiconductor element is suppressed. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a cross-sectional view of a semiconductor device of a first embodiment.

[0012] Figure 2 is a cross-sectional view of a semiconductor device of a comparative example.

[0013] Figure 3 is a cross-sectional view of a semiconductor device of a second embodiment.

[0014] Figure 4 is a cross-sectional view of a semiconductor device of a third embodiment.

[0015] Figure 5 is a cross-sectional view of a semiconductor device of a fourth embodiment.

[0016] Figure 6 is a cross-sectional view of a semiconductor device of a fifth embodiment.

[0017] Figure 7 is a cross-sectional view of a semiconductor device of a sixth embodiment.

[0018] Figure 8 is a cross-sectional view of a semiconductor device of a seventh embodiment.

[0019] Figure 9 is a cross-sectional view of a semiconductor device of an eighth embodiment.

[0020] Figure 10 is a cross-sectional view of a semiconductor device of a ninth embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, the embodiments will be described with reference to the drawings. Further, in each of the following embodiments, the same reference numerals are assigned to the same or equivalent portions, and the description thereof will be omitted.

[0022] (First Embodiment)

[0023] The semiconductor device of the present embodiment suppresses thermal interference of the semiconductor elements adjacent to each other. Specifically, as shown in Figure 1 The semiconductor device 10 is provided with a component-embedded substrate 20 and a cooling member 70.

[0024] The component-embedded substrate 20 has a substrate 25, a first semiconductor element 31, a second semiconductor element 32, a first via 41, a first wiring layer 51, a second via 42, a third via 43, a second wiring layer 52, a fourth via 44, a first heat dissipation member 61, a second heat dissipation member 62, and a thermal interference suppression member 65.

[0025] The substrate 25 is a printed substrate formed of a glass epoxy resin such as FR4. Note that FR4 is an abbreviation of Flame Retardant Type 4. Hereinafter, the thickness direction of the substrate 25 will be simply referred to as the thickness direction DT.

[0026] Further, the substrate 25 includes a substrate surface 252 and a substrate back surface 254. The substrate surface 252 is a surface intersecting the thickness direction DT. The substrate back surface 254 is a surface intersecting the thickness direction DT, and is a surface opposite to the substrate surface 252. Also, the substrate surface 252 and the substrate back surface 254 are orthogonal to the thickness direction DT.

[0027] The first semiconductor element 31 is a MOSFET or an IGBT, and is embedded in the substrate 25. Note that the first semiconductor element 31 is disposed on the substrate surface 252 side in the inside of the substrate 25. Note that MOSFET is an abbreviation of Metal-Oxide-Semiconductor Field-Effect Transistor. IGBT is an abbreviation of Insulated Gate Bipolar Transistor.

[0028] The second semiconductor element 32 is a MOSFET or an IGBT, and is embedded in the substrate 25. Note that the second semiconductor element 32 is disposed on the substrate surface 252 side in the inside of the substrate 25. Note that the second semiconductor element 32 is arranged at intervals from the first semiconductor element 31 in a direction orthogonal to the thickness direction DT. Thus, the first semiconductor element 31 and the second semiconductor element 32 are adjacent to each other in the direction orthogonal to the thickness direction DT.

[0029] The first via hole 41 is formed of copper or the like, and thus has conductivity. Further, the first via hole 41 is built in the substrate 25, and is connected to the side of the substrate surface 252 in the first semiconductor element 31 in the thickness direction DT. In addition, the first via hole 41 is arranged at intervals in a direction orthogonal to the thickness direction DT.

[0030] The first wiring layer 51 is formed of copper or the like, and thus has conductivity. Further, the first wiring layer 51 is built in the substrate 25, and is connected to the side opposite to the first via hole 41 in the first semiconductor element 31 in the thickness direction DT. In addition, the first wiring layer 51 extends in a direction orthogonal to the thickness direction DT.

[0031] The second via hole 42 is formed of copper or the like, and thus has conductivity. Further, the second via hole 42 is built in the substrate 25, and is connected to the side opposite to the first wiring layer 51 in the first via hole 41 in the thickness direction DT. In addition, the second via hole 42 is arranged at intervals in a direction orthogonal to the thickness direction DT. Further, the portion of the second via hole 42 on the side opposite to the first wiring layer 51 is exposed from the substrate surface 252, and is connected to an electronic component such as a capacitor, a chip resistor, or the like, which is not shown.

[0032] The third via hole 43 is formed of copper or the like, and thus has conductivity. Further, the third via hole 43 is built in the substrate 25, and is connected to the side of the substrate surface 252 in the second semiconductor element 32 in the thickness direction DT. In addition, the third via hole 43 is arranged at intervals in a direction orthogonal to the thickness direction DT.

[0033] The second wiring layer 52 is formed of copper or the like, and thus has conductivity. Further, the second wiring layer 52 is built in the substrate 25, and is connected to the side opposite to the second semiconductor element 32 in the third via hole 43 in the thickness direction DT. In addition, the second wiring layer 52 extends in a direction orthogonal to the thickness direction DT.

[0034] The fourth via hole 44 is formed of copper or the like, and thus has conductivity. Further, the fourth via hole 44 is built in the substrate 25, and is connected to the side opposite to the third via hole 43 in the second wiring layer 52. In addition, the fourth via hole 44 is arranged at intervals in a direction orthogonal to the thickness direction DT. Further, the portion of the fourth via hole 44 on the side opposite to the second wiring layer 52 is exposed from the substrate surface 252, and is connected to an electronic component such as a capacitor, a chip resistor, or the like, which is not shown.

[0035] The first heat dissipation member 61 is formed of a metal such as copper or aluminum or graphite. Thus, the first heat dissipation member 61 has a relatively high thermal conductivity. Further, the first heat dissipation member 61 is built in the substrate 25 and disposed on the substrate back surface 254 side in the inside of the substrate 25. Furthermore, the first heat dissipation member 61 is connected to the side opposite to the first through-hole 41 in the first semiconductor element 31 in the thickness direction DT. Thus, when the first semiconductor element 31 generates heat, the heat from the first semiconductor element 31 is conducted to the first heat dissipation member 61 and dissipated.

[0036] The second heat dissipation member 62 is formed of a metal such as copper or aluminum or graphite. Thus, the second heat dissipation member 62 has a relatively high thermal conductivity. Further, the second heat dissipation member 62 is built in the substrate 25 and disposed on the substrate back surface 254 side in the inside of the substrate 25. Furthermore, the second heat dissipation member 62 is arranged at intervals with the first heat dissipation member 61 in a direction orthogonal to the thickness direction DT. Further, the second heat dissipation member 62 is connected to the side opposite to the third through-hole 43 in the second semiconductor element 32 in the thickness direction DT. Thus, when the second semiconductor element 32 generates heat, the heat from the second semiconductor element 32 is conducted to the second heat dissipation member 62 and dissipated.

[0037] The heat interference suppression member 65 is formed of a metal such as copper or aluminum or graphite. Thus, the heat interference suppression member 65 has a relatively high thermal conductivity, which is higher than that of the substrate 25. Further, the heat interference suppression member 65 is formed, for example, in a cylindrical shape with the length in the thickness direction DT as the height. Furthermore, the heat interference suppression member 65 is built in the substrate 25 and disposed between the first heat dissipation member 61 and the second heat dissipation member 62. With such a configuration, the heat conducted from the first semiconductor element 31 to the first heat dissipation member 61 and the heat conducted from the second semiconductor element 32 to the second heat dissipation member 62 are conducted to the heat interference suppression member 65. The heat conducted from the first heat dissipation member 61 and the second heat dissipation member 62 to the heat interference suppression member 65 is dissipated to the outside of the component built-in substrate 20.

[0038] Furthermore, the heat interference suppression member 65 includes an exposed surface 650. The exposed surface 650 is a surface that intersects the thickness direction DT and is exposed from the substrate 25. Further, in this case, the exposed surface 650 is orthogonal to the thickness direction DT and is exposed from the substrate back surface 254.

[0039] Further, the thermal interference suppression member 65 is formed by a via filling plating, a via plating, a copper damascene, a caulking, or the like. The via filling plating is a method of forming by plating a hole of the substrate 25 formed by a drilling process or the like. The via plating is a method of forming by plating each layer of the substrate 25. The copper damascene is a method of forming by pressing a copper pin or the like into a hole of the substrate 25 formed by a drilling process or the like. The caulking is a method of forming by inserting a member into a hole of the substrate 25 formed by a drilling process or the like and deforming the inserted member to be fixed to the substrate 25.

[0040] The cooling member 70 is connected to the back surface 254 of the substrate and the exposed surface 650, and cools the thermal interference suppression member 65. Thereby, heat conducted to the thermal interference suppression member 65 is dissipated to the cooling member 70. Therefore, heat from the first heat dissipation member 61 and the second heat dissipation member 62 is easily conducted to the thermal interference suppression member 65. Further, the cooling member 70 is, for example, a pipe or the like, and the thermal interference suppression member 65 is cooled by flowing cooling water in the cooling member 70. Alternatively, the cooling member 70 is, for example, a fin in which a plurality of flat plates are arranged, a corrugated fin, a pin fin, or the like formed of a metal such as copper, aluminum, or the like or a material having a relatively high thermal conductivity such as graphite.

[0041] The semiconductor device 10 of the first embodiment is configured as described above. Next, a case where the semiconductor device 10 suppresses thermal interference between the first semiconductor element 31 and the second semiconductor element 32 will be described.

[0042] Here, in the comparative example of the semiconductor device 10, Figure 2 In the comparative example of the semiconductor device 10, the first semiconductor element 31 and the second semiconductor element 32 generate heat. At this time, heat of the first semiconductor element 31 is easily conducted to the second semiconductor element 32 and heat of the second semiconductor element 32 is easily conducted to the first semiconductor element 31 by the first heat dissipation member 61 and the second heat dissipation member 62. Thereby, thermal interference between the first semiconductor element 31 and the second semiconductor element 32 adjacent to each other easily occurs. Therefore, damage of the first semiconductor element 31 and the second semiconductor element 32 easily occurs. Further, the junction of the first semiconductor element 31 and the first heat dissipation member 61 easily deteriorates. Furthermore, the junction of the second semiconductor element 32 and the second heat dissipation member 62 easily deteriorates. Further, in order to suppress the thermal interference between the first semiconductor element 31 and the second semiconductor element 32 adjacent to each other, the distance between the first semiconductor element 31 and the second semiconductor element 32 adjacent to each other is sometimes increased. When the distance between the first semiconductor element 31 and the second semiconductor element 32 adjacent to each other is increased, the component-embedded substrate 20 is upsized.

[0043] The semiconductor device 10 of this embodiment has the component-embedded substrate 20 with the heat interference suppression member 65. The heat interference suppression member 65 is embedded in the substrate 25 and is disposed between the first heat dissipation member 61 and the second heat dissipation member 62. Thus, the heat interference suppression member 65 conducts heat from the first heat dissipation member 61 and the second heat dissipation member 62 and dissipates the heat from the first heat dissipation member 61 and the second heat dissipation member 62 to the outside of the component-embedded substrate 20.

[0044] Thus, heat conducted from the first semiconductor element 31 to the first heat dissipation member 61 is conducted to the heat interference suppression member 65. Further, heat conducted to the heat interference suppression member 65 is dissipated to the outside of the component-embedded substrate 20. Therefore, heat conducted from the first semiconductor element 31 to the first heat dissipation member 61 is less likely to be conducted to the second heat dissipation member 62 and the second semiconductor element 32. Further, heat conducted from the second semiconductor element 32 to the second heat dissipation member 62 is conducted to the heat interference suppression member 65. Further, heat conducted to the heat interference suppression member 65 is dissipated to the outside of the component-embedded substrate 20. Therefore, heat conducted from the second semiconductor element 32 to the second heat dissipation member 62 is less likely to be conducted to the first heat dissipation member 61 and the first semiconductor element 31. Thus, heat interference between the first semiconductor element 31 and the second semiconductor element 32 is suppressed.

[0045] Further, since heat interference between the first semiconductor element 31 and the second semiconductor element 32 is suppressed, deterioration of the junction of the first semiconductor element 31 and the first heat dissipation member 61 and the junction of the second semiconductor element 32 and the second heat dissipation member 62 is suppressed. Further, the distance between the first semiconductor element 31 and the second semiconductor element 32 in a direction orthogonal to the thickness direction DT can be reduced. Thus, the component-embedded substrate 20 can be prevented from being upsized.

[0046] Further, the wiring in the semiconductor device 10 can also be reduced, and thus the increase in the inductance of the semiconductor device 10 is suppressed. Further, since the increase in the inductance of the semiconductor device 10 is suppressed, the decrease in the switching speed of the first semiconductor element 31 and the second semiconductor element 32 is suppressed. Thus, the switching loss of the first semiconductor element 31 and the second semiconductor element 32 can be suppressed.

[0047] Further, in the semiconductor device 10 of the first embodiment, the following effects are also exerted.

[0048] [1-1] The heat interference suppression member 65 includes an exposed surface 650. The exposed surface 650 intersects the thickness direction DT and is exposed from the substrate 25. Further, the exposed surface 650 is exposed from the substrate back surface 254 in this embodiment. Further, the semiconductor device 10 has a cooling member 70. The cooling member 70 is connected to the exposed surface 650 and cools the heat interference suppression member 65.

[0049] Thus, the heat conducted to the thermal interference suppression member 65 is conducted to the cooling member 70 and dissipated. Therefore, the heat conducted from the first semiconductor element 31 to the first heat dissipating member 61 and the heat conducted from the second semiconductor element 32 to the second heat dissipating member 62 are easily conducted to the thermal interference suppression member 65, and thus easily dissipated to the outside of the component-embedded substrate 20. Consequently, the thermal interference suppression effect of the thermal interference suppression member 65 is enhanced.

[0050] [1-2] The thermal conductivity of the thermal interference suppression member 65 is higher than the thermal conductivity of the substrate 25 .

[0051] As a result, heat conducted from the first semiconductor element 31 to the first heat dissipating member 61 and heat conducted from the second semiconductor element 32 to the second heat dissipating member 62 is more easily conducted to the heat interference suppression member 65 than to the substrate 25, and thus is easily dissipated to the outside of the component-embedded substrate 20. Consequently, the heat interference suppression effect of the heat interference suppression member 65 is enhanced.

[0052] (Second embodiment)

[0053] In the second embodiment, if Figure 3 As shown in FIG, the form of the thermal interference suppression member 65 is different from that of the first embodiment. Other than that, it is the same as the first embodiment.

[0054] Specifically, the thermal interference suppression member 65 extends in the thickness direction DT and penetrates the substrate surface 252 and the substrate back surface 254. Therefore, the thermal interference suppression member 65 includes a first exposed surface 651 and a second exposed surface 652 instead of the exposed surface 650.

[0055] The first exposed surface 651 corresponds to the exposed surface 650 , intersects the thickness direction DT, and is exposed from the substrate back surface 254 . The first exposed surface 651 is perpendicular to the thickness direction DT and is connected to the cooling member 70 .

[0056] The second exposed surface 652 is a surface of the thermal interference suppression member 65 opposite to the first exposed surface 651, intersecting the thickness direction DT and exposed from the substrate surface 252. Here, the second exposed surface 652 is orthogonal to the thickness direction DT.

[0057] The semiconductor device 10 of the second embodiment is configured as described above. In the second embodiment as well, the same effects as those of the first embodiment are achieved.

[0058] (Third embodiment)

[0059] In a third embodiment, if Figure 4 As shown in FIG, the configuration of the cooling member 70 is different from that of the second embodiment. Other configurations are the same as those of the second embodiment.

[0060] Specifically, the semiconductor device 10 is provided with a plurality of cooling members 70. In addition, the cooling members 70 are connected to the second exposed surface 652 in addition to the substrate back surface 254 and the first exposed surface 651. Furthermore, the cooling members 70 are connected to a part of the substrate surface 252 so as not to interfere with an unillustrated electronic component such as a capacitor, chip resistor, or the like connected to the second through-hole 42 and the fourth through-hole 44.

[0061] The semiconductor device 10 of the third embodiment is configured as described above. In the third embodiment, the same effects as those of the second embodiment are exerted.

[0062] (Fourth Embodiment)

[0063] In the fourth embodiment, as shown in FIG. 6, the form of the heat interference suppression member 65 is different from that of the first embodiment. Other than this, the fourth embodiment is the same as the first embodiment. Figure 5

[0064] Specifically, the heat interference suppression member 65 is formed in a circular truncated cone shape with the length in the thickness direction DT as the height, instead of being formed in a cylindrical shape. In addition, the heat interference suppression member 65 includes a first surface 661 and a second surface 662 instead of the exposed surface 650.

[0065] The first surface 661 and the second surface 662 are surfaces intersecting the thickness direction DT. Also, the first surface 661 and the second surface 662 are orthogonal to the thickness direction DT here. In addition, the area of the second surface 662 is larger than the area of the first surface 661. Also, the second surface 662 is exposed from the substrate back surface 254 and connected to the cooling member 70.

[0066] The semiconductor device 10 of the fourth embodiment is configured as described above. In the fourth embodiment, the same effects as those of the first embodiment are exerted. In addition, in the fourth embodiment, the following effects are also exerted.

[0067] [2] The heat interference suppression member 65 is formed in a circular truncated cone shape with the length in the thickness direction DT as the height. Also, the heat interference suppression member 65 includes a first surface 661 and a second surface 662. In addition, the area of the second surface 662 is larger than the area of the first surface 661. Also, the second surface 662 is exposed from the substrate back surface 254 and connected to the cooling member 70.

[0068] ​Thus, in the case where the volume is fixed, the size of the surface exposed from the back surface 254 of the substrate becomes larger than when the heat interference suppression member 65 is in a cylindrical shape. Thus, cooling of the heat interference suppression member 65 by the cooling member 70 is easily performed. Thus, heat from the first heat dissipation member 61 and the second heat dissipation member 62 is easily conducted to the heat interference suppression member 65, and thus heat dissipation to the outside of the component-mounting substrate 20 is easily performed. Thus, the heat interference suppression effect of the heat interference suppression member 65 is improved.

[0069] Further, the heat interference suppression member 65 is in a truncated cone shape, and thus in the case where the radius and the height are fixed, the size of the heat interference suppression member 65 can be reduced compared to when the heat interference suppression member 65 is in a cylindrical shape. Thus, the amount of use of the material for forming the heat interference suppression member 65 can be reduced. Thus, the cost of the heat interference suppression member 65 can be reduced, and thus the cost of the semiconductor device 10 can be reduced.

[0070] (Fifth Embodiment)

[0071] In the fifth embodiment, as shown in FIG. 5, the configuration of the heat interference suppression member 65 is different from that of the first embodiment. Other than this, the fifth embodiment is the same as the fourth embodiment. Figure 6

[0072] Specifically, instead of the second surface 662, the first surface 661 is exposed from the back surface 254 of the substrate and is connected to the cooling member 70.

[0073] The semiconductor device 10 of the fifth embodiment is configured as described above. In the fifth embodiment, the same effects as those of the fourth embodiment are also exerted.

[0074] (Sixth Embodiment)

[0075] In the sixth embodiment, as shown in FIG. 6, the configuration of the heat interference suppression member 65 is different from that of the first embodiment. Other than this, the sixth embodiment is the same as the first embodiment. Figure 7

[0076] Specifically, the heat interference suppression member 65 is provided as hollow instead of solid. Thus, a space is formed inside the heat interference suppression member 65. Further, both ends of the heat interference suppression member 65 in the thickness direction DT are open. Thus, in this case, the heat interference suppression member 65 is formed in a cylindrical shape.

[0077] The semiconductor device 10 of the sixth embodiment is configured as described above. In the sixth embodiment, the same effects as those of the first embodiment are also exerted. Further, in the sixth embodiment, the following effects are also exerted.

[0078] ​​[3]A space is formed inside the heat interference suppression member 65. The heat transfer rate of the space is relatively small, and therefore heat conducted from the first semiconductor element 31 to the heat interference suppression member 65 via the first heat dissipation member 61 is difficult to conduct to the second heat dissipation member 62 and the second semiconductor element 32. Further, heat conducted from the second semiconductor element 32 to the heat interference suppression member 65 via the second heat dissipation member 62 is difficult to conduct to the first heat dissipation member 61 and the first semiconductor element 31. Thus, the heat interference suppression effect of the heat interference suppression member 65 is improved.

[0079] (Seventh Embodiment)

[0080] In the seventh embodiment, as shown in FIG. 7, the form of the heat interference suppression member 65 is different from that of the sixth embodiment. Other than this, the seventh embodiment is the same as the sixth embodiment. Figure 8

[0081] Specifically, both ends of the heat interference suppression member 65 in the thickness direction DT are closed instead of being open. Thus, the heat interference suppression member 65 is formed in a bottomed cylindrical shape. Note that the heat interference suppression member 65 is not limited to having both ends in the thickness direction DT closed, and can have one end in the thickness direction DT closed and the other end in the thickness direction DT open.

[0082] The semiconductor device 10 of the seventh embodiment is configured as described above. In the seventh embodiment, the same effects as those of the sixth embodiment are also obtained.

[0083] (Eighth Embodiment)

[0084] In the eighth embodiment, as shown in FIG. 8, the form of the heat interference suppression member 65 is different from that of the first embodiment. Other than this, the eighth embodiment is the same as the first embodiment. Figure 9

[0085] Specifically, the heat interference suppression member 65 does not protrude from the substrate 25. Thus, the heat interference suppression member 65 does not include the exposed surface 650.

[0086] The semiconductor device 10 of the eighth embodiment is configured as described above. In the eighth embodiment, the same effects as those of the first embodiment are also obtained.

[0087] (Ninth Embodiment)

[0088] In the ninth embodiment, as shown in FIG. 9, the form of the heat interference suppression member 65 is different from that of the first embodiment. Other than this, the ninth embodiment is the same as the first embodiment. Figure 10

[0089] ​​​Specifically, the heat interference suppression member 65 is formed in a T-shape in cross section when the heat interference suppression member 65 is cut in the thickness direction DT, instead of being formed in a cylindrical shape.

[0090] The semiconductor device 10 of the ninth embodiment is configured as described above. In the ninth embodiment, the same effects as those of the first embodiment are also obtained.

[0091] (Other Embodiments)

[0092] The present disclosure is not limited to the foregoing embodiments, and the foregoing embodiments can be appropriately changed. In addition, in each of the foregoing embodiments, components configuring the embodiments are of course not necessarily essential except for cases where it is particularly indicated that they are essential, cases where it is clearly recognized as essential in principle, and the like. The foregoing embodiments can also be appropriately combined.

Claims

1. A semiconductor device characterized by comprising: a component-embedded substrate, the component-embedded substrate having: a substrate; a first semiconductor element embedded in the substrate; a second semiconductor element embedded in the substrate and arranged at a distance from the first semiconductor element in a direction orthogonal to a thickness direction of the substrate; a first heat dissipation member embedded in the substrate and connected to the first semiconductor element in the thickness direction; a second heat dissipation member embedded in the substrate and connected to the second semiconductor element in the thickness direction; and a heat interference suppression member embedded in the substrate and arranged between the first heat dissipation member and the second heat dissipation member to dissipate heat.

2. The semiconductor device according to claim 1, characterized in that: the heat interference suppression member includes an exposed surface that intersects the thickness direction and is exposed from the substrate, the semiconductor device includes a cooling member connected to the exposed surface.

3. The semiconductor device according to claim 2, characterized in that: the substrate includes: a substrate surface that intersects the thickness direction and is a surface on a side of the first semiconductor element and the second semiconductor element; and a substrate back surface that intersects the thickness direction and is a surface on a side opposite the substrate surface, the exposed surface is exposed from the substrate back surface.

4. The semiconductor device according to claim 1, characterized in that: the substrate includes: a substrate surface that intersects the thickness direction and is a surface on a side of the first semiconductor element and the second semiconductor element; and a substrate back surface that intersects the thickness direction and is a surface on a side opposite the substrate surface, the heat interference suppression member extends in the thickness direction and penetrates the substrate surface and the substrate back surface.

5. The semiconductor device according to claim 1, characterized in that: the heat interference suppression member is formed in a circular truncated cone shape with a length in the thickness direction as a height.

6. The semiconductor device according to claim 5, characterized in that: the heat interference suppression member includes: a first surface that intersects the thickness direction; and a second surface that intersects the thickness direction and has a larger area than the first surface, the substrate includes: a substrate surface that intersects the thickness direction and is a surface on a side of the first semiconductor element and the second semiconductor element; and a substrate back surface that intersects the thickness direction and is a surface on a side opposite the substrate surface, the second surface is exposed from the substrate back surface, the semiconductor device includes a cooling member connected to the second surface.

7. The semiconductor device according to claim 1, characterized in that: a space is formed inside the heat interference suppression member.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that: a thermal conductivity of the heat interference suppression member is higher than a thermal conductivity of the substrate. ​

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