Packaging structure based on RISC-V processor chip

Abstract

A packaging structure based on an RISC-V processor chip comprises a ceramic substrate, a heat dissipation cover is fixed to the ceramic substrate through SE4450 heat-conducting glue, a chip is welded to the ceramic substrate and located in the heat dissipation cover, and the SE4450 heat-conducting glue is coated between the upper surface of the chip and the lower wall of the heat dissipation cover so that the chip can be supported and subjected to heat conduction. And a plurality of pins are arranged at the lower end of the ceramic substrate. The RISC-V architecture processor chip comprises a serdes module, a DDR module and other high-speed sensitive signal modules, and in order to ensure the quality of various signals, the same-layer regional ground plane laying is carried out according to the wiring positions of different modules in the design of the ground plane of the substrate. Meanwhile, design and placement of different ground pins need to be paid attention to when the external pins are arranged and designed, ground pins of serdes signals are arranged around the positions of the serdes signal pins for wrapping, and ground pins of DDR signals are also arranged around the positions of the DDR signal pins for wrapping, so that the effects of isolating and enhancing signal backflow are achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a packaging structure based on a RISC-V processor chip. BACKGROUND

[0002] The semiconductor packaging technology is mainly to package the bare chip designed and manufactured by the integrated circuit in a structure, which has the functions of bare chip input and output signal, power supply, ground and mechanical support, and guarantees the heat dissipation and stability of the chip. As the bridge of information transmission between the chip and the circuit board, the packaging technology directly affects the electrical, thermal, optical and mechanical properties of the device and integrated circuit, and directly determines the size, weight, application, life, performance and cost of the electronic product.

[0003] At present, although the embedded high-performance processor chip has certain development, there are still obvious deficiencies in the upstream and downstream cooperation and industrialization capability. On the one hand, the core key technology is derived from abroad, and there is strong dependence on foreign technology. The gap between the technology level of domestic products and foreign products limits the industrial promotion. On the other hand, the upstream and downstream industry chain of high-performance and high-reliability chips has poor cooperation capability, and the domestic self-determination rate is low. Based on the open source RISC-V instruction set, the completely independent RISC-V high-performance processor chip product developed by forward design can not only meet the high-performance computing application demand of satellite Internet, traditional spaceflight and commercial spaceflight fields, but also can be downwardly transformed and applied to the fields of avionics, weapon equipment and industrial Internet application, and meet the urgent demand of related high-performance computing, intelligent AI processing and high-reliability application.

[0004] For the RISC-V high-performance processor chip, the number of its bare chip pins is often more than 2000, and it contains many high-speed signals, which belongs to high-density high-speed SoC bare chip. Its packaging design needs to meet the requirements of miniaturization, lightness, high density, high reliability and the like, so the technical advancement, process maturity and design rationality of the packaging design are crucial. To realize the batch and standardized production of a RISC-V high-performance processor chip, especially for high-density high-speed SoC bare chip, the design of the packaging substrate needs to consider the design rationality and take into account the process realizability, maturity and other requirements, to ensure that the product meets the application demand and application environment requirement. SUMMARY

[0005] The present application provides a packaging structure based on a RISC-V processor chip to solve the above-mentioned deficiencies of the prior art, realize high-reliability packaging of the RISC-V processor chip for spaceflight application, and also meet the miniaturization and lightness requirements of the RISC-V processor chip.

[0006] In order to achieve the purpose of the present application, the following technologies are adopted: The application discloses a packaging structure based on a RISC-V processor chip, which comprises a ceramic substrate, a heat dissipation cover fixed on the ceramic substrate through SE4450 heat conductive glue, and a chip welded on the ceramic substrate and located in the heat dissipation cover, and SE4450 heat conductive glue is coated between the upper surface of the chip and the lower wall of the heat dissipation cover to support and conduct heat for the chip. The lower end of the ceramic substrate is provided with a plurality of pins, and the junction between the outer periphery of the lower end of the chip and the ceramic substrate is fixedly connected through the filling material of U8410-302 to protect the bumps on the ceramic substrate.

[0007] Further, the ceramic substrate comprises a plurality of alumina ceramic layers, each alumina ceramic layer is provided with a tungsten alloy metal layer, and the alumina ceramic layers are formed by pressing and sintering at a temperature of 1600 DEG C, each alumina ceramic layer is provided with a plurality of tungsten alloy metal vias, and the tungsten alloy metal layers are conductive through the tungsten alloy metal vias. Alumina is used because it has the advantages of high mechanical strength, high thermal conductivity, corrosion resistance, stable chemical properties and the like. The signal transmission line is made of tungsten because of its high melting point, which facilitates the sintering and pressing forming of the ceramic substrate, and the structural characteristics will not change during the forming process. In addition, the ceramic substrate of this material also has high hardness strength, thereby further strengthening the impact resistance and other properties of the ceramic substrate. In addition, it also has a low thermal expansion coefficient, thereby avoiding the problem of deformation or damage of the substrate in an environment with large temperature changes. And it also has good electrical conductivity and thermal conductivity, so it is the best material for making metal layers.

[0008] Further, the chip is a RISC-V processor chip.

[0009] Further, in order to ensure the flatness of the flip chip process and the coplanarity after the external pin welding, the flip pad surface and the lead-out pad surface need to be ground during the substrate production process, and the end surface coplanarity of the lower end of the pin is ≤100μm. The upper end surface of the ceramic substrate is provided with a plurality of bump pads, and the upper end surface coplanarity of the bump pads is ≤27μm.

[0010] Further, the bump is made of Cu / Ni / SnAg 1.8 .

[0011] Further, the heat dissipation cover is made of Al-SiC, and the lower wall of the heat dissipation cover is provided with a groove, and the chip is located in the groove.

[0012] Further, the material of the pin is Pb90Sn10, and the pin is welded to the bottom of the ceramic substrate through Sn63Pb37.

[0013] The above technical scheme has the following advantages: The signal outlet of the application is designed on different layers, and is punched down to different layers one circle after another from the outside to the inside according to the bump distribution for welding the chip, and the interlayer spacing is designed between each signal outlet layer.

[0014] The RISC-V architecture processor chip contains serdes, DDR and other high-speed sensitive signal modules. In order to ensure the quality of various signals, the same layer regional ground plane is laid according to the wiring position of different modules in the design of the substrate ground plane. At the same time, when designing the external pin arrangement, attention should be paid to the design and placement of different ground pins. Serdes signal ground pins are arranged around the serdes signal pin position to wrap it, and DDR signal ground pins are arranged around the DDR signal pin position to wrap it, which plays a role in isolation and enhancing signal reflow.

[0015] Compared with resin substrate processor chips, the packaging structure adopts a high-temperature co-fired ceramic substrate sintered and pressed by multiple layers of ceramics. High-temperature co-fired ceramics have the advantages of stable structure, high mechanical strength, corrosion resistance, high temperature resistance, high thermal conductivity, and good chip heat dissipation, which can meet the high reliability requirements of aerospace environment applications. Secondly, tungsten alloy is used as a signal transmission line, which can significantly improve the stability of the chip package in the space with large temperature fluctuations. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to make the purpose, technical scheme and advantages of the application more clear, the application will be further described in detail below with reference to the drawings.

[0017] Figure 1 A perspective structure of a packaging structure based on a RISC-V processor chip is shown Figure 1 .

[0018] Figure 2 A perspective structure of a packaging structure based on a RISC-V processor chip is shown Figure 2 .

[0019] Figure 3 A perspective structure of a ceramic substrate is shown. DETAILED DESCRIPTION

[0020] As Figure 1-Figure 2 shown, a packaging structure based on a RISC-V processor chip includes a ceramic substrate 1, a heat dissipation cover 2 is fixed on the ceramic substrate 1 through a heat-conducting glue, a chip 4 is welded on the ceramic substrate 1, the chip 4 is a RISC-V processor chip, the chip 4 is located in the heat dissipation cover 2, and a heat-conducting glue is coated between the upper surface of the chip 4 and the lower wall of the heat dissipation cover 2, a plurality of pins 3 are arranged at the lower end of the ceramic substrate 1, and the junction between the lower end of the chip 4 and the ceramic substrate 1 is fixedly connected through glue.

[0021] Specifically, the ceramic substrate 1 comprises multiple alumina ceramic layers, each of which is provided with a tungsten alloy metal layer, and the alumina ceramic layers are formed by pressing and sintering, each of the alumina ceramic layers is provided with multiple tungsten alloy metal vias, and the tungsten alloy metal layers are conductive through the tungsten alloy metal vias.

[0022] Specifically, the end face of the lower end of the pin 3 has a coplanarity of ≤100μm, the upper end face of the ceramic substrate 1 is provided with multiple bump pads, and the upper end face of the bump pad has a coplanarity of ≤27μm.

[0023] In addition, the bump is made of Cu / Ni / SnAg 1.8 The material of the pin 3 is Pb90Sn10, and the pin 3 is welded to the bottom of the ceramic substrate 1 by Sn63Pb37.

[0024] As shown in Figure 3 The lower side of the first ceramic layer 11 is provided with the second ceramic layer 12, the lower side of the second ceramic layer 12 is provided with the third ceramic layer 13, the lower side of the third ceramic layer 13 is provided with the fourth ceramic layer 14, the lower side of the fourth ceramic layer 14 is provided with the fifth ceramic layer 15, the lower side of the fifth ceramic layer 15 is provided with the sixth ceramic layer 16, the lower side of the sixth ceramic layer 16 is provided with the seventh ceramic layer 17, the lower side of the seventh ceramic layer 17 is provided with the eighth ceramic layer 18, the lower side of the eighth ceramic layer 18 is provided with the ninth ceramic layer 19, the lower side of the ninth ceramic layer 19 is provided with the tenth ceramic layer 110, the lower side of the tenth ceramic layer 110 is provided with the eleventh ceramic layer 111, the lower side of the eleventh ceramic layer 111 is provided with the twelfth ceramic layer 112, the lower side of the twelfth ceramic layer 112 is provided with the thirteenth ceramic layer 113, the lower side of the thirteenth ceramic layer 113 is provided with the fourteenth ceramic layer 114, the lower side of the fourteenth ceramic layer 114 is provided with the fifteenth ceramic layer 115, the lower side of the fifteenth ceramic layer 115 is provided with the sixteenth ceramic layer 116, the lower side of the sixteenth ceramic layer 116 is provided with the seventeenth ceramic layer 117, the upper side of the first ceramic layer 11 is provided with the first metal layer 21, and the first metal layer 21 has multiple bumps.

[0025] The upper side of the second ceramic layer 12 is provided with a second metal layer 22, the upper side of the third ceramic layer 13 is provided with a third metal layer 23, the upper side of the fourth ceramic layer 14 is provided with a fourth metal layer 24, the upper side of the fifth ceramic layer 15 is provided with a fifth metal layer 25, the upper side of the sixth ceramic layer 16 is provided with a sixth metal layer 26, the upper side of the seventh ceramic layer 17 is provided with a seventh metal layer 27, the upper side of the eighth ceramic layer 18 is provided with an eighth metal layer 28, the upper side of the ninth ceramic layer 19 is provided with a ninth metal layer 29, the upper side of the tenth ceramic layer 110 is provided with a tenth metal layer 210, the upper side of the eleventh ceramic layer 111 is provided with an eleventh metal layer 211, the upper side of the twelfth ceramic layer 112 is provided with a twelfth metal layer 212, the upper side of the thirteenth ceramic layer 113 is provided with a thirteenth metal layer 213, the upper side of the fourteenth ceramic layer 114 is provided with a fourteenth metal layer 214, the upper side of the fifteenth ceramic layer 115 is provided with a fifteenth metal layer 215, the upper side of the sixteenth ceramic layer 116 is provided with a sixteenth metal layer 216, the upper side of the seventeenth ceramic layer 117 is provided with a seventeenth metal layer 217, the lower side of the seventeenth ceramic layer 117 is provided with an eighteenth metal layer, and the pin 3 is welded on the eighteenth metal layer.

[0026] The four corners of the first metal layer 21 are provided with four mark patterns, one of which is in a rectangular structure, and the other three are in a circular structure.

[0027] The second metal layer 22 is provided with a second layer power supply ground, a second layer input / output power supply ground, a second layer storage ground and a second layer serializer analog ground. The second layer power supply ground, the second layer input / output power supply ground, the second layer storage ground and the second layer serializer analog ground are connected to the first metal layer 21 through the metal via formed on the first ceramic layer 11.

[0028] The third metal layer 23 has a plurality of third layer digital power supply areas and a plurality of third layer metal leads. Adjacent third layer digital power supply areas are connected to each other to form a third layer power supply area. The third layer metal leads are respectively used for the lead-out and transmission of serializer differential pair signals, 1533B differential pair signals and storage signals. The third layer metal leads used for the lead-out and transmission of serializer differential pair signals and 1533B differential pair signals adopt a paired lead-out mode in the third metal layer 23. The third layer metal leads used for the lead-out and transmission of serializer differential pair signals, 1533B differential pair signals and storage signals are in a zigzag structure, so that the transmission distances of the signals in the third layer metal leads are equal, thereby meeting the requirement of controlling the same delay when transmitting serializer differential pair signals, 1533B differential pair signals and storage signals. The third metal layer 23 is connected to the first metal layer 21 through a metal via.

[0029] The third layer metal leads are connected to the first metal layer 21 through metal vias formed on the first ceramic layer 11 and the second ceramic layer 12, and each third layer metal lead is wrapped by a third layer input / output power supply ground, a third layer storage ground and a third layer serializer analog ground according to its function. The third layer input / output power supply ground, the third layer storage ground and the third layer serializer analog ground for wrapping the third layer metal leads are connected to the second layer input / output power supply ground, the second layer storage ground and the second layer serializer analog ground on the second metal layer 22 through metal vias formed on the second ceramic layer 12. The third layer digital power supply area is connected to the first metal layer 21 through metal vias formed on the first ceramic layer 11 and the second ceramic layer 12. The outgoing ends of the third layer metal leads are connected to the eighteenth metal layer through metal vias formed on the fourth ceramic layer 14, the fifth ceramic layer 15, the sixth ceramic layer 16, the seventh ceramic layer 17, the eighth ceramic layer 18, the ninth ceramic layer 19, the tenth ceramic layer 110, the eleventh ceramic layer 111, the twelfth ceramic layer 112, the thirteenth ceramic layer 113, the fourteenth ceramic layer 114, the fifteenth ceramic layer 115, the sixteenth ceramic layer 116 and the seventeenth ceramic layer 117.

[0030] The fourth metal layer 24 has a fourth layer power supply ground, a fourth layer input / output power supply ground, a fourth layer storage ground and a fourth layer serializer analog ground. The fourth layer power supply ground is connected to the second layer power supply ground on the second metal layer 22 through metal vias formed on the second ceramic layer 12 and the third ceramic layer 13. The fourth layer input / output power supply ground, the fourth layer storage ground and the fourth layer serializer analog ground are connected to the third layer input / output power supply ground, the third layer storage ground and the third layer serializer analog ground on the third metal layer 23 through metal vias formed on the third ceramic layer 13, respectively.

[0031] The fifth metal layer 25 has a plurality of fifth layer digital power supply areas and a plurality of fifth layer metal leads. Adjacent fifth layer digital power supply areas are connected to each other to form a fifth layer power supply area. The fifth layer metal leads are used for the outgoing and transmission of serializer differential pair signals, 1533B differential pair signals and storage signals. The fifth layer metal leads for the outgoing and transmission of serializer differential pair signals and 1533B differential pair signals are in a paired outgoing mode in the fifth metal layer 25. The fifth layer metal leads for the outgoing and transmission of serializer differential pair signals, 1533B differential pair signals and storage signals are in a zigzag structure so that the transmission distances of the signals passing through the fifth layer metal leads are equal. The fifth metal layer 25 is connected to the convex points on the second circle of the first metal layer 21 from outside to inside through metal vias.

[0032] The fifth layer metal leads are connected to the first metal layer 21 through the metal vias formed in the first ceramic layer 11, the second ceramic layer 12, the third ceramic layer 13 and the fourth ceramic layer 14 respectively, and each of the fifth layer metal leads is wrapped by the fifth layer input / output power supply ground, the fifth layer storage ground and the fifth layer serializer analog ground according to its function. The fifth layer input / output power supply ground, the fifth layer storage ground and the fifth layer serializer analog ground for wrapping the fifth layer metal leads are connected to the fourth layer input / output power supply ground, the fourth layer storage ground and the fourth layer serializer analog ground on the fourth metal layer 24 through the metal vias formed in the fourth ceramic layer 14. The fifth layer digital power supply area is connected to the third layer digital power supply area on the third metal layer 23 through the metal vias formed in the third ceramic layer 13 and the fourth ceramic layer 14. The outgoing ends of the fifth layer metal leads are connected to the eighteenth metal layer through the metal vias formed in the fifth ceramic layer 15, the sixth ceramic layer 16, the seventh ceramic layer 17, the eighth ceramic layer 18, the ninth ceramic layer 19, the tenth ceramic layer 110, the eleventh ceramic layer 111, the twelfth ceramic layer 112, the thirteenth ceramic layer 113, the fourteenth ceramic layer 114, the fifteenth ceramic layer 115, the sixteenth ceramic layer 116 and the seventeenth ceramic layer 117 respectively.

[0033] The sixth metal layer 26 has the sixth layer power supply ground, the sixth layer input / output power supply ground, the sixth layer storage ground and the sixth layer serializer analog ground. The sixth layer power supply ground is connected to the fourth layer power supply ground on the fourth metal layer 24 through the metal vias formed in the fourth ceramic layer 14 and the fifth ceramic layer 15. The sixth layer input / output power supply ground, the sixth layer storage ground and the sixth layer serializer analog ground are connected to the fifth layer input / output power supply ground, the fifth layer storage ground and the fifth layer serializer analog ground through the metal vias formed in the fifth ceramic layer 15 respectively.

[0034] The seventh metal layer 27 has a plurality of seventh layer digital power supply areas and a plurality of seventh layer metal leads. Adjacent seventh layer digital power supply areas are connected to each other to form a seventh layer power supply area. The seventh layer metal leads are used for the outgoing and transmission of serializer differential pair signals, 1533B differential pair signals and storage signals respectively. The seventh layer metal leads for the outgoing and transmission of serializer differential pair signals and 1533B differential pair signals are arranged in pairs in the seventh metal layer 27. The seventh layer metal leads for the outgoing and transmission of serializer differential pair signals, 1533B differential pair signals and storage signals are arranged in a zigzag structure so that the transmission distances of the signals passing through the seventh layer metal leads are equal. The seventh metal layer 27 is connected to the third circle of the bumps on the first metal layer 21 from the outside to the inside through the metal vias.

[0035] The seventh layer metal leads are connected to the first metal layer 21 through the metal vias formed in the first ceramic layer 11, the second ceramic layer 12, the third ceramic layer 13, the fourth ceramic layer 14, the fifth ceramic layer 15 and the sixth ceramic layer 16, respectively. Each of the seventh layer metal leads is wrapped by the seventh layer input / output power supply ground, the seventh layer storage ground and the seventh layer serializer analog ground according to its function. The seventh layer input / output power supply ground, the seventh layer storage ground and the seventh layer serializer analog ground for wrapping the seventh layer metal leads are connected to the sixth layer input / output power supply ground, the sixth layer storage ground and the sixth layer serializer analog ground on the sixth metal layer 26 through the metal vias formed in the sixth ceramic layer 16. The seventh layer digital power supply area is connected to the fifth layer digital power supply area on the fifth metal layer 25 through the metal vias formed in the fifth ceramic layer 15 and the sixth ceramic layer 16. The outgoing ends of the seventh layer metal leads are connected to the eighteenth metal layer through the metal vias formed in the seventh ceramic layer 17, the eighth ceramic layer 18, the ninth ceramic layer 19, the tenth ceramic layer 110, the eleventh ceramic layer 111, the twelfth ceramic layer 112, the thirteenth ceramic layer 113, the fourteenth ceramic layer 114, the fifteenth ceramic layer 115, the sixteenth ceramic layer 116 and the seventeenth ceramic layer 117, respectively.

[0036] The eighth metal layer 28 has the eighth layer power supply ground, the eighth layer input / output power supply ground, the eighth layer storage ground, the eighth layer serializer analog ground and the eighth layer input / output power supply. The eighth layer power supply ground is connected to the sixth layer power supply ground on the sixth metal layer 26 through the metal vias formed in the sixth ceramic layer 16 and the seventh ceramic layer 17. The eighth layer input / output power supply ground, the eighth layer storage ground and the eighth layer serializer analog ground are connected to the seventh layer input / output power supply ground, the seventh layer storage ground and the seventh layer serializer analog ground on the seventh metal layer 27 through the metal vias formed in the seventh ceramic layer 17, respectively. Part of the input / output power supply ground and the input / output power supply on the first metal layer 21 are connected to the eighth layer input / output power supply ground and the eighth layer input / output power supply on the eighth metal layer 28 through the metal vias formed in the first ceramic layer 11, the second ceramic layer 12, the third ceramic layer 13, the fourth ceramic layer 14, the fifth ceramic layer 15, the sixth ceramic layer 16 and the seventh ceramic layer 17, and the outgoing end of the eighth layer input / output power supply ground is connected to the input / output power supply ground plane.

[0037] The ninth metal layer 29 has a plurality of ninth layer digital power supply areas and a plurality of ninth layer metal leads. Adjacent ninth layer digital power supply areas are connected to each other to form a ninth layer power supply area. The ninth layer metal leads are respectively used for the output and transmission of the serializer differential pair signal, the 1533B differential pair signal and the storage signal. The ninth layer metal leads used for the output and transmission of the serializer differential pair signal and the 1533B differential pair signal are in a pair output mode in the ninth metal layer 29. The ninth layer metal leads used for the output and transmission of the serializer differential pair signal, the 1533B differential pair signal and the storage signal are in a zigzag structure so that the transmission distances of the signals in the ninth layer metal leads are equal. The ninth metal layer 29 is connected to the fifth ring of bumps on the first metal layer 21 through metal vias.

[0038] The ninth layer metal leads are connected to the first metal layer 21 through metal vias formed in the first ceramic layer 11, the second ceramic layer 12, the third ceramic layer 13, the fourth ceramic layer 14, the fifth ceramic layer 15, the sixth ceramic layer 16, the seventh ceramic layer 17 and the eighth ceramic layer 18. Each ninth layer metal lead is wrapped by a ninth layer input / output power supply ground, a ninth layer storage ground and a ninth layer serializer analog ground according to its function. The ninth layer input / output power supply ground, the ninth layer storage ground and the ninth layer serializer analog ground used for wrapping the ninth layer metal leads are connected to the eighth layer input / output power supply ground, the eighth layer storage ground and the eighth layer serializer analog ground on the eighth metal layer 28 through metal vias formed in the eighth ceramic layer 18. The ninth layer digital power supply areas are connected to the seventh layer digital power supply areas on the seventh metal layer 27 through metal vias formed in the seventh ceramic layer 17 and the eighth ceramic layer 18. The output ends of the ninth layer metal leads are connected to the eighteenth metal layer through metal vias formed in the ninth ceramic layer 19, the tenth ceramic layer 110, the eleventh ceramic layer 111, the twelfth ceramic layer 112, the thirteenth ceramic layer 113, the fourteenth ceramic layer 114, the fifteenth ceramic layer 115, the sixteenth ceramic layer 116 and the seventeenth ceramic layer 117.

[0039] The tenth metal layer 210 has a tenth layer power supply ground, a tenth layer input / output power supply ground, a tenth layer storage ground and a tenth layer serializer analog ground. The tenth layer power supply ground is connected to the eighth layer power supply ground on the eighth metal layer 28 through metal vias formed in the eighth ceramic layer 18 and the ninth ceramic layer 19. The tenth layer input / output power supply ground, the tenth layer storage ground and the tenth layer serializer analog ground are connected to the ninth layer input / output power supply ground, the ninth layer storage ground and the ninth layer serializer analog ground through metal vias formed in the ninth ceramic layer 19.

[0040] The eleventh metal layer 211 has a plurality of eleventh layer digital power supply areas and a plurality of eleventh layer metal leads. Adjacent eleventh layer digital power supply areas are connected to each other to form an eleventh layer power supply area. The eleventh layer metal leads are respectively used for the output and transmission of the serializer differential pair signal, the 1533B differential pair signal and the storage signal. The eleventh layer metal leads used for the output and transmission of the serializer differential pair signal and the 1533B differential pair signal are in a pair output mode in the eleventh metal layer 211. The eleventh layer metal leads used for the output and transmission of the serializer differential pair signal, the 1533B differential pair signal and the storage signal are in a zigzag structure so that the transmission distances of the signals in the eleventh layer metal leads are equal. The eleventh metal layer 211 is connected to the bumps in the sixth circle of the first metal layer 21 from the outside to the inside through the metal vias.

[0041] The eleventh layer metal leads are connected to the first metal layer 21 through the metal vias formed in the first ceramic layer 11, the second ceramic layer 12, the third ceramic layer 13, the fourth ceramic layer 14, the fifth ceramic layer 15, the sixth ceramic layer 16, the seventh ceramic layer 17, the eighth ceramic layer 18, the ninth ceramic layer 19 and the tenth ceramic layer 110. Each of the eleventh layer metal leads is wrapped by the eleventh layer input / output power supply ground, the eleventh layer storage ground and the eleventh layer serializer analog ground according to its function. The eleventh layer input / output power supply ground, the eleventh layer storage ground and the eleventh layer serializer analog ground used for wrapping the eleventh layer metal leads are connected to the tenth layer input / output power supply ground, the tenth layer storage ground and the tenth layer serializer analog ground on the tenth metal layer 210 through the metal vias formed in the tenth ceramic layer 110. The eleventh layer digital power supply areas are connected to the ninth layer digital power supply areas on the ninth metal layer 29 through the metal vias formed in the ninth ceramic layer 19 and the tenth ceramic layer 110. The output ends of the eleventh layer metal leads are connected to the eighteenth metal layer through the metal vias formed in the eleventh ceramic layer 111, the twelfth ceramic layer 112, the thirteenth ceramic layer 113, the fourteenth ceramic layer 114, the fifteenth ceramic layer 115, the sixteenth ceramic layer 116 and the seventeenth ceramic layer 117.

[0042] The twelfth metal layer 212 has a twelfth layer power supply ground, a twelfth layer input / output power supply ground, a twelfth layer storage ground and a twelfth layer serializer analog ground. The twelfth layer power supply ground is connected to the tenth layer power supply ground through the metal vias formed in the tenth ceramic layer 110 and the eleventh ceramic layer 111. The twelfth layer input / output power supply ground, the twelfth layer storage ground and the twelfth layer serializer analog ground are connected to the eleventh layer input / output power supply ground, the eleventh layer storage ground and the eleventh layer serializer analog ground through the metal vias formed in the eleventh ceramic layer 111, respectively.

[0043] The thirteenth metal layer 213 has a plurality of thirteenth layer digital power supply areas and a plurality of thirteenth layer metal leads. Adjacent thirteenth layer digital power supply areas are connected to each other to form a thirteenth layer power supply area. The thirteenth layer metal leads are respectively used for the output and transmission of the serializer differential pair signal, the 1533B differential pair signal and the storage signal. The thirteenth layer metal leads for outputting and transmitting the serializer differential pair signal and the 1533B differential pair signal are in a paired output mode in the thirteenth metal layer 213. The thirteenth layer metal leads for outputting and transmitting the serializer differential pair signal, the 1533B differential pair signal and the storage signal are in a zigzag structure so that the transmission distances of the signals in the thirteenth layer metal leads are equal. The thirteenth metal layer 213 is connected to the bumps on the remaining part of the sixth ring on the first metal layer 21 through the metal vias.

[0044] The thirteenth layer metal leads are connected to the first metal layer 21 through the metal vias formed in the first ceramic layer 11, the second ceramic layer 12, the third ceramic layer 13, the fourth ceramic layer 14, the fifth ceramic layer 15, the sixth ceramic layer 16, the seventh ceramic layer 17, the eighth ceramic layer 18, the ninth ceramic layer 19, the tenth ceramic layer 110, the eleventh ceramic layer 111 and the twelfth ceramic layer 112. Each thirteenth layer metal lead is wrapped by the thirteenth layer input / output power supply ground, the thirteenth layer storage ground and the thirteenth layer serializer analog ground according to its function. The thirteenth layer input / output power supply ground, the thirteenth layer storage ground and the thirteenth layer serializer analog ground for wrapping the thirteenth layer metal leads are connected to the twelfth layer input / output power supply ground, the twelfth layer storage ground and the twelfth layer serializer analog ground on the twelfth metal layer 212 through the metal vias formed in the twelfth ceramic layer 112. The thirteenth layer digital power supply area is connected to the eleventh layer digital power supply area on the eleventh metal layer 211 through the metal vias formed in the eleventh ceramic layer 111 and the twelfth ceramic layer 112. The analog power supply of the input / output power supply in the storage and the serializer signal on the first metal layer 21 is connected to the thirteenth metal layer 213 through the metal vias formed in the first ceramic layer 11, the second ceramic layer 12, the third ceramic layer 13, the fourth ceramic layer 14, the fifth ceramic layer 15, the sixth ceramic layer 16, the seventh ceramic layer 17, the eighth ceramic layer 18, the ninth ceramic layer 19, the tenth ceramic layer 110, the eleventh ceramic layer 111 and the twelfth ceramic layer 112, and forms the input / output power supply area in the storage and the analog power supply area of the serializer signal on the thirteenth metal layer 213.

[0045] The fourteenth metal layer 214 has a fourteenth layer power ground, a fourteenth layer input / output power ground, a fourteenth layer memory ground, and a fourteenth layer serializer analog ground. The fourteenth layer power ground is connected to the twelfth layer power ground of the twelfth metal layer 212 through a metal via formed on the twelfth ceramic layer 112 and the thirteenth ceramic layer 113. The fourteenth layer input / output power ground, the fourteenth layer memory ground, and the fourteenth layer serializer analog ground are connected to the thirteenth layer input / output power ground, the thirteenth layer memory ground, and the thirteenth layer serializer analog ground, respectively, through metal vias formed on the thirteenth ceramic layer 113.

[0046] The fifteenth metal layer 215 has a fifteenth layer input / output power plane, a fifteenth layer digital power area, a fifteenth layer input / output power ground plane, a fifteenth layer serializer analog ground plane, and a fifteenth layer serializer digital power area. The fifteenth layer input / output power plane is connected to the eighth layer input / output power on the eighth metal layer 28 through metal vias formed on the eighth ceramic layer 18, the ninth ceramic layer 19, the tenth ceramic layer 110, the eleventh ceramic layer 111, the twelfth ceramic layer 112, the thirteenth ceramic layer 113, and the fourteenth ceramic layer 114. The fifteenth layer digital power area is connected to the thirteenth layer digital power area on the thirteenth metal layer 213 through metal vias formed on the thirteenth ceramic layer 113 and the fourteenth ceramic layer 114. The fifteenth layer input / output power ground plane and the fifteenth layer serializer analog ground plane are connected to the fourteenth layer input / output power ground and the fourteenth layer serializer analog ground on the fourteenth metal layer 214 through metal vias formed on the fourteenth ceramic layer 114. A portion of the serializer digital power on the first metal layer 21 is connected to the fifteenth layer serializer digital power area of the fifteenth metal layer 215 through metal vias formed on the first ceramic layer 11, the second ceramic layer 12, the third ceramic layer 13, the fourth ceramic layer 14, the fifth ceramic layer 15, the sixth ceramic layer 16, the seventh ceramic layer 17, the eighth ceramic layer 18, the ninth ceramic layer 19, the tenth ceramic layer 110, the eleventh ceramic layer 111, the twelfth ceramic layer 112, the thirteenth ceramic layer 113, and the fourteenth ceramic layer 114.

[0047] The sixteenth metal layer 216 has a sixteenth layer power ground, a sixteenth layer input / output power supply ground, a sixteenth layer serializer analog ground, and a sixteenth layer serializer digital power ground. The sixteenth layer power ground is connected to the fourteenth layer power ground of the fourteenth metal layer 214 through a metal via formed in the fourteenth ceramic layer 114 and the fifteenth ceramic layer 115. The sixteenth layer input / output power supply ground and the sixteenth layer serializer analog ground are connected to the fifteenth layer input / output power plane and the fifteenth layer serializer analog ground plane on the fifteenth metal layer 215 through metal vias formed in the fifteenth ceramic layer 115. The sixteenth layer serializer digital power ground is connected to the first metal layer 21 through metal vias formed in the first ceramic layer 11, the second ceramic layer 12, the third ceramic layer 13, the fourth ceramic layer 14, the fifth ceramic layer 15, the sixth ceramic layer 16, the seventh ceramic layer 17, the eighth ceramic layer 18, the ninth ceramic layer 19, the tenth ceramic layer 110, the eleventh ceramic layer 111, the twelfth ceramic layer 112, the thirteenth ceramic layer 113, the fourteenth ceramic layer 114, and the fifteenth ceramic layer 115.

[0048] The seventeenth metal layer 217 has a seventeenth layer digital power region, a seventeenth layer input / output power supply ground plane, a seventeenth layer serializer analog ground plane, and a seventeenth layer serializer digital power region. The seventeenth layer digital power region is connected to the fifteenth layer digital power region on the fifteenth metal layer 215 through metal vias formed in the fifteenth ceramic layer 115 and the sixteenth ceramic layer 116. The seventeenth layer input / output power supply ground plane and the seventeenth layer serializer analog ground plane are connected to the sixteenth layer input / output power supply ground and the sixteenth layer serializer analog ground on the sixteenth metal layer 216 through metal vias formed in the sixteenth ceramic layer 116, respectively. The seventeenth layer serializer digital power region is connected to the fifteenth layer serializer digital power region on the fifteenth metal layer 215 through metal vias formed in the fifteenth ceramic layer 115 and the sixteenth ceramic layer 116.

[0049] The above description is merely that of the preferred embodiments of the present application, and is not intended to limit the present application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. A package structure based on a RISC-V processor chip, characterized in that, The application relates to a ceramic substrate (1) on which a heat dissipation cover (2) is fixed through heat-conducting glue, a chip (4) is welded on the ceramic substrate (1), the chip (4) is located in the heat dissipation cover (2), heat-conducting glue is coated between the upper surface of the chip (4) and the lower wall of the heat dissipation cover (2), the lower end of the ceramic substrate (1) is provided with a plurality of pins (3), and the lower end outer periphery of the chip (4) is fixedly connected with the ceramic substrate (1) through glue at the junction.

2. The RISC-V processor core based package structure of claim 1, wherein, The ceramic substrate (1) comprises a plurality of alumina ceramic layers, each alumina ceramic layer is provided with a tungsten alloy metal layer, the alumina ceramic layers are formed by pressing and sintering, each alumina ceramic layer is provided with a plurality of tungsten alloy metal vias, and the tungsten alloy metal layers are conductive through the tungsten alloy metal vias.

3. The RISC-V processor core based package structure of claim 1, wherein, The chip (4) is a RISC-V processor chip.

4. The RISC-V processor core based package structure of claim 1, wherein, The end face of the lower end of the pin (3) has a coplanarity of less than or equal to 100 mu m.

5. The RISC-V processor core based package structure of claim 1, wherein, The upper end face of the ceramic substrate (1) is provided with a plurality of bump pads, and the upper end face of the bump pad has a coplanarity of less than or equal to 27 mu m.

6. The RISC-V processor core based package structure of claim 5, wherein, The bumps are made of Cu / Ni / SnAg 1.8 made.

7. The RISC-V processor core based package structure of claim 1, wherein, The heat dissipation cover (2) is made of Al-SiC, the lower wall of the heat dissipation cover (2) is provided with a groove, and the chip (4) is located in the groove.

8. The RISC-V processor core based package structure of claim 1, wherein, The material of the pin (3) is Pb90Sn10, and the pin (3) is welded to the bottom of the ceramic substrate (1) through Sn63Pb37.

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