Semiconductor device package

Abstract

The invention provides a semiconductor device package. The semiconductor device package includes a plurality of leads, an encapsulation body, and a solder element. The plurality of leads includes a first lead. The encapsulation body is disposed at both sides of the first lead. The solder element is disposed over a top surface of the first lead. In a cross-sectional view view, the first lead and the encapsulation jointly define a space that tapers in a first direction from the top surface toward a lower surface of the first lead, and the space is configured to direct the solder element to flow from the top surface toward a bottom portion of the space along a first lateral surface of the first lead.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to a semiconductor device package. BACKGROUND

[0002] Wettable flanks can be used to improve solderability of quad flat no-lead packages (QFNs) and reduce inspection costs after soldering by optical inspection. Wettable flanks can also improve solder quality of QFNs, which can meet the criteria of solder quality by visual observation.

[0003] However, existing wettable flank-QFNs (WF-QFNs) have structural weaknesses in terms of burr defects when performing a cutting operation on the wettable flanks. Due to the ductile properties of the leads in the QFN, a portion of the leads can be gradually elongated and become burr defects during the cutting operation, which can cause shorting defects between the leads and make it difficult to achieve mass production. SUMMARY

[0004] In one or more configurations, a semiconductor device package includes a plurality of leads, an encapsulation body, and a solder element. The plurality of leads includes a first lead. The encapsulation body is disposed at both sides of the first lead. The solder element is disposed over a top surface of the first lead. In a cross-sectional view, the first lead and the encapsulation body collectively define a space that narrows in a first direction from the top surface toward a lower surface of the first lead, and the space is configured to direct the solder element to flow from the top surface along a first lateral surface of the first lead toward a bottom portion of the space.

[0005] In one or more configurations, a semiconductor device package includes a plurality of leads and a first barrier portion. The plurality of leads includes a first lead having a first lateral surface and a second lateral surface opposite the first lateral surface. The first barrier portion is disposed between the leads and spaced apart from the first and second lateral surfaces by a first gap and a second gap, respectively, the gaps being configured to accommodate a solder element, wherein the first gap has a first width and the second gap has a second width less than the first width.

[0006] In one or more configurations, a semiconductor device package includes a plurality of leads and an encapsulation body. The plurality of leads includes a first lead. The encapsulation body includes a first portion and a second portion spaced apart from the first portion, wherein the first and second portions are disposed between the leads and spaced apart from the leads by a first gap and a second gap, respectively. The first lead includes a first burr extending into the first gap and a second burr extending into the second gap, and in a cross-sectional view, an area of the first burr is different from an area of the second burr. BRIEF DESCRIPTION OF DRAWINGS

[0007] Aspects of the disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that the various features may not be drawn to scale, and that the dimensions of the various features may be arbitrarily increased or decreased for the clarity of discussion.

[0008] Figure 1 Perspective view of a portion of a semiconductor device package according to some embodiments of the disclosure.

[0009] Figure 1A Perspective view of a portion of a semiconductor device package according to some embodiments of the disclosure.

[0010] Figure 1B Perspective view of a portion of a semiconductor device package according to some embodiments of the disclosure.

[0011] Figure 1C Perspective view of a portion of a semiconductor device package according to some embodiments of the disclosure.

[0012] Figure 2A Perspective view of a portion of a semiconductor device package according to some embodiments of the disclosure.

[0013] Figure 2B Perspective view of a portion of a semiconductor device package according to some embodiments of the disclosure.

[0014] Figure 2C Perspective view of a portion of a semiconductor device package according to some embodiments of the disclosure.

[0015] Figure 3A Top view of a portion of a semiconductor device package according to some embodiments of the disclosure.

[0016] Figure 3B Top view of a portion of a semiconductor device package according to some embodiments of the disclosure.

[0017] Figure 3C Cross-section of a portion of a semiconductor device package according to some embodiments of the disclosure.

[0018] Figure 3D Cross-section of a portion of a semiconductor device package according to some embodiments of the disclosure.

[0019] Figure 4A Scanning electron micrograph image of a portion of a semiconductor device package according to some embodiments of the disclosure.

[0020] Figure 4B Scanning electron micrograph image of a portion of a semiconductor device package according to some embodiments of the disclosure.

[0021] Figure 5 ,Figure 5A 、 Figure 5B 、 Figure 6 、 Figure 6A 、 Figure 6B 、 Figure 7 、 Figure 7A and Figure 7B FIG. 1 illustrates various stages of an exemplary method for manufacturing a semiconductor device package according to some embodiments of the present disclosure.

[0022] Common element symbols are used throughout the drawings and detailed description to indicate the same or similar elements. The present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate various stages in the manufacture of a semiconductor device package according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0023] Figure 1 is a perspective view of a semiconductor device package 1 according to some configurations of the present disclosure. Figure 1A is a perspective view of a portion of a semiconductor device package 1 according to some configurations of the present disclosure. Figure 1B is a perspective view of a portion of a semiconductor device package 1 according to some configurations of the present disclosure. The semiconductor device package 1 can include an encapsulation body 10, a die pad 20, a plurality of leads 30, and a solder element 60. Note that the solder element 60 is omitted in Figure 1 and Figure 1A . Figure 1 and Figure 1A The structures shown in Figure 1B may include the solder element 60 shown in

[0024] The encapsulation body 10 can encapsulate the die pad 20 and the leads 30. The encapsulation body 10 can have a surface 10al (also referred to as an "upper surface" of a "top surface") and a surface 101 (also referred to as a "lateral surface," a "side surface," or a "side") connected to the surface 10al. In some configurations, the surface 101 faces away from a central region of the semiconductor device package 1. The encapsulation body 10 can include an insulating material or a dielectric material. The encapsulation body 10 can be made of or include a molding material, which can include, for example, a novolac-based resin, an epoxy-based resin, a silicone-based resin, or other suitable encapsulation material. Suitable fillers, such as powdered Si02, can also be included. In some configurations, the encapsulation body 10 includes an epoxy resin, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material including silicon dispersed therein, or a combination thereof.

[0025] In some configurations, the encapsulant 10 has or defines a plurality of cavities 10C (also referred to as "recesses" or "trenches"). The encapsulant 10 can further have surfaces 102 and 103 (also referred to as "lateral surfaces," "side surfaces," or "sides") and a surface 10a2 (also referred to as an "upper surface" of the encapsulant 10) connected to the surfaces 102 and 103. In some configurations, each of the cavities 10C is defined by the surfaces 102 and 103 and the surface 10a2, and the surface 10a2 is also referred to as a bottom surface of the cavities 10C. In some configurations, at least one of the leads 30 is partially exposed by at least one of the cavities 10C or disposed in at least one of the cavities. The encapsulant 10 can be disposed at both sides of at least one of the leads 30.

[0026] In some configurations, the encapsulant 10 includes barrier portions 10R. The barrier portions 10R can be referred to as tapered portions or partition walls. In some configurations, each of the barrier portions 10R can be defined by two cavities 10C. In some configurations, the barrier portions 10R are disposed between the leads 30. In some configurations, the leads 30 are disposed between the barrier portions 10R. The barrier portions 10R can be configured to act as a safety wall to prevent an inter-lead short circuit.

[0027] In some configurations, the barrier portions 10R have side surfaces or end surfaces (e.g., surface 101) facing away from a center region of the semiconductor device package 1. In some configurations, the side surfaces or end surfaces (e.g., surface 101) of the barrier portions 10R taper toward the surface 10al of the encapsulant 10. In some configurations, the side surfaces or end surfaces (e.g., surface 101) of the barrier portions 10R include an upper portion 1011 and a lower portion 1012 that is wider than the upper portion 1011, and the upper portion 1011 has a top surface (e.g., surface 10al) of the encapsulant 10. In some configurations, a roughness of the surface 101 is greater than a roughness of the surface 10al. In some configurations, the surface 101 and the surface 10al of the encapsulant 10 are produced by two different techniques, such that the roughness of the surfaces is different.

[0028] In some configurations, the barrier portion 10R further has a top surface (e.g., surface 10al) connected to the surface 101. In some configurations, the top surface (e.g., surface 10al) of the barrier portion 10R tapers toward the surface 101. In some configurations, the barrier portion 10R includes a first portion that contacts the lead 30 and a second portion that is spaced apart from the lead 30, and the width W2 of the first portion is greater than the width Wl of the second portion. In some configurations, the second portion of the barrier portion 10R having the width Wl has a side surface or an end surface (e.g., surface 101). In some configurations, the side surface or the end surface (e.g., surface 101) of the barrier portion 10R tapers toward the top surface (e.g., surface 10al) of the barrier portion 10R. In some configurations, the side surface or the end surface (e.g., surface 101) of the barrier portion 10R includes an upper portion 1011 and a lower portion 1012 that is wider than the upper portion 1011, and the upper portion 1011 has the top surface (e.g., surface 10al) of the barrier portion 10R.

[0029] In some configurations, the barrier portion 10R further has a side surface or a lateral surface (e.g., surfaces 102 and 103) facing the lead 30. In some configurations, the roughness of the surface 101 is less than the roughness of the surface 102. In some configurations, the roughness of the surface 101 is less than the roughness of the surface 103. In some configurations, the roughness of the surface 101 is greater than the roughness of the surface 10al. In some configurations, the surface 102 includes a curved surface. In some configurations, the surface 103 includes a curved surface. In some configurations, the surface 101 and the surfaces 102 and 103 of the encapsulation body 10 are produced by two different techniques, such that the roughness of the cut surfaces is different. In some configurations, the surface 101 is formed by a mechanical cutting operation, and the surfaces 102 and 103 are formed by an energy-beam ablation operation. The barrier portion 10R can include an organic material, and the heat generated by the energy-beam ablation operation can more severely damage the surfaces 102 and 103 than the damage to the surface 101 by the mechanical cutting operation, so the roughness of the surfaces 102 and 103 is greater than the roughness of the surface 101.

[0030] Die pads 20 can be embedded in or encapsulated by encapsulant 10. Die pads 20 can be exposed from surface 10al of encapsulant 10. Die pads 20 can be disposed in a relatively central region of encapsulant 10. Die pads 20 can be separated from leads 30. Die pads 20 can be made of or include copper, copper alloy, or another suitable metal or metal alloy. In some embodiments, die pads 20 can include copper (Cu), Cu alloy, iron (Fe), Fe alloy, nickel (Ni), Ni alloy, or any other suitable metal or metal alloy, or combinations thereof. Die pads 20 can be configured to, for example, act as a carrier on which electronic components (not shown) are disposed.

[0031] Leads 30 can be embedded in or encapsulated by encapsulant 10. Leads 30 can be exposed from surfaces 10al and 101 of encapsulant 10. Leads 30 can be made of or include copper, copper alloy, or another suitable metal or metal alloy. In some embodiments, leads 30 can include Cu, Cu alloy, Fe, Fe alloy, Ni, Ni alloy, or any other suitable metal or metal alloy, or combinations thereof. Leads 30 can act as solder wettable flanks, which can be used for inspection to ensure the quality of the joint between a semiconductor device package (e.g., semiconductor package structure l) and other electronic components (e.g., motherboard, not shown).

[0032] In some configurations, the leads 30 have surfaces 30al and 30a2 (also referred to as "upper surfaces" or "top surfaces"), a surface 30a3 (also referred to as a "bottom surface"), and surfaces 3011 and 3012 (also referred to as "lateral surfaces"). The surface 30al can be referred to as a top surface or an upper surface of the lead 30, and the surface 30a2 can be referred to as a lower surface of the lead 30. The surfaces 3011 and 3012 can be collectively referred to as lateral surfaces 301 of the lead 30. In some configurations, the surface 30al of the lead 30 is substantially parallel to a top surface (e.g., surface 10al) of the encapsulation 10 (or the barrier portion 10R). In some configurations, the surface 3011 is substantially aligned with a surface 101 of the encapsulation 10. In some configurations, an end surface (e.g., surface 101) of the barrier portion 10R is substantially aligned or coplanar with a lateral surface (e.g., surface 3011) of the lead 30. In some configurations, the barrier portion 10R is disposed between the leads 30 and tapers toward the surface 3011 of at least one of the leads 30. In some configurations, the lead 30 includes a wettable flanking surface. In some configurations, the wettable flanking surface is defined by the surface 3012 and is recessed with respect to the surface 101 of the encapsulation 10 (or the barrier portion 10R). In some configurations, the surface 3012 functions as a wettable flanking surface. In some configurations, one or more of the barrier portions 10R disposed between the leads 30 can extend into one or more of the wettable flanking surfaces (e.g., surface 3012) of one or more of the leads 30. In some configurations, the lead 30 includes a lower portion having an end surface (e.g., surface 3011) that is substantially aligned or coplanar with the surface 101 of the encapsulation 10 (or the barrier portion 10R). In some configurations, the width Wl of the barrier portion 10R is different than the width W3 of the lead 30.

[0033] In some configurations, the lead 30 separates the cavity 10C into gaps Gl and G2 (also referred to as "cavities" or "sub-cavities"). The lead 30 has a side 303 facing the gap Gl and a side 302 facing the gap G2. The side 302 can be opposite the side 303. The side 303 can include surfaces 3031, 3032, and 3033, the surface 3031 can be connected to the surface 30a2, the surface 3032 can be connected to the surface 30al, and the surface 3033 can contact or be covered by the encapsulant 10. The side 302 can include surfaces 3021, 3022, and 3033, the surface 3021 can be connected to the surface 30a2, the surface 3022 can be connected to the surface 30al, and the surface 3023 can contact or be covered by the encapsulant 10. The surface 3011 can extend between the side 302 and the side 303. In some configurations, the encapsulant 10 includes portions (e.g., barrier portions 10R) that are spaced apart from each other and disposed between the leads 30, and the portions (or barrier portions 10R) are spaced apart from the leads 30 by the gap Gl and the gap G2, respectively. The gap Gl can be defined by the surfaces 10a2 and 103 of the encapsulant 10 and the side 303 (or surfaces 3031 and 3032) of the lead 30. The gap G2 can be defined by the surfaces 10a2 and 102 of the encapsulant 10 and the side 302 (or surfaces 3021 and 3022) of the lead 30. In some configurations, the surface 103 defines at least a portion of the gap Gl and includes a curved surface from a top view perspective. In some configurations, the surface 103 defines a curved shape with a top surface of the barrier portion 10R. In some configurations, the surface 102 defines at least a portion of the gap G2 and includes a curved surface from a top view perspective. In some configurations, the barrier portion 10R is spaced apart from the side 303 or the surface 3032 by the gap Gl, and the barrier portion 10R is spaced apart from the side 302 or the surface 3022 by the gap G2. In some configurations, the gaps Gl and G2 are configured to accommodate the solder element 60. In some configurations, the encapsulant 10 and the lead 30 collectively define one or more spaces (e.g., the cavity 10C). The cavity 10C (or the gaps Gl and G2) can be collectively referred to as a gap structure. In some configurations, the space is configured to direct the solder element 60 to flow from the surface 30al along one or more side surfaces (e.g., surfaces 3012, 3022, and 3032) of the lead 30 toward a bottom portion of the space.

[0034] Referring to Figure 1BIn some configurations, the solder elements 60 extend over or along the surfaces 30al, 3012, and 30a2 of the leads 30. In some configurations, the solder elements 60 further cover at least a portion of the surface 3011 of the leads 30. In some configurations, the solder elements 60 include portions that fill or completely fill the gaps G1 and G2. In some configurations, the solder elements 60 contact the surfaces 10al, 102, and 103. In some configurations, the solder elements 60 can partially cover the surfaces 10al and 101 of the encapsulation 10. In some configurations, a portion of the surface 30al of the leads 30 can be exposed by the solder elements 60. Note that a portion of the right solder element 60 is omitted from the figure to show the cross-section 60C1 of the solder elements 60 over the encapsulation 10 and the leads 30.

[0035] According to some configurations of the present disclosure, the barrier portion 10R protrudes from the surface 3012 of the leads 30 such that no gap connecting or communicating adjacent leads 30 is formed before performing a mechanical cutting operation to complete singulation operations for forming the semiconductor device package 1. Thus, the residue of the leads 30 formed during the mechanical cutting operation can be prevented from being driven or carried by the saw blade to extend and connect adjacent leads 30. Therefore, the metal burrs can be prevented from extending between adjacent leads 30, the burr effect can be prevented, and thus short circuits between the leads 30 can be prevented. In view of the above, in the case that the barrier portion 10R effectively prevents the burr effect, the pitch of the leads 30 can be further reduced and / or the distribution density of the leads 30 can be further increased, and the processing tolerance of the singulation operation can be increased, which can further improve yield.

[0036] In addition, according to some configurations of the present disclosure, the surface 101 is substantially aligned or coplanar with the surface 3011 of the leads 30, and the residue from the leads 30 that is originally attached or adhered to the wheel can be scraped off by the surface 101. Therefore, the residue from the leads 30 can be effectively removed from the semiconductor device package 1, the burr effect can thus be prevented, and short circuits between the leads 30 can accordingly be prevented.

[0037] Furthermore, according to some configurations of the present disclosure, the gaps G1 and G2 can accommodate more solder material, thus can enhance the joint strength and prevent short circuit due to excess solder material electrically connecting two adjacent leads 30. Moreover, according to some configurations of the present disclosure, the barrier portion 10R (or surface 10a1) is tapered toward the surface 101, thus the accommodation space provided by the gaps G1 and G2 is increased, which further facilitates enhancing the joint strength between the solder material and the leads 30. In addition, the stepped profile of the leads 30 (e.g., surfaces 3012 and 30a2) can provide a larger area to joint the conductive layer, such as the solder material, thereby increasing the rigidity of the semiconductor device package 1.

[0038] Figure 1C A perspective view of a portion of a semiconductor device package according to some configurations of the present disclosure. In some configurations, Figure 1C is Figure 1 and Figure 1A A perspective view of a portion of the semiconductor device package 1 shown in

[0039] In some configurations, the solder elements 60 are disposed over the surface 30a1 of the leads. Note that a portion of the middle solder element 60 is omitted from the figure to show the cross-section 60C2 of the solder element 60 over the encapsulant 10 and the leads 30, and a portion of the right solder element 60 is omitted from the figure to show the cross-section 60C3 of the solder element 60 over the encapsulant 10 and the leads 30. In some configurations, the solder elements 60 extend over or along the surfaces 30a1, 3012, and 30a2 of the leads 30. In some configurations, the solder elements 60 further cover at least a portion of the surface 3011 of the leads 30. In some configurations, the solder elements 60 include portions that are filled or completely filled in the gaps G1 and G2. In some configurations, the solder elements 60 contact the surfaces 10a1, 102, and 103. In some configurations, the solder elements 60 do not contact the surface 10a1 and the surface 101 of the encapsulant 10. In some configurations, the solder elements 60 completely cover the surface 30a1 of the leads 30.

[0040] Figure 2A A perspective view of a portion of a semiconductor device package according to some configurations of the present disclosure. Figure 2A The structure shown in Figure 1A is similar to the structure in Figure 2A and the differences therebetween are described as follows. In some configurations, Figure 1 The structure shown in Figure 2A may be a portion of the semiconductor device package 1 in Figure 2A Note that the solder elements 60 are omitted from Figure 1B in order to clearly show the structure. Figure 1Csolder element 60 shown in

[0041] In some configurations, surface 3012 is inclined relative to surface 30al of lead 30. In some configurations, surface 30a2 is not parallel to surface 30al of lead 30. In some configurations, surface 30a2 is inclined relative to surface 3011 of lead 30. In some configurations, the upper surface (e.g., surface 30a2) extends between a lateral surface (e.g., surface 3012) and a lateral surface (e.g., surface 3011) of lead 30, and an angle Θ1 defined by the lateral surface (e.g., surface 3012) and the upper surface (e.g., surface 30a2) is greater than 90 degrees. In some configurations, an angle Θ2 defined by a lateral surface (e.g., surface 3012) and a top surface (e.g., surface 30al) of lead 30 is greater than 90 degrees. In some configurations, an angle defined by a lateral surface (e.g., surface 3011) and an upper surface (e.g., surface 30a2) of lead 30 is greater than 90 degrees. In some configurations, surfaces 3012 and 30al define a stepped slope for contacting or engaging a conductive layer, such as a solder material.

[0042] In some configurations, encapsulation 10 and lead 30 collectively define one or more spaces (e.g., or cavities 10C). In some configurations, the space (or cavity 10C) tapers in a direction DR1 from surface 30al of lead 30 toward surface 30a2. In some configurations, the space is configured to direct the flow of solder element from surface 30al along one or more lateral surfaces (e.g., surfaces 3012, 3022, and 3032) of lead 30 toward a bottom portion of the space. In some configurations, surface 101 of encapsulation 10 tapers in a direction DR2 opposite to direction DR1.

[0043] According to some configurations of the disclosure, surface 101 of barrier portion 10R tapers toward surface 10al, gaps G1 and G2 can accommodate more solder material, thus can enhance the strength of the joint between the solder material and lead 30 and prevent short circuit due to excess solder material electrically connecting two adjacent leads 30.

[0044] In addition, according to some configurations of the disclosure, surfaces 3012 and 30al of lead 30 define a stepped slope for contacting or engaging a conductive layer, such as a solder material. This structure can provide a larger area to engage the conductive layer, thereby increasing the hardness of the semiconductor device package.

[0045] Figure 2B Perspective view of a portion of a semiconductor device package according to some configurations of the disclosure. Figure 2B The structure shown in Figure 1A is similar to the structure in Figure 2BThe structure shown in FIG. 1A can be a portion of a semiconductor device package 1 according to some configurations of the present disclosure. Figure 1 The structure shown in FIG. 1A can be a portion of a semiconductor device package 1 according to some configurations of the present disclosure. Figure 2B The solder element 60 shown in FIG. 1A can be omitted in FIG. 1B. Figure 2B The structure shown in FIG. 1A can be a portion of a semiconductor device package 1 according to some configurations of the present disclosure. Figure 1B The structure shown in FIG. 1A can be a portion of a semiconductor device package 1 according to some configurations of the present disclosure. Figure 1C The solder element 60 shown in FIG. 1A can be omitted in FIG. 1B.

[0046] In some configurations, the lead 30 includes an extension (also referred to as a "lower portion") having a surface 101 as an end surface and a surface 30a2 as an upper surface. In some configurations, the height of the upper surface (e.g., surface 30a2) of the extension of the lead 30 increases toward the surface 103 of the encapsulant 10. In some configurations, the height of the upper surface (e.g., surface 30a2) of the extension of the lead 30 increases toward the gap Gl.

[0047] In some configurations, the barrier portion 10R and the side 303 of the lead 30 define a gap Gl (or cavity), and the extension of the lead 30 is partially disposed in the gap Gl (or cavity). In some configurations, the extension of the lead 30 tapers toward the gap Gl (or cavity). In some configurations, the extension of the lead 30 further covers a corner portion of the surface 101 adjacent to the gap Gl. In some configurations, the extension of the lead 30 contacts the surface 103 of the encapsulant 10. In some configurations, a gap G2 (or cavity) is located between the surface 102 of the encapsulant 10 and the side 302 of the lead 30. In some configurations, the gaps Gl and G2 are on opposite sides of the lead 30. In some configurations, the extension of the lead 30 is spaced apart from the surface 102 of the encapsulant 10. In some configurations, the height of the upper surface (e.g., surface 30a2) of the extension of the lead 30 increases toward the gap Gl (or cavity) relative to a bottom surface (e.g., surface 10a2) of the gap Gl (or cavity).

[0048] The cavity 10C (or gaps Gl and G2) can be collectively referred to as a gap structure. In some configurations, the lead 30 includes a portion 30A (also referred to as a "flash" or "projection") that extends into the gap Gl (or gap structure). The extension of the lead 30 can include the portion 30A (or flash).

[0049] Figure 2C A perspective view of a portion of a semiconductor device package according to some configurations of the present disclosure. Figure 2C The structure shown in FIG. 1A can be a portion of a semiconductor device package 1 according to some configurations of the present disclosure. Figure 1A The structure shown in FIG. 1A can be a portion of a semiconductor device package 1 according to some configurations of the present disclosure. Figure 2C The structure shown in FIG. 1A can be a portion of a semiconductor device package 1 according to some configurations of the present disclosure. Figure 1 The structure shown in FIG. 1A can be a portion of a semiconductor device package 1 according to some configurations of the present disclosure. Figure 2C The solder element 60 shown in FIG. 1A can be omitted in FIG. 1B.Figure 2C The structure shown in may include Figure 1B or Figure 1C The solder element 60 is shown in FIG.

[0050] Cavity 10C (or gaps G1 and G2) may be collectively referred to as a gap structure. In some configurations, lead 30 includes a portion 30A (also referred to as a "protrusion") extending into gaps G1 and G2 (or gap structure). The extension of lead 30 may include portions 30A and 30B (also referred to as "burrs"). In some configurations, portion 30A (or burrs) extends into gap G1, and portion 30B (or burrs) extends into gap G2. In some configurations, the area of ​​portion 30A (or burrs) is different from the area of ​​portion 30B (or burrs) in the cross-sectional view. In some configurations, the height of portion 30A is higher than the height of portion 30B relative to surface 10a3 (or bottom surface) of lead 30. In some configurations, two or more of leads 30 may each have portions 30A and 30B, and portions 30A of leads 30 extend in the same direction.

[0051] In some configurations, the semiconductor device package further includes a plating 31 positioned over the extension of the lead 30. In some configurations, the plating 31 has a lateral surface 311 that is substantially aligned with or coplanar with a lateral surface of the lead 30 (e.g., surface 3011). In some configurations, the plating 31 is partially disposed in or extends into the gap G1 (or cavity). In some configurations, the plating 31 is partially disposed in or extends into the gap G2 (or cavity). The plating 31 may be made of or include tin (Sn), antimony (Sb), silver (Ag), nickel (Ni), palladium (Pd), gold (Au), or a combination thereof. The plating 31 may be made of or include a material having higher solder wettability than the lead 30.

[0052] In some configurations, the plating 31 covers the lead 30, with the surface 3011 of the lead 30 exposed by the plating 31. In some configurations, the upper surface 31a2 of the plating 31 gradually narrows toward the gap G1. In some configurations, the lateral surface 3112 of the plating 31 is recessed relative to the surface 3011 of the lead 30. In some configurations, the upper surface 31a1 of the plating 31 is substantially aligned with the surface 10a1 of the encapsulation body 10 (or barrier portion 10R). In some configurations, the plating 31 further covers the sides 302 and 303 of the lead 30.

[0053] In some configurations, the roughness of the lateral surface 311 is greater than the roughness of the upper surface 31a2. In some configurations, the roughness of the lateral surface 311 is greater than the roughness of the lateral surface 3112. In some configurations, the roughness of the lateral surface 311 is greater than the roughness of the upper surface 31a1. The surface 311 of the plating layer 31 can be formed by a mechanical cutting operation and thus have an increased roughness.

[0054] In some configurations, the roughness of the surface 3011 of the lead 30 is greater than the roughness of the upper surface 31a2 of the plating layer 31. In some configurations, the roughness of the surface 3011 of the lead 30 is greater than the roughness of the lateral surface 3112 of the plating layer 31. In some configurations, the roughness of the surface 3011 of the lead 30 is greater than the roughness of the upper surface 31a1 of the plating layer 31. The surface 3011 of the lead 30 may be formed by a mechanical cutting operation and thus has a relatively greater roughness than the surfaces 30a2, 3112, and 31a1.

[0055] Figure 3A is a top view of a portion of a semiconductor device package according to some configurations of the present disclosure. Figure 3A The structure shown in Figure 1A The structure shown in FIG is similar to that shown in FIG, and the differences therebetween are described below. In some configurations, Figure 3A The structure shown in Figure 1 A portion of a semiconductor device package 1 is shown. Note that for clarity, the Figure 3A The solder element 60 is omitted. Figure 3A The structure shown in may include Figure 1B or Figure 1C The solder element 60 is shown in FIG.

[0056] In some configurations, the semiconductor device package includes at least leads 30, 30', and 30". In some configurations, the encapsulation body 10 includes barrier portions 10R and 10R' spaced apart from each other. In some configurations, a width W1 of the barrier portion 10R is different from a width W1' of the barrier portion 10R'. In some configurations, the barrier portion 10R is between the leads 30 and 30", and the barrier portion 10R' is between the leads 30 and 30'. In some configurations, the barrier portion 10R (or the second portion of the barrier portion 10R) is spaced apart from the lead 30 by a distance D2, and the barrier portion 10R is spaced apart from the lead 30″ by a distance D1 that is different from the distance D2. In some configurations, the barrier portion 10R′ (or the second portion of the barrier portion 10R′) is spaced apart from the lead 30 by a distance D3, and the barrier portion 10R′ is spaced apart from the lead 30′ by a distance D4 that is different from the distance D3. In some configurations, the lead 30 is spaced apart from the barrier portion 10R by a distance D2, and the lead 30 is spaced apart from the barrier portion 10R′ by a distance D3 that is different from the distance D2. In some configurations, the distances D1, D2, D3, and D4 may be referred to as the widths of gaps G2a, G1, G2, and G1b, respectively.

[0057] In some configurations, side 303 (or surface 3032) of lead 30 is exposed to gap G1 for a length L2, and side 302 (or surface 3022) of lead 30 is exposed to gap G2 for a length L3 that is different from length L2. In some configurations, lead 30' is exposed to gap G1b for a length L4 that is different from length L3. In some configurations, lead 30' is further exposed to gap G2b for a length that is different from length L4. In some configurations, lead 30" is exposed to gap G2a for a length L1 that is different from length L2. In some configurations, lead 30" is further exposed to gap G1a for a length that is different from length L1. In some configurations, lengths L1, L2, L3, and L4 may be referred to as the lengths of gaps G2a, G1, G2, and G1b, respectively. In some configurations, length L30 of lead 30 is greater than at least one of the lengths of the gaps. In some configurations, length L30 of lead 30 is greater than the length of a gap.

[0058] In some configurations, the differences in lengths L1 , L2 , L3 , and L4 and the differences in distances D1 , D2 , D3 , and D4 may be caused by misalignment of the energy beam ablation region with the location of lead 30 .

[0059] Figure 3B is a top view of a portion of a semiconductor device package according to some configurations of the present disclosure. Figure 3B The structure shown in Figure 3A The structures shown in are similar, and the differences therebetween are described below. In some configurations, Figure 3B The structure shown in Figure 1part of semiconductor device package 1 according to some configurations of the present disclosure. Note that solder elements 60 are omitted in Figure 3B Figure 3B the structure shown in FIG. 1 1 can include Figure 1B or Figure 1C solder elements 60 shown in FIG. 1 1.

[0060] In some configurations, referring to Figure 2A surface 3012 is inclined with respect to surface 30a1 of lead 30.

[0061] Figure 3C is a cross-section of a portion of a semiconductor device package according to some configurations of the present disclosure. Figure 3C the structure shown in FIG. 1 1 is similar to a portion of the structure shown in FIG. 1 1, and the differences therebetween are described as follows. In some configurations, Figure 1A the structure shown in FIG. 1 1 can be Figure 3C part of semiconductor device package 1 according to some configurations of the present disclosure. Note that solder elements 60 are omitted in Figure 1 Figure 3C Figure 3C the structure shown in FIG. 1 1 can include Figure 1B or Figure 1C solder elements 60 shown in FIG. 1 1.

[0062] In some configurations, the extensions of lead 30 are disposed in gaps G1, G1 a and G1 b, respectively, partially. In some configurations, the extensions of lead 30 are tapered toward gaps G1, G1 a and G1 b, respectively. In some configurations, the extensions of lead 30 are spaced apart from surface 102 of encapsulant 10. In some configurations, a height of an upper surface (e.g., surface 30a2) of at least one of the extensions of lead 30 increases toward gap G1, G1 a and / or G1 b with respect to a bottom surface (e.g., surface 10a2) of gap G1, G1 a and / or G1 b.

[0063] Figure 3D is a cross-section of a portion of a semiconductor device package according to some configurations of the present disclosure. Figure 3D the structure shown in FIG. 1 1 is similar to the structure shown in FIG. 1 1, and the differences therebetween are described as follows. In some configurations, Figure 3C the structure shown in FIG. 1 1 can be Figure 3D part of semiconductor device package 1 according to some configurations of the present disclosure. Note that solder elements 60 are omitted in Figure 1 Figure 3D Figure 3D the structure shown in FIG. 1 1 can include Figure 1B or Figure 1C solder elements 60 shown in FIG. 1 1.

[0064] ​​​​​In some configurations, the semiconductor device package further includes platings 31, 31', and 31" over the extensions of leads 30, 30', and 30", respectively. In some configurations, plating 31 tapers toward surfaces 102 and 103 of encapsulant 10 in the cross-sectional view. In some configurations, plating 31 includes portions 31A and 31B that extend into gaps Gl and G2. In some configurations, plating 31' is partially disposed in gap Glb and spaced apart from surface 103 by a portion of lead 30'. In some configurations, plating 31' includes portions 31A and 31B that extend into gaps Glb and G2b. In some configurations, plating 31' contacts the bottom surface of gap G2b. In some configurations, plating 31" contacts surfaces 102 and 103 of encapsulant 10. In some configurations, plating 31" includes portions 31A and 31B that extend into gaps Gl a and G2a.

[0065] Figure 4A A scanning electron micrograph image of a portion of a semiconductor device package according to some embodiments of the disclosure is shown. In some configurations, Figure 4A the structure shown in Figure 1 may be a portion of semiconductor device package 1 in Figure 4A . Note that solder elements 60 are omitted in Figure 4A for clarity. Figure 1B the structure shown in Figure 1C may include solder elements 60 shown in

[0066] In some configurations, lead 30 has an upper portion that protrudes above surface 3012. The upper portion can include surface 30al as a top surface. In some configurations, surfaces 3012 and 30a2 are sloped surfaces that are not perpendicular to surface 30al. In some configurations, surface 30a2 has a non-uniform width. In some configurations, surface 103 and surface 102 of encapsulant 10 (not shown in Figure 4A ) are rough surfaces.

[0067] Figure 4B A scanning electron micrograph image of a portion of a semiconductor device package according to some embodiments of the disclosure is shown. In some configurations, Figure 4B the structure shown in Figure 1 may be a portion of semiconductor device package 1 in Figure 4A . Note that solder elements 60 are omitted in Figure 4A for clarity. Figure 1B the structure shown in Figure 1C may include solder elements 60 shown in

[0068] In some configurations, a portion of the lead 30 is exposed by the plating layer 31 and protrudes upward in the gap Gl. In some configurations, a portion of the plating layer 31 is disposed in the gap G2. In some configurations, the plating layer 31 has a non-uniform thickness.

[0069] Figure 5 , Figure 5A , Figure 5B , Figure 6 , Figure 6A , Figure 6B , Figure 7 , Figure 7A and Figure 7B illustrate various stages of an exemplary method for fabricating a semiconductor device package according to some embodiments of the present disclosure.

[0070] Referring to Figure 5 , a package structure including two or more non-isolated semiconductor device package units can be provided. Each of the semiconductor device package units can include a die pad 20 and a plurality of leads 30. The package structure can include an encapsulation material 100 encapsulating the die pad 20 and the leads 30. In some configurations, a surface 30al (or a top surface) of the lead 30 is exposed by the encapsulation material 100.

[0071] Referring to Figure 5A and Figure 5B , Figure 5A is a cross-section along line 5A-5A' in Figure 5 , and Figure 5B is a cross-section along line 5B-5B' in Figure 5 . The semiconductor device package unit can include a semiconductor device 40 and a plurality of wires 50. The semiconductor device 40 can be disposed on the die pad 20. The semiconductor device 40 can include an integrated circuit (IC). The wires 50 can be disposed on the semiconductor device 40. The wires 50 can be configured to electrically connect the semiconductor device 40 with the leads 30. The wires 50 can include or be made of one or more metallic materials, such as copper (Cu), silver (Ag), aluminum (Al), gold (Au), or alloys thereof. The encapsulation material 100 can cover the semiconductor device 40 and the wires 50. The die pad 20 and the leads 30 can be exposed by an upper surface 100a of the encapsulation material 100.

[0072] Referring to Figure 6 , Figure 6A and Figure 6B , Figure 6A is a cross-section along line 6A-6A' in Figure 6 , and Figure 6B is a cross-section along line 6B-6B' in Figure 6 .

[0073] A first singulation operation can be performed to half-cut the package structure. In some configurations, an energy beam ablation operation is performed to half-cut the package structure from the upper surface 100a of the encapsulation material 100, thereby forming a plurality of recesses r1. The recesses r1 can be formed between two adjacent semiconductor device package units. The recesses r1 can surround a periphery of each of the semiconductor device package units. In some configurations, the recesses r1 are spaced apart from each other by portions of the encapsulation material 100. In some configurations, each or two of the leads 30 are partially exposed by one of the recesses r1. In some configurations, the recesses r1 expose portions of the leads 30 without connecting or communicating side surfaces (e.g., sides 302 and 303) of adjacent leads 30. In some configurations, portions of the upper surface 100a are irradiated to remove portions of the encapsulation material 100 by an energy beam, thereby forming the recesses r1. In some configurations, each of the recesses r1 is formed by an energy beam. In some configurations, the recesses r1 are formed one by one along a periphery of each of the semiconductor device package units. In some configurations, the energy beam is applied on the lead regions but not on the continuous edge regions of the semiconductor device package units. The energy beam can be a laser beam, such as an ultraviolet (UV) laser beam, which can have a wavelength of about 200 nm, but is not limited thereto. The kind and intensity of the energy beam can be selected depending on the materials of the encapsulation material 100 and the leads 30, such that the energy beam can remove the target material. In some configurations, the energy beam can remove portions of the encapsulation material 100 without damaging or almost damaging the leads 30. After performing the energy beam ablation operation, the surfaces 102 and 103 of the encapsulation material 100 are exposed to the recesses r1. In some configurations, the surfaces 3012, 3022, and 3032 of the leads 30 are exposed to the recesses r1.

[0074] The energy beam ablation operation can have different selectivity to the encapsulation material 100 and the leads 30. Thus, the leads 30 can be partially exposed by the encapsulation material 100. After performing the energy beam ablation operation, the leads 30 can have three lateral surfaces (e.g., surfaces 3012, 3022, and 3032) exposed to the recesses r1. The surfaces 102 and 103 of the encapsulation material 100 formed by the energy beam ablation operation can have a greater roughness. Thus, the surfaces 102 and 103 of the encapsulation body 10 can be rough surfaces as shown in Figure 4A .

[0075] In some configurations, the energy beam ablation operation can further remove portions of the encapsulation material 100 such that the recesses r1 can have a greater depth. In some configurations, the lateral surfaces (e.g., surfaces 3021 and 3031) of the leads 30 can be exposed from the recesses r1. Figure 1A

[0076] Referring to Figure 7 , Figure 7A and​Figure 7B , Figure 7A is a cross-section along line 7A-7A' in Figure 7 and Figure 7B is a cross-section along line 7B-7B' in Figure 7 .

[0077] A second singulation operation can be performed to separate the semiconductor device package units across the recess r1, thereby forming the semiconductor device package 1. In some configurations, the second singulation operation can remove portions of the encapsulation material 100 and portions of the leads 30. In some configurations, the second singulation operation can include a mechanical cutting operation. In some configurations, the mechanical cutting operation can include using a mechanical cutting tool 700, such as a saw blade, to cut the encapsulation material 100 and the leads 30. The mechanical cutting tool 700 can be a cutting wheel, a wheel segment, or the like. After performing the second singulation operation, a surface 101 (or lateral surface) of the encapsulation body 10 can be formed, and a surface 3011 of the leads 30 can be formed from and exposed by the surface 101 of the encapsulation body 10. The width (or aperture) of the recess r1 is greater than the width (or distance) of the gap between the surfaces 101 of the encapsulation body 10 adjacent the semiconductor device package 1.

[0078] In some configurations, a cutting wheel or wheel segment is used as the mechanical cutting tool 700 to cut through the package structure across the recess r1, thereby separating the semiconductor device package 1. In some configurations, the mechanical cutting tool 700 (or wheel segment) cuts through the recess r1 with the blade rotating in the direction DR1. In some configurations, referring to Figures 1A to 2C , the gaps G1 and G2 formed by the recess r1 are spaced apart from each other by a barrier portion 10R of the encapsulation body 10 formed by the mechanical cutting tool 700, and the residue from the leads 30 formed during the mechanical cutting operation can extend into the gaps G1 and G2, thus the residue from the leads 30 are spaced apart from each other by the barrier portion 10R formed by mechanically cutting the encapsulation material 100 across the recess r1. In some configurations, referring to Figure 2B and 2C , the extensions of the leads 30 partially disposed in the gap G1 and optionally in the gap G2 can be formed from the residue from the leads 30 and extend into the gaps G1 and G2 during the mechanical cutting operation.

[0079] In some configurations, referring to Figure 7 and Figure 2BWhen the lead 30 is cut by the mechanical cutting tool 700 (or wheel), due to the ductile nature of the metal material (e.g., Cu) of the lead 30, metal burrs may be generated and extend in the direction of blade rotation DR1. Consequently, the extended portion of the lead 30 may include a portion formed by the metal burrs and partially filling the gap G1, and the portion in the gap G1 may protrude upward due to the direction of blade rotation DR1. Furthermore, due to the direction of blade rotation DR1, less residue from the lead may accumulate in the gap G2.

[0080] In some configurations, an electroplating process may be performed to deposit plating on exposed surfaces (eg, Figure 6 30a1, 3012, 3022 and 3033) shown in FIG. Figure 2C , and the singulation operation further includes cutting the plating layer 31 to form a surface 311 of the plating layer 31 exposed at a gap created by the cutting.

[0081] In some configurations, see Figure 7 and Figure 2C When the lead 30 and the plating 31 covering the lead 30 are cut by the mechanical cutting tool 700 (or wheel), due to the ductile nature of the metal material (e.g., Cu) of the lead 30 and plating 31, metal burrs may be generated and extend in the direction of blade rotation DR1. Consequently, the extended portion of the lead 30 may include a portion formed by the metal burrs and partially filling the gap G1, and the plating 31 may also include a portion formed by the metal burrs and partially filling the gap G1. In some configurations, the portion of the lead 30 and plating 31 in the gap G1 may protrude upward due to the direction of blade rotation DR1. Additionally, due to the direction of blade rotation DR1, less residue from the lead may accumulate in the gap G2. In some configurations, the metal burrs formed by the lead 30 and plating 31 and filling the gap G1 protrude upward, while the metal burrs formed by the lead 30 and plating 31 and filling the gap G2 extend downward.

[0082] In some configurations, solder elements 60 may be disposed or formed on leads 30 .

[0083] In some cases where two singulation operations are performed using a saw blade, the lateral surfaces of the leads can have a burr defect (e.g., a metal burr) caused by residues from the leads adhering to the saw blade, especially during the first singulation operation (i.e., the half-cut operation). For example, when a gap is formed between the leads after the first singulation operation (e.g., the half-cut operation), residues from the leads can be further formed during the second singulation operation, and these residues can adhere to the saw blade and be driven or carried by the saw blade to further extend into the gap between the adjacent leads. The residues can be referred to as a burr defect, which can undesirably connect the adjacent leads and cause a short circuit between the leads.

[0084] According to some configurations of the present disclosure, an energy beam ablation operation is used to replace the first singulation operation to half-cut the package structure, thereby reducing the residue formation of the leads 30 and adhesion on the saw blade, so that no or less burr defect is formed on the lateral surfaces (e.g., the surfaces 3011) of the leads 30.

[0085] In addition, according to some configurations of the present disclosure, the first singulation operation for half-cutting the package structure forms a plurality of grooves r1, which are spaced apart from each other by the portions of the encapsulation material 100, such that no gap is formed to connect the adjacent leads 30 during the first singulation operation. Thus, the residues of the leads 30 formed during the second singulation operation (e.g., the mechanical cutting operation) can be prevented from being driven or carried by the saw blade to extend and connect the adjacent leads 30. Therefore, the metal burr can be blocked from extending between the adjacent leads 30, the burr effect can be prevented, and thus the short circuit between the leads 30 can be prevented. In view of the above, the distance between the leads 30 can be further reduced, and / or the distribution density of the leads 30 can be further increased, the portions of the encapsulation material 100 formed by the grooves r1 effectively prevent the burr effect, and the processing tolerance of the singulation operation can be increased, which can further increase the yield.

[0086] Furthermore, according to some configurations of the present disclosure, the surface 101 of the encapsulation material 100 and the surface 3011 of the leads 30 are formed by the same mechanical cutting operation that cuts through the encapsulation material 100 of the grooves r1, and the portions of the surface 101 between the grooves r1 protrude beyond the surface 3012 of the leads 30. Therefore, the residues of the leads 30 that are originally attached or adhered to the saw blade can be scraped off by the protruding surface 101. Thus, the residues from the leads 30 can be effectively removed from the semiconductor device package 1, the burr effect can be prevented, and the short circuit between the leads 30 can be accordingly prevented.

[0087] Further, according to some configurations of the present disclosure, the gaps G1 and G2 formed by the recesses r1 are spaced apart from each other by the barrier portion 10R of the encapsulation 10 formed by the mechanical cutting tool 700. Thus, the barrier portion 10R can be configured as a safety wall to prevent inter-lead short during the singulation operation, and the residues of the leads 30 formed during the mechanical cutting operation can extend into the gaps G1 and G2, thus the residues of the leads 30 can be spaced apart from each other by the barrier portion 10R formed by mechanically cutting through the encapsulation material 100 of the recesses r1. Thus, the burr effect can be prevented, and the short between the leads 30 can be accordingly prevented. In addition, the residues in the gaps G1 and G2 can provide a greater area for the joining of a conductive layer, such as a solder material, and thus the hardness of the semiconductor device package can be further enhanced.

[0088] Unless otherwise defined, spatial descriptions, such as, for example, "above", "below", "upper", "left", "right", "down", "top", "bottom", "vertical", "horizontal", "side", "higher", "lower", "upper", "on", "under", etc., are indicated with respect to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for purposes of illustration only and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the advantages of embodiments of the present disclosure are not deviated by such arrangements.

[0089] As used herein, the terms "approximately", "substantially", "generally", and "about" are used to describe and account for small variations. When used in connection with an event or circumstance, these terms can refer to instances in which the event or circumstance occurs exactly, as well as instances in which the event or circumstance occurs in close proximity. For example, when used in connection with a numerical value, these terms can refer to a range of variation of less than or equal to ±10% of the stated numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, a first numerical value can be considered "substantially" the same as or equal to a second numerical value if the first numerical value is within a range of variation of less than or equal to ±10% of the second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, "substantially" vertical can refer to a range of angular variation of less than or equal to ±10° from 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0090] Two surfaces can be considered coplanar or substantially coplanar if the amount of displacement between the two surfaces is no more than 5 pm, no more than 2 pm, no more than 1 pm, or no more than 0.5 pm. A surface can be considered substantially flat if the amount of displacement between the highest point and the lowest point of the surface is no more than 5 pm, no more than 2 pm, no more than 1 pm, or no more than 0.5 pm.

[0091] As used herein, the singular forms "a," "an," and "the" can include plural referents unless the context clearly dictates otherwise.

[0092] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to transport an electric current. A conductive material generally refers to a material that presents little or no resistance to the flow of electric current. One unit of measure of conductivity is the siemens per meter (S / m). Generally, a conductive material is one that has a conductivity greater than about 10 4 S / m, such as at least 10 5 S / m, or at least 10 6 S / m. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0093] Further, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood as having been followed by the term "and more specifically" followed by a description of each numerical value and sub-range being specifically encompassed by the range. It will further be understood that all references given herein are based on unrounded values and that, as a result, a little variation in the numerical value of the refened-to value is accepted.

[0094] While the disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not intended to be limiting. Those skilled in the art will appreciate that various modifications can be made to the processes described and illustrated herein, and that such modifications are intended to fall within the true spirit and scope of the present disclosure, as defined by the following claims. The drawings can not be drawn to scale. Variations in processes reproducing the present disclosure in actual devices can occur as a result of manufacturing processes and tolerances. There can be other embodiments of the disclosure not specifically illustrated. The specification and drawings are, accordingly, to be regarded simply as illustrative and not restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims. While the disclosed methods have been described herein with reference to particular operations performed in a particular order, it will be understood that these operations can be combined, sub-divided, or re-ordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of operations are not a limitation of the present disclosure.

Claims

1. A semiconductor device package comprising: a plurality of leads including a first lead; an encapsulation disposed at both sides of the first lead; and a solder element disposed over a top surface of the first lead; wherein in a cross-sectional view, the first lead and the encapsulation collectively define a space that tapers in a first direction from the top surface toward a lower surface of the first lead, and the space is configured to direct the solder element to flow from the top surface along a first lateral surface of the first lead toward a bottom portion of the space.

2. The semiconductor device package of claim 1, wherein the encapsulation has lateral surfaces that taper in a second direction opposite the first direction.

3. The semiconductor device package of claim 2, wherein the first lead further has a second lateral surface that is substantially coplanar with the lateral surfaces of the encapsulation.

4. The semiconductor device package of claim 3, wherein the first lateral surface of the first lead is recessed relative to the lateral surfaces of the encapsulation.

5. The semiconductor device package of claim 1, wherein an angle defined by the first lateral surface and the lower surface of the first lead is greater than 90 degrees.

6. The semiconductor device package of claim 5, wherein an angle defined by the first lateral surface and the top surface of the first lead is greater than 90 degrees.

7. The semiconductor device package of claim 6, wherein the solder element extends over the top surface, the first lateral surface, and the lower surface of the first lead.

8. The semiconductor device package of claim 7, wherein the first lead further has a second lateral surface, the lower surface extends between the first lateral surface and the second lateral surface, and the solder element further covers at least a portion of the second lateral surface of the first lead.

9. A semiconductor device package comprising: a plurality of leads including a first lead having a first lateral surface and a second lateral surface opposite the first lateral surface; and a first barrier portion disposed between the leads and spaced apart from the first lateral surface and the second lateral surface by a first gap and a second gap, respectively, the first gap and the second gap configured to accommodate a solder element, wherein the first gap has a first width and the second gap has a second width less than the first width.

10. The semiconductor device package of claim 9, further comprising a second barrier portion disposed between the leads and spaced apart from the first barrier portion, wherein a width of the first barrier portion is different than a width of the second barrier portion.

11. The semiconductor device package of claim 9, wherein the first gap has a first length and the second gap has a second length different than the first length.

12. The semiconductor device package of claim 11, wherein a length of the first lead is greater than at least one of the first length and the second length. ​ 13. The semiconductor device package of claim 9, wherein the first lead further has a third lateral surface extending between the first lateral surface and the second lateral surface, a first lateral surface of the first barrier portion is substantially coplanar with the third lateral surface of the first lead, and a top surface of the first barrier portion tapers toward the first lateral surface of the first barrier portion.

14. The semiconductor device package of claim 13, wherein the first barrier portion further has a second lateral surface defining at least a portion of the first gap, and the second lateral surface further defines a curved shape with the top surface of the first barrier portion.

15. The semiconductor device package of claim 14, wherein a roughness of the second lateral surface of the first barrier portion facing the first lead is greater than a roughness of the first lateral surface of the first barrier portion.

16. The semiconductor device package of claim 14, wherein a roughness of the second lateral surface of the first barrier portion facing the first lead is greater than a roughness of the top surface of the first barrier portion.

17. A semiconductor device package, comprising: a plurality of leads including a first lead; and an encapsulation body including a first portion and a second portion spaced apart from the first portion, wherein the first portion and the second portion are disposed between and spaced apart from the leads by a first gap and a second gap, respectively; wherein the first lead includes a first flash extending into the first gap and a second flash extending into the second gap, and in a cross-sectional view, an area of the first flash is different than an area of the second flash.

18. The semiconductor device package of claim 17, wherein a height of the first flash is higher than a height of the second flash relative to a bottom surface of the first lead.

19. The semiconductor device package of claim 18, wherein the plurality of leads further includes a second lead different from the first lead, the second lead including a third flash and a fourth flash extending into a third gap and a fourth gap, respectively, and the first flash of the first lead and the third flash of the second lead extend toward substantially the same direction.

20. The semiconductor device package of claim 17, further comprising a plating layer over the first lead, and a lateral surface of the plating layer is substantially coplanar with a lateral surface of the first lead.

Images