Phase-locked loop
By arranging the signal interfaces of the phase frequency detector and charge pump in the phase-locked loop in a one-to-one correspondence and arranging the MOS transistors of the charge pump in a row, the problem of module interface disorder was solved, and the signal quality and phase-locking effect of the phase-locked loop were improved.
Patent Information
- Application Number
- CN202410457531.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-16
- Publication Date
- 2025-10-24
AI Technical Summary
In existing phase-locked loops, the interfaces of modules such as phase frequency detectors, charge pumps, and oscillators are disordered, resulting in a chaotic wiring layout that affects signal quality and phase-locking performance.
By arranging the signal interfaces of the phase frequency detector and the charge pump in a one-to-one correspondence, and arranging the MOS transistors of the charge pump in a row, the consistency of the external and internal layout of the module is improved, ensuring the accuracy of signal transmission.
This improved the quality of the generated voltage-controlled signal, enhanced the phase-locking effect of the phase-locked loop, reduced wiring difficulty, and saved costs.
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Figure CN120834810A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the field of electronic technology, in particular, to a phase-locked loop. BACKGROUND
[0002] A phase-locked loop (PLL) is a circuit system used to achieve frequency and phase locking and tracking between an input signal and a reference signal generated by a local oscillator. The basic principle is to continuously adjust the frequency and phase of the local oscillator so that it remains synchronized with the input signal, thereby achieving stable and accurate frequency synthesis, clock synchronization and signal modulation functions.
[0003] In related technologies, the modules of the phase frequency detector, charge pump and oscillator constituting the phase-locked loop are divided, although interfaces are left for connection after division, the interfaces of different modules are disordered, the layout of the connection lines between different modules is chaotic, consistency is not high, which leads to poor quality of generated signals, and further affects the phase-locked effect of the phase-locked loop. SUMMARY
[0004] The purpose of the present disclosure is to provide a phase-locked loop to solve the problems in the related art.
[0005] In order to achieve the above purpose, the present disclosure provides a phase-locked loop, which comprises a phase frequency detector, a charge pump and an oscillator, the phase frequency detector, the charge pump and the oscillator are connected in sequence, and the oscillator is connected with the phase frequency detector; The plurality of signal interfaces of the phase frequency detector and the plurality of signal interfaces of the charge pump are one-to-one corresponding according to the arrangement order, wherein a plurality of MOS tubes in the charge pump are arranged in a line; The phase frequency detector is configured to determine the phase difference and the frequency difference between the input signal and the feedback signal according to the input signal and the feedback signal, obtain a difference signal and transmit the difference signal to the charge pump through the plurality of signal interfaces of the phase frequency detector; The charge pump is configured to receive the difference signal through the plurality of signal interfaces of the charge pump, and generate a voltage-controlled signal according to the difference signal; The oscillator is configured to control the frequency of an output signal according to the voltage-controlled signal, so as to generate the feedback signal according to the output signal and transmit the feedback signal to the phase frequency detector.
[0006] Optionally, the plurality of signal interfaces of the phase frequency detector and the plurality of signal interfaces of the charge pump are aligned according to the arrangement order.
[0007] Optionally, the plurality of signal interfaces of the phase frequency detector comprises a first signal outlet, a second signal outlet, a third signal outlet and a fourth signal outlet, and the plurality of signal interfaces of the charge pump comprises a first signal inlet, a second signal inlet, a third signal inlet and a fourth signal inlet. The first signal outlet, the second signal outlet, the third signal outlet and the fourth signal outlet are respectively aligned with the first signal inlet, the second signal inlet, the third signal inlet and the fourth signal inlet. The first signal outlet is configured to be activated when the input signal leads the feedback signal, the third signal outlet is configured to be activated when the input signal lags the feedback signal, the second signal outlet outputs a signal opposite to the signal output by the first signal outlet, and the fourth signal outlet outputs a signal opposite to the signal output by the third signal outlet.
[0008] Optionally, the first signal outlet and the second signal outlet are arranged adjacently, the third signal outlet and the fourth signal outlet are arranged adjacently, and the second signal outlet and the fourth signal outlet are arranged symmetrically.
[0009] Optionally, the plurality of signal interfaces of the phase frequency detector comprises, in the order of arrangement, the second signal outlet, the first signal outlet, the third signal outlet and the fourth signal outlet; or the first signal outlet, the second signal outlet, the fourth signal outlet and the third signal outlet; or the third signal outlet, the fourth signal outlet, the second signal outlet and the first signal outlet; or the fourth signal outlet, the third signal outlet, the first signal outlet and the second signal outlet.
[0010] Optionally, the charge pump comprises a single charge pump or a double charge pump.
[0011] Optionally, the phase-locked loop further comprises a filter, and the charge pump is connected to the oscillator through the filter. The filter is configured to filter the voltage control signal generated by the charge pump and transmit the filtered voltage control signal to the oscillator.
[0012] Optionally, the phase-locked loop further comprises a frequency divider, and the oscillator is connected to the phase frequency detector through the frequency divider. The frequency divider is configured to divide the output signal of the oscillator to obtain a frequency-divided signal, and transmit the frequency-divided signal to the phase frequency detector as the feedback signal.
[0013] Optionally, the charge pump is arranged in a first preset direction of the phase frequency detector, and the frequency divider is arranged in a second preset direction of the phase frequency detector, the first preset direction of the phase frequency detector and the second preset direction of the phase frequency detector being perpendicular to each other.
[0014] Optionally, the filter is arranged in a first preset direction of the charge pump, and the oscillator is arranged in a second preset direction of the charge pump, the first preset direction of the charge pump and the second preset direction of the charge pump being perpendicular to each other, the first preset direction of the phase frequency detector and the first preset direction of the charge pump being parallel to each other, and the second preset direction of the phase frequency detector and the second preset direction of the charge pump being parallel to each other.
[0015] With the technical solution, the plurality of signal interfaces of the phase frequency detector and the plurality of signal interfaces of the charge pump are one-to-one corresponding in the arrangement order, and the plurality of MOS transistors in the charge pump are arranged in a line. The phase frequency detector is configured to determine the phase difference and the frequency difference between the input signal and the feedback signal according to the input signal and the feedback signal, obtain a difference signal, and transmit the difference signal to the charge pump through the plurality of signal interfaces of the phase frequency detector. The charge pump is configured to receive the difference signal through the plurality of signal interfaces of the charge pump, and generate a voltage control signal according to the difference signal. The oscillator is configured to control the frequency of the output signal according to the voltage control signal, so as to generate the feedback signal according to the output signal and transmit the feedback signal to the phase frequency detector. By one-to-one corresponding the interfaces of the phase frequency detector and the charge pump in the order, the consistency of the external layout of the module is improved, and by arranging the MOS transistors of the charge pump in a line, the consistency of the internal layout of the module is improved, so as to improve the quality of the generated voltage control signal, and further improve the phase locking effect of the phase-locked loop.
[0016] Other features and advantages of the present disclosure will be described in detail in the following detailed description section. BRIEF DESCRIPTION OF DRAWINGS
[0017] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, and are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation on the present disclosure. In the drawings: Figure 1 is a connection diagram of a phase frequency detector and a charge pump.
[0018] Figure 2 is another connection diagram of a phase frequency detector and a charge pump.
[0019] Figure 3 is a distribution diagram of a phase-locked loop.
[0020] Figure 4 is a block diagram of a phase-locked loop according to an exemplary embodiment.
[0021] Figure 5 is a connection diagram of a phase frequency detector and a charge pump according to an exemplary embodiment.
[0022] Figure 6 is another connection diagram of a phase frequency detector and a charge pump according to an exemplary embodiment.
[0023] Figure 7 is a distribution diagram of MOS transistors in a charge pump according to an exemplary embodiment.
[0024] Figure 8 is another distribution diagram of MOS transistors in a charge pump according to an exemplary embodiment.
[0025] Figure 9 is a distribution diagram of a phase-locked loop according to an exemplary embodiment.
[0026] Figure 10 is a comparison diagram of a voltage control signal of a phase-locked loop according to an exemplary embodiment. DETAILED DESCRIPTION
[0027] The specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to illustrate and explain the present disclosure, and are not intended to limit the present disclosure.
[0028] In the following description, the words "first", "second", etc. are used only for the purpose of distinguishing the described objects, and cannot be understood as indicating or implying relative importance, nor indicating or implying an order.
[0029] A phase-locked loop is a circuit system for realizing frequency and phase locking and tracking between an input signal and a reference signal generated by a local oscillator. The basic principle is to continuously adjust the frequency and phase of the local oscillator so that it remains synchronized with the input signal, thereby realizing functions such as stable and accurate frequency synthesis, clock synchronization, and signal modulation.
[0030] In the related art, please refer to Figures 1-3 , the phase frequency detector 11 (PFD), charge pump 12 (CP), oscillator 13, etc. modules constituting the phase-locked loop are divided, although interfaces are left for connection after division, the interfaces of different modules are disordered, the layout of the connection lines between different modules is chaotic, the consistency is not high, which leads to poor quality of the generated signal, and further affects the phase-locked effect of the phase-locked loop.
[0031] The MOS tubes in the charge pump 12 are arranged in a matrix, and each MOS tube is connected to a signal interface of the charge pump 12 through internal wiring of the charge pump 12.
[0032] To solve the above technical problems, the plurality of metal-oxide-semiconductor field-effect transistors (MOS) in the charge pump 12 are arranged in a line according to the one-to-one correspondence of the plurality of signal interfaces of the phase frequency detector 11 and the plurality of signal interfaces of the charge pump 12 in the arrangement order; the phase frequency detector 11 is configured to determine the phase difference and the frequency difference between the input signal and the feedback signal according to the input signal and the feedback signal, obtain a difference signal, and transmit the difference signal to the charge pump 12 through the plurality of signal interfaces of the phase frequency detector 11; the charge pump 12 is configured to receive the difference signal through the plurality of signal interfaces of the charge pump 12, and generate a voltage control signal VC according to the difference signal; and the oscillator 13 is configured to control the frequency of an output signal according to the voltage control signal VC, so as to generate a feedback signal according to the output signal and transmit the feedback signal to the phase frequency detector 11. By arranging the interfaces of the phase frequency detector 11 and the charge pump 12 in a one-to-one correspondence in order, the consistency of the external layout of the module is improved, and by arranging the MOS tubes of the charge pump 12 in a line, the consistency of the internal layout of the module is improved, so as to improve the quality of the generated voltage control signal VC, and further improve the phase locking effect of the phase-locked loop.
[0033] Figure 4 is a block diagram of a phase-locked loop according to an example embodiment, as shown in Figure 4 The phase-locked loop includes a phase frequency detector 11, a charge pump 12, and an oscillator 13, the phase frequency detector 11, the charge pump 12, and the oscillator 13 are connected in sequence, and the oscillator 13 is connected with the phase frequency detector 11.
[0034] The plurality of signal interfaces of the phase frequency detector 11 and the plurality of signal interfaces of the charge pump 12 are in one-to-one correspondence according to the arrangement order.
[0035] It should be understood that the plurality of signal interfaces of the phase frequency detector 11 and the plurality of signal interfaces of the charge pump 12 are in one-to-one correspondence, that is, one signal interface of the phase frequency detector 11 corresponds to one signal interface of the charge pump 12, and the arrangement serial numbers of the corresponding two signal interfaces on the modules to which they belong are the same.
[0036] For example, the plurality of signal interfaces of the phase frequency detector 11 are respectively a first signal outlet OUP, a second signal outlet OUPB, a third signal outlet ODN, and a fourth signal outlet ODNB, the plurality of signal interfaces of the charge pump 12 are respectively a first signal inlet IUP, a second signal inlet IUPB, a third signal inlet IDN, and a fourth signal inlet IDNB, the first signal outlet OUP corresponds to the first signal inlet IUP, the second signal outlet OUPB corresponds to the second signal inlet IUPB, the third signal outlet ODN corresponds to the third signal inlet IDN, and the fourth signal outlet ODNB corresponds to the fourth signal inlet IDNB. If the arrangement order of the plurality of signal interfaces of the phase frequency detector 11 is fourth signal outlet ODNB, first signal outlet OUP, second signal outlet OUPB, and third signal outlet ODN in sequence, the arrangement order of the plurality of signal interfaces of the charge pump 12 is fourth signal inlet IDNB, first signal inlet IUP, second signal inlet IUPB, and third signal inlet IDN in sequence correspondingly.
[0037] Figure 5 Fig. 1 is a connection diagram of a phase frequency detector 11 and a charge pump 12 according to an exemplary embodiment. As shown in Fig. 1, the plurality of signal interfaces of the phase frequency detector 11 and the plurality of signal interfaces of the charge pump 12 are aligned according to the arrangement order. That is, the arrangement order of the plurality of signal interfaces of the phase frequency detector 11 and the plurality of signal interfaces of the charge pump 12 is the same and aligned. Figure 5
[0038] Figure 6 Fig. 2 is another connection diagram of a phase frequency detector 11 and a charge pump 12 according to an exemplary embodiment. As shown in Fig. 2, the plurality of signal interfaces of the phase frequency detector 11 and the plurality of signal interfaces of the charge pump 12 are the same in arrangement but not aligned. Figure 6
[0039] Figure 7 Fig. 3 is a distribution diagram of MOS transistors in a charge pump 12 according to an exemplary embodiment. As shown in Fig. 3, the plurality of MOS transistors in the charge pump 12 are arranged in a line. Figure 7
[0040] The phase frequency detector 11 is configured to determine the phase difference and the frequency difference between the input signal and the feedback signal according to the input signal and the feedback signal, obtain a difference signal, and transmit the difference signal to the charge pump 12 through the plurality of signal interfaces of the phase frequency detector 11.
[0041] The charge pump 12 is configured to receive the difference signal through the plurality of signal interfaces of the charge pump 12, and generate a voltage control signal VC according to the difference signal.
[0042] The oscillator 13 is configured to control the frequency of an output signal according to the voltage control signal VC, and generate the feedback signal according to the output signal and transmit the feedback signal to the phase frequency detector 11.
[0043] The feedback signal is generated according to the output signal and transmitted to the phase frequency detector 11, which can be understood as transmitting the output signal to the phase frequency detector 11 as the feedback signal.
[0044] By sequentially and one-to-one corresponding the interfaces of the phase frequency detector 11 and the charge pump 12, the consistency of the external layout of the module is improved, and by arranging the MOS tubes of the charge pump 12 in a line, the consistency of the internal layout of the module is improved, so as to improve the quality of the generated voltage control signal VC and further improve the phase locking effect of the phase-locked loop.
[0045] In a possible implementation, the plurality of signal interfaces of the phase frequency detector 11 and the plurality of signal interfaces of the charge pump 12 are aligned according to the arrangement order.
[0046] By arranging the plurality of signal interfaces of the phase frequency detector 11 and the plurality of signal interfaces of the charge pump 12 to be aligned according to the arrangement order, the length of the connection line between the signal interfaces of the phase frequency detector 11 and the signal interfaces of the charge pump 12 is shortened, the wiring difficulty is reduced, and the cost is saved.
[0047] In a possible implementation, the plurality of signal interfaces of the phase frequency detector 11 includes a first signal outlet OUP, a second signal outlet OUPB, a third signal outlet ODN, and a fourth signal outlet ODNB, and the plurality of signal interfaces of the charge pump 12 includes a first signal inlet IUP, a second signal inlet IUPB, a third signal inlet IDN, and a fourth signal inlet IDNB.
[0048] The first signal outlet OUP, the second signal outlet OUPB, the third signal outlet ODN, and the fourth signal outlet ODNB are respectively aligned with the first signal inlet IUP, the second signal inlet IUPB, the third signal inlet IDN, and the fourth signal inlet IDNB; The first signal outlet OUP is used to be activated when the input signal leads the feedback signal, the third signal outlet ODN is used to be activated when the input signal lags behind the feedback signal, the output signal of the second signal outlet OUPB is the inverse signal of the output signal of the first signal outlet OUP, and the output signal of the fourth signal outlet ODNB is the inverse signal of the output signal of the third signal outlet ODN.
[0049] In a possible implementation, the first signal outlet OUP and the second signal outlet OUPB are arranged adjacent to each other, the third signal outlet ODN and the fourth signal outlet ODNB are arranged adjacent to each other, and the second signal outlet OUPB and the fourth signal outlet ODNB are symmetrically arranged.
[0050] It should be understood that in the case of four signal outlets, the first and fourth are symmetrically arranged with each other, and the second and third are symmetrically arranged with each other.
[0051] The second signal outlet OUPB and the fourth signal outlet ODN are symmetrically arranged. It can be understood that when the arrangement order of the second signal outlet OUPB is the first, the arrangement order of the fourth signal outlet ODN is the fourth, when the arrangement order of the second signal outlet OUPB is the second, the arrangement order of the fourth signal outlet ODN is the third, when the arrangement order of the second signal outlet OUPB is the third, the arrangement order of the fourth signal outlet ODN is the second, and when the arrangement order of the second signal outlet OUPB is the fourth, the arrangement order of the fourth signal outlet ODN is the first.
[0052] For example, the plurality of signal interfaces of the phase frequency detector 11 includes, in order of arrangement: the second signal outlet OUPB, the first signal outlet OUP, the third signal outlet ODN, and the fourth signal outlet ODN; or, the first signal outlet OUP, the second signal outlet OUPB, the fourth signal outlet ODN, and the third signal outlet ODN; or, the third signal outlet ODN, the fourth signal outlet ODN, the second signal outlet OUPB, and the first signal outlet OUP; or, the fourth signal outlet ODN, the third signal outlet ODN, the first signal outlet OUP, and the second signal outlet OUPB.
[0053] Correspondingly, the plurality of signal interfaces of the charge pump 12 includes, in order of arrangement: the second signal inlet IUPB, the first signal inlet IUP, the third signal inlet IDN, and the fourth signal inlet IDNB; or, the first signal inlet IUP, the second signal inlet IUPB, the fourth signal inlet IDNB, and the third signal inlet IDN; or, the third signal inlet IDN, the fourth signal inlet IDNB, the second signal inlet IUPB, and the first signal inlet IUP; or, the fourth signal inlet IDNB, the third signal inlet IDN, the first signal inlet IUP, and the second signal inlet IUPB.
[0054] By symmetrically arranging the positions of the two reverse signal interfaces, one interface can be directly copied to manufacture the other interface in the manufacturing process, thereby improving the production efficiency.
[0055] In a possible implementation, the charge pump 12 includes a single charge pump or a double charge pump.
[0056] Figure 7is a distribution diagram of MOS transistors in a charge pump 12 according to an exemplary embodiment. As shown in Figure 7 The charge pump 12 is a single charge pump, and all the MOS transistors in the single charge pump are arranged in a line.
[0057] For example, the voltage control signal VC can be led out through the MOS transistor corresponding to the second signal inlet IUPB and the MOS transistor corresponding to the third signal inlet IDN.
[0058] In other embodiments, the voltage control signal VC can also be led out through the MOS transistor corresponding to the first signal inlet IUP and the MOS transistor corresponding to the fourth signal inlet IDNB.
[0059] Figure 8 is another distribution diagram of MOS transistors in a charge pump 12 according to an exemplary embodiment. As shown in Figure 8 The charge pump 12 is a double charge pump, and all the MOS transistors in the double charge pump are arranged in a line.
[0060] For example, the voltage control signal VC can be led out through the MOS transistor corresponding to the second signal inlet IUPB and the MOS transistor corresponding to the third signal inlet IDN.
[0061] In other embodiments, the voltage control signal VC can also be led out through the MOS transistor corresponding to the first signal inlet IUP and the MOS transistor corresponding to the fourth signal inlet IDNB.
[0062] In a possible implementation, referring to Figure 9 The phase-locked loop further includes a filter 14, and the charge pump 12 is connected with the oscillator 13 through the filter 14; the filter 14 is configured to filter the voltage control signal VC generated by the charge pump 12 and transmit the filtered voltage control signal VC to the oscillator 13.
[0063] The filter 14 is configured to filter and stabilize the voltage control signal VC, so as to ensure smooth change of the control voltage, avoid frequent fluctuations and interference, improve the quality of the voltage control signal VC, and further improve the phase-locked effect of the phase-locked loop.
[0064] In a possible implementation, the phase-locked loop further includes a frequency divider 15, and the oscillator 13 is connected with the phase frequency detector 11 through the frequency divider 15; the frequency divider 15 is configured to divide the output signal of the oscillator 13 to obtain a divided signal and transmit the divided signal to the phase frequency detector 11 as a feedback signal.
[0065] The frequency divider 15 is configured to transmit the output signal of the oscillator 13 to the phase frequency detector 11 after frequency division, so that the phase-locked loop can reduce the phase error of the output frequency, so that the feedback signal more accurately tracks the frequency and phase of the input signal, and improves the stability and accuracy of the phase-locked loop.
[0066] In a possible implementation, please refer to Figure 9 , the charge pump 12 is arranged in a first preset direction of the phase frequency detector 11, and the frequency divider 15 is arranged in a second preset direction of the phase frequency detector 11, the first preset direction of the phase frequency detector 11 and the second preset direction of the phase frequency detector 11 are perpendicular to each other.
[0067] In a possible implementation, the filter 14 is arranged in a first preset direction of the charge pump 12, and the oscillator 13 is arranged in a second preset direction of the charge pump 12, the first preset direction of the charge pump 12 and the second preset direction of the charge pump 12 are perpendicular to each other, the first preset direction of the phase frequency detector 11 and the first preset direction of the charge pump 12 are parallel to each other, and the second preset direction of the phase frequency detector 11 and the second preset direction of the charge pump 12 are parallel to each other.
[0068] By arranging the phase-locked loop in the above manner, the voltage control signal VC is not disturbed by other signals such as clock signals and digital signals, the quality of the voltage control signal VC is ensured, and the phase-locked effect of the phase-locked loop is improved.
[0069] Figure 10 is a voltage control signal comparison diagram of a phase-locked loop according to an exemplary embodiment. In the diagram, VC-1 represents a voltage control signal before simulation, and VC-2 represents a voltage control signal after simulation. Due to the optimization of the layout, the ripple of the voltage control signal is basically consistent, and the disturbance of irrelevant signals is not introduced.
[0070] The preferred embodiments of the present disclosure are described in detail above with reference to the drawings, but the present disclosure is not limited to the specific details in the above-described embodiments. Within the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.
[0071] In addition, it should be noted that each specific technical feature described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, various possible combination manners are not described again in the present disclosure.
[0072] In addition, various different embodiments of the present disclosure can also be combined in any manner, as long as they do not deviate from the idea of the present disclosure, and they should also be considered as disclosed by the present disclosure.
Claims
1. A phase-locked loop, characterized by The phase-locked loop comprises a phase frequency detector, a charge pump and an oscillator, which are connected in sequence, and the oscillator is connected with the phase frequency detector; The signal interfaces of the phase frequency detector and the signal interfaces of the charge pump are one-to-one corresponding in the arrangement order, wherein the MOS transistors in the charge pump are arranged in a line; The phase frequency detector is configured to determine the phase difference and the frequency difference between the input signal and the feedback signal according to the input signal and the feedback signal, obtain a difference signal, and transmit the difference signal to the charge pump through the signal interfaces of the phase frequency detector; The charge pump is configured to receive the difference signal through the signal interfaces of the charge pump, and generate a voltage control signal according to the difference signal; The oscillator is configured to control the frequency of an output signal according to the voltage control signal, so as to generate the feedback signal according to the output signal and transmit the feedback signal to the phase frequency detector.
2. The phase-locked loop of claim 1, wherein, The signal interfaces of the phase frequency detector and the signal interfaces of the charge pump are aligned in the arrangement order.
3. The phase-locked loop of claim 2, wherein, The signal interfaces of the phase frequency detector comprise a first signal outlet, a second signal outlet, a third signal outlet and a fourth signal outlet, and the signal interfaces of the charge pump comprise a first signal inlet, a second signal inlet, a third signal inlet and a fourth signal inlet; The first signal outlet, the second signal outlet, the third signal outlet and the fourth signal outlet are aligned with the first signal inlet, the second signal inlet, the third signal inlet and the fourth signal inlet, respectively; The first signal outlet is configured to be activated when the input signal leads the feedback signal, the third signal outlet is configured to be activated when the input signal lags behind the feedback signal, the output signal of the second signal outlet is the reverse signal of the output signal of the first signal outlet, and the output signal of the fourth signal outlet is the reverse signal of the output signal of the third signal outlet.
4. The phase-locked loop of claim 3, wherein, The first signal outlet and the second signal outlet are arranged adjacently, the third signal outlet and the fourth signal outlet are arranged adjacently, and the second signal outlet and the fourth signal outlet are arranged symmetrically.
5. The phase-locked loop of claim 4, wherein, The signal interfaces of the phase frequency detector comprise the following arranged in sequence in the arrangement order: The second signal outlet, the first signal outlet, the third signal outlet and the fourth signal outlet; or The first signal outlet, the second signal outlet, the fourth signal outlet and the third signal outlet; or The third signal outlet, the fourth signal outlet, the second signal outlet and the first signal outlet; or The fourth signal outlet, the third signal outlet, the first signal outlet and the second signal outlet.
6. The phase-locked loop of claim 1, wherein, The charge pump comprises a single charge pump or a double charge pump.
7. The phase-locked loop of claim 1, wherein, The phase-locked loop further comprises a filter, and the charge pump is connected with the oscillator through the filter; The filter is configured to filter the voltage control signal generated by the charge pump, and transmit the filtered voltage control signal to the oscillator.
8. The phase-locked loop of claim 7, wherein, The phase-locked loop further comprises a frequency divider, and the oscillator is connected to the phase-frequency detector via the frequency divider; The frequency divider is used to perform frequency division processing on the output signal of the oscillator to obtain a frequency-divided signal, and transmit the frequency-divided signal as the feedback signal to the phase-frequency detector.
9. The phase-locked loop of claim 8, wherein, The charge pump is arranged in a first preset direction of the phase frequency detector, and the frequency divider is arranged in a second preset direction of the phase frequency detector. The first preset direction of the phase frequency detector and the second preset direction of the phase frequency detector are perpendicular to each other.
10. The phase-locked loop of claim 9, wherein, The filter is arranged in a first preset direction of the charge pump, the oscillator is arranged in a second preset direction of the charge pump, the first preset direction of the charge pump is perpendicular to the second preset direction of the charge pump, the first preset direction of the phase-frequency detector is parallel to the first preset direction of the charge pump, and the second preset direction of the phase-frequency detector is parallel to the second preset direction of the charge pump.