Clock synchronization phase-locked loop based on fractional order filter
By designing a clock synchronization phase-locked loop based on a fractional-order filter, and employing an equivalent fractional-order capacitor filter circuit and an RC filter circuit, the specific implementation problem of the fractional-order phase-locked loop was solved, improving the stability and performance of the phase-locked loop, and achieving faster locking and more stable signal output.
Patent Information
- Application Number
- CN202520032732.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-07
- Publication Date
- 2025-12-30
- Estimated Expiration
- 2035-01-07
AI Technical Summary
Existing research on fractional phase-locked loops mainly focuses on theoretical analysis and approximate numerical simulations, lacking concrete implementation circuits, resulting in insufficient performance and stability of the phase-locked loops.
A clock synchronization phase-locked loop based on a fractional-order filter was designed, including a frequency and phase detector, a charge pump, a loop-order filter, and a voltage-controlled oscillator. An equivalent fractional-order capacitor filter circuit and an RC filter circuit were adopted, and the filter order was changed from an integer 1 to between 0 and 1. The parameters were optimized to improve stability and performance.
This significantly improves the stability and performance of the phase-locked loop, reduces locking time, and enhances signal stability and synchronization performance.
Smart Images
Figure CN223744708U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to communication network technical field especially relates to a clock synchronization phase-locked loop based on fractional order filter. BACKGROUND
[0002] Clock phase-locked loop technology is the core technology of clock synchronization system, and the quality of clock phase-locked loop output clock directly influences whether digital communication network can work normally, so a reliable clock phase-locked loop is very important for synchronization system.
[0003] Compared with traditional clock phase-locked loop, fractional order phase-locked loop constructs fractional order phase-locked loop by introducing fractional order filter, expands the order of phase-locked loop from integer to real number, and significantly improves the flexibility and performance of system design.The parameter selection and circuit realization of fractional order phase-locked loop directly influence the performance and stability of phase-locked loop.But the current existing research on various fractional order phase-locked loops stays in theoretical analysis and approximate numerical simulation, and there is no specific implementation circuit of fractional order phase-locked loop. SUMMARY
[0004] In view of above-mentioned analysis, the utility model aims at providing a clock synchronization phase-locked loop based on fractional order filter, solves the circuit realization problem of fractional order filter, improves the performance and stability of phase-locked loop based on the building of equivalent fractional order capacitor filter circuit.
[0005] The utility model mainly aims at realizing through the following technical schemes:
[0006] A clock synchronization phase-locked loop based on fractional order filter, including frequency discriminator, charge pump, loop order filter and voltage controlled oscillator;
[0007] The frequency discriminator includes main clock input end and local clock input end;
[0008] The charge pump is electrically connected between the output end of the frequency discriminator and the input end of loop order filter;
[0009] The loop order filter is fractional order filter, and equivalent fractional order capacitor filter circuit and RC filter circuit are arranged in parallel;The output end of loop order filter is electrically connected to the input end of voltage controlled oscillator;
[0010] The voltage controlled oscillator output end outputs local clock, and is electrically connected to the local clock input end of frequency discriminator.
[0011] Furthermore, the equivalent fractional-order capacitor filter circuit includes a resistor R and N filter groups, wherein the i-th filter group includes a resistor Ri and a capacitor Ci connected in parallel, i∈{1,2…n}; the resistor R and the N filter groups are connected in series; wherein one end of the resistor R is electrically connected to the output terminal of the charge pump, the other end is electrically connected to the first filter group, and the last filter group is grounded.
[0012] Furthermore, the frequency and phase detector includes two D flip-flops and a feedback clear logic gate, wherein the feedback clear logic gate is an AND gate; the D terminals of the two D flip-flops are both connected to a high level, and their R terminals are electrically connected and then connected to the output terminal of the logic gate; the CK terminal of the first D flip-flop is the main clock input terminal, and its Q terminal is electrically connected to the first input terminal of the logic gate; the CK terminal of the second D flip-flop is the local clock input terminal, and its Q terminal is electrically connected to the second input terminal of the logic gate.
[0013] Furthermore, the charge pump includes three N-type MOS transistors and three P-type MOS transistors arranged sequentially;
[0014] In this configuration, the drain of the first N-type MOSFET is connected to the power supply, its source is electrically connected to the source of the second N-type MOSFET, and its gate is electrically connected to the gate of the second N-type MOSFET. The drain of the second N-type MOSFET is electrically connected to the source of the third N-type MOSFET. The gate of the third N-type MOSFET is electrically connected to the second input terminal of the logic gate, and its drain is electrically connected to the drain of the first P-type MOSFET. The gate of the first P-type MOSFET is electrically connected to the first input terminal of the logic gate, and its source is electrically connected to the drain of the second P-type MOSFET. The gate of the second P-type MOSFET is electrically connected to the gate and drain of the third P-type MOSFET, and they are all grounded. The source of the second P-type MOSFET is electrically connected to the source of the third P-type MOSFET, and they are all connected to the power supply.
[0015] Furthermore, the voltage-controlled oscillator includes three controllable MOSFETs, three inverters, and three capacitors; wherein, the gates of the three MOSFETs are commonly connected to the output of the filter; the input of the first inverter is electrically connected to the source of the third MOSFET, and is also connected to the local clock input of the frequency and phase detector; the output of the first inverter is electrically connected to the drain of the first MOSFET, the source of the first MOSFET is electrically connected to the input of the second inverter, the output of the second inverter is electrically connected to the drain of the second MOSFET, the source of the second MOSFET is electrically connected to the input of the third inverter, and the output of the third inverter is electrically connected to the drain of the third MOSFET; the sources of the three MOSFETs are each grounded after passing through a capacitor.
[0016] Furthermore, when the master clock frequency is 30MHz, the order of the equivalent fractional-order capacitor filter circuit is 0.46.
[0017] The number of filter groups N is 5.
[0018] Furthermore, the resistance and capacitance values in the equivalent fractional-order capacitor filter circuit are as follows:
[0019]
[0020] Furthermore, the resistance and capacitance values in the RC filter circuit are as follows:
[0021] R0 = 1kΩ
[0022] C0 = 100pF.
[0023] The filtering frequency of the fractional capacitor filter circuit is:
[0024] w b =6.04MHz
[0025] w h =39.72MHz.
[0026] Compared with the prior art, the present invention can achieve at least the following beneficial effects:
[0027] This invention improves the stability and performance of the phase-locked loop by constructing a fractional-order charge pump phase-locked loop, changing the loop filter order from an integer of 1 to a value between 0 and 1, and designing an equivalent circuit based on specific clock frequency, filter frequency, resistance, capacitance values, and other parameters.
[0028] Those skilled in the art will understand that this utility model does not involve any software improvements. This utility model simply requires connecting various devices with corresponding functions through the connection relationships given in the embodiments of this utility model, without involving any program software improvements. As for the connection methods between the various hardware devices with corresponding functions, these can all be implemented by those skilled in the art using existing technology, and will not be described in detail here.
[0029] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages will become apparent from the description or be learned by practicing this invention. The objectives and other advantages of this invention can be realized and obtained through the details specifically pointed out in the text and accompanying drawings. Attached Figure Description
[0030] The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0031] Figure 1 This is a schematic diagram of the clock synchronization phase-locked loop structure based on a fractional-order filter in an embodiment of this utility model;
[0032] Figure 2 This is a schematic diagram of a clock synchronization phase-locked loop based on a fractional-order filter for a 30MHz master clock in an embodiment of this utility model.
[0033] Figure 3 This is a schematic diagram comparing the control voltage curves of FOCPPLL (fractional clock synchronous phase-locked loop) and CPPPLL under the same parameters in the embodiments of this utility model. Detailed Implementation
[0034] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.
[0035] A specific embodiment of this utility model is as follows: Figure 1 As shown, a clock synchronization phase-locked loop based on a fractional-order filter is disclosed, including a frequency and phase detector, a charge pump, a fractional-order filter, and a voltage-controlled oscillator;
[0036] The frequency and phase detector includes a master clock input and a local clock input.
[0037] The charge pump is electrically connected between the output of the frequency and phase detector and the input of the loop-order filter.
[0038] The loop filter is a fractional-order filter, comprising an equivalent fractional-order capacitor filter circuit and an RC filter circuit arranged in parallel; the output terminal of the loop filter is electrically connected to the input terminal of the voltage-controlled oscillator.
[0039] The output terminal of the voltage-controlled oscillator outputs a local clock and is electrically connected to the local clock input terminal of the frequency and phase detector.
[0040] Specifically, such as Figure 2 As shown, the equivalent fractional-order capacitor filter circuit includes a resistor R and N filter groups, wherein the i-th filter group includes a resistor Ri and a capacitor Ci connected in parallel, i∈{1,2…N}; the resistor R and the N filter groups are connected in series; wherein one end of the resistor R is electrically connected to the output terminal of the charge pump, the other end is electrically connected to the first filter group, and the last filter group is grounded.
[0041] In the design of CPPLL (charge pump phase-locked loop), the LF (loop filter) is a key module used to filter the input error signal and convert it into a control signal to adjust the output of the voltage-controlled oscillator. It can not only remove high-frequency noise components, but also bring better phase noise shaping capability, loop stability, tracking speed and locking range.
[0042] The fractional-order charge pump phase-locked loop (FOCPPLL) in this embodiment uses an equivalent fractional-order capacitor filter circuit to change the filter order α from an integer 1 to between 0 and 1. It uses an equivalent fractional-order capacitor instead of a traditional integer-order capacitor, which not only ensures clock synchronization performance but also overcomes the problem of loop instability.
[0043] Furthermore, this embodiment is based on the 30MHz master clock frequency commonly used in multi-source sensor communication networks, and the conventional parameter settings of the clock synchronization phase-locked loop, such as a voltage-controlled oscillator gain of 30*10. 6 Hz / V, output amplitude 1V, charge pump initial current 20*10 -6 A, Charge pump gain 6*10 -5 Frequency and phase detector time delay 1*10 -11 The parameters of the phase-locked loop (PLL) are optimized and tuned, and compared with the passive component library of the IEC 60063 standard. The values are rounded to the nearest standard value, resulting in the following PLL parameter values:
[0044] The equivalent fractional-order capacitor filter circuit has an order of 0.46.
[0045] Filtering frequency range [w b ,w h ]for:
[0046] The number of filter groups N is set to 5;
[0047] The resistance and capacitance values in the equivalent fractional-order capacitor filter circuit are as follows:
[0048]
[0049] The RC filter circuit includes a resistor R0 and a capacitor C0 connected in series, where the resistance and capacitance values are as follows:
[0050] R0 = 1kΩ
[0051] C0 = 100pF.
[0052] This embodiment, through extensive theoretical research and experimental verification, realizes the specific circuit design and practical application of a fractional-order phase-locked loop, improving the stability and performance of the phase-locked loop.
[0053] Furthermore, the frequency and phase detector in this embodiment includes two D flip-flops and a feedback clear logic gate, wherein the feedback clear logic gate is an AND gate; the D terminals of the two D flip-flops are both connected to a high level, and their R terminals are electrically connected and then connected to the output terminal of the logic gate; the CK terminal of the first D flip-flop is the main clock input terminal, and its Q terminal is electrically connected to the first input terminal of the logic gate; the CK terminal of the second D flip-flop is the local clock input terminal, and its Q terminal is electrically connected to the second input terminal of the logic gate; the Q terminals of the first and second D flip-flops serve as the output terminals of the frequency and phase detector and are electrically connected to the charge pump.
[0054] The charge pump consists of three N-type MOSFETs and three P-type MOSFETs arranged sequentially.
[0055] In this configuration, the drain of the first N-type MOSFET is connected to the power supply, its source is electrically connected to the source of the second N-type MOSFET, and its gate is electrically connected to the gate of the second N-type MOSFET. The drain of the second N-type MOSFET is electrically connected to the source of the third N-type MOSFET. The gate of the third N-type MOSFET is electrically connected to the second input terminal of the logic gate, and its drain is electrically connected to the drain of the first P-type MOSFET. The gate of the first P-type MOSFET is electrically connected to the first input terminal of the logic gate, and its source is electrically connected to the drain of the second P-type MOSFET. The gate of the second P-type MOSFET is electrically connected to the gate and drain of the third P-type MOSFET, and they are all grounded. The source of the second P-type MOSFET is electrically connected to the source of the third P-type MOSFET, and they are all connected to the power supply.
[0056] The voltage-controlled oscillator (VCO) includes three controllable MOSFETs, three inverters, and three capacitors. The gates of the three MOSFETs serve as the input terminals of the VCO and are electrically connected to the output terminal of the filter. The input terminal of the first inverter is electrically connected to the source terminal of the third MOSFET, serving as the output terminal of the VCO and connected to the local clock input terminal of the frequency and phase detector. The output terminal of the first inverter is electrically connected to the drain terminal of the first MOSFET, the source terminal of the first MOSFET is electrically connected to the input terminal of the second inverter, the output terminal of the second inverter is electrically connected to the drain terminal of the second MOSFET, the source terminal of the second MOSFET is electrically connected to the input terminal of the third inverter, and the output terminal of the third inverter is electrically connected to the drain terminal of the third MOSFET. The sources of each of the three MOSFETs are grounded after passing through a capacitor.
[0057] In this embodiment, the frequency and phase detector outputs UP and DOWN signals from its two Q terminals based on the phase difference between the master clock and the local clock to control the charging and discharging process of the subsequent charge pump. The reset signal generated by the UP and DOWN signals after passing through the logic gate is connected to the R terminal. The charge pump consists of a current mirror and a MOS switch. The UP and DOWN signals control the charge pump MOS transistor drain to charge and discharge the subsequent capacitor. The control signal Vctrl is filtered and then enters the ring voltage-controlled oscillator (VCO). The three inverters of the ring VCO provide sufficient negative feedback gain to make the VCO oscillate continuously. The controllable MOS equivalent resistance and capacitor form an RC circuit to provide a controllable time constant for the VCO. The control signal adjusts the gate voltage of the MOS transistor to change the time constant of the ring VCO, thereby adjusting the oscillation frequency.
[0058] The phase-locked loop based on a fractional-order loop filter in this embodiment is compared with an integer-order phase-locked loop with the same parameters. Figure 3 As shown, it can be observed that the clock synchronization phase-locked loop based on a fractional-order filter, after parameter optimization in this embodiment, can achieve a shorter locking time and a more stable signal than the integer-order phase-locked loop, verifying the effectiveness and practicality of the clock synchronization phase-locked loop based on a fractional-order filter proposed in this embodiment.
[0059] In summary, this utility model presents a clock synchronization phase-locked loop based on a fractional-order filter. By constructing a fractional-order charge pump phase-locked loop, the filter order is changed from an integer of 1 to a value between 0 and 1. Based on specific clock frequency, filter frequency, resistance, capacitance values, and other parameters, an equivalent circuit is designed. Combined with the design of frequency and phase detectors, charge pumps, and voltage-controlled oscillators in the phase-locked loop, the stability and performance of the phase-locked loop are greatly improved.
[0060] Those skilled in the art will understand that this utility model does not involve any software improvements. This utility model simply requires connecting various devices with corresponding functions through the connection relationships given in the embodiments of this utility model, without involving any program software improvements. As for the connection methods between the various hardware devices with corresponding functions, these can all be implemented by those skilled in the art using existing technology, and will not be described in detail here.
[0061] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present utility model should be included within the protection scope of the present utility model.
Claims
1. A clock synchronization phase-locked loop based on a fractional order filter, characterized in that, The frequency discriminator includes a main clock input end and a local clock input end; The frequency discriminator includes a main clock input end and a local clock input end; The charge pump is electrically connected between the output end of the frequency discriminator and the input end of the loop filter; The loop filter is a fractional order filter, and includes an equivalent fractional order capacitor filter circuit and an RC filter circuit arranged in parallel; and the output end of the loop filter is electrically connected to the input end of the voltage-controlled oscillator. The voltage-controlled oscillator outputs a local clock and is electrically connected to the local clock input end of the frequency discriminator.
2. The fractional filter based clock synchronization phase-locked loop of claim 1, wherein, The equivalent fractional order capacitor filter circuit includes a resistor R and N filter groups, wherein the i-th filter group includes a resistor Ri and a capacitor Ci connected in parallel, i∈{1,2…n}; the resistor R and the N filter groups are connected in series; one end of the resistor R is electrically connected to the output end of the charge pump, the other end is electrically connected to the first filter group, and the last filter group is grounded.
3. The fractional filter based clock synchronization phase-locked loop of claim 2, wherein, The frequency discriminator includes two D flip-flops and a feedback clear logic gate, and the feedback clear logic gate is an AND gate; the D ends of the two D flip-flops are both connected to a high level, and the R ends are electrically connected and are commonly connected to the output end of the logic gate; the CK end of the first D flip-flop is the main clock input end, the Q end is electrically connected to the first input end of the logic gate, and the CK end of the second D flip-flop is the local clock input end, and the Q end is electrically connected to the second input end of the logic gate.
4. The fractional filter based clock synchronization phase-locked loop of claim 3, wherein, The charge pump includes three N-type MOS tubes and three P-type MOS tubes arranged in sequence; The drain of the first N-type MOS tube is connected to a power supply, the source level is electrically connected to the source level of the second N-type MOS tube, and the gate is electrically connected to the gate of the second N-type MOS tube; the drain of the second N-type MOS tube is electrically connected to the source level of the third N-type MOS tube; the gate of the third N-type MOS tube is electrically connected to the second input end of the logic gate, and the drain is electrically connected to the drain of the first P-type MOS tube; the gate of the first P-type MOS tube is electrically connected to the first input end of the logic gate, the source level is electrically connected to the drain of the second P-type MOS tube, the gate of the second P-type MOS tube is electrically connected to the gate and the drain of the third P-type MOS tube, and is commonly grounded, the source of the second P-type MOS tube is electrically connected to the source level of the third P-type MOS tube, and is commonly connected to the power supply.
5. The fractional filter based clock synchronization phase-locked loop of claim 4, wherein, The voltage-controlled oscillator includes three controllable MOS tubes, three inverters and three capacitors; wherein the gates of the three MOS tubes are commonly electrically connected to the output end of the filter; the input end of the first inverter is electrically connected to the source level of the third MOS tube, and is commonly connected to the local clock input end of the frequency discriminator; the output end of the first inverter is electrically connected to the drain of the first MOS tube, the source level of the first MOS tube is electrically connected to the input end of the second inverter, the output end of the second inverter is electrically connected to the drain of the second MOS tube, the source level of the second MOS tube is electrically connected to the input end of the third inverter, and the output end of the third inverter is electrically connected to the drain of the third MOS tube; the source levels of the three MOS tubes are grounded through a capacitor respectively.
6. The fractional filter based clock synchronization phase-locked loop of claim 2, wherein, The order of the equivalent fractional order capacitance filter circuit is 0.46 when the main clock frequency is 30MHz.
7. The fractional filter based clock synchronization phase locked loop of claim 6, wherein, The number N of the filter groups is 5.
8. The fractional filter based clock synchronization phase locked loop of claim 7, wherein, The resistance and capacitance values in the equivalent fractional order capacitance filter circuit are respectively:
9. The fractional order filter based clock synchronization phase-locked loop of claim 6, characterized in that The resistance and capacitance values in the RC filter circuit are respectively: R0=1kΩ C0=100pF.
10. The fractional filter based clock synchronization phase-locked loop of claim 6, wherein, The filter frequency of the fractional order capacitance filter circuit is: w b = 6.04 MHz w h = 39.72 MHz.