Board card image acquisition method and system

Abstract

The application relates to the technical field of image data acquisition, in particular to a board card image acquisition method and system. The method constructs an input channel mapping table through an image acquisition board card, performs multi-channel synchronous trigger processing according to the input channel mapping table, generates a concurrent frame scheduling template, generates a frame block structure according to the concurrent frame scheduling template, generates a frame buffer object according to the frame block structure, performs channel priority driven frame block splicing according to the frame block structure and the frame buffer object, generates a complete frame image structure, performs format packaging and output according to the complete frame image structure, and obtains an image output data frame. The application can effectively support stable data transmission and processing capacity of a board card system in a high-concurrency and multi-source image acquisition task.

Description

Technical Field

[0001] This application relates to the field of image data acquisition technology, and in particular to a method and system for acquiring images from a circuit board. Background Technology

[0002] An image acquisition board is a hardware device used to capture analog or digital image signals from cameras, scanners or other imaging devices and transmit them to a computer for processing. In a multi-channel image acquisition system, the image acquisition board usually needs to receive, synchronize, reconstruct, and output image data from multiple sensors or cameras in parallel.

[0003] Existing technologies generally rely on fixed acquisition hardware structures and channel binding mechanisms, lacking the ability to flexibly handle multi-channel frame rate differences, asynchronous data alignment, and channel frame stitching order. This results in the inability to guarantee the temporal consistency and channel integrity of the image structure in complex acquisition scenarios such as heterogeneous sensors, inconsistent frame rates, or out-of-order data blocks. Furthermore, when faced with multi-channel synchronous scheduling tasks, existing image acquisition systems typically employ hardware-triggered fixed synchronization modes for image data acquisition. While this method can meet basic multi-channel concurrent acquisition needs, it still suffers from poor flexibility in acquisition configuration and limited scalability of scheduling strategies.

[0004] Therefore, there is an urgent need to design a method and system for acquiring circuit board images. Summary of the Invention

[0005] Based on this, it is necessary to provide a method and system for acquiring board images that can set up a multi-channel synchronous frame scheduling organization method based on a channel mapping structure to address the above-mentioned technical problems. This method can construct a frame scheduling template with frame rate awareness and synchronization tag recognition capabilities in the initial stage of acquisition, thereby realizing the structured organization and scheduling logic binding of channel frame streams.

[0006] The technical solution of this invention is as follows:

[0007] A method for acquiring board image, the method comprising:

[0008] An input channel mapping table is constructed based on the image acquisition board. Multi-channel synchronous triggering processing is performed according to the input channel mapping table to generate a concurrent frame scheduling template.

[0009] A frame block structure is generated based on the concurrent frame scheduling template, and a frame buffer object is generated based on the frame block structure.

[0010] Based on the frame block structure and the frame buffer object, channel priority-driven frame block stitching is performed to generate a complete frame image structure;

[0011] Based on the complete frame image structure, the format is encapsulated and output to obtain the image output data frame.

[0012] Specifically, an input channel mapping table is constructed based on the image acquisition board, and multi-channel synchronous triggering processing is performed according to the input channel mapping table to generate a concurrent frame scheduling template, including:

[0013] Based on the image acquisition board, channel mapping is established using the image source interface configuration to obtain the input channel mapping table;

[0014] Based on the input channel mapping table, execute the synchronous trigger logic configuration and frame stream structure division to generate a concurrent frame scheduling template.

[0015] Specifically, based on the image acquisition board, channel mapping is established using the image source interface configuration to obtain an input channel mapping table, including:

[0016] Obtain the device interface properties of the image acquisition board;

[0017] Obtain the channel support information of the image acquisition board;

[0018] Establish static mappings for the channels and construct an input channel mapping table.

[0019] Specifically, based on the input channel mapping table, synchronous triggering logic configuration and frame stream structure partitioning are performed to generate a concurrent frame scheduling template, including:

[0020] Synchronization channels are filtered and grouped according to the input channel mapping table;

[0021] In response to the completion of synchronization channel screening and grouping, trigger signal organization rules are constructed, and concurrent frame scheduling templates are generated.

[0022] Specifically, generating a frame block structure based on the concurrent frame scheduling template, and generating a frame buffer object based on the frame block structure; including:

[0023] The frame stream structure is split according to the concurrent frame scheduling template to generate a cross-channel aligned frame block structure;

[0024] Based on the frame block structure, buffer allocation and registration are performed to generate frame buffer objects.

[0025] Specifically, based on the frame block structure and the frame buffer object, channel priority-driven frame block stitching is performed to generate a complete frame image structure, including:

[0026] Prepare for channel frame block scheduling based on the frame block structure and the frame buffer object;

[0027] In response to the completion of channel frame block scheduling preparation, priority-driven frame block splicing is performed, and a complete frame image structure is generated.

[0028] Specifically, based on the complete frame image structure, the image output data frame is obtained by format encapsulation and output, including:

[0029] Based on the complete frame image structure, perform image frame format standardization processing and add image frame headers and frame control information;

[0030] In response to completing the image frame format standardization process and adding image frame headers and frame control information, data integrity encapsulation and cache alignment are performed, and the image output data frame is obtained.

[0031] Specifically, a board image acquisition system is also provided, the system comprising:

[0032] The scheduling template generation module is used to construct an input channel mapping table based on the image acquisition board, perform multi-channel synchronous triggering processing according to the input channel mapping table, and generate a concurrent frame scheduling template.

[0033] A buffer object generation module is used to generate a frame block structure based on the concurrent frame scheduling template, and to generate a frame buffer object based on the frame block structure.

[0034] The image structure generation module is used to perform channel priority-driven frame block stitching based on the frame block structure and the frame buffer object to generate a complete frame image structure.

[0035] The output data generation module is used to encapsulate and output the image data according to the complete frame image structure to obtain the image output data frame.

[0036] Specifically, the scheduling template generation module is also used to: establish channel mapping based on the image acquisition board and using the image source interface configuration to obtain an input channel mapping table; and execute synchronous trigger logic configuration and frame stream structure division according to the input channel mapping table to generate a concurrent frame scheduling template.

[0037] Specifically, the scheduling template generation module is also used to: obtain the device interface attributes of the image acquisition board; obtain the channel support information of the image acquisition board; establish a static mapping of the channels and construct an input channel mapping table.

[0038] Specifically, the scheduling template generation module is also used to: filter and group synchronous channels according to the input channel mapping table; and in response to completing the synchronous channel filtering and grouping, construct trigger signal organization rules and generate concurrent frame scheduling templates.

[0039] Specifically, the buffer object generation module is further configured to: split the frame stream structure according to the concurrent frame scheduling template to generate a cross-channel aligned frame block structure; and allocate and register buffers according to the frame block structure to generate a frame buffer object.

[0040] Specifically, the image structure generation module is further configured to: prepare channel frame block scheduling based on the frame block structure and the frame buffer object; and in response to the completion of channel frame block scheduling preparation, perform priority-driven frame block stitching and generate a complete frame image structure.

[0041] Specifically, the output data generation module is further configured to: perform image frame format standardization processing and add image frame headers and frame control information according to the complete frame image structure; in response to completing the image frame format standardization processing and adding image frame headers and frame control information, perform data integrity encapsulation and cache alignment processing, and obtain image output data frames.

[0042] Optionally, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps described in the above-described board image acquisition method.

[0043] Optionally, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps described in the above-described board image acquisition method.

[0044] This invention relates to machine learning and deep learning technologies, and its technical effects are as follows:

[0045] (1) The above-mentioned board image acquisition method and system construct an input channel mapping table based on the image acquisition board, perform multi-channel synchronous triggering processing according to the input channel mapping table, and generate a concurrent frame scheduling template. Specifically, the channel mapping is established using the image source interface configuration to obtain the input channel mapping table. Then, the synchronous triggering logic configuration and frame stream structure division are executed according to the input channel mapping table to generate a concurrent frame scheduling template. This realizes the derivation of a flexible concurrent frame scheduling template through a structured input mapping table, has the ability to define explicit frame groups and sort channels, and can support heterogeneous channel synchronous scheduling modeling and frame structure integration organization, breaking through the limitation of "interface binding is fixed structure" in the traditional method.

[0046] (2) A frame block structure is generated according to the concurrent frame scheduling template, and a frame buffer object is generated according to the frame block structure. The frame block structure and the frame buffer object are used to perform channel priority-driven frame block splicing to generate a complete frame image structure. The channel frame segments are uniformly organized and periodically demarcated within the frame scheduling template structure. The frame block synthesis is based on the strict alignment logic of the cross-channel synchronous acquisition cycle. The output structure realizes unified access and cross-channel mapping, and has more system-level synchronous coherence in data structure definition and scheduling control.

[0047] (3) Based on the complete frame image structure, the format is encapsulated and output to obtain the image output data frame. Through frame block-level splicing and channel priority control, the structure of different channel contents can be controlled and combined, which effectively improves the adjustability and determinism of cross-channel frame combination. Finally, the data output carrier is directly used in the downstream modules of the image acquisition system, including image encoding and compression, real-time display, storage caching or neural network inference input. The data frame set has a complete structure and standardized format encapsulation. It has the characteristics of cross-channel alignment, clear buffer mapping and controllable channel splicing order, which can effectively support the board system's stable data transmission and processing capabilities in high-concurrency, multi-source image acquisition tasks. Attached Figure Description

[0048] Figure 1 This is a flowchart illustrating a method for acquiring board images in one embodiment;

[0049] Figure 2 This is a structural block diagram of a board image acquisition system in one embodiment;

[0050] Figure 3 This is a structural block diagram of a computer device in one embodiment. Detailed Implementation

[0051] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0052] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0053] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0054] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0055] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0056] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0057] In one embodiment, a terminal is provided, the terminal being configured to: construct an input channel mapping table based on an image acquisition board; perform multi-channel synchronous triggering processing according to the input channel mapping table to generate a concurrent frame scheduling template; generate a frame block structure according to the concurrent frame scheduling template, and generate a frame buffer object according to the frame block structure; perform channel priority-driven frame block splicing according to the frame block structure and the frame buffer object to generate a complete frame image structure; and perform format encapsulation and output according to the complete frame image structure to obtain an image output data frame.

[0058] The terminal may be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices.

[0059] In one embodiment, such as Figure 1 As shown, a method for acquiring board images is provided, the method comprising:

[0060] Step S100: Construct an input channel mapping table based on the image acquisition board, perform multi-channel synchronous triggering processing according to the input channel mapping table, and generate a concurrent frame scheduling template;

[0061] Step S200: Generate a frame block structure according to the concurrent frame scheduling template, and generate a frame buffer object according to the frame block structure;

[0062] Step S300: Perform channel priority-driven frame block stitching based on the frame block structure and the frame buffer object to generate a complete frame image structure;

[0063] Step S400: Perform format encapsulation and output according to the complete frame image structure to obtain the image output data frame.

[0064] In this embodiment, an input channel mapping table is constructed based on the image acquisition board. Multi-channel synchronous triggering processing is performed according to the input channel mapping table to generate a concurrent frame scheduling template. A frame block structure is generated based on the concurrent frame scheduling template, and a frame buffer object is generated based on the frame block structure. Channel priority-driven frame block splicing is performed based on the frame block structure and the frame buffer object to generate a complete frame image structure. The complete frame image structure is then formatted and output to obtain an image output data frame. This effectively supports the board system's stable data transmission and processing capabilities in high-concurrency, multi-source image acquisition tasks.

[0065] In one embodiment, step S100: Constructing an input channel mapping table based on the image acquisition board, performing multi-channel synchronous triggering processing according to the input channel mapping table, and generating a concurrent frame scheduling template, including:

[0066] Step S110: Based on the image acquisition board, use the image source interface configuration to establish channel mapping and obtain the input channel mapping table;

[0067] Step S120: Execute synchronous trigger logic configuration and frame stream structure division according to the input channel mapping table to generate a concurrent frame scheduling template.

[0068] In this embodiment, channel mapping is first established based on the image acquisition board using the image source interface configuration to obtain the input channel mapping table. Then, synchronous triggering logic configuration and frame stream structure division are executed according to the input channel mapping table to generate a concurrent frame scheduling template. This enables the derivation of a flexible concurrent frame scheduling template through a structured input mapping table, and provides explicit frame group definition and channel sorting capabilities. It can support heterogeneous channel synchronous scheduling modeling and frame structure integration organization, breaking through the limitation of "interface binding equals fixed structure" in the traditional method.

[0069] In one embodiment, step S110: Based on the image acquisition board, channel mapping is established using the image source interface configuration to obtain an input channel mapping table, including:

[0070] Step S111: Obtain the device interface attributes of the image acquisition board;

[0071] Step S112: Obtain the channel support information of the image acquisition board;

[0072] Step S113: Establish static mapping of channels and construct input channel mapping table.

[0073] In this embodiment, device interface attributes are first acquired by calling the standard image acquisition interface of the image acquisition board. This process is based on the PCIe image source interface protocol to identify and read basic device information. Then, the channel information supported by the board itself and its integrated computing and interface modules is obtained from the image acquisition board driver or SDK interface to complete the initialization of the receive channel resource table. The reading of acquisition board resource information is completed through mature interfaces or register configuration.

[0074] After completing resource awareness on both the input (data interface of external camera) and output (data encapsulation interface after the generation of complete frame image structure), all image sources are prioritized according to bandwidth and frame rate requirements and bound according to heuristic matching method to complete the static mapping of image sources and channels.

[0075] Finally, the system organizes each pair of "image source-channel" binding relationships into structured entries, forming an input channel mapping table. This input channel mapping table will be used as direct input in step S120 to generate the concurrent frame scheduling template, and will be used to delineate frame group boundaries and configure synchronization mechanisms.

[0076] Specifically, the input channel mapping table is as follows: Its expression is: In the formula The total number of entries; wherein, the input channel mapping table The Middle Item For ordered tuples: .

[0077] Furthermore, It is the first Item The corresponding image source number; It is the first Item The corresponding bound board channel number; It is the first Item The corresponding image source interface type; It is the first Item The corresponding resolution, in the form of , This refers to the number of horizontal pixels. This refers to the number of vertical pixels. It is the first Item The corresponding acquisition frame rate; It is the first Item The corresponding synchronization flag takes the value {1, 1}, where 1 indicates participation in synchronization and 0 indicates non-participation.

[0078] In one embodiment, step S120: Executing synchronous trigger logic configuration and frame stream structure partitioning according to the input channel mapping table to generate a concurrent frame scheduling template, including:

[0079] Step S121: Perform synchronization channel filtering and grouping according to the input channel mapping table;

[0080] Step S122: In response to the completion of synchronization channel filtering and grouping, construct trigger signal organization rules and generate concurrent frame scheduling templates.

[0081] In this embodiment, based on the channel mapping table Configure synchronous triggering logic and divide frame stream structure to generate a structured concurrent frame scheduling template. .

[0082] The concurrent frame scheduling template clarifies which channels need to be acquired in parallel within the same frame time slice, which are asynchronous channels, and organizes the frame order structure of each channel within each frame group.

[0083] Specifically, the process begins with filtering and grouping synchronous channels, followed by constructing trigger signal organization rules, and finally organizing the frame structure and outputting the template.

[0084] Furthermore, when performing synchronization channel screening and grouping, the trigger signal of each channel is judged according to the synchronization triggering logic involved. It is checked whether the trigger signal reaches the preset threshold requirement. The channel that meets the condition is assigned the value "Sync_Tag=1", indicating that the channel is selected as the synchronization trigger reference. The channel that does not meet the condition is assigned the value "Sync_Tag=0".

[0085] Specifically, from Filter all entries that satisfy "Sync_Tag=1" and the synchronization tag in these entries. Updated to Its set is ,but:

[0086] ;

[0087] By comparing the frame rate of each channel with the reference channel within an error tolerance limit, logical verification of frame synchronization conditions is achieved, thereby determining the frame rate consistency between channels. Based on the frame rate consistency, the synchronization channel is further divided into several synchronization frame groups, each group being... Then the set of synchronization frame groups is:

[0088] ;

[0089] in, Total number of frames Group number, Represents frame group All channel entries Actual frame rate The only equal value, i.e. .

[0090] Each frame group The frame acquisition of all channels is designed to be triggered simultaneously, and a set of concurrent frames are output synchronously.

[0091] When constructing trigger signal organization rules, the system bases them on channel binding relationships (i.e. In (fields), construct the frame trigger sequence matrix Its expression is: ,in For frame number, Indicates the first In the synchronization group, the first The frame's trigger timestamp.

[0092] This matrix is ​​generated according to a standard synchronization protocol, ensuring accurate alignment of multi-channel data acquisition in each frame group.

[0093] Next, during frame structure organization and template output, for each synchronization group Establish a structural template The expression for each template item is:

[0094] ;

[0095] in, It is the frame trigger interval. ; It is the intra-frame channel arrangement order, according to Sort in ascending order; finally, summarize all synchronization group templates to form a unified concurrent frame scheduling template:

[0096] ;

[0097] The concurrent frame scheduling template will be used for frame number marking and memory write structure organization in subsequent steps.

[0098] Existing image acquisition solutions mostly employ fixed hardware-side synchronization settings (such as CameraLink synchronous acquisition group configuration), which only support fixed parallel acquisition of a limited number of channels and lack the ability to dynamically generate frame group scheduling templates before acquisition. This embodiment utilizes a structured input mapping table. Derive flexible The template has the ability to explicitly define frame groups and sort channels, and can support heterogeneous channel synchronous scheduling modeling and frame structure integration organization, breaking through the limitation of "interface binding means fixed structure" in the traditional method.

[0099] In one embodiment, step S200: generating a frame block structure based on the concurrent frame scheduling template, and generating a frame buffer object based on the frame block structure; includes:

[0100] Step S210: Perform frame stream structure splitting according to the concurrent frame scheduling template to generate cross-channel aligned frame block structure;

[0101] Step S220: Allocate and register buffers according to the frame block structure to generate frame buffer objects.

[0102] In this embodiment, in step S210, the concurrent frame scheduling template is received. In clarifying each synchronization frame group Trigger interval within and channel arrangement Then, based on this template, the multi-channel frame stream data is structurally split to form a frame block structure that can be aligned across channels. .

[0103] Specifically, firstly, the frame data is delimited in time sequence, then the frame block structure is synthesized, and finally, cross-group frame block fusion and output structure unification are performed.

[0104] Step S3, during the time-series delimitation of frame data, involves processing each scheduling template item. The system uses time intervals Periodically scan the input channel stream belonging to the channel group. Each channel data segment.

[0105] For each channel The corresponding frame acquisition interval is denoted as , indicating channel Above, the first The time interval occupied by each frame block in the scheduling process is expressed as follows:

[0106] ;

[0107] in, For the first Each frame block in the channel The start time of the scheduling is determined by the scheduling offset. With period Iterative generation: The iterative generation process is as follows: Based on the preset start delay and fixed frame acquisition rhythm of each channel group, starting from the first starting time point, it gradually moves backward and generates multiple acquisition time points in sequence until the entire acquisition cycle is covered. For channel The frame acquisition duration is determined by looking up a table based on the frame size and transmission rate. Specifically, it is derived from the channel frame scheduling parameter table. This table establishes a fixed value or range for frame block transmission time based on different channel types, resolutions, frame rates, and channel bandwidth characteristics. During scheduling, the transmission time is determined according to the channel... The physical configuration identifier is used to query the parameter table and obtain the corresponding standard unit frame block scheduling duration. This table lookup process is completed through static register mapping or by preloading the configuration during the driver initialization phase.

[0108] When performing frame block structure synthesis, the same frame group All channels under the synchronous acquisition cycle The corresponding frame segments are aggregated uniformly, specifically those with the same frame rate. The channel is assigned to the frame group and with a unified scheduling cycle The organization is such that each frame acquisition synchronization schedule is assigned a unique index. This corresponds one-to-one with the generation of each group of frames, and the scheduling cycle index of the frame block scheduling within the channel naturally corresponds to this. ,Right now This results in logically aligned frame blocks. The unified frame group scheduling structure is represented by the following formula, which shows the result of frame synchronization scheduling of multiple physical channels under a unified frame rate constraint:

[0109] ;

[0110] Each frame block Includes channel groups All members in the The frames within a single acquisition cycle are the basic concurrent units of the frame structure.

[0111] Next, during the process of cross-group frame block fusion and output structure unification, all channel groups are... Frame block sequence The output frame block structure is obtained by merging the elements into a single block:

[0112] ;

[0113] Indicates the scheduling period Within, all the frame blocks of all channels are split, aligned and then merged to form a unified set of frame blocks.

[0114] Unlike existing methods that involve independently acquiring and then stitching frames together, this method organizes channel frames uniformly and delimits them periodically within a frame scheduling template structure; frame block synthesis is based on a strict cross-channel synchronous acquisition cycle. Alignment logic; output structure It achieves unified access and cross-channel mapping, and has greater system-level synchronization and coherence in data structure definition and scheduling control.

[0115] Furthermore, in step S220, the frame memory size is first calculated and the mapping unit is determined. Then, based on the image resolution, pixel depth, number of channels and data layout mode, a mature intra-frame buffer mapping mechanism is used to analyze each frame of image data and calculate the minimum continuous buffer size required for each frame.

[0116] Next, the channel frames spanning multiple frame blocks are aggregated to form a fixed buffer unit template. Then, buffer allocation is performed using memory pool allocation, a common practice in embedded systems. Physical memory addresses are pre-allocated for all frames within each frame block, and a logical mapping between frame blocks and memory blocks is established. Finally, frame buffer registration is performed using the registration function provided by the image acquisition card SDK. Each buffer is registered with its associated channel, acquisition period, frame block index, and other structured parameters, generating a frame buffer object. Each object records the following information: its associated frame block number, channel number, buffer address and length, the frame's position index within the frame block, and a pointer structure that can be used for scheduling reference.

[0117] The final output framebuffer object is:

[0118] ;

[0119] in, : No. Channel in frame block The corresponding framebuffer object; It is the block number to which it belongs, equivalent to This indicates that the buffer belongs to the first... One frame block; It is the channel number, equivalent to The image acquisition channel corresponding to the identifier buffer; It is a physical or virtual memory address, representing the starting address of the buffer for this frame of data in the system; It is the buffer size, calculated based on the frame resolution and pixel format; It is the splicing position index of this frame in the frame block, which is used for the generation of the image structure of subsequent frames; It is a pointer to a buffer management structure, which can be referenced by the operating system or driver scheduling.

[0120] In one embodiment, step S300: performing channel priority-driven frame block stitching based on the frame block structure and the frame buffer object to generate a complete frame image structure, including:

[0121] Step S310: Prepare for channel frame block scheduling based on the frame block structure and the frame buffer object;

[0122] Step S320: In response to the completion of channel frame block scheduling preparation, priority-driven frame block splicing is performed, and a complete frame image structure is generated.

[0123] In this embodiment, channel priority-driven frame block splicing is performed based on the following: the output cross-channel aligned frame block set, combined with the equations in the aforementioned dialogue, yields its overall expression as follows:

[0124] ;

[0125] The framebuffer object obtained in step S220:

[0126] ;

[0127] The scheduling-driven mechanism specifically includes: a channel priority table. ; indicates a channel To the passage The priority of each image acquisition channel decreases progressively. This channel priority table originates from the classification settings of the importance, latency sensitivity, or image quality level of each image acquisition channel task during the system design phase. Its generation methods include presets in system initialization or device drivers, as well as evaluations based on channel characteristics. As a basic input configuration parameter used for sorting decisions in scheduling logic, it is a common static or dynamic priority allocation mechanism in engineering implementation.

[0128] Specifically, the process begins with channel frame block scheduling preparation, followed by priority-driven frame block splicing, and finally, frame image structure output generation.

[0129] During channel frame block scheduling preparation, for each output frame block The system iterates through the channel frame entries it contains. and according to the channel signs Match the corresponding buffer object Extract its valid data pointer Location information This results in the following data pairs:

[0130] ;

[0131] In the formula, Indicates during the scheduling period Inside, passage The frame block data corresponds to the stitching input unit in the image stitching process, which is used to drive the data of this channel to be written into the final frame image structure;

[0132] Indicates channel In the cycle The data pointer address within the frame buffer, which points to the starting location of the actual frame data storage; Indicates channel The data is indexed to the stitching target location in the frame image structure, i.e., in which logical / pixel location region of the entire frame image the data should be written.

[0133] When performing priority-driven frame block splicing, for the same frame block The system follows the priority table. The channels are traversed sequentially, and the buffer data of each channel is written to the target frame image buffer in turn:

[0134] If satisfied The writing order follows this pattern:

[0135] ;

[0136] This formula represents the scheduling period. Middle, passage ,aisle ,……,aisle The execution order of the frame block data and the corresponding stitching input units during the image stitching process is as follows:

[0137] Indicates during the scheduling period In the process, channels are executed sequentially according to their priority from highest to lowest. ,aisle ,……,aisle The frame concatenation operation; each write uses its The referenced data content, and in accordance with Complete data pasting at the specified location; current period The complete frame image structure is denoted as:

[0138] ;

[0139] In the formula, Indicates the current scheduling period The complete frame image structure generated internally; Indicates the scheduling period The set of channels involved in scheduling; during the generation of frame image structure output, along with all synchronization cycles After the traversal is complete, a series of complete frame image structures are obtained:

[0140] ;

[0141] Each frame of the image Each corresponds to a stitched image buffer unit, possessing a complete structure and consistent order. In existing technologies, frame image structures are often based on independent frame acquisition for each channel followed by unified buffering and stitching, lacking a channel priority scheduling mechanism, and the stitching granularity is mostly whole frames or complete buffers. However, this embodiment achieves controllable combination of the structure of different channel contents through frame block-level stitching and channel priority control, effectively improving the adjustability and determinism of cross-channel frame combination.

[0142] In one embodiment, step S400: Based on the complete frame image structure, perform format encapsulation and output to obtain an image output data frame, including:

[0143] Step S410: Perform image frame format standardization processing and add image frame headers and frame control information according to the complete frame image structure;

[0144] Step S420: In response to completing the image frame format standardization process and adding image frame headers and frame control information, perform data integrity encapsulation and buffer alignment processing, and obtain the image output data frame.

[0145] In this embodiment, the process of encapsulating the image output data frame includes:

[0146] First, image frame format standardization is performed: for each frame image structure It adopts a mature general image memory encapsulation model to perform standard arrangement of the stitched multi-channel data.

[0147] Next, image frame headers and frame control information are added: Before the standard image data area, the system uses TIFF or a custom frame structure encapsulation protocol to insert frame header information, including but not limited to: frame number, timestamp (generated uniformly by the system), image size and resolution, channel number and order description, and data integrity check value (such as CRC). This process is automatically generated using existing frame description table templates.

[0148] Next, data integrity encapsulation and cache alignment are performed: using a mature DMA cache alignment algorithm, the structure of each frame is filled with system-aligned bytes (such as 128B or 256B); utilizing system-interface standards such as USB Video Class, MIPI-CSI, or PCIe data stream formats, the encapsulated frames are sent to the output buffer, ready for external transmission. Finally, the final set of image output data frames is formed.

[0149] After the above packaging process, the system is formed as follows:

[0150] ;

[0151] in, Output a complete set of image data frames; Indicates the total number of scheduling cycles; each All of these are image output data frames with complete structure, uniform format, and transmittable capability, which can be used for subsequent machine learning inference, image compression, storage, or network transmission.

[0152] The final output data frame set As the final data output carrier in the board image acquisition method, it is directly used in the downstream modules of the image acquisition system, including image encoding and compression, real-time display, storage caching or neural network inference input. The data frame set has a complete structure and standardized format encapsulation, and has the characteristics of cross-channel alignment, clear buffer mapping and controllable channel splicing order. It can effectively support the board system's stable data transmission and processing capabilities in high-concurrency, multi-source image acquisition tasks.

[0153] Therefore, this application sets up a multi-channel synchronous frame scheduling organization method based on channel mapping structure, which can build a frame scheduling template with frame rate awareness and synchronization tag recognition capabilities in the initial stage of acquisition, realize the structured organization and scheduling logic binding of channel frame streams, thereby solving the problems of fixed channel synchronization mode, unconfigurable scheduling and weak structure organization capability in traditional methods, and improving the versatility and stability of the system in high-channel asynchronous acquisition scenarios.

[0154] In summary, this application first constructs an input channel mapping table based on an image acquisition board, performs multi-channel synchronous triggering processing based on the input channel mapping table, generates a concurrent frame scheduling template, establishes channel mapping using image source interface configuration, obtains the input channel mapping table, and then executes synchronous triggering logic configuration and frame stream structure partitioning based on the input channel mapping table to generate a concurrent frame scheduling template. This enables the derivation of a flexible concurrent frame scheduling template through a structured input mapping table, has explicit frame group definition and channel sorting capabilities, and can support heterogeneous channel synchronous scheduling modeling and frame structure integration organization, breaking through the limitation of "interface binding equals fixed structure" in traditional methods.

[0155] Then, a frame block structure is generated according to the concurrent frame scheduling template, and a frame buffer object is generated according to the frame block structure. The frame block structure and the frame buffer object are used to perform channel priority-driven frame block stitching to generate a complete frame image structure. The channel frame segments are uniformly organized and periodically demarcated within the frame scheduling template structure. Frame block synthesis is based on strict alignment logic of cross-channel synchronous acquisition cycle. The output structure realizes unified access and cross-channel mapping, and has greater system-level synchronous coherence in data structure definition and scheduling control.

[0156] Next, the complete frame image structure is format-encapsulated and output to obtain image output data frames. Through frame block-level splicing and channel priority control, the structure of different channel contents can be controlled and combined, effectively improving the adjustability and determinism of cross-channel frame combination. The final data output carrier is directly used in downstream modules of the image acquisition system, including image encoding and compression, real-time display, storage caching, or neural network inference input. This data frame set has a complete structure and standardized format encapsulation, and has the characteristics of cross-channel alignment, clear buffer mapping, and controllable channel splicing order. It can effectively support the board system's stable data transmission and processing capabilities in high-concurrency, multi-source image acquisition tasks.

[0157] In one embodiment, such as Figure 2 As shown, a board image acquisition system is also provided, the system comprising:

[0158] The scheduling template generation module is used to construct an input channel mapping table based on the image acquisition board, perform multi-channel synchronous triggering processing according to the input channel mapping table, and generate a concurrent frame scheduling template.

[0159] A buffer object generation module is used to generate a frame block structure based on the concurrent frame scheduling template, and to generate a frame buffer object based on the frame block structure.

[0160] The image structure generation module is used to perform channel priority-driven frame block stitching based on the frame block structure and the frame buffer object to generate a complete frame image structure.

[0161] The output data generation module is used to encapsulate and output the image data according to the complete frame image structure to obtain the image output data frame.

[0162] In another embodiment, the scheduling template generation module is further configured to: establish channel mapping based on the image acquisition board and using the image source interface configuration to obtain an input channel mapping table; and execute synchronous triggering logic configuration and frame stream structure division according to the input channel mapping table to generate a concurrent frame scheduling template.

[0163] In another embodiment, the scheduling template generation module is further configured to: obtain the device interface attributes of the image acquisition board; obtain the channel support information of the image acquisition board; establish a static mapping of the channels; and construct an input channel mapping table.

[0164] In another embodiment, the scheduling template generation module is further configured to: perform synchronization channel filtering and grouping according to the input channel mapping table; and in response to the completion of synchronization channel filtering and grouping, construct trigger signal organization rules to generate a concurrent frame scheduling template.

[0165] In another embodiment, the buffer object generation module is further configured to: split the frame stream structure according to the concurrent frame scheduling template to generate a cross-channel aligned frame block structure; and allocate and register buffers according to the frame block structure to generate a frame buffer object.

[0166] In another embodiment, the image structure generation module is further configured to: prepare channel frame block scheduling based on the frame block structure and the frame buffer object; and in response to the completion of channel frame block scheduling preparation, perform priority-driven frame block stitching and generate a complete frame image structure.

[0167] In another embodiment, the output data generation module is further configured to: perform image frame format standardization processing and add image frame headers and frame control information according to the complete frame image structure; in response to completing the image frame format standardization processing and adding image frame headers and frame control information, perform data integrity encapsulation and cache alignment processing, and obtain image output data frames.

[0168] In one embodiment, such as Figure 3 As shown, a computer device is also provided, including a memory and a processor. The memory stores a computer program and an operating system. When the processor executes the computer program, it implements the steps described in the machine vision-based separator sieve surface separation and detection method. The computer device also includes a system bus, internal memory, network structure, display screen, and input devices.

[0169] In one embodiment, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps described in the board image acquisition method.

[0170] It should be noted that the information interaction and execution process between the above modules are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, which will not be repeated here.

[0171] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0172] It should be noted that the information interaction and execution process between the above modules are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, which will not be repeated here.

[0173] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0174] This application also provides a network device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor executes the computer program to implement the steps in any of the above method embodiments.

[0175] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0176] This application provides a computer program product that, when run on a mobile terminal, enables the mobile terminal to implement the steps described in the above-described method embodiments.

[0177] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the above-described embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a photographic device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0178] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0179] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0180] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0181] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0182] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

[0183] One embodiment of this application also provides a computer device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor executes the computer program to implement the steps in any of the above-described methods.

[0184] The computer device may include, but is not limited to, a processor and memory. Those skilled in the art will understand that the above description is an example of a computer device and does not constitute a limitation on the computer device. It may include more or fewer components than described above, or a combination of certain components, or different components, such as input / output devices, network access devices, etc.

[0185] The processor referred to can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0186] In some embodiments, the memory may be an internal storage unit of the computer device, such as a hard drive or RAM. In other embodiments, the memory may be an external storage device of the computer device, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory may include both internal and external storage units of the computer device. The memory is used to store the operating system, applications, bootloader, data, and other programs, such as the program code of the computer program. The memory can also be used to temporarily store data that has been output or will be output.

[0187] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0188] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for acquiring board images, characterized in that, The method includes: An input channel mapping table is constructed based on the image acquisition board. Multi-channel synchronous triggering processing is performed according to the input channel mapping table to generate a concurrent frame scheduling template. The process of generating a frame block structure based on the concurrent frame scheduling template and generating a frame buffer object based on the frame block structure specifically includes: splitting the frame stream structure based on the concurrent frame scheduling template to generate a cross-channel aligned frame block structure; and allocating and registering buffers based on the frame block structure to generate a frame buffer object. Based on the frame block structure and the frame buffer object, channel priority-driven frame block stitching is performed to generate a complete frame image structure; Based on the complete frame image structure, the format is encapsulated and output to obtain the image output data frame.

2. The board image acquisition method according to claim 1, characterized in that, An input channel mapping table is constructed based on the image acquisition board. Multi-channel synchronous triggering processing is performed according to the input channel mapping table to generate a concurrent frame scheduling template, including: Based on the image acquisition board, channel mapping is established using the image source interface configuration to obtain the input channel mapping table; Based on the input channel mapping table, execute the synchronous trigger logic configuration and frame stream structure division to generate a concurrent frame scheduling template.

3. The board image acquisition method according to claim 2, characterized in that, Based on the image acquisition board, channel mapping is established using the image source interface configuration, resulting in an input channel mapping table, including: Obtain the device interface properties of the image acquisition board; Obtain the channel support information of the image acquisition board; Establish static mappings for the channels and construct an input channel mapping table.

4. The board image acquisition method according to claim 2, characterized in that, Based on the input channel mapping table, synchronous triggering logic configuration and frame stream structure partitioning are performed to generate a concurrent frame scheduling template, including: Synchronization channels are filtered and grouped according to the input channel mapping table; In response to the completion of synchronization channel screening and grouping, trigger signal organization rules are constructed, and concurrent frame scheduling templates are generated.

5. The board image acquisition method according to claim 1, characterized in that, Based on the frame block structure and the frame buffer object, channel priority-driven frame block stitching is performed to generate a complete frame image structure, including: Prepare for channel frame block scheduling based on the frame block structure and the frame buffer object; In response to the completion of channel frame block scheduling preparation, priority-driven frame block splicing is performed, and a complete frame image structure is generated.

6. The board image acquisition method according to claim 1, characterized in that, Based on the complete frame image structure, the image is formatted and output to obtain an image output data frame, including: Based on the complete frame image structure, perform image frame format standardization processing and add image frame headers and frame control information; In response to completing the image frame format standardization process and adding image frame headers and frame control information, data integrity encapsulation and buffer alignment are performed, and the resulting image output data frame is obtained.

7. A board image acquisition system, characterized in that, The system includes: The scheduling template generation module is used to construct an input channel mapping table based on the image acquisition board, perform multi-channel synchronous triggering processing according to the input channel mapping table, and generate a concurrent frame scheduling template. The buffer object generation module is used to generate a frame block structure based on the concurrent frame scheduling template, and to generate a frame buffer object based on the frame block structure. Specifically, it includes: splitting the frame stream structure based on the concurrent frame scheduling template to generate a cross-channel aligned frame block structure; and allocating and registering buffers based on the frame block structure to generate a frame buffer object. The image structure generation module is used to perform channel priority-driven frame block stitching based on the frame block structure and the frame buffer object to generate a complete frame image structure. The output data generation module is used to encapsulate and output the image data according to the complete frame image structure to obtain the image output data frame.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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