Photoelectric conversion device and equipment

Abstract

The invention relates to a photoelectric conversion device and equipment. A photoelectric conversion device includes a pixel array and a read circuit having a plurality of column circuits configured to read signals from the pixel array. Each pixel includes a photoelectric converter that accumulates charges corresponding to incident light, a charge-voltage converter, a transporter that transports the charges from the photoelectric converter to the charge-voltage converter, a first amplification transistor that amplifies a voltage of the charge-voltage converter, a first current source that supplies a first current to the first amplification transistor, and a second current source that supplies a second current to the second amplification transistor. A storage device that holds an output of the first amplification transistor; and a second amplification transistor that amplifies a voltage supplied from the storage device. Each column circuit includes a second current source that supplies a second current to the second amplification transistor. The first current is less than the second current.

Description

TECHNICAL FIELD

[0001] The present application relates to a photoelectric conversion apparatus and an equipment. BACKGROUND

[0002] Japanese Patent Publication No. 2022-51548 describes a global shutter type CMOS image sensor in which each pixel includes a memory for holding a signal. In the global shutter method, a charge accumulation operation is started and ended at the same time in all pixels.

[0003] However, in the global shutter type CMOS image sensor, since the operation of writing a signal corresponding to the charge accumulated in the photoelectric converter into the memory is performed at the same time in all pixels, the peak of the current consumption becomes significantly large. SUMMARY

[0004] The present application provides a technique that is advantageous in suppressing the peak of the current consumption.

[0005] A first aspect of the present application provides a photoelectric conversion apparatus including: a pixel array including a plurality of pixels arranged to form a plurality of rows and a plurality of columns; and a reading circuit including a plurality of column circuits configured to read a signal from the pixel array, wherein each pixel includes: a photoelectric converter configured to accumulate a charge corresponding to incident light; a charge-voltage converter; a transporter configured to transport the charge from the photoelectric converter to the charge-voltage converter; a first amplification transistor configured to amplify a voltage of the charge-voltage converter; a first current source configured to supply a first current to the first amplification transistor; a storage configured to hold an output of the first amplification transistor; and a second amplification transistor configured to amplify a voltage supplied from the storage, each column circuit includes a second current source configured to supply a second current to the second amplification transistor, and the first current is smaller than the second current.

[0006] A second aspect of the present application provides an equipment including: a photoelectric conversion apparatus as defined in the first aspect of the present application; and a processing apparatus configured to process a signal output from the photoelectric conversion apparatus.

[0007] Other features of the present application will become apparent from the following description of example embodiments with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a view schematically showing an example of an arrangement of a photoelectric conversion apparatus according to an embodiment;

[0009] Figure 2 is a functional block diagram showing an example of an arrangement of a photoelectric conversion device according to an embodiment;

[0010] Figure 3 is a functional block diagram showing an example of an arrangement of a photoelectric conversion device according to an embodiment; Figure 1 and Figure 2 is a circuit diagram showing an example of an arrangement of a part of one pixel and one column circuit in the photoelectric conversion device exemplarily shown in

[0011] Figures 4A to 4C is a view showing three operation modes;

[0012] Figure 5 is a timing chart exemplarily showing a write operation in period B;

[0013] Figure 6 is a timing chart exemplarily showing a read operation in period C;

[0014] Figure 7 is a view showing an arrangement in which a pixel array is divided into a plurality of blocks;

[0015] Figure 8 is a timing chart exemplarily showing a partial global shutter mode; and

[0016] Figure 9 is a view showing an example of an arrangement of an apparatus according to an embodiment. DETAILED DESCRIPTION

[0017] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments are not intended to limit the scope of the claimed invention. A plurality of features described in the embodiments are not intended to limit the invention to all such features, and a plurality of such features can be appropriately combined. Furthermore, in the drawings, the same or similar components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0018] Figure 1 An example of an arrangement of a photoelectric conversion device 10 according to an embodiment is shown. Figure 2 An example of an arrangement of a photoelectric conversion device 10 according to an embodiment is shown. Figure 1 is a functional block diagram showing an example of an arrangement of a photoelectric conversion device according to an embodiment; Figure 1In the example of the arrangement shown in FIG. 1, the photoelectric conversion device 10 can be formed by stacking three substrates 100, 200, and 300. Each of the first substrate 100, the second substrate 200, and the third substrate 300 can include a semiconductor layer and a wiring structure. However, this is merely an example, and the photoelectric conversion device 10 can be formed by a single substrate, two substrates, or four or more substrates.

[0019] The first substrate 100 can include a first array 110 in which a plurality of first pixel components 30 are arranged to form a plurality of rows and a plurality of columns; a first control circuit 20; and a first vertical scanning circuit 120. The second substrate 200 can include a second array 210 in which a plurality of second pixel components 40 are arranged to form a plurality of rows and a plurality of columns; a second control circuit 21; a second vertical scanning circuit 220; and a bias generation circuit 230. One first pixel component 30 and one second pixel component 40 can constitute one pixel (a pixel PIX, which will be described later). That is, the first substrate 100 and the second substrate 200 can constitute a pixel array PA in which a plurality of pixels are arranged to form a plurality of rows and a plurality of columns.

[0020] The first vertical scanning circuit 120 is configured to control, for example, accumulation of electric charge in a photoelectric converter of each of the plurality of pixels, transportation of the electric charge from the photoelectric converter to a charge-voltage converter, reset of the charge-voltage converter, and output of a signal corresponding to a voltage of the charge-voltage converter. The first control circuit 20 can be configured to control the first vertical scanning circuit 120. The second vertical scanning circuit 220 can be configured to control, for example, a write operation of writing a signal into a storage device in each of the plurality of pixels and a read operation of a signal from the storage device. The second control circuit 21 can be configured to control the second vertical scanning circuit 220 and the bias generation circuit 230. The bias generation circuit 230 can be configured to generate a bias voltage or the like for controlling a first current source (which will be described later) in each pixel. The first vertical scanning circuit 120 and the second vertical scanning circuit 220 constitute a controller CNT that controls the plurality of pixels.

[0021] The third substrate 300 may include a readout circuit 310, a column control circuit 320 configured to control a plurality of column circuits 50 of the readout circuit 310, a bias generation circuit 330, a ramp generator 340, and a third control circuit 22, wherein the readout circuit 310 includes a plurality of column circuits 50 configured to read signals from the pixel array PA. The third control circuit 22 controls the column control circuit 320, the bias generation circuit 330, and the ramp generator 340. Each column circuit 50 is arranged to form a pixel readout signal for a corresponding column from among a plurality of columns of the pixel array PA. The bias generation circuit 330 may be configured to generate a bias voltage, etc., for controlling a second current source (described later) in each pixel. The ramp generator 340 may be configured to generate a ramp signal RAMP (described later) for AD conversion and supply it to the plurality of column circuits 50.

[0022] Figure 3 Shown Figure 1 and Figure 2 An example of arrangement of one pixel PIX and a part of a column circuit 50 in the photoelectric conversion device 10 is exemplarily shown in FIG. One pixel PIX can be composed of one first pixel component 30 and one second pixel component 40.

[0023] The first pixel component 30 that can be arranged in the first substrate 100 may include, for example, two photoelectric converters 115 and 116, but it may include only one photoelectric converter or three or more photoelectric converters. The first pixel component 30 may include a charge-voltage converter FD, transporters 113 and 114 that transport the charge accumulated in the photoelectric converters 115 and 116 to the charge-voltage converter FD, respectively, and a first reset unit 112 that resets the charge-voltage converter FD. The charge-voltage converter FD is a capacitor that converts charge into voltage and may include, for example, a floating diffusion formed by a diffusion region of a semiconductor layer, and parasitic capacitance. The first pixel component 30 may also include a first amplifying transistor 111 that amplifies the voltage of the charge-voltage converter FD. The first pixel component 30 may also include a first selection transistor 117, but the first selection transistor 117 may be omitted.

[0024] The second pixel assembly 40, which may be arranged in the second substrate 200, may include, for example, a first current source CS1, a first current source switching transistor 218 (a first control transistor), a storage device HLD, and sample / hold switches 213, 214, and 215. The second pixel assembly 40 may also include a second amplifying transistor 211, a second selecting transistor 219, and a second reset unit 212.

[0025] The column circuit 50 (read circuit 310) which can be arranged in the third substrate 300 can include a second current source switch transistor 315 (second control transistor), a second current source CS2, a read line 316, and a comparator circuit 311.

[0026] Each of the photoelectric converters 115 and 116 includes an anode and a cathode. The anodes of the photoelectric converters 115 and 116 can be connected to a ground potential SGND or a predetermined potential for the photoelectric converters 115 and 116. Each of the cathodes of the photoelectric converters 115 and 116 can be connected to one of the source and drain of the transistors forming the conveyers 113 and 114, respectively. Transport signals TXA and TXB are supplied from the first vertical scanning circuit 120 to the gates of the transistors forming the conveyers 113 and 114, respectively. The other of the source and drain of each of the transistors forming the conveyers 113 and 114 can be connected to the charge-voltage converter FD.

[0027] One of the source and drain of the transistor forming the first reset unit 112 can be connected to the charge-voltage converter FD, and the other can be connected to a power supply potential SVDD for the photoelectric converters 115 and 116. A first reset signal RES is supplied from the first vertical scanning circuit 120 to the gate of the transistor forming the first reset unit 112. The gate of the first amplification transistor 111 can be connected to the charge-voltage converter FD, one of the source and drain of the first amplification transistor 111 can be connected to the power supply potential SVDD, and the other can be connected to one of the source and drain of the first selection transistor 117. The other of the source and drain of the first selection transistor 117 can be connected to a read node VREADP of the second substrate 200 from the first substrate 100 via a first connection portion 1-1. A first selection signal SEL is supplied from the first vertical scanning circuit 120 to the gate of the first selection transistor 117. The first amplification transistor 111 and the first current source CS1 constitute a first source follower amplification circuit.

[0028] The read node VREADP can be connected to the first current source CS1 via the first current source switching transistor 218. A block selection signal BLK can be supplied from the first vertical scanning circuit 120 to the gate of the first current source switching transistor 218. The first current source CS1 can include, for example, a series connection of the first current source transistor 217 and the first cascode transistor 216, but can be formed of a single current source transistor or have another arrangement. Control voltages VBIAS1 and VGATE1 can be supplied from the bias generation circuit 230 to the gates of the first current source transistor 217 and the first cascode transistor 216, respectively. One of the source and drain of the first current source switching transistor 218 can be connected to the read node VREADP, and the other can be connected to, for example, the first cascode transistor 216. One of the source and drain of the first current source transistor 217 is connected to the first cascode transistor 216, and the other is connected to an analog circuit ground potential AGND.

[0029] One of the source and drain of each of the sampling switches 213, 214, and 215 can be connected to the read node VREADP. The other of the source and drain of each of the sampling switches 213, 214, and 215 can be connected to one end of each of the memories (hold capacitors) CN, CA, and CAB, respectively. The other end of each of the memories CN, CA, and CAB can be connected to a memory ground potential MGND. Control signals SWN, SWA, and SWAB can be supplied from the second vertical scanning circuit 220 to the gates of the sampling switches 213, 214, and 215, respectively. One of the source and drain of the transistors forming the second reset unit 212 can be connected to the memory power supply potential MVDD, and the other can be connected to the read node VREADP.

[0030] The gate of the second amplification transistor 211 can be connected to the read node VREADP, one of the source and drain can be connected to the memory power supply potential MVDD, and the other can be connected to one of the source and drain of the second selection transistor 219. The other of the source and drain of the second selection transistor 219 can be connected from the second substrate 200 to the output node VLOUT of the third substrate 300 via the second connection portion 2-1. A second selection signal SELM can be supplied from the second vertical scanning circuit 220 to the gate of the second selection transistor 219.

[0031] The output node VLOUT includes a read line (vertical signal line) 316 arranged to extend in the column direction, and is connected to the pixel PIX in the row selected by the second selection signal SELM among the pixels PIX arranged in a column (whose second amplification transistor 211).

[0032] The output node VLOUT can be connected to a second current source CS2 via a second current source switching transistor 315. A block selection signal BLKM can be supplied from the column control circuit 320 to the gate of the second current source switching transistor 315. The second current source CS2 can include, for example, a series connection of a second current source transistor 314 and a second cascode transistor 313, but can be formed of a single current source transistor or have another arrangement. The second amplification transistor 211 and the second current source CS2 constitute a second source follower amplification circuit. A control voltage VBIAS2 and VGATE2 can be supplied from a bias generation circuit 330 to the gates of the second current source transistor 314 and the second cascode transistor 313, respectively. One of the source and drain of the second current source switching transistor 315 can be connected to the output node VLOUT, and the other can be connected to, for example, the second cascode transistor 313. One of the source and drain of the second current source transistor 314 is connected to the second cascode transistor 313, and the other is connected to the ground potential AGND. The ground potential AGND of the third substrate 300 can be connected to the ground potential AGND of the second substrate 200 via a second connection portion 2-2.

[0033] Further, the output node VLOUT can be connected to one of the differential input terminals of a comparator circuit 311 connected to the analog circuit power supply potential AVDD and the analog circuit ground potential AGND. A ramp signal RAMP can be supplied from a ramp generator 340 to the other of the differential input terminals of the comparator circuit 311. Note that, based on a comparison result as an output of the comparator circuit 311, an image signal is converted from an analog signal to a digital signal.

[0034] In the above example, by isolating the power supply potentials SVDD, MVDD, and AVDD from the ground potentials SGND, MGND, and AGND from each other, the influence of fluctuations in the power supply potentials on other circuits is reduced. However, the present application is not limited to the above example, and a common power supply potential and a common ground potential can be used.

[0035] In the above example, the cascode transistors 216 and 313 are provided to suppress current changes caused by fluctuations in the drain voltages of the current source transistors 217 and 314. However, if the current changes caused by fluctuations in the drain voltages of the current source transistors 217 and 314 are small, the cascode transistors 216 and 313 are unnecessary.

[0036] The photoelectric conversion apparatus 10 can be configured to control the plurality of pixels PIX by a partial global shutter (PGS) method. Alternatively, the vertical drive circuit 30 can have a partial global shutter mode for controlling the plurality of pixels PIX by a partial global shutter (PGS) method, and a global shutter mode for controlling the plurality of pixels PIX by a global shutter (GS) method. The mode control can be performed by, for example, a mode instruction signal to the main controller (not shown) from the outside. The partial global shutter (PGS) method is a method of dividing the plurality of pixels PIX constituting the pixel array PA into a plurality of blocks (as shown in FIG. 8) and driving the pixels of each block by a global shutter method. Each block can include pixels arranged in the same row, and pixels arranged in different rows. In other words, each block can include an arbitrary number of pixels PIX whose positions are specified by two or more rows and two or more columns. Figure 7

[0037] Figure 4A The operation of the photoelectric conversion apparatus 10 in the global shutter (GS) mode is schematically shown. The period A is a period of accumulation during which the photoelectric converters 115 and 116 accumulate electric charges. The period B is a period of writing during which a signal (noise level or optical signal) corresponding to the electric charges accumulated by the photoelectric converters 115 and 116 is written to the storage device HLD (memory CN, CA, and CAB). The period C is a period of reading during which the signal is read from the plurality of pixels PIX (whose storage device HLD) constituting the pixel array PA in units of one row or a predetermined number of rows. In the global shutter mode, the operation in the period A is performed simultaneously in all the pixels PIX, and the operation in the period B is performed simultaneously in all the pixels PIX. Further, in the global shutter mode, the operation in the period C is performed so that the signal is sequentially read from the pixel array in units of one row or a predetermined number of rows.

[0038] Figure 5 ​A write operation in the period B is exemplarily shown. The accumulation period is until immediately before the time tl, and the period B (i.e., a write period) is from the time tl to the time tlO. First, immediately before the time tl, the first reset signal RES is at a high level, a transistor of the first reset unit 112 is turned ON, and the charge-voltage converter FD is set (reset) at a voltage corresponding to the power supply potential SVDD. Further, immediately before the time tl, the second reset signal RESC is also at a high level, a transistor of the second reset unit 212 is turned ON, and the read node VREADP is set (reset) at a voltage corresponding to the power supply potential MVDD. Further, immediately before the time tl, the control signals SWN, SWA, and SWAB are also at a high level, the sampling switches 213, 214, and 215 are turned ON, and one end of each of the memories CN, CA, and CAB is set (reset) at a voltage corresponding to the power supply potential SVDD.

[0039] Then, at the time tl, the second reset signal RESC is changed from a high level to a low level, so that a transistor of the second reset unit 212 is switched from ON to OFF. Further, at the time tl, the control signals SWN, SWA, and SWAB are changed from a high level to a low level, so that the sampling switches 213, 214, and 215 are switched from ON to OFF. That is, each of the memories CN, CA, and CAB holds a voltage immediately before the time tl. Further, at the time tl, the first selection signal SEL and the block selection signal BLK are changed from a low level to a high level, so that the first selection transistor 117 and the first current source switch transistor 218 are switched from OFF to ON. Thereby, a current flows through the first amplification transistor 111. In this state, the first amplification transistor 111 outputs a voltage (level) corresponding to the voltage of the charge-voltage converter FD to the read node VREADP.

[0040] Subsequently, at the time t2, the first reset signal RES is changed from a high level to a low level. If there is no noise, the voltage of the charge-voltage converter FD is maintained at the reset voltage, but in practice, it is set to a noise level corresponding to the noise.

[0041] Subsequently, from the time t2 to the time t3, the control signal SWN is set at a high level and the sampling switch 213 is switched to ON, so that a noise signal voltage (hereinafter referred to as an N signal) corresponding to the noise level is written in the memory CN. Then, at the time t3, the control signal SWN is changed from a high level to a low level. Thereby, the sampling switch 213 is switched from ON to OFF, and the memory CN holds the N signal.

[0042] Then, from time t4 to time t5, the first transport signal TXA is set at the high level, the transistor forming the first transporter 113 is switched on, and the charge in the first photoelectric converter 115 is transported to the charge-voltage converter FD. From time t5 to time t6, the control signal SWA is set at the high level, so that the sampling switch 214 is switched from off to on. Thereby, the first optical signal voltage (hereinafter referred to as SA signal) corresponding to the charge in the first photoelectric converter 115 is written in the memory CA. Then, at time t6, the control signal SWA is changed from the high level to the low level. Thereby, the sampling switch 214 is switched from on to off, and the memory CA holds the SA signal.

[0043] From time t7 to time t8, the first transport signal TXA and the second transport signal TXB are set at the high level, and the transistor forming the first transporter 113 and the transistor forming the second transporter 114 are switched on. Thereby, the charge in the first photoelectric converter 115 and the charge in the second photoelectric converter 116 are transported to the charge-voltage converter FD. In the charge-voltage converter FD, the charge from the first photoelectric converter 115 and the charge from the second photoelectric converter 116 are added.

[0044] From time t9 to time t10, the control signal SWAB is set at the high level, so that the sampling switch 215 is switched on. Thereby, the second optical signal voltage (hereinafter referred to as SAB signal) corresponding to the charges from the first photoelectric converter 115 and the second photoelectric converter 116 is written in the memory CAB. Then, at time t10, the control signal SWB is changed from the high level to the low level, so that the sampling switch 215 is changed from the high level to the low level. Thereby, the sampling switch 215 is changed from on to off, and the memory CAB holds the SAB signal. In this way, the N signal, the SA signal, and the SAB signal of each pixel PIX are held by the memories CN, CA, and CAB, respectively.

[0045] Figure 6 The read operation in the period C is exemplified. The period B ends at time t21. The read period (one horizontal scanning period) of the signals from the pixels PIX in the first row is from time t21 to time t30. Figure 6 The read period of the signals from the pixels PIX in the first row and the second row is exemplified.

[0046] At time t21, the selection signal SELM(1) (the number in parentheses indicates the row number) for the first row is changed from low to high, and the second selection transistor 219 of the pixel PIX in the first row is switched from off to on. In addition, at time t21, the block selection signal BLKM is changed from low to high, and the second current source switching transistor 315 is switched from off to on. Thereby, a current flows through the second amplification transistor 211 of the pixel PIX in the first row, and thus a signal can be read from the pixel PIX in the first row.

[0047] Then, from time t21 to time t22, the second reset signal RESC is set at high, and the voltage of the read node VREADP is set to a voltage corresponding to the power supply potential MVDD. Note that the voltage of the read node VREADP can be set to another voltage. Thereafter, from time t23 to time t24, the control signal SWN is set at high, and the sampling switch 213 is switched on. Thereby, the N signal held by the memory CN is supplied to the gate of the second amplification transistor 211, and the second amplification transistor 211 outputs a voltage corresponding to the N signal to the output node VLOUT. The comparator circuit 311 compares the voltage of the output node VLOUT with the ramp signal RAMP, and outputs a comparison result. A later-stage circuit (not shown) can be configured to output, as digital data corresponding to the N signal, a time (a count value of a counter) from the start of the comparison operation of the comparator circuit 311 to the inversion of the comparison result.

[0048] Subsequently, from time t24 to time t25, the second reset signal RESC is again set at high, and the voltage of the read node VREADP is set to a voltage corresponding to the power supply potential MVDD. This operation can reduce the influence of the state before the reading of a signal from the selected memory on the signal read from the selected memory.

[0049] From time t26 to time t27, the control signal SWA is set at high, and the sampling switch 214 is switched on. Thereby, the SA signal held by the memory CA is supplied to the gate of the second amplification transistor 211, and the second amplification transistor 211 outputs a voltage corresponding to the SA signal to the output node VLOUT. The comparator circuit 311 compares the voltage of the output node VLOUT with the ramp signal RAMP, and outputs a comparison result. A later-stage circuit (not shown) can be operated to output, as digital data corresponding to the SA signal, a time (a count value of a counter) from the start of the comparison operation of the comparator circuit 311 to the inversion of the comparison result.

[0050] Further, from time t27 to time t28, the second reset signal RESC is again set at the high level, and the voltage of the read node VREADP is set to the voltage corresponding to the power supply potential MVDD. From time t29 to time t30, the control signal SWAB is set at the high level, and the sampling switch 215 is switched on. Thereby, the SAB signal held by the memory CAB is supplied to the gate of the second amplification transistor 211, and the second amplification transistor 211 outputs the voltage corresponding to the SAB signal to the output node VLOUT. The comparator circuit 311 compares the voltage of the output node VLOUT with the ramp signal RAMP, and outputs the comparison result. A later stage circuit (not shown) can operate to output, as digital data corresponding to the SAB signal, the time (the count value of the counter) from the start of the comparison operation by the comparator circuit 311 to the inversion of the comparison result.

[0051] At time t30, the selection signal SELM(1) for the first row is changed from the high level to the low level, and the second selection transistor 219 of the pixel PIX in the first row is switched from on to off. On the other hand, at time t30, the selection signal SELM(2) for the second row is changed from the low level to the high level, and the second selection transistor 219 of the pixel PIX in the second row is switched from off to on. From time t30 to time t39, the read operation of the signal from the pixel PIX in the second row is performed similarly to the read operation of the signal from the pixel PIX in the first row. Thereafter, the signals from the pixels from the third row to the last row are similarly read.

[0052] The block selection signal BLKM can be changed from the high level to the low level at the timing at which the period C ends.

[0053] In the above-described example, the N signal, the SA signal, and the SAB signal are read from each pixel, but this is merely an example. For example, the N signal, the SA signal, and the SB signal (the SB signal is the optical signal level read from the photoelectric converter 116) can be read from each pixel. Alternatively, the N signal and the SAB signal can be read from each pixel. Alternatively, the N signal, the SB signal, and the SAB signal can be read from each pixel.

[0054] Note that the above-described arrangement and operation of the photoelectric conversion apparatus are merely examples for facilitating understanding, and the overall arrangement of the photoelectric conversion apparatus, the arrangement of each pixel, the driving method of each pixel, and the like can be changed as appropriate.

[0055] In this embodiment, the first current source CS1 (first current source transistor 217) is configured or controlled to supply the first amplification transistor 111 with a first current. The second current source CS2 (second current source transistor 314) is configured or controlled to supply the second amplification transistor 211 with a second current. Here, the first current (the magnitude of which) is preferably smaller than the second current (the magnitude of which). This can be adjusted by, for example, the voltage levels of the control voltages VBIAS1 and VBIAS2 generated by the bias generation circuits 230 and 330, respectively. For example, if the first current source transistor 217 and the second current source transistor 314 are formed by NMOS transistors, the first current (the magnitude of which) can be made smaller than the second current (the magnitude of which) by setting VBIAS1 < VBIAS2. It is preferable that the first current (the magnitude of which) satisfy at least one of the following conditions: 90% or less, 80% or less, 70% or less, 60% or less, 50% or less, 40% or less, 30% or less, 20% or less, and 10% or less of the second current (the magnitude of which). Alternatively, it is preferable that the first current (the magnitude of which) satisfy at least one of the following conditions: 1 / 2 or less, 1 / 4 or less, 1 / 8 or less, 1 / 16 or less, 1 / 32 or less, 1 / 64 or less, 1 / 128 or less, 1 / 256 or less, and 1 / 512 or less of the second current (the magnitude of which).

[0056] The advantage of making the first current (the magnitude of which) smaller than the second current (the magnitude of which) will be described below. One first amplification transistor 111 to which one first current source CS1 (first current source transistor 217) supplies the first current writes a signal in one of the memory CN, CA, and CAB at a time. Therefore, the current (the magnitude of which) required for one first current source CS1 (first current source transistor 217) is relatively small.

[0057] On the other hand, one second amplification transistor 211 to which one second current source CS2 (second current source transistor 314) supplies the second current needs to drive the load (capacitance) of the read line 316 extending in the column direction and the plurality of second selection transistors 219 connected thereto. Therefore, the current (the magnitude of which) required for one second current source CS2 (second current source transistor 314) is relatively large. Therefore, the first current (the magnitude of which) can be made smaller than the second current (the magnitude of which). In the global shutter mode, the first current sources CS1 (first current source transistors 217) of the plurality of pixels PIX constituting the pixel array PA are operated at the same time in the period B (writing period). Therefore, making the first current (the magnitude of which) smaller than the second current (the magnitude of which) is useful for suppressing the peak of the current consumption. By suppressing the peak of the current consumption, the power supply potential and the ground potential can be stabilized, and this is advantageous in reducing noise. Furthermore, suppressing the peak of the current consumption is also advantageous in reducing the amount of power consumption.

[0058] Figure 4B and Figure 4C Each of Figure 4B and Figure 4C Each of Figure 4B and 4C In the example shown in each of

[0059] In the example shown in Figure 4B , the read circuit 310 starts the period C (read period) in all of the pixels in the plurality of pixels PIX before the end of the period A (accumulation period) and the period B (write period). From another perspective, in the example shown in Figure 4B , the read operation (operation in the period C) in one block is performed in parallel with the operation in the period A or the period B (operation in the period A or B) in another block. In the example shown in Figure 4B , for example, the read circuit 310 performs the read operation on the signal from each block at the end of the write operation in each block.

[0060] In the example shown in Figure 4C , the read circuit 310 starts the period C (read period) in all of the pixels in the plurality of pixels PIX after the end of the period A (accumulation period) and the period B (write period). Figure 4C The example shown in

[0061] A partial global shutter (PGS) mode can be realized by, for example, providing a first selection signal SEL and a block selection signal BLK for each block so that they can be individually controlled for each block. More specifically, a plurality of first selection signals SEL1, SEL2,..., SELN and a plurality of block selection signals BLK1, BLK2,..., BLKN are provided, and they can be driven as shown in the following example in the partial global shutter (PGS) mode. Figure 8

[0062] Let I PGS be a peak value of current consumption of the first current source CS1 in a period A of a partial global shutter (PGS) mode, and I GS be a peak value of current consumption of the first current source CS1 in a period A of a global shutter (GS) mode, then I PGS = I GS / N holds. N is the number of blocks. In the partial global shutter mode, the control voltages VBIAS1 and VBIAS2 generated by the bias generation circuits 230 and 330 can also be adjusted so that the first current (its magnitude) is smaller than the second current (its magnitude).

[0063] In the above example, the plurality of pixels PIX constituting the pixel array PA are divided into N blocks, and the accumulation period and the write period are controlled for each block, but the accumulation period and the write period can be controlled for two or more predetermined numbers of blocks.

[0064] The size of the block (for example, the number of rows) can be decided so that the number of rows in which the write operation is performed per unit time is larger than the number of rows in which the read operation is performed per unit time.

[0065] According to making the first current flowing from the first current source CS1 smaller than the second current flowing from the second current source CS2, the W / L ratio of the first amplification transistor 111 can be made smaller than the W / L ratio of the second amplification transistor 211. Alternatively, according to making the first current flowing from the first current source CS1 smaller than the second current flowing from the second current source CS2, the area of the first amplification transistor 111 (its active region) can be made smaller than the area of the second amplification transistor 211 (its active region).

[0066] The W / L ratio and the area of a transistor will be described below. The current I flowing between the source and the drain of a transistor is expressed by the following formula:

[0067] I = β (W / L) · (Vgs - Vth)... (1)

[0068] where β is a gain coefficient, W is a channel width, L is a channel length, Vgs is a gate-source voltage, and Vth is a threshold voltage.

[0069] ​The channel width W and the channel length L are determined by the arrangement of the transistor. As expressed by Equation (1), the current I flowing between the source and the drain of the transistor is proportional to the W / L ratio of the channel width W and the channel length L of the transistor. According to making the first current flowing from the first current source CS1 smaller than the second current flowing from the second current source CS2, it is possible to make the current allowed to flow through the first amplification transistor 111 smaller than the current allowed to flow through the second amplification transistor 211.

[0070] Accordingly, according to making the first current flowing from the first current source CS1 smaller than the second current flowing from the second current source CS2, it is possible to make the W / L ratio of the first amplification transistor 111 lower than the W / L ratio of the second amplification transistor 211. If the channel length L of the first amplification transistor 111 is equal to the channel length L of the second amplification transistor 211, it is possible to make the channel width W of the first amplification transistor 111 smaller than the channel width W of the second amplification transistor 211. In other words, it is possible to make the area of the first amplification transistor 111 (active region thereof) smaller than the area of the second amplification transistor 211 (active region thereof). Making the area of the first amplification transistor 111 (active region thereof) small is advantageous in reducing the pixel size.

[0071] According to making the first current flowing from the first current source CS1 smaller than the second current flowing from the second current source CS2, it is possible to make the W / L ratio of the first current source transistor 217 lower than the W / L ratio of the second current source transistor 314. If the channel length L of the first current source transistor 217 is equal to the channel length L of the second current source transistor 314, it is possible to make the channel width W of the first current source transistor 217 smaller than the channel width W of the second current source transistor 314. In other words, it is possible to make the area of the first current source transistor 217 (active region thereof) smaller than the area of the second current source transistor 314 (active region thereof).

[0072] [Application Examples]

[0073] One application example of the photoelectric conversion apparatus 10 is an image capturing apparatus that generates an image (image data) by capturing an optical image. Other application examples of the photoelectric conversion apparatus are a distance measuring apparatus (an apparatus for focus detection, distance measurement using time of flight (TOF), and the like) and a light measuring apparatus (an apparatus for measuring the amount of incident light, and the like).

[0074] Reference Figure 9The following will describe equipment EQ incorporating the photoelectric conversion apparatus 10. The equipment EQ can include at least one of the photoelectric conversion apparatus 10 configured as an image sensor, an optical device 1040, a control device 1050, a processing device 1060, a display device 1070, a storage device 1080, and a mechanical device 1090. The optical device 1040 is implemented by, for example, a lens, a shutter, and a mirror. The control device 1050 controls the semiconductor chip 210. The control device 1050 is, for example, a semiconductor device such as an ASIC.

[0075] The processing device 1060 processes a signal output from the semiconductor chip 210. The processing device 1060 is a semiconductor device such as a CPU or an ASIC for forming an analog front end (AFE) or a digital front end (DFE). The display device 1070 is an EL display device or a liquid crystal display device that displays information (image) obtained by the semiconductor chip 210. The storage device 1080 is a magnetic device or a semiconductor device that stores information (image) obtained by the semiconductor chip 210. The storage device 1080 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0076] The mechanical device 1090 includes a moving or propelling unit such as a motor or an engine. In the equipment EQ, a signal output from the semiconductor chip 210 is displayed on the display device 1070 or transmitted to an external device through a communication device (not shown) included in the equipment EQ. Therefore, the equipment EQ can include the storage device 1080 and the processing device 1060 in addition to the memory circuit and the arithmetic circuit included in the semiconductor chip 210. The mechanical device 1090 can be controlled based on a signal output from the semiconductor chip 210.

[0077] Further, the equipment EQ is applicable to electronic equipment such as an information terminal (for example, a smartphone or a wearable terminal) having a photographing function or a camera (for example, a lens-interchangeable camera, a compact camera, a camcorder, or a surveillance camera) having a photographing function. The mechanical device 1090 in the camera can drive components of the optical device 1040 so as to perform a zooming, focusing operation, and a shutter operation. Alternatively, the mechanical device 1090 in the camera can move the semiconductor chip 210 so as to perform an anti-vibration operation.

[0078] Further, the equipment EQ can be a transport equipment such as a vehicle, a ship, or an airplane. The mechanical device 1090 in the transport equipment can be used as a mobile device. The equipment EQ as the transport equipment is suitable for an equipment that transports the semiconductor chip 210 or an equipment that assists and / or automates driving (steering) using a photographing function. The processing device 1060 for assisting and / or automating driving (steering) can perform processing for operating the mechanical device 1090 as a mobile device based on information obtained by the semiconductor chip 210. Alternatively, the equipment EQ can be a medical equipment such as an endoscope, a measuring equipment such as a distance measuring sensor, an analysis equipment such as an electron microscope, an office equipment such as a copier, or an industrial equipment such as a robot.

[0079] While the present application has been described with reference to example embodiments, it is to be understood that the application is not limited to the disclosed example embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. A photoelectric conversion device, the photoelectric conversion device comprising: a pixel array including a plurality of pixels arranged to form a plurality of rows and a plurality of columns; and a reading circuit including a plurality of column circuits configured to read signals from the pixel array, wherein each pixel includes a photoelectric converter configured to accumulate a charge corresponding to incident light, a charge-voltage converter, a transporter configured to transport the charge from the photoelectric converter to the charge-voltage converter, a first amplification transistor configured to amplify a voltage of the charge-voltage converter, a first current source configured to supply a first current to the first amplification transistor, a storage configured to hold an output of the first amplification transistor, and a second amplification transistor configured to amplify a voltage supplied from the storage, each column circuit includes a second current source configured to supply a second current to the second amplification transistor, and the first current is smaller than the second current.

2. The apparatus according to claim 1, further comprising a controller configured to control the plurality of pixels, wherein, the controller causes the plurality of pixels to simultaneously perform a write operation of transporting a charge from the photoelectric converter to the charge-voltage converter by the transporter and writing an output of the first amplification transistor into the storage.

3. The apparatus according to claim 1, further comprising a controller configured to control the plurality of pixels divided into a plurality of blocks, wherein the controller controls the plurality of pixels so that a period during which each pixel of the plurality of pixels performs a write operation of transporting a charge from the photoelectric converter to the charge-voltage converter by the transporter and writing an output of the first amplification transistor into the storage by the storage is the same within each individual block and is different between the plurality of blocks.

4. The apparatus according to claim 3, wherein the reading circuit performs a read operation of a signal from each block when the write operation in each block ends.

5. The apparatus according to claim 3, wherein the reading circuit starts a read operation of a signal from the plurality of pixels after the write operation in all of the plurality of blocks ends.

6. The apparatus according to claim 3, wherein each pixel further includes a first control transistor, the first amplification transistor, the first current source, and the first control transistor are connected in series, and the controller performs a write operation by turning on the first control transistor.

7. The apparatus according to claim 1, wherein the first current source includes a first current source transistor, and the second current source includes a second current source transistor, and a voltage is supplied to a gate of the first current source transistor and a gate of the second current source transistor so that the first current is smaller than the second current.

8. The apparatus according to claim 1, wherein A W / L ratio indicative of a channel width W to a channel length L of the first amplification transistor is lower than a W / L ratio of the second amplification transistor.

9. The apparatus according to claim 1, wherein, An area of the first amplification transistor is smaller than an area of the second amplification transistor.

10. The apparatus according to claim 1, wherein, The first current source includes a series connection of a first current source transistor and a first cascode transistor.

11. The apparatus according to claim 1, wherein, The second current source includes a series connection of a second current source transistor and a second cascode transistor.

12. The apparatus according to claim 1, wherein, The read circuit is arranged in a different substrate from a substrate in which the at least second amplification transistor of each of the plurality of pixels is arranged.

13. The apparatus according to any one of claims 1 to 12, wherein, Each column circuit includes a read line, and The second amplification transistor of each of the pixels forming a column among the plurality of pixels is connected to the read line of the corresponding column circuit among the plurality of column circuits.

14. The apparatus according to claim 13, wherein, Each pixel further includes a selection transistor, and The second amplification transistor of each of the pixels forming a column among the plurality of pixels is connected to the read line of the corresponding column circuit among the plurality of column circuits via the selection transistor.

15. The apparatus according to any one of claims 1 to 12, wherein, Components of the plurality of pixels are arranged in no less than two substrates.

16. An apparatus comprising: The photoelectric conversion apparatus according to any one of claims 1 to 15; and A processing apparatus configured to process a signal output from the photoelectric conversion apparatus.

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