Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the following steps: forming a plurality of conductive structures; forming a plurality of semiconductor main bodies which are positioned on one side of the conductive structure along the first direction and are connected with the conductive structure; forming a first dielectric layer, wherein the first dielectric layer is positioned among the plurality of conductive structures; forming a second dielectric layer, wherein the second dielectric layer is positioned among the plurality of semiconductor main bodies; and forming a third dielectric layer, wherein the third dielectric layer is located between the first dielectric layer and the second dielectric layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method of manufacturing the same. BACKGROUND

[0002] Semiconductor devices, such as dynamic random access memory (DRAM), are one of the most important access components in electronic systems, and usually adopt a transistor and a capacitor to form a 1T1C structure as a memory cell. Such a 1T1C structure makes the dynamic random access memory have a high integration and a low cost, and has an irreplaceable position in computer access devices. With the rapid development of semiconductor technology, dynamic random access memory is rapidly developing towards high density and high quality. SUMMARY

[0003] According to an aspect of the present disclosure, a semiconductor device is provided, comprising: a plurality of conductive structures; a plurality of semiconductor bodies, the semiconductor bodies being located on one side of the conductive structures along a first direction and connected with the conductive structures; a first dielectric layer between the plurality of conductive structures; a second dielectric layer between the plurality of semiconductor bodies; and a third dielectric layer between the first dielectric layer and the second dielectric layer.

[0004] In some embodiments, a dimension of the conductive structure in a cross section perpendicular to the first direction is greater than a dimension of the semiconductor body in a cross section perpendicular to the first direction.

[0005] In some embodiments, the conductive structure and the semiconductor body form a step structure at a connection therebetween, the step structure comprising a side surface extending along the first direction and a step surface extending along a second direction.

[0006] In some embodiments, a dimension of the step structure along the second direction is the same in the first direction, and a dimension of the step structure along the first direction is the same in the second direction.

[0007] In some embodiments, the conductive structure comprises at least a metal semiconductor compound layer.

[0008] In some embodiments, a metal element in the metal semiconductor compound layer comprises nickel, cobalt or titanium.

[0009] In some embodiments, the conductive structure further comprises a semiconductor layer, the semiconductor layer being in contact with the semiconductor body and located on a side of the metal semiconductor compound layer close to the semiconductor body.

[0010] In some embodiments, the material of the semiconductor layer comprises single-crystal material or polycrystal material.

[0011] In some embodiments, the conductive structure further comprises a metal layer, which is located on the side of the metal semiconductor compound layer away from the semiconductor layer.

[0012] In some embodiments, the third dielectric layer has a different etching selectivity ratio than the first dielectric layer.

[0013] In some embodiments, the first dielectric layer comprises oxide and the third dielectric layer comprises nitride.

[0014] In some embodiments, the third dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer; the first sub-dielectric layer extends along a second direction and covers the second dielectric layer, the second sub-dielectric layer extends along a first direction and covers part of the side surface of the semiconductor body; the second direction is perpendicular to the first direction.

[0015] In some embodiments, the semiconductor body extends into the conductive structure from one end of the two ends of the semiconductor body oppositely arranged along the first direction; the surface of the semiconductor body close to the conductive structure is higher than the surface of the second sub-dielectric layer close to the conductive structure.

[0016] In some embodiments, the sum of the size of the second sub-dielectric layer and the semiconductor body along the second direction is the same as the size of the conductive structure along the second direction.

[0017] In some embodiments, a plurality of semiconductor bodies are arranged in an array; the semiconductor device further comprises: a plurality of storage structures, each of the storage structures is located on the side of the two sides of the conductive structure along the first direction away from the semiconductor body, and is connected with the conductive structure; a plurality of word lines, each of the word lines is coupled with at least one side surface of each semiconductor body in a row of semiconductor bodies; a plurality of bit lines, each of the bit lines is coupled with the surface of each semiconductor body in a column of semiconductor bodies oppositely arranged along the first direction and away from the conductive structure.

[0018] In some embodiments, the word line is located on one side surface of the semiconductor body; or, the word line is located on two oppositely arranged side surfaces of the semiconductor body; or, the word line surrounds the side surface of the semiconductor body.

[0019] In some embodiments, two semiconductor bodies adjacent to each other form a semiconductor body group, two semiconductor bodies in a semiconductor body group are separated by a first isolation structure; two semiconductor body groups adjacent to each other are separated by a second isolation structure; the two word lines are respectively located in two side faces of the corresponding semiconductor bodies in the semiconductor body group, away from the side face of the first isolation structure.

[0020] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a plurality of conductive structures; forming a plurality of semiconductor bodies, the semiconductor bodies being located on one side of the conductive structures along a first direction and connected with the conductive structures; forming a first dielectric layer between the plurality of conductive structures; forming a second dielectric layer between the plurality of semiconductor bodies; and forming a third dielectric layer between the first dielectric layer and the second dielectric layer.

[0021] In some embodiments, the semiconductor bodies and the conductive structures are formed by: forming a plurality of initial semiconductor bodies extending along the first direction; the plurality of initial semiconductor bodies are separated by an initial dielectric layer; removing part of the initial dielectric layer along the first direction to expose part of the initial semiconductor bodies; the remaining initial dielectric layer forms the second dielectric layer; forming a liner layer covering the exposed side faces of the initial semiconductor bodies; filling a first dielectric layer between the liner layer; removing part of the initial semiconductor bodies; the remaining initial semiconductor bodies form the semiconductor bodies; removing part of the liner layer covering the side faces of the first dielectric layer to form a plurality of first grooves; the remaining liner layer forms the third dielectric layer; and forming the conductive structures in the first grooves.

[0022] In some embodiments, the surface of the remaining initial semiconductor bodies is higher than the surface of the third dielectric layer close to the first dielectric layer.

[0023] In some embodiments, the liner layer and the first dielectric layer have different etching selectivity ratios.

[0024] In some embodiments, forming the conductive structures in the first grooves comprises: forming an initial semiconductor layer in the first grooves; and performing a metallization process on the initial semiconductor layer to form a metal semiconductor compound layer.

[0025] In some embodiments, forming the initial semiconductor layer in the first grooves comprises: forming the initial semiconductor layer in the first grooves by a deposition process, and the material of the initial semiconductor layer comprises a polycrystalline material.

[0026] In some embodiments, the forming the initial semiconductor layer in the first trench includes forming the initial semiconductor layer in the first trench by an epitaxy process, and a material of the initial semiconductor layer includes a single crystal material.

[0027] In some embodiments, the method further includes forming a metal layer on the metal-semiconductor compound layer.

[0028] In some embodiments, the method further includes forming a storage structure on a side of the conductive structure away from the semiconductor body in two sides of the conductive structure along the first direction; forming a word line on at least one side of the semiconductor body; and forming a bit line on a surface of the semiconductor body away from the conductive structure in two surfaces of the semiconductor body oppositely arranged along the first direction.

[0029] Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device includes: forming a plurality of conductive structures; forming a plurality of semiconductor bodies, the semiconductor bodies being located on a side of the conductive structures along a first direction and connected with the conductive structures; forming a first dielectric layer between the plurality of conductive structures; forming a second dielectric layer between the plurality of semiconductor bodies; and forming a third dielectric layer between the first dielectric layer and the second dielectric layer. The conductive structures are formed by thickening and metallizing a part of an initial semiconductor body used to form the semiconductor bodies, while the semiconductor bodies are formed by another part of the initial semiconductor body. Since the initial semiconductor body is formed in one step from bottom to top, and the conductive structures and the semiconductor bodies share the same initial semiconductor body, the conductive structures and the semiconductor bodies can be directly self-aligned, and the conductive structures with larger size can be obtained by thickening the initial semiconductor body through the spacer layer (corresponding to the third dielectric layer), so as to improve the connection window between the conductive structures and the storage structures, and also to reduce the contact resistance.

[0030] Meanwhile, the spacer layer is conformally formed on the surface of the initial semiconductor body by the way of thickening the initial semiconductor body through the spacer layer, and the process controllability is good. In addition, the way of thickening the initial semiconductor body through the spacer layer does not need to provide an additional mask layer, which is conducive to reducing the manufacturing cost. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 A structure diagram of a dynamic random access memory provided by embodiments of the present disclosure Figure 1 ;

[0032] Figure 2a-2d A structure diagram of a conductive structure in a manufacturing process provided by embodiments of the present disclosure

[0033] Figure 3 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is provided.

[0034] Figures 4a to 4d A cross-sectional view of a process for forming an initial semiconductor body according to an embodiment of the present disclosure is provided.

[0035] Figures 5a to 5d A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided. Figure 1 ;

[0036] Figures 6a to 6c A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided. Figure 1 ;

[0037] Figures 7a to 7e A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided.

[0038] Figures 8a to 8d A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided. Figure 3 ;

[0039] Figures 9a to 9e A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided.

[0040] Figures 10a to 10i A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided.

[0041] Figures 11a to 11c A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided.

[0042] Figures 12a to 12d A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided. ;

[0043] Figure 13 A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided.

[0044] Figure 14 A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided. Figure 3 .

[0045] In the drawings, which are not necessarily drawn to scale, like numerals describe similar components throughout the several views. Like numerals having different letter suffixes can represent different instances of the components. The drawings illustrate generally, by way of example, various embodiments discussed herein. DETAILED DESCRIPTION

[0046] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. While example embodiments of the present disclosure are described herein, the present disclosure can be embodied in various forms without being limited to specific described embodiments. Rather, these embodiments are provided as examples of implementing the present disclosure, with the understanding that the scope of the disclosure is to be given the broadest interpretation in accordance with the appended claims.

[0047] In the following description, numerous specific details are given to provide a thorough understanding of the present disclosure. However, it will be apparent that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known structures and techniques have not been described in order to avoid obscuring the understanding of this description. In the following description, numerous specific details are presented to provide a thorough understanding of the present disclosure. One skilled in the relevant art, however, will recognize that the present disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. Some features have not been described in detail because they can be apparent to one skilled in the art, or can not be necessary for an understanding of the present disclosure.

[0048] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0049] It is to be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device described herein is turned over, then a relative prefi x term such as "below" can be interpreted as "above" or "up". The spatially relative terms can be interpreted differently depending on the particular orientation of the device. Thus, the examples described herein should be understood not to be limited to the following described orientations, but are to be interpreted as a broader description of the application, in suitable form. The application or devices shown in the figures can be manufactured, used, or shipped in a number of positions and orientations. For example, the device can be inverted or rotated about 90-degrees (or another suitable angle). Accordingly, the spatially relative terms can, as appropriate, mean both the absolute directions as well as the reverse directions.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0051] In order to enable a person skilled in the art to more fully understand the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present disclosure.

[0052] The semiconductor device related to the embodiments of the present disclosure is at least a part of a final device structure to be used in subsequent processes. Here, the final device can include a memory, which includes but is not limited to a dynamic random access memory, and only the dynamic random access memory is taken as an example for description below. However, it should be noted that the description of the dynamic random access memory in the following embodiments is only used to illustrate the present disclosure, and does not limit the scope of the present disclosure.

[0053] The semiconductor device related to the embodiments of the present disclosure is at least a part of a final device structure to be used in subsequent processes. Here, the final device can include a memory, which includes but is not limited to a dynamic random access memory, and only the dynamic random access memory is taken as an example for description below. However, it should be noted that the description of the dynamic random access memory in the following embodiments is only used to illustrate the present disclosure, and does not limit the scope of the present disclosure.

[0054] With the development of dynamic random access memory technology, the size of the storage unit is getting smaller and smaller, and its array architecture is from 8F 2 to 6F 2 to 4F 2 ; in addition, based on the requirements of dynamic random access memory for ion and leakage current, the architecture of the memory is from planar array transistor to recess gate array transistor, from recess gate array transistor to buried channel array transistor, and from buried channel array transistor to vertical channel array transistor.

[0055] In some embodiments of the present disclosure, regardless of whether planar transistors or buried transistors are used, the dynamic random access memory is composed of multiple memory cells, each of which is composed of a transistor and a capacitor controlled by the transistor, that is, the dynamic random access memory includes a 1 transistor (T, Transistor) and 1 capacitor (C, Capacitance) (1T1C) architecture; its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0056] The following combination Figure 1 A detailed description of one of the architectures of dynamic random access memory is given. Figure 1 Before illustrating a semiconductor device, various directions that may be used in the following description are defined. The direction in which the semiconductor body extends is defined as a first direction (i.e., the Z direction). A second direction (i.e., the X direction) and a third direction (i.e., the Y direction) intersecting with each other are defined in a plane perpendicular to the Z direction. In some embodiments, the X direction, the Y direction, and the Z direction may be perpendicular to each other.

[0057] A cross-sectional view of a three-dimensional (3D) dynamic random access memory 100 including vertical transistors is provided in an embodiment of the present disclosure; Figure 1 As shown, dynamic random access memory 100 includes a first device 102 and a second device 104 stacked on top of first device 102 along the Z-axis. First device 102 and second device 104 are connected via a bonding interface 106. First device 102 and second device 104 may be connected via hybrid bonding or other methods. In some embodiments, second device 104 may be bonded face-to-face on top of first device 102 at bonding interface 106. First device 102 may include a first substrate 1010, peripheral circuitry 1012 located on one side of first substrate 1010, and a first interconnect layer 1016 located on a side of peripheral circuitry 1012 away from first substrate 1010. First interconnect layer 1016 is configured to transmit electrical signals of peripheral circuitry 1012. Peripheral circuitry 1012 may include a plurality of transistors 1014. In some embodiments, trench isolation (such as shallow trench isolation STI) and doped regions (such as the well, source, and drain of the transistor 1014 ) may also be formed on or in the first substrate 1010 .

[0058] The first device 102 can also include a first bonding layer 1018 at the bonding interface 106 and located on a side of the first interconnect layer 1016 away from the peripheral circuit 1012. The first bonding layer 1018 can include a plurality of first bonding contacts 1019 and a dielectric that electrically isolates the first bonding contacts 1019. The first bonding contacts 1019 and the surrounding dielectric in the first bonding layer 1018 can be used for hybrid bonding. In contrast, the second device 104 can also include a second bonding layer 1020 at the bonding interface 106 and located on a side of the first bonding layer 1018 away from the first interconnect layer 1016. The second bonding layer 1020 can include a plurality of second bonding contacts 1021 and a dielectric that electrically isolates the second bonding contacts 1021. The second bonding contacts 1021 and the surrounding dielectric in the second bonding layer 1020 can be used for hybrid bonding. Here, the second bonding contacts 1021 contact the first bonding contacts 1019 at the bonding interface 106.

[0059] In some embodiments, the peripheral circuit 1012 can also include word lines (WL) and word line drivers / row decoders in the second interconnect layer 1022 coupled to the first bonding contacts 1019 in the first bonding layer 1018 and the second bonding contacts 1021 in the second bonding layer 1020 and the first interconnect layer 1016. In other embodiments, the peripheral circuit 1012 can also include bit lines 1023 (BL) and bit line drivers / column decoders in the second interconnect layer 1022 coupled to the first bonding contacts 1019 in the first bonding layer 1018 and the second bonding contacts 1021 in the second bonding layer 1020 and the first interconnect layer 1016, where the second interconnect layer 1022 includes the bit lines 1023 above the second bonding layer 1020, the bit lines 1023 used to transmit electrical signals. In other embodiments, the first device 102 and the second device 104 can not be connected by bonding, but instead can be integrated on the same substrate (only the first substrate, not the second substrate) and connected directly by one or more interconnect layers between the first device 102 and the second device 104. In this case, the first bonding layer 1018 and the first bonding contacts 1019 are not present in the first device 102, the second bonding layer 1020 and the second bonding contacts 1019 are not present in the second device 104, and the bonding interface 106 is not present between the first device 102 and the second device 104.

[0060] Reference Figure 1 The second device 104 also includes an array of memory cells on the second interconnect layer 1022, which can include a plurality of memory cells 1024, a second substrate 1048 on the memory cells 1024, and a third interconnect layer 1050 on the second substrate 1048. Figure 1A cross-section of a dynamic random access memory 100 in the middle can be taken along the bit line direction (X-axis direction), and a bit line 1023 in a second interconnect layer 1022 extending laterally in the X-axis direction can be coupled to a column of memory cells 1024.

[0061] Here, each memory cell 1024 can include a vertical transistor 1026 and a capacitor structure 1028 coupled to the vertical transistor 1026; the vertical transistor 1026 includes a semiconductor body 1030 extending vertically (in the Z-axis direction) and a gate structure 1036 contacting one side of the semiconductor body 1030 in the bit line direction (X-axis direction); in other embodiments, the gate structure can also fully surround the semiconductor body, half- surround the semiconductor body, be located at two opposite sides of the semiconductor body, etc., which are not elaborated here. Here, the gate structure 1036 includes a gate electrode 1034 and a gate dielectric 1032 located between the gate electrode 1034 and the semiconductor body 1030 in the bit line direction (X-axis direction). In some embodiments, the gate dielectric 1032 abuts one side of the semiconductor body 1030, and the gate electrode 1034 abuts the gate dielectric 1032.

[0062] In some embodiments, the semiconductor body 1030 has two ends (an upper end and a lower end) in the vertical direction (Z-axis direction), and one end (e.g., the lower end in the middle) extends beyond the gate dielectric 1032 into an interlayer dielectric (ILD) layer in the vertical direction (Z-axis direction), and the other end (e.g., the upper end in the middle) of the semiconductor body 1030 is flush with a corresponding end of the gate dielectric 1032. In other embodiments, both ends (the upper end and the lower end) of the semiconductor body 1030 extend beyond the gate electrode 1034 into the ILD layer in the vertical direction (Z-axis direction). Figure 1 Figure 1 In some embodiments, the semiconductor body 1030 has two ends (an upper end and a lower end) in the vertical direction (Z-axis direction), and one end (e.g., the lower end in the middle) extends beyond the gate dielectric 1032 into an interlayer dielectric (ILD) layer in the vertical direction (Z-axis direction), and the other end (e.g., the upper end in the middle) of the semiconductor body 1030 is flush with a corresponding end of the gate dielectric 1032. In other embodiments, both ends (the upper end and the lower end) of the semiconductor body 1030 extend beyond the gate electrode 1034 into the ILD layer in the vertical direction (Z-axis direction).

[0063] ​The vertical transistor 1026 can also include a source 1038 and a drain 1040 disposed at two end portions (upper end portion and lower end portion) of the semiconductor body 1030 in the vertical direction (Z-axis direction), respectively (the positions of the source and the drain can be exchanged, and hereinafter, the upper end portion is taken as the source 1038 and the lower end portion is taken as the drain 1040 as an example). In some embodiments, the source 1038 is coupled to the capacitor 1028, and the drain 1040 is coupled to the bit line 1023.

[0064] Since the gate electrode can be part of or extend in the word line direction as a word line, the second device 104 of the dynamic random access memory 100 can also include a plurality of word lines each extending in the word line direction (Y-axis direction). Here, each word line 1034 can be coupled to a row of the memory cell 1024.

[0065] The vertical transistor 1026 extends vertically through and contacts the word line 1034, and the drain 1040 of the vertical transistor 1026 at its lower end portion contacts the bit line 1023. Therefore, due to the vertical arrangement of the vertical transistor 1026, the word line 1034 and the bit line 1023 can be disposed in different planes in the vertical direction, which simplifies the wiring of the word line 1034 and the bit line 1023. Here, the vertical transistor 1026 can be arranged in a mirror-symmetrical manner to increase the density of the memory cell 1024 in the bit line direction (X-axis direction). Two adjacent vertical transistors 1026 in the bit line direction are mirror-symmetrical to each other with respect to the trench isolation 1060, that is, the second device 104 can include a plurality of trench isolations 1060 each extending in the word line direction (Y-axis direction) parallel to the word line 1034 and disposed between two adjacent rows of the semiconductor body 1030 of the vertical transistor 1026. In some embodiments, the rows of the vertical transistor 1026 separated by the trench isolation 1060 are mirror-symmetrical to each other with respect to the trench isolation 1060. It should be understood that the trench isolation 1060 can include an air gap each disposed laterally between adjacent semiconductor bodies 1030. The second device 104 also includes a plurality of gate isolations 1062 each extending in the word line direction (Y-axis direction) parallel to the word line 1034 and disposed between two adjacent rows of the word line 1034 of the vertical transistor 1026. It should be understood that the dimensions of the gate isolation 1062 and the word line 1034 in the bit line direction (X-axis direction) can be the same as or different from the dimensions of the trench isolation 1060 in the bit line direction (X-axis direction); when the dimensions of the gate isolation 1062 and the word line 1034 in the bit line direction (X-axis direction) are different, the spacing between the plurality of semiconductor bodies 1030 arranged in the bit line direction (X-axis direction) is different, that is, the plurality of semiconductor bodies 1030 arranged in the bit line direction (X-axis direction) are non-uniformly arranged.

[0066] As Figure 1 As shown, the capacitor structure 1028 is located above the source 1038 of the vertical transistor 1026 (ie, the upper end of the semiconductor body 1030 ) and contacts the source 1038 . The capacitor structure 1028 may be a vertical capacitor.

[0067] In some embodiments, a conductive structure 1064 is formed between the capacitor structure 1028 and the vertical transistor 1026 to reduce contact resistance. Figure 1 As shown, the conductive structure 1064 may include a semiconductor layer, a metal-semiconductor compound layer, and a metal layer stacked sequentially from bottom to top.

[0068] like Figure 1 As shown, the second device 104 may further include a capacitor contact 1047 in contact with the common plate of the vertical transistor 1026 for coupling the second electrode 1046 of the capacitor structure 1028 to the peripheral circuit 1012 or directly to ground. In some embodiments, the ILD layer forming the capacitor structure 1028 has the same dielectric material as the two ILD layers into which the semiconductor body 1030 extends, such as silicon oxide. The configuration of the capacitor structure 1028 may include any suitable structure and configuration, such as a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor.

[0069] like Figure 1 As shown, vertical transistor 1026 extends vertically through word line 1034 and contacts word line 1034, a drain 1040 of vertical transistor 1026 at its lower end contacts bit line 1023, and a source 1038 of vertical transistor 1026 at its upper end contacts capacitor structure 1028. That is, due to the vertical arrangement of vertical transistor 1026, bit line 1023 and capacitor structure 1028 can be arranged in different planes in the vertical direction and vertically coupled to opposite ends of vertical transistor 1026 of memory cell 1024. In some embodiments, bit line 1023 and capacitor structure 1028 are arranged on opposite sides of vertical transistor 1026 in the vertical direction, which simplifies the routing of bit line 1023 and reduces the coupling capacitance between bit line 1023 and capacitor structure 1028 compared to conventional memory cells in which the bit line and capacitor structure are arranged on the same side of a planar transistor.

[0070] In some embodiments, the vertical transistor 1026 is disposed vertically between the capacitance structure 1028 and the bonding interface 106. That is, the vertical transistor 1026 can be arranged closer to the peripheral circuit 1012 of the first device 102 and the bonding interface 106 than the capacitance structure 1028. As the bit line 1023 and the capacitance structure 1028 are coupled to opposite ends of the vertical transistor 1026, as such, the bit line 1023 (as part of the second interconnect layer 1022) is disposed vertically between the vertical transistor 1026 and the bonding interface 106 to reduce interconnect routing distance and complexity.

[0071] In some embodiments, the second device 104 further includes a second substrate 1048 disposed above the memory cell 1024, and a pad-out third interconnect layer 1050 above the memory cell 1024. The pad-out third interconnect layer 1050 can include interconnects in one or more ILD layers, e.g., contact pads 1054.

[0072] In some embodiments, the second device 104 further includes one or more contacts 1052 extending through portions of the pad-out third interconnect layer 1050 and the second substrate 1048 to couple the pad-out third interconnect layer 1050 to the memory cell 1024 and the second interconnect layer 1022. As such, the peripheral circuit 1012 can be coupled to the memory cell 1024 through the first interconnect layer 1016 and the second interconnect layer 1022 and the second bonding layer 1020 and the first bonding layer 1018, and the peripheral circuit 1012 and the memory cell 1024 can be coupled to external circuits through the contacts 1052 and the pad-out third interconnect layer 1050.

[0073] As previously mentioned, to reduce contact resistance between the capacitance structure 1028 and the vertical transistor 1026, a conductive structure 1064 is disposed between the capacitance structure 1028 and the vertical transistor 1026. Embodiments of the present disclosure provide a method of fabricating the conductive structure 1064, with reference to Figure 2a-2d .

[0074] As shown in FIG. 20, a mask layer 2020 is formed on the semiconductor body 1030 (which is subsequently used to form the aforementioned vertical transistor 1026). Figure 2a

[0075] As shown in FIG. 21, a conductive hole 2030 is formed in the mask layer 2020 using a self-alignment technique to expose a surface of the semiconductor body 1030 proximate to the mask layer 2020. Figure 2b

[0076] Figure 2c ​​​As shown, a semiconductor material (e.g., polysilicon) is deposited in the conductive hole 2030, the semiconductor material is optionally doped, and the semiconductor material is etched back (EB) to form a semiconductor layer 6010; then, a metal semiconductor compound layer 5010, such as cobalt silicide (CoSi), is formed on the semiconductor layer.

[0077] As shown, a metal material is deposited in the conductive hole 2030, and chemical mechanical polish (CMP) is performed to form a metal layer 1130, such as titanium nitride (TiN), tungsten (W), etc., on the metal semiconductor compound layer 5010. The semiconductor layer 6010, the metal semiconductor compound layer 5010, and the metal layer 1130 form a conductive structure 1064. Figure 2d

[0078] In the above embodiment, the alignment accuracy between the semiconductor body 1030 and the conductive structure greatly depends on the pattern accuracy of the mask layer, and the photolithography process corresponding to the mask layer requires high accuracy. Meanwhile, the depth difference between the semiconductor body and the word line in the Z-axis direction, technical defects existing in the process of forming the metal silicide layer, etc., increase the difficulty of alignment between the conductive structure 1064 and the semiconductor body 1030. In addition, the cost of the mask layer and other problems also increase the manufacturing cost.

[0079] To solve one or more of the above problems, the disclosure embodiments also provide a method for manufacturing a semiconductor device. Referring to Figure 3 Figure 3 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the disclosure is shown; the method comprises:

[0080] Step S301: forming a plurality of conductive structures;

[0081] Step S302: forming a plurality of semiconductor bodies, the semiconductor bodies being located on one side of the conductive structures along a first direction and connected to the conductive structures;

[0082] Step S303: forming a first dielectric layer between the plurality of conductive structures;

[0083] Step S304: forming a second dielectric layer between the plurality of semiconductor bodies;

[0084] Step S305: forming a third dielectric layer between the first dielectric layer and the second dielectric layer.

[0085] It should be understood that the steps shown in the above embodiments are not exclusive, and other steps can be performed before, after, or between any of the steps shown. Figure 3 It should be understood that the steps shown in the above embodiments are not exclusive, and other steps can be performed before, after, or between any of the steps shown.​​ Figure 3 The steps shown in the above can be adjusted in sequence according to actual needs. It should be noted that the semiconductor device can include one conductive structure, one semiconductor body and one storage structure, or multiple conductive structures, multiple semiconductor bodies and multiple storage structures. Here and hereinafter, the semiconductor device is taken as an example including multiple conductive structures, multiple semiconductor bodies and multiple storage structures.

[0086] As described above, there can be various different relative positions between the gate structure and the semiconductor body in the semiconductor device, and the specific manufacturing method corresponding to the different relative positions is different. In the embodiment of the present disclosure, the two gate structures corresponding to the two semiconductor bodies adjacent to each other are taken as an example to be described, and based on this, the semiconductor device can include multiple conductive structures, multiple semiconductor bodies and multiple storage structures arranged in an array along the X-axis direction and the Y-axis direction. It should be understood that the following method for forming the semiconductor structure is only used to illustrate the present disclosure, and is not used to limit the scope of the present disclosure. Figure 1 The back-to-back arrangement is shown in the above.

[0087] The method for forming the conductive structure and the semiconductor body includes various methods, and several exemplary methods are shown in the embodiment of the present disclosure. The forming process of the multiple conductive structures and the multiple semiconductor bodies will be described in detail below with reference to the drawings.

[0088] In the process of performing steps S301 to S305, first, the forming process of the conductive structure and the semiconductor body is introduced.

[0089] In some embodiments, the conductive structure and the semiconductor body are formed, including:

[0090] The multiple initial semiconductor bodies extending along the first direction are formed; the multiple initial semiconductor bodies are separated by an initial dielectric layer;

[0091] Part of the initial dielectric layer is removed along the first direction, and part of the initial semiconductor body is exposed; the remaining initial semiconductor body forms the semiconductor body;

[0092] At least part of the exposed initial semiconductor body is subjected to a metallization process to form a metal semiconductor compound layer; the exposed initial semiconductor body subjected to the metallization process serves as the conductive structure.

[0093] Figures 4a to 4d A cross-sectional view in the process of forming the initial semiconductor body is provided for the embodiment of the present disclosure. It should be noted that, Figure 4c A cross-sectional view along AA' direction is shown in the above. Figure 4b The forming process of the multiple initial semiconductor bodies will be described in detail below with reference to the drawings.

[0094] Referring to Figure 4a , a substrate 4000 is provided, and the material of the substrate 4000 can be a semiconductor material, such as silicon, and more specifically, the material of the substrate 4000 can be monocrystalline silicon.

[0095] Referring to Figure 4b , Figure 4c , a plurality of initial semiconductor bodies 4010 arranged in an array are formed in the substrate 4000. In some embodiments, the initial semiconductor bodies 4010 can be formed by first forming a plurality of trenches extending along the X-axis direction in the substrate 4000, filling the trenches with an insulating material (such as silicon oxide), and then forming a plurality of trenches extending along the Y-axis direction in the substrate 4000, the trenches extending along the Y-axis direction being adjusted according to the relative positions between the gate structures and the semiconductor bodies, Figure 4b As shown in FIG. 4B, when the two gate structures corresponding to the two semiconductor bodies are arranged back-to-back, the trenches extending along the Y-axis direction include trenches of different sizes arranged alternately, and the remaining insulating material after the trenches are filled is removed, thereby forming the initial semiconductor bodies 4010 arranged in an array.

[0096] It should be noted that Figure 4c The shape of the cross section of the initial semiconductor body along the X-axis and the Y-axis shown in FIG. 4A is square, which is only used for illustration and does not limit the shape of the cross section of the initial semiconductor body and the semiconductor body formed subsequently from the initial semiconductor body, and the shape of the cross section of the initial semiconductor body and the semiconductor body can also include a rectangle, a circle, an ellipse, an approximate shape of these shapes, etc.

[0097] In other embodiments, the initial semiconductor bodies 4010 can also be formed by first forming a plurality of trenches extending along the Y-axis direction in the substrate 4000, filling the trenches with an insulating material (such as silicon oxide), and then forming a plurality of trenches extending along the X-axis direction in the substrate 4000.

[0098] In some specific embodiments, the trenches extending along the X-axis direction and / or the Y-axis direction can be formed by a photolithography process (hereinafter can be understood as lithography-etch (LE)). The method for filling the trenches with an insulating material includes but is not limited to a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc.

[0099] Next, referring to Figure 4dAccording to the requirements of subsequent semiconductor device manufacturing processes, a first isolation structure 4020 and a second isolation structure 4030 are formed in the trench extending along the Y-axis direction. It can be understood that the first isolation structure 4020 is similar to Figure 1 The role of the trench isolation 1060 is similar to the second isolation structure 4030. Figure 1 The function of the middle gate isolation 1062.

[0100] In some embodiments, as Figure 4d The first isolation structure 4020 may include an air gap 4021 and a capping layer 4022, wherein the air gap 4021 may include air; the material of the capping layer 4022 includes but is not limited to silicon oxide. In other embodiments, the first isolation structure 4020 may also include a conductive material layer and a protective layer ( Figure 4d (not shown), the conductive material layer can provide a good electrostatic shielding effect. However, it should be noted that when the first isolation structure 4020 includes a conductive material layer, the protective layer must surround the conductive material layer to prevent the conductive material layer from contacting the semiconductor pillar. In some specific embodiments, the method for forming the first isolation structure 4020 includes, but is not limited to, PVD, CVD, ALD, and other processes.

[0101] In some embodiments, as Figure 4d The second isolation structure 4030 may include a gate structure 4031, a gate spacer 4032 between the gate structures, and an initial dielectric layer 4033 above the gate structure, wherein the gate structure 4031 may include a gate electrode and a gate dielectric. Optionally, the gate structure 4031 may further include a barrier layer located between the gate electrode and the gate dielectric. The material of the gate electrode may include, but is not limited to, tungsten, the material of the gate dielectric may include, but is not limited to, silicon oxide, and the material of the barrier layer may include, but is not limited to, titanium nitride. The material of the gate spacer 4032 and the material of the initial dielectric layer 4033 may be the same or different. Exemplarily, the material of the gate spacer 4032 and the material of the initial dielectric layer 4033 are both silicon oxide. In some specific embodiments, the method of forming the gate structure 4031 in the second isolation structure 4030 includes, but is not limited to, deposition, etching, and other processes; the method of forming the gate spacer 4022 in the second isolation structure 4030 includes, but is not limited to, deposition, etching, and other processes; the method of forming the initial dielectric layer 4033 in the second isolation structure 4030 includes, but is not limited to, deposition, CMP, and other processes.

[0102] It should be noted that, from the attached Figure 2aThe cross-sectional views of the manufacturing process described below are intermediate stages of the manufacturing process, and some of the structural features shown in the figures can not be the final product form of the semiconductor device. For example, the lower end of the word line (gate electrode) shown in the figures is connected together, while the lower end of the word line (gate electrode) in the final product of the semiconductor device is disconnected, forming a back-to-back structure.

[0103] Figures 5a to 5d A cross-sectional view of a process of forming a conductive structure and a semiconductor body according to some embodiments of the present disclosure Figure 1 In some embodiments of the present disclosure, the surface of the initial semiconductor body exposed at the upper end is metallized. Specifically:

[0104] Reference Figure 5a A plurality of initial semiconductor bodies 4010 extending along the Z-axis direction are formed; the plurality of initial semiconductor bodies 4010 are separated by an initial dielectric layer 4033. The specific formation of the initial semiconductor body 4010 can refer to the examples given in the foregoing Figures 4a to 4d .

[0105] Reference Figure 5b Starting from the top of the initial dielectric layer, part of the initial dielectric layer 4033 is removed along the Z-axis direction, exposing part of the initial semiconductor body. At this time, the initial semiconductor body 4010 includes exposed initial semiconductor body 4011 and unexposed initial semiconductor body 4012. In some embodiments, after part of the initial dielectric layer is removed, the top surface of the remaining initial dielectric layer is higher than the top surface of the gate electrode, i.e., there is a height difference h between the remaining initial dielectric layer and the gate electrode. Thus, the corresponding part of the initial semiconductor body of the height difference can be used to form the drain or source of the vertical transistor. In some specific embodiments, the method of removing part of the initial dielectric layer 4033 includes but is not limited to dry etching.

[0106] Reference Figure 5c At least part of the exposed initial semiconductor body 4011 is subjected to a metallization process to form a metal-semiconductor compound layer 5010. In some specific embodiments, the metal elements in the metal-semiconductor compound layer 5010 include but are not limited to nickel, cobalt, or titanium, etc.

[0107] In some specific embodiments, forming the metal-semiconductor compound layer 5010 specifically includes: forming an initial metal layer (not shown in the figure) covering the exposed surface of the structure to be metallized (including the top surface and the side surface of the exposed initial semiconductor body 4011 in the figure); annealing the structure to be metallized with the initial metal layer to form a metal-semiconductor compound layer. Figure 5b Figure 5c

[0108] ​​It should be noted that the metallization process is mainly carried out in the semiconductor material covering the initial metal layer, and is not carried out in the non-semiconductor material covering the initial metal layer, such as oxide or nitride material. Therefore, after forming the metal semiconductor compound layer, it is generally necessary to remove the excess initial metal layer covering the non-semiconductor material.

[0109] Figures 6a to 6c The cross-sectional schematic diagrams of the metal semiconductor compound layer in different proportions in the semiconductor material in several metallization processes provided by the embodiments of the present disclosure Figure 1 It should be noted that, Figures 6a to 6c corresponding to several possible metallization cases. Figure 5c

[0110] In some specific embodiments, as shown in Figure 6a , during the metallization process, the exposed initial semiconductor body 4011 is fully metallized, and based on this, the formed conductive structure 1064 is entirely a metal semiconductor compound layer, and the initial semiconductor body 4012 not exposed forms a semiconductor body 1030.

[0111] In some specific embodiments, as shown in Figure 6b , during the metallization process, the exposed initial semiconductor body 4011 is partially metallized, and the inside of the exposed initial semiconductor body 4011 is still a semiconductor layer 6010, and based on this, the formed conductive structure 1064 includes a semiconductor layer 6010 and a metal semiconductor compound layer 5010 surrounding the semiconductor layer 6010, and the initial semiconductor body 4012 not exposed forms a semiconductor body 1030. It can be understood that since the semiconductor layer 6010 is actually a part of the exposed initial semiconductor body 4011, it is consistent with the material of the entire initial semiconductor body, such as single crystal silicon, and there is no interface between it and the initial semiconductor body 4012 not exposed.

[0112] In some specific embodiments, as shown in Figure 6c , during the metallization process, the exposed initial semiconductor body 4011 is fully metallized, and at the same time, the metal semiconductor compound layer 5010 further extends into the initial semiconductor body 4012 not exposed. It should be noted that at this time, the metal semiconductor compound extending into the initial semiconductor body 4012 not exposed may not necessarily be the regular shape shown in Figure 6c . Based on this, the formed conductive structure 1064 overlaps with the initial semiconductor body 4012 not exposed to a certain extent, at this time, the formed conductive structure 1064 is entirely a metal semiconductor compound layer, and the part of the initial semiconductor body 4012 not exposed which is not metallized forms a semiconductor body 1030.

[0113] ​It can be understood that, in the foregoing embodiments, the conductive structure 1064 is directly formed by using a part of the initial semiconductor body 4010, and the semiconductor body 1030 is directly formed by using another part of the initial semiconductor body 4010. Because the initial semiconductor body 4010 is once formed from bottom to top, and the conductive structure 1064 and the semiconductor body 1030 share the same initial semiconductor body 4010, the conductive structure 1064 and the semiconductor body 1030 can be directly self-aligned, and the use of a mask layer is omitted. In this way, the alignment accuracy between the conductive structure and the semiconductor body in the embodiments of the present application is high, the process difficulty is low, the mask layer can be omitted, the manufacturing process can be saved, and the manufacturing cost of the semiconductor device can be reduced.

[0114] Here, the self-alignment can be understood as that the geometric centers of the conductive structure 1064 and the semiconductor body 1030 are aligned; or the side surface of the conductive structure 1064 is aligned with the side surface of the semiconductor body along the Z-axis direction; or the conductive structure and the semiconductor body 1030 are overlapped in the normal projection of the cross section perpendicular to the first direction. It should be noted that, due to manufacturing errors and the like, there is a small deviation between the geometric centers of the two, or a small size change (overall thickening or thinning) of the exposed initial semiconductor body 4011 before and after the metallization process, and the like are within the scope of protection of the present application.

[0115] In some embodiments, referring to Figure 5d After the plurality of conductive structures 1064 are formed, the first dielectric layer 5020 is filled between the plurality of conductive structures 1064, and the top surface of the first dielectric layer 5020 is not lower than the top surface of the conductive structure 1064; the remaining initial dielectric layer forms the second dielectric layer 5030; the material of the first dielectric layer 5020 is the same as or different from the material of the second dielectric layer 5030. In some specific embodiments, the material of the first dielectric layer 5020 is the same as the material of the second dielectric layer 5030, for example, both are silicon oxide. In other specific embodiments, the material of the first dielectric layer 5020 is different from the material of the second dielectric layer 5030, for example, the material of the first dielectric layer 5020 is silicon nitride or silicon nitride boron, and the material of the second dielectric layer 5030 is silicon oxide. In some specific embodiments, the method for filling the first dielectric layer 5020 includes but is not limited to PVD, CVD and the like.

[0116] It should be noted that the material selection of the first dielectric layer 5020 is mainly considered for the formation of the storage structure in the subsequent process. Specifically, the storage structure includes a capacitor, and when the capacitor is formed, the capacitor has a relatively long size along the Z-axis direction, so that a plurality of support layers are generally formed, and the insulating layer filled in the support layer is hollowed out. The material of the insulating layer can include silicon oxide. In order to prevent the insulating layer between the support layers from affecting the second dielectric layer 5030 by using wet etching, the first dielectric layer 5020 needs to be set as a material with a different etching selection ratio from the insulating layer to play a blocking role. Therefore, when the material of the first dielectric layer 5020 is silicon nitride or silicon nitride boron, it can directly play a blocking role. When the material of the first dielectric layer 5020 is silicon oxide, a layer of material with a different etching selection ratio from the insulating layer needs to be formed on the first dielectric layer 5020 before the capacitor is formed.

[0117] It should be noted that in the scenario of the back-to-back gate structure, the arrangement of the plurality of semiconductor bodies along the X-axis is not uniform, and the self-alignment of the conductive structure and the semiconductor body also presents an uneven arrangement along the X-axis, while the storage structure connected with the conductive structure presents a uniform arrangement along the X-axis. At this time, in order to improve the connection window between the conductive structure and the storage structure, the size of the bottom of the storage structure can be expanded. In some specific embodiments, the size of the end of the storage structure close to the conductive structure in the cross section perpendicular to the Z-axis direction is greater than the size of the end of the storage structure away from the conductive structure in the cross section perpendicular to the Z-axis direction.

[0118] In some specific embodiments, the method further includes:

[0119] forming a semiconductor thickening layer on the periphery of the exposed initial semiconductor body by an epitaxial process before at least the partially exposed initial semiconductor body is subjected to the metallization process;

[0120] at least the exposed initial semiconductor body and the semiconductor thickening layer are subjected to the metallization process to form the metal semiconductor compound layer; and the exposed initial semiconductor body and the semiconductor thickening layer subjected to the metallization process serve as the conductive structure.

[0121] Figures 7a to 7e A cross-sectional schematic diagram II of a process for forming a conductive structure and a semiconductor body is provided in the embodiments of the present disclosure. In the embodiments of the present disclosure, the surface of the upper end of the initial semiconductor body is thickened before being subjected to the metallization process. Specifically:

[0122] Reference Figure 7a a plurality of initial semiconductor bodies 4010 extending along the Z-axis direction are formed; the plurality of initial semiconductor bodies 4010 are separated by an initial dielectric layer 4033. Wherein, the specific formation manner of the initial semiconductor body 4010 can refer to the foregoing Figures 4a to 4dThe examples given in the foregoing description are for the purpose of illustrating the application and the present application is not limited to such examples.

[0123] Referring to Figure 7b A portion of the initial dielectric layer 4033 is removed along the Z-axis direction from the top of the initial dielectric layer, exposing a portion of the initial semiconductor body, at this time, the initial semiconductor body 4010 includes exposed initial semiconductor body 4011 and unexposed initial semiconductor body 4012. Wherein, the specific forming method of removing a portion of the initial dielectric layer can refer to the description in the foregoing Figure 5b .

[0124] Referring to Figure 7c A semiconductor thickening layer 7010 is formed on the side surface of the exposed initial semiconductor body 4011 by an epitaxial process. Here, based on each exposed surface of the exposed initial semiconductor body 4011, the semiconductor thickening layer is uniformly formed. That is, the size of the semiconductor thickening layer along the Z-axis direction is uniformly changed, and the size along the direction perpendicular to the Z-axis direction is also uniformly changed. The cross-sectional shape of the exposed initial semiconductor body 4011 and the semiconductor thickening layer 7010 together along the plane formed by the intersection of the X-axis and the Y-axis is the same as the cross-sectional shape of the exposed initial semiconductor body 4011 along the plane. In some embodiments, the material of the exposed initial semiconductor body 4011 and the semiconductor thickening layer 7010 is monocrystalline silicon. In some embodiments, the thickness of the semiconductor thickening layer 7010 (1 / 2 of the size along the X-axis direction) can be adjusted according to the actual process, and the thickness of the semiconductor thickening layer 7010 is exemplarily in the range of 1-5nm.

[0125] In some embodiments, the semiconductor thickening layer 7010 can also be located on the top of the exposed initial semiconductor body 4011 (not shown in Figure 7c ).

[0126] Referring to Figure 7d At least a portion of the exposed initial semiconductor body 4011 and the semiconductor thickening layer 7010 is at least subjected to a metallization process to form a metal semiconductor compound layer 5010. In some embodiments, the metal elements in the metal semiconductor compound layer 5010 include but are not limited to nickel, cobalt or titanium, etc.

[0127] In some embodiments, forming the metal semiconductor compound layer 5010 includes: forming an initial metal layer covering the exposed surface of the structure to be subjected to the metallization process (including the top surface of the exposed initial semiconductor body 4011 and the side surface of the semiconductor thickening layer 7010 in Figure 7c ); and annealing the structure to be subjected to the metallization process formed with the initial metal layer to form the metal semiconductor compound layer.

[0128] It should be noted that in the process of metallization, the metal-semiconductor compound layer can exist in different proportions in the semiconductor material with different degrees of metallization. In some embodiments, in the process of metallization, the exposed initial semiconductor body 4011 and the semiconductor thickening layer 7010 are fully metallized together, based on which the formed conductive structure 1064 is all metal-semiconductor compound layer, and the initial semiconductor body 4012 not exposed forms the semiconductor body 1030. For details, please refer to Figure 7d

[0129] In some embodiments, in the process of metallization, the exposed initial semiconductor body 4011 and the semiconductor thickening layer 7010 are partially metallized, and the inside of the exposed initial semiconductor body 4011 is still a semiconductor layer 6010, based on which the formed conductive structure 1064 includes a semiconductor layer 6010 and a metal-semiconductor compound layer 5010 surrounding the semiconductor layer 6010, and the initial semiconductor body 4012 not exposed forms the semiconductor body 1030. It can be understood that since the semiconductor layer 6010 is actually a part of the exposed initial semiconductor body 4011, it is consistent with the material of the entire initial semiconductor body, such as single crystal silicon, and there is no interface between it and the initial semiconductor body 4012 not exposed. For details, please refer to Figure 6b

[0130] In some embodiments, in the process of metallization, the exposed initial semiconductor body 4011 and the semiconductor thickening layer 7010 are fully metallized, and the metal-semiconductor compound layer 5010 further extends into the initial semiconductor body 4012 not exposed. It should be noted that at this time, the metal-semiconductor compound extending into the initial semiconductor body 4012 not exposed may not necessarily be a regular shape, such as the middle bottom being lower than the edge bottom. Based on this, there is a certain overlap between the formed conductive structure 1064 and the initial semiconductor body 4012 not exposed, at this time, the formed conductive structure 1064 is all metal-semiconductor compound layer, and the part of the initial semiconductor body 4012 not exposed which is not metallized forms the semiconductor body 1030. For details, please refer to Figure 6c

[0131] ​​​It can be understood that in the foregoing embodiments, the conductive structure 1064 is formed by thickening and metallizing part of the initial semiconductor body 4010, while the semiconductor body 1030 is formed by the other part of the initial semiconductor body 4010. Because the initial semiconductor body 4010 is formed in one step from bottom to top, and the conductive structure 1064 and the semiconductor body 1030 share the same initial semiconductor body 4010, the conductive structure 1064 and the semiconductor body 1030 can be directly self-aligned, the semiconductor thickening layer makes the structure to be metallized thicker than the semiconductor body, a larger size conductive structure can be obtained, thereby improving the connection window between the conductive structure and the storage structure, and further reducing the contact resistance can also be achieved.

[0132] In some embodiments, referring to Figure 7d After forming the plurality of conductive structures 1064, the first dielectric layer 5020 is filled between the plurality of conductive structures 1064; the remaining initial dielectric layer forms the second dielectric layer 5030; the material of the first dielectric layer 5020 is the same as or different from the material of the second dielectric layer 5030. In some specific embodiments, the material of the first dielectric layer 5020 is the same as the material of the second dielectric layer 5030, for example, both are silicon oxide. In other specific embodiments, the material of the first dielectric layer 5020 is different from the material of the second dielectric layer 5030, for example, the material of the first dielectric layer 5020 is silicon nitride or silicon nitride boron, and the material of the second dielectric layer 5030 is silicon oxide.

[0133] In some embodiments, the semiconductor body and the conductive structure are formed, including:

[0134] An initial semiconductor body extending along the first direction is formed; a plurality of initial semiconductor bodies are separated by an initial dielectric layer; one surface of the initial semiconductor body exposed relative to the other surface along the first direction;

[0135] The initial semiconductor body is metallized by using the exposed surface to form a metal semiconductor compound layer; the metal semiconductor compound layer is used as the conductive structure, and the remaining part of the initial semiconductor body which is not metallized forms the semiconductor body.

[0136] Figures 8a to 8d A cross-sectional view of a process for forming a conductive structure and a semiconductor body provided by an embodiment of the present disclosure Figure 3 In an embodiment of the present disclosure, the upper end of the initial semiconductor body is metallized directly by using the exposed top surface of the initial semiconductor body. Specifically:

[0137] Referring to Figure 8a, form a plurality of initial semiconductor bodies 4010 extending along the direction of the Z-axis; the plurality of initial semiconductor bodies 4010 are separated by an initial dielectric layer 4033. The initial semiconductor bodies 4010 can be formed in the manner described above with reference to the examples given in the foregoing. Figures 4a to 4d

[0138] Referring to Figure 8b , an initial metal layer 8010 is formed covering the top surface of the initial semiconductor bodies 4010. At this time, the initial metal layer 8010 covers the top surface of the initial semiconductor bodies 4010 and the top surface of the initial dielectric layer 4033. The structure to be metallized with the initial metal layer is subjected to annealing treatment. As described above, the metallization process is mainly carried out in the semiconductor material covering the initial metal layer 8010.

[0139] Based on this, referring to Figure 8c , the top-exposed initial semiconductor bodies 4011 are subjected to metallization treatment to form a metal-semiconductor compound layer 5010. In some embodiments, the metal elements in the metal-semiconductor compound layer 5010 include but are not limited to nickel, cobalt, or titanium, etc. The remaining metal layer 8011 covering the top surface of the initial dielectric layer 4033 still exists. The metal-semiconductor compound layer is used as the conductive structure 1064, and the remaining part of the initial semiconductor bodies that are not metallized form the semiconductor bodies 1030.

[0140] The metallization process does not occur in non-semiconductor materials, such as oxide or nitride, covering the initial metal layer. Based on this, referring to Figure 8d , after the metal-semiconductor compound layer is formed, the remaining metal layer 8011 covering the non-semiconductor material is removed.

[0141] It can be understood that in the foregoing embodiments, the exposed top of the initial semiconductor bodies 4010 is directly metallized to form the conductive structure 1064, and another part of the initial semiconductor bodies 4010 is used to form the semiconductor bodies 1030. Because the initial semiconductor bodies 4010 are monolithically formed from bottom to top, and the conductive structure 1064 and the semiconductor bodies 1030 share the same initial semiconductor bodies 4010, the conductive structure 1064 and the semiconductor bodies 1030 can be directly self-aligned, and this scheme is relatively Figure 5a-5d The scheme shown further reduces the process of removing the initial dielectric layer, and the scheme is simple and further saves the manufacturing process.

[0142] ​It should be noted that the material of the first dielectric layer between the plurality of conductive structures is the same as the material of the second dielectric layer between the plurality of semiconductor bodies. In some embodiments, both are silicon oxide. As previously described, if the insulating material used in the subsequent process for forming the storage structure includes silicon oxide, a barrier layer with a different etching selectivity ratio than silicon oxide needs to be formed on the second dielectric layer before the storage structure is formed.

[0143] It should be noted that in the foregoing several embodiments, since the conductive structure shares the same semiconductor pillar with the semiconductor body used to form the vertical transistor, the source and drain doping of the vertical transistor before or after metallization will leave doping ions in the conductive structure. Based on this, the semiconductor body extends along the first direction; the conductive structure has doping ions, and the type of the doping ions is the same as the doping type of the doping ions in the opposite ends of the semiconductor body along the first direction.

[0144] In some embodiments, forming the semiconductor pillar semiconductor body and the interconnection structure conductive structure includes:

[0145] forming a plurality of initial semiconductor bodies extending along the first direction; the plurality of initial semiconductor bodies are separated by an initial dielectric layer;

[0146] removing part of the initial semiconductor bodies to form a second trench in the initial dielectric layer; the remaining initial semiconductor bodies form the semiconductor body;

[0147] widening the second trench to form a first trench; the size of the first trench along the second direction is greater than the size of the second trench along the second direction, and the second direction is perpendicular to the first direction;

[0148] forming the conductive structure in the first trench.

[0149] Figures 9a to 9e A cross-sectional schematic diagram four in a process of forming a conductive structure and a semiconductor body provided by an embodiment of the present disclosure. In the embodiment of the present disclosure, after removing the upper end of the initial semiconductor body, the removed position is widened, and the semiconductor material formed in the widened part is metallized. Specifically:

[0150] Reference Figure 9a forming a plurality of initial semiconductor bodies 4010 extending along the Z-axis direction; the plurality of initial semiconductor bodies 4010 are separated by an initial dielectric layer 4033. Wherein, the specific forming method of the initial semiconductor body 4010 can refer to the examples given in the foregoing Figures 4a to 4d .

[0151] Reference Figure 9bA portion of the initial semiconductor body 4010 is removed along the Z-axis direction from the top of the initial dielectric layer, and a second trench 9010 is formed in the initial dielectric layer 4033. In some embodiments, after the portion of the initial semiconductor body 4010 is removed, the top surface of the remaining initial semiconductor body is higher than the top surface of the gate electrode, and the remaining initial semiconductor body forms the semiconductor body. In some specific embodiments, the method of forming the second trench 9010 can include, but is not limited to, dry etching.

[0152] It can be understood that, after the portion of the initial semiconductor body 4010 is removed, the size of the second trench 9010 along the second direction (i.e., the X-axis direction) is the same as the size of the initial semiconductor body 4010 along the second direction (i.e., the X-axis direction), and the size of the second trench 9010 along the third direction (i.e., the Y-axis direction) is the same as the size of the initial semiconductor body 4010 along the third direction (i.e., the Y-axis direction).

[0153] In some embodiments, referring to Figure 9c , a portion of the initial dielectric layer 4033 on the side surface of the second trench 9010 is removed, and a widening process is performed on the second trench 9010 to form a first trench 9020. In some specific embodiments, the method of removing a portion of the initial dielectric layer 4033 on the side surface of the second trench 9010 can include, but is not limited to, dry etching.

[0154] It can be understood that, after the widening process is performed on the second trench 9010, the size L1 of the first trench 9020 along the second direction (i.e., the X-axis direction) is greater than the size L2 of the second trench 9010 along the second direction (i.e., the X-axis direction); and / or, the size of the first trench 9020 along the third direction (i.e., the Y-axis direction) is greater than the size of the second trench 9010 along the third direction (i.e., the Y-axis direction).

[0155] Referring to Figure 9d , the conductive structure 1064 is formed in the first trench 9020. In some embodiments, the formation of the conductive structure in the first trench 9020 can specifically include: first forming an initial semiconductor layer 9030 in the first trench 9020. In some specific embodiments, the initial semiconductor layer 9030 is formed in the first trench 9020 by a deposition process, and the material of the initial semiconductor layer includes a polycrystalline material, such as polysilicon. In other specific embodiments, the initial semiconductor layer 9030 is formed in the first trench 9020 by an epitaxy process, and the material of the initial semiconductor layer includes a single-crystal material, such as single-crystal silicon.

[0156] Referring to Figure 9eThe initial semiconductor layer 9030 is subjected to a metallization process to form a metal semiconductor compound layer 5010, which is used as the conductive structure 1064. The specific metallization process can be understood by referring to the aforementioned metallization process.

[0157] It should be noted that in the embodiments of the present disclosure, the second groove 9010 can also not be widened, and the metal semiconductor compound layer 5010 is directly formed in the second groove 9010 to obtain the conductive structure 1064.

[0158] In some embodiments, the semiconductor body and the conductive structure are formed by:

[0159] A plurality of initial semiconductor bodies extending along the first direction are formed; the plurality of initial semiconductor bodies are separated by an initial dielectric layer;

[0160] Part of the initial dielectric layer is removed along the first direction to expose part of the initial semiconductor bodies;

[0161] A liner layer covering the exposed side surfaces of the initial semiconductor bodies is formed;

[0162] A first dielectric layer is filled between the liner layers;

[0163] Part of the initial semiconductor bodies is removed; the remaining initial semiconductor bodies form the semiconductor body; and the remaining initial dielectric layer forms the second dielectric layer;

[0164] Part of the liner layer covering the side surface of the first dielectric layer is removed to form a plurality of first grooves; and the remaining liner layer forms a third dielectric layer;

[0165] The conductive structure is formed in the first grooves.

[0166] Figures 10a to 10i A cross-sectional view of a process for forming a conductive structure and a semiconductor body according to an embodiment of the present disclosure is provided. In the embodiments of the present disclosure, a liner layer is formed around the exposed upper end of the initial semiconductor body to form a semiconductor material with a larger size than the initial semiconductor body in subsequent processes, and the semiconductor material is subjected to a metallization process. Specifically:

[0167] Reference Figure 10a A plurality of initial semiconductor bodies 4010 extending along the Z-axis direction are formed; the plurality of initial semiconductor bodies 4010 are separated by an initial dielectric layer 4033. The specific formation of the initial semiconductor body 4010 can be understood by referring to the examples given in the foregoing Figures 4a to 4d .

[0168] Reference Figure 10bA portion of the initial dielectric layer 4033 is removed along the Z-axis direction from the top of the initial dielectric layer 4033 to expose a portion of the initial semiconductor body, at this time, the initial semiconductor body 4010 includes exposed initial semiconductor body 4011 and unexposed initial semiconductor body 4012. The remaining initial dielectric layer forms a second dielectric layer 5030; wherein the specific forming method of removing a portion of the initial dielectric layer can refer to the description in the foregoing Figure 5b

[0169] Referring to Figure 10c A liner layer 1110 is formed on the top surface and side surface of the exposed initial semiconductor body 4011. Here, the liner layer 1110 is uniformly formed based on each exposed surface of the exposed initial semiconductor body 4011, that is, the size of the liner layer along the Z-axis direction is uniformly changed, and the size along the direction perpendicular to the Z-axis direction is also uniformly changed. The cross-sectional shape of the exposed initial semiconductor body 4011 and the liner layer 1110 together along the plane formed by the intersection of the X-axis and the Y-axis is the same as the cross-sectional shape of the exposed initial semiconductor body 4011 along the plane. In some embodiments, the method of forming the liner layer 1110 includes but is not limited to PVD, CVD, ALD and the like. In some embodiments, the thickness of the liner layer 1110 (1 / 2 of the size along the X-axis direction) can be adjusted according to the actual process, and the thickness of the liner layer 1110 is exemplarily in the range of 1-5nm.

[0170] Referring to Figure 10d The first dielectric layer 5020 is filled between the liner layers 1110. In some embodiments, the etching selectivity ratio of the liner layer 1110 and the first dielectric layer is different. Exemplarily, the material of the first dielectric layer 5020 can include an oxide such as silicon oxide; the material of the liner layer 1110 can include a nitride such as silicon nitride, silicon oxynitride or one or more of high dielectric materials. In some embodiments, the method of forming the first dielectric layer 5020 includes depositing a first dielectric material layer between the liner layers 1110 by PVD, CVD and the like, and removing a portion of the first dielectric material layer by CMP and the like, wherein a portion of the liner layer 1110 located on the top of the exposed initial semiconductor body 4011 is removed at the same time when a portion of the first dielectric material layer is removed to expose the top of the initial semiconductor body 4011.

[0171] Referring to Figure 10e A portion of the exposed initial semiconductor body 4011 is removed along the Z-axis direction from the top of the exposed initial semiconductor body 4011, and the surface S1 of the remaining initial semiconductor body is higher than the surface of the liner layer 1110 perpendicular to the first direction. The remaining initial semiconductor body forms the semiconductor body 1030. In some embodiments, the method of removing a portion of the initial semiconductor body 4011 includes but is not limited to a dry etching process.​

[0172] Reference Figure 10f , removing part of the liner layer 1110 covering the side surface of the first dielectric layer 5020 to form a plurality of first grooves 9020, the remaining liner layer 1110 forms the third dielectric layer 1120, and the surface S1 of the remaining initial semiconductor body is higher than the surface S2 of the third dielectric layer close to the first dielectric layer. In some embodiments, the method of removing part of the liner layer 1110 covering the side surface of the first dielectric layer 5020 includes but is not limited to a wet etching process.

[0173] In some embodiments, the third dielectric layer 1120 can at least include a first sub-dielectric layer, and the third dielectric layer 1120 can include a first sub-dielectric layer 1121 and a second sub-dielectric layer 1122; wherein the first sub-dielectric layer 1121 extends along the second direction, i.e., the X-axis direction, and covers the second dielectric layer 5030, and the second sub-dielectric layer 1122 extends along the first direction, i.e., the Z-axis direction, and covers part of the side surface of the initial semiconductor body 4010.

[0174] In some embodiments, the remaining initial semiconductor body extends into the first groove 9020 at one end of the two ends of the remaining initial semiconductor body relatively arranged along the first direction and close to the first groove 9020; and the surface S1 of the remaining initial semiconductor body close to the first groove 9020 is higher than the surface S3 of the second sub-dielectric layer 1122 close to the first groove 9020.

[0175] In some embodiments, the sum of the size of the second sub-dielectric layer 1122 and the remaining initial semiconductor body in the second direction, i.e., the Y-axis direction, is the same as the size of the first groove 9020 in the second direction, i.e., the Y-axis direction.

[0176] It can be understood that the size of the first groove 9020 in the second direction, i.e., the X-axis direction, is greater than the size of the initial semiconductor body 4010 in the second direction, i.e., the X-axis direction, and at the same time, the size of the first groove 9020 in the third direction, i.e., the Y-axis direction, is greater than the size of the initial semiconductor body 4010 in the third direction, i.e., the Y-axis direction. That is, the size of the liner layer after removal for subsequent formation of the conductive structure is greater than the size of the initial semiconductor body, which achieves the effect of thickening the conductive structure, and the thickness of the liner layer is the thickness of the conductive structure compared to the initial semiconductor body 4010 being thickened.

[0177] In addition, due to the large area, the second dielectric layer 5030 may have defects such as voids when filled. Here S1 is higher than S2, which can protect the second dielectric layer 5030 from being exposed, thereby avoiding the etching liquid entering the voids when removing part of the liner layer 1110 covering the side surface of the first dielectric layer 5020 by wet etching, causing adverse consequences.

[0178] Next, refer to Figure 10g 、 Figure 10h and Figure 10i , forming the conductive structure 1064 in the first trench 9020. In some embodiments, forming the conductive structure in the first trench includes: forming an initial semiconductor layer 9030 in the first trench; and performing a metallization process on the initial semiconductor layer 9030 to form a metal-semiconductor compound layer 5010.

[0179] In some specific embodiments, reference Figure 10g , forming an initial semiconductor layer in the first trench, including: forming the initial semiconductor layer 9030 in the first trench 9020 through a deposition process, the material of the initial semiconductor layer 9030 including a polycrystalline material, such as polysilicon.

[0180] Figures 10a to 10f and Figure 11a 、 Figure 11b and Figure 11c A sixth cross-sectional schematic diagram of a process of forming a conductive structure and a semiconductor body provided in an embodiment of the present disclosure.

[0181] In some specific embodiments, reference Figure 11a , forming an initial semiconductor layer in the first trench, including: forming the initial semiconductor layer 9030 in the first trench 9020 by an epitaxial process, the material of the initial semiconductor layer 9030 including a single crystal material, such as single crystal silicon.

[0182] Next, refer to Figure 10h and Figure 11b The initial semiconductor layer 9030 is metallized to form a metal-semiconductor compound layer 5010 , and the unmetallized initial semiconductor layer 9030 is formed into a semiconductor layer 6010 .

[0183] It should be noted that, here, the metal-semiconductor compound layer 5010 extends along the second direction or the third direction. In other words, the plane of the metal-semiconductor compound layer 5010 is perpendicular to the first direction. In some specific embodiments, the metal element in the metal compound layer includes, but is not limited to, nickel, cobalt, or titanium. The specific metallization process can be understood with reference to the aforementioned metallization process. Here, the semiconductor layer 6010 contacts the semiconductor body 1030 and is located on the side of the metal-semiconductor compound layer 5010 that is closer to the semiconductor body 1030.

[0184] Next, in some embodiments, reference Figure 10i and Figure 11cIn some embodiments, the metal layer 1130 is formed on the metal-semiconductor compound layer 5010, and is located on the side of the metal-semiconductor compound layer 5010 away from the semiconductor layer 6010. In some embodiments, the material of the metal layer 1130 includes, but is not limited to, tungsten or copper.

[0185] It should be noted that in the process of metallization, the metal-semiconductor compound layer can have different proportions in the initial semiconductor with different degrees of metallization, and the metal layer can be selectively added. Figures 12a to 12d FIG. 2 is a schematic diagram of a cross section of a metal-semiconductor compound layer in a semiconductor material in several metallization processes according to some embodiments of the present disclosure.

[0186] In some embodiments, as shown in FIG. 9A, in the process of metallization, the initial semiconductor layer 9030 is partially metallized, the top of the initial semiconductor layer 9030 is metallized, and the remaining part of the initial semiconductor layer 9030 is not metallized. At the same time, the top of the initial semiconductor layer 9030 also forms a metal layer 1130. Based on this, the formed conductive structure 1064 includes the semiconductor layer 6010, the metal-semiconductor compound layer 5010, and the metal layer 1130 which are sequentially and layerwisely arranged. Figure 12a In some embodiments, as shown in FIG. 9B, in the process of metallization, the initial semiconductor layer 9030 is partially metallized, the top of the initial semiconductor layer 9030 is metallized, and the remaining part of the initial semiconductor layer 9030 is not metallized. At the same time, the top of the initial semiconductor layer 9030 no longer forms a metal layer. Based on this, the formed conductive structure 1064 includes the semiconductor layer 6010 and the metal-semiconductor compound layer 5010 which are sequentially and layerwisely arranged.

[0187] Figure 12b In some embodiments, as shown in FIG. 9C, in the process of metallization, the initial semiconductor layer 9030 is completely metallized, and the top of the initial semiconductor layer 9030 no longer forms a metal layer. Based on this, the formed conductive structure 1064 is completely a metal-semiconductor compound layer.

[0188] In some embodiments, as shown in FIG. 9D, in the process of metallization, the initial semiconductor layer 9030 is completely metallized, and the top of the initial semiconductor layer 9030 no longer forms a metal layer. Based on this, the formed conductive structure 1064 is completely a metal-semiconductor compound layer. Figure 12c In some embodiments, as shown in FIG. 9E, in the process of metallization, the initial semiconductor layer 9030 is completely metallized, and the top of the initial semiconductor layer 9030 no longer forms a metal layer. Based on this, the formed conductive structure 1064 is completely a metal-semiconductor compound layer.

[0189] Figure 12d ​​As shown, during the metallization process, the initial semiconductor layer 9030 is completely metallized, while the metal-semiconductor compound layer 5010 extends further into the initial semiconductor body 4010 below the third dielectric layer. Furthermore, no metal layer is formed on top of the initial semiconductor layer 9030. Consequently, there is a certain overlap between the formed conductive structure 1064 and the initial semiconductor body 4010 below the third dielectric layer. In this case, the formed conductive structure 1064 is entirely a metal-semiconductor compound layer, while the unmetallized portion of the initial semiconductor body 4010 below the third dielectric layer forms the semiconductor body 1030.

[0190] It will be appreciated that in the aforementioned embodiment, a portion of the initial semiconductor body 4010 is thickened and metallized to form the conductive structure 1064, while another portion of the initial semiconductor body 4010 is used to form the semiconductor body 1030. Because the initial semiconductor body 4010 is formed in one piece from bottom to top, and the conductive structure 1064 and the semiconductor body 1030 share the same initial semiconductor body 4010, the conductive structure 1064 and the semiconductor body 1030 can be directly self-aligned. Furthermore, by thickening the initial semiconductor body 4010 through the liner layer, a larger conductive structure can be obtained, thereby increasing the connection window between the conductive structure and the storage structure and further reducing contact resistance.

[0191] At the same time, by thickening the initial semiconductor body 4010 through the liner layer, the liner layer can be conformally formed on the surface of the initial semiconductor body, and the process controllability is good; in addition, by thickening the initial semiconductor body 4010 through the liner layer, no additional mask layer is required, which is conducive to reducing production costs.

[0192] The production of the conductive structure and semiconductor body has been completed here. Next, the production of other structures of the semiconductor device will be introduced.

[0193] Next, a storage structure is formed on one side of the conductive structure along the first direction and away from the surface of the semiconductor body. The method for forming the storage structure is relatively mature and will not be described in detail here.

[0194] In some specific embodiments, the storage structure includes a capacitor; forming the storage structure includes forming a cup-shaped capacitor CUP, a cylindrical capacitor CYL, or a pillar-shaped capacitor PIL. The shape of the capacitor can be selected and set according to actual needs and is not limited in this disclosure.

[0195] In some embodiments, the method further includes: forming a word line on at least one side of the semiconductor body; and forming a bit line on a surface away from the conductive structure among two surfaces of the semiconductor body opposite to each other along the first direction.

[0196] Here, the word line can extend along a third direction, and the bit line can extend along a second direction.

[0197] In some embodiments, forming the word line on at least one side of the semiconductor body comprises: forming the word line on one side of the semiconductor body; forming the word line on two oppositely arranged sides of the semiconductor body; forming a word line surrounding the side of the semiconductor body.

[0198] It can be understood that the conductive structure in the embodiments of the present disclosure can be applied to different word line (gate structure) scenarios. For example, the conductive structure in the embodiments of the present disclosure can be applied to a scenario in which two word line structures corresponding to two adjacent semiconductor bodies are arranged back to back, and the drawings in the embodiments of the present disclosure are used to illustrate the scenario of back-to-back arrangement.

[0199] In some specific embodiments, two adjacent semiconductor bodies form a semiconductor body group, and the two semiconductor bodies in the semiconductor body group are spaced apart by a first isolation structure (i.e. Figure 4d the first isolation structure 4020 in FIG. 4A); two adjacent semiconductor body groups are spaced apart by a second isolation structure (i.e. Figure 4d the final form corresponding to the second isolation structure 4030 in FIG. 4B, in which the lower end of the gate electrode is disconnected); and forming the word line on at least one side of the semiconductor body comprises: forming the word line on one side of the corresponding semiconductor body in the semiconductor body group, which is away from the first isolation structure.

[0200] In the embodiments of the present disclosure, by ingenious use of the initial semiconductor body, self-alignment of the conductive structure and the semiconductor body can be achieved, which can increase the alignment accuracy of the semiconductor body of the conductive structure, reduce the alignment difficulty of the two, improve the reliability of the semiconductor device, save the manufacturing time and cost, and improve the process speed and efficiency. On the other hand, the metal semiconductor compound layer as the material of the conductive structure between the semiconductor body and the storage structure has a low resistivity, can realize better electrical connection between the semiconductor body and the storage structure, and improve the reliability of the semiconductor device.

[0201] The embodiments of the present disclosure also provide a semiconductor device, comprising: a plurality of conductive structures; a plurality of semiconductor bodies, the semiconductor bodies being located on one side of the conductive structures along a first direction and connected with the conductive structures; a first dielectric layer located between the plurality of conductive structures; a second dielectric layer located between the plurality of semiconductor bodies; and a third dielectric layer located between the first dielectric layer and the second dielectric layer.

[0202] In some embodiments, the size of the conductive structure in the cross section perpendicular to the first direction is greater than the size of the semiconductor body in the cross section perpendicular to the first direction.

[0203] In some embodiments, the conductive structure and the semiconductor body form a step structure at a junction of the two, the step structure comprising a side surface extending along the first direction and a step surface extending along the second direction.

[0204] In some embodiments, the step structure has a same dimension along the second direction in the first direction, and the step structure has a same dimension along the first direction in the second direction.

[0205] In some embodiments, the conductive structure further comprises a metal semiconductor compound layer.

[0206] In some embodiments, the metal element in the metal semiconductor compound layer comprises nickel, cobalt or titanium.

[0207] In some embodiments, the conductive structure further comprises a semiconductor layer, the semiconductor layer being in contact with the semiconductor body and located on a side of the metal semiconductor compound layer close to the semiconductor body.

[0208] In some embodiments, the semiconductor layer comprises a single crystal material or a polycrystalline material.

[0209] In some embodiments, the conductive structure further comprises a metal layer, the metal layer being located on a side of the metal semiconductor compound layer away from the semiconductor layer.

[0210] In some embodiments, the metal layer comprises tungsten or copper.

[0211] In some embodiments, the third dielectric layer has a different etching selectivity ratio than the first dielectric layer.

[0212] In some embodiments, the first dielectric layer comprises an oxide and the third dielectric layer comprises a nitride.

[0213] In some embodiments, the third dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer; the first sub-dielectric layer extends along the second direction and covers the second dielectric layer, the second sub-dielectric layer extends along the first direction and covers part of the side surface of the semiconductor body; the second direction is perpendicular to the first direction.

[0214] In some embodiments, one of the two ends of the semiconductor body relative to the first direction extends into the conductive structure; a surface of the semiconductor body close to the conductive structure is higher than a surface of the second sub-dielectric layer close to the conductive structure.

[0215] In some embodiments, the sum of the size of the second sub-dielectric layer and the semiconductor body in the second direction is the same as the size of the conductive structure in the second direction.

[0216] In some embodiments, the plurality of semiconductor bodies are arranged in an array; the semiconductor device further comprises: a plurality of storage structures, each of the storage structures is located on a side away from the semiconductor body of the conductive structure in two sides of the conductive structure along the first direction, and is connected with the conductive structure; a plurality of word lines, each of the word lines is coupled with at least one side surface of each semiconductor body in a row of the semiconductor bodies; and a plurality of bit lines, each of the bit lines is coupled with a surface away from the conductive structure of two surfaces of each semiconductor body in a column of the semiconductor bodies along the first direction.

[0217] In some embodiments, the word line is located on one side surface of the semiconductor body; or, the word line is located on two opposite side surfaces of the semiconductor body; or, the word line surrounds the side surface of the semiconductor body.

[0218] In some embodiments, two adjacent semiconductor bodies form a semiconductor body group, and the two semiconductor bodies in a semiconductor body group are spaced apart by a first isolation structure; two adjacent semiconductor body groups are spaced apart by a second isolation structure; and the two word lines are respectively located on two side surfaces of the corresponding semiconductor bodies in the semiconductor body group, away from the first isolation structure.

[0219] In some embodiments, the storage structure comprises a capacitor; and the capacitor comprises a cup-shaped capacitor, a cylinder-shaped capacitor or a pillar-shaped capacitor.

[0220] It should be noted that the features of each structure in the semiconductor device described above can be understood with reference to the features of each structure described in the method for manufacturing the semiconductor device.

[0221] In some embodiments, the semiconductor device comprises a memory device, and the memory device comprises a DRAM.

[0222] Figure 13 A structure diagram of a dynamic random access memory according to an embodiment of the present disclosure is shown in FIG. 2; as Figure 13As shown, the semiconductor device 100 comprises: a plurality of conductive structures 1064; a plurality of semiconductor bodies 1030, which are located on one side of the conductive structures 1064 along a first direction (e.g., the Z-axis) and are connected to the conductive structures 1064; a first dielectric layer 5020, which is located between the plurality of conductive structures 1064; a second dielectric layer 5030, which is located between the plurality of semiconductor bodies 1030; and a third dielectric layer 1120, which is located between the first dielectric layer 5020 and the second dielectric layer 5030. The conductive structures 1064 are arranged in alignment with the geometric centers of the semiconductor bodies 1030, and it should be understood that the alignment here excludes slight deviations caused by manufacturing errors and the like. The conductive structures 1064 have a dimension along a second direction (e.g., the X-axis) that is greater than a dimension of the semiconductor bodies 1030 along the second direction (e.g., the X-axis), and the conductive structures 1064 have the same amount of excess dimension on both sides relative to the semiconductor bodies 1030. The conductive structures 1064 comprise, in order along the first direction, a semiconductor layer, a metal-semiconductor compound layer, and a metal layer. In addition, the third dielectric layer 1120 can be clearly distinguished from the first dielectric layer 5020 and the second dielectric layer 5030. Figure 13 Other structures shown in Figure 1 may be understood with reference to Figure 14 . Figure 3 A structure of a dynamic random access memory provided by an embodiment of the present disclosure is shown in Figure 13 . The difference is that the conductive structures 1064 comprise, in order along the first direction, a semiconductor layer and a metal-semiconductor compound layer.

[0223] It should be noted that Figure 13 and Figure 14 shown are only application examples of the conductive structures and the semiconductor bodies in the dynamic random access memory in the foregoing embodiments of the present disclosure, and it can be understood that other conductive structures and semiconductor bodies in the foregoing embodiments of the present disclosure can also be similarly applied to the dynamic random access memory.

[0224] It should be noted that Figure 13 and Figure 14 shown are similar Figure 1 only examples in which the first device 102 and the second device 104 are connected by bonding, and it can be understood that other conductive structures and semiconductor bodies in the foregoing embodiments of the present disclosure can also be similarly applied to the case in which the foregoing first device 102 and second device 104 are directly stacked on the same substrate.

[0225] It should be noted that Figure 13 and Figure 14 shown are similar Figure 1Only the example that two adjacent semiconductor bodies correspond to two gate structures respectively arranged back to back is shown, and it can be understood that other conductive structures in the foregoing embodiments of the present disclosure can also be applied to the various different cases that the foregoing gate structures are located on the same side of the semiconductor body, the gate structures are located on the opposite sides of the semiconductor body, and the gate structures surround the semiconductor body.

[0226] The embodiment of the present disclosure further provides a storage system, comprising: the semiconductor device as described in the foregoing embodiments of the present disclosure; and a memory controller connected with the semiconductor device and used for controlling the semiconductor device.

[0227] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0228] The specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited to this, any person skilled in the art in the technical range disclosed by the present disclosure, can easily think of changes or replacement, should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a plurality of conductive structures; a plurality of semiconductor bodies, which are located on one side of the conductive structures along a first direction and connected to the conductive structures; a first dielectric layer, which is located between the conductive structures; a second dielectric layer, which is located between the semiconductor bodies; a third dielectric layer, which is located between the first dielectric layer and the second dielectric layer.

2. The semiconductor device according to claim 1, wherein The size of the conductive structures in a cross section perpendicular to the first direction is greater than the size of the semiconductor bodies in a cross section perpendicular to the first direction.

3. The semiconductor device of claim 2, wherein, The conductive structures and the semiconductor bodies form a stepped structure at the connection between the two, which comprises a side surface extending along the first direction and a stepped surface extending along a second direction.

4. The semiconductor device according to claim 3, wherein The size of the stepped structure along the second direction is the same in the first direction, and the size of the stepped structure along the first direction is the same in the second direction.

5. The semiconductor device of claim 1, wherein The conductive structure at least comprises a metal semiconductor compound layer.

6. The semiconductor device of claim 5, wherein, The metal element in the metal semiconductor compound layer comprises nickel, cobalt or titanium.

7. The semiconductor device of claim 5, wherein The conductive structure further comprises a semiconductor layer, which is in contact with the semiconductor body and located on the side of the metal semiconductor compound layer close to the semiconductor body.

8. The semiconductor device of claim 7, wherein, The material of the semiconductor layer comprises single crystal material or polycrystalline material.

9. The semiconductor device of claim 7, wherein, The conductive structure further comprises a metal layer, which is located on the side of the metal semiconductor compound layer away from the semiconductor layer.

10. The semiconductor device of claim 1, wherein The etching selectivity ratio of the third dielectric layer to the first dielectric layer is different.

11. The semiconductor device of claim 10, wherein, The first dielectric layer comprises oxide, and the third dielectric layer comprises nitride.

12. The semiconductor device of claim 1, wherein The third dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer; the first sub-dielectric layer extends along a second direction and covers the second dielectric layer, and the second sub-dielectric layer extends along a first direction and covers part of the side surface of the semiconductor body; the second direction is perpendicular to the first direction.

13. The semiconductor device of claim 12, wherein, One end of the semiconductor body located on the opposite side of the semiconductor body along the first direction extends into the conductive structure; the surface of the semiconductor body close to the conductive structure is higher than the surface of the second sub-dielectric layer close to the conductive structure.

14. The semiconductor device of claim 13, wherein, The sum of the size of the second sub-dielectric layer and the semiconductor body in the second direction is the same as the size of the conductive structure in the second direction.

15. The semiconductor device of claim 1, wherein The semiconductor bodies are arranged in an array. The semiconductor device further comprises: a plurality of storage structures, each of which is located on the side of the conductive structure away from the semiconductor body along the first direction and connected to the conductive structure; a plurality of word lines, which are coupled to at least one side surface of each semiconductor body in a row of semiconductor bodies; a plurality of bit lines, which are coupled to the surface of each semiconductor body in a column of semiconductor bodies away from the conductive structure along the first direction.

16. The semiconductor device of claim 15, wherein, The word line is located on one side surface of the semiconductor body. Alternatively, the word line is located on the two opposite side surfaces of the semiconductor body. Alternatively, the word line surrounds the side surface of the semiconductor body.

17. The semiconductor device of claim 16, wherein, Two semiconductor bodies adjacent to each other form a semiconductor body group, two semiconductor bodies in a semiconductor body group are separated by a first isolation structure; two semiconductor body groups adjacent to each other are separated by a second isolation structure. Two word lines are respectively located at two sides of a corresponding semiconductor body in the semiconductor body group, and one side of the two sides is far away from the first isolation structure.

18. A method of fabricating a semiconductor device, comprising: The method comprises: forming a plurality of conductive structures; forming a plurality of semiconductor bodies, the semiconductor bodies being located on one side of the conductive structures along a first direction and connected with the conductive structures; forming a first dielectric layer between the plurality of conductive structures; forming a second dielectric layer between the plurality of semiconductor bodies; forming a third dielectric layer between the first dielectric layer and the second dielectric layer.

19. The method of fabricating a semiconductor device according to Claim 18, wherein The forming of the semiconductor bodies and the conductive structures comprises: forming a plurality of initial semiconductor bodies extending along the first direction; the plurality of initial semiconductor bodies are separated by an initial dielectric layer; removing part of the initial dielectric layer along the first direction to expose part of the initial semiconductor bodies; the remaining initial dielectric layer forms the second dielectric layer; forming a liner layer covering the exposed side of the initial semiconductor body; filling a first dielectric layer between the liner layer; removing part of the initial semiconductor body; the remaining initial semiconductor body forms the semiconductor body; removing part of the liner layer covering the side of the first dielectric layer to form a plurality of first trenches; the remaining liner layer forms a third dielectric layer; forming the conductive structure in the first trench.

20. The method of fabricating a semiconductor device according to Claim 19, wherein The surface of the remaining initial semiconductor body is higher than the surface of the third dielectric layer close to the first dielectric layer.

21. The method of fabricating a semiconductor device according to Claim 19, wherein The etching selectivity ratio of the liner layer and the first dielectric layer is different.

22. The method of fabricating a semiconductor device according to Claim 19, wherein The forming of the conductive structure in the first trench comprises: forming an initial semiconductor layer in the first trench; forming a metal semiconductor compound layer by metallization treatment on the initial semiconductor layer.

23. The method of fabricating a semiconductor device according to Claim 22, wherein The forming of the initial semiconductor layer in the first trench comprises: forming the initial semiconductor layer in the first trench by a deposition process, and the material of the initial semiconductor layer comprises a polycrystalline material.

24. The method of fabricating a semiconductor device according to Claim 22, wherein The forming of the initial semiconductor layer in the first trench comprises: forming the initial semiconductor layer in the first trench by an epitaxy process, and the material of the initial semiconductor layer comprises a single crystal material.

25. The method of fabricating a semiconductor device according to Claim 22, wherein The method further comprises: forming a metal layer on the metal semiconductor compound layer.

26. The method of fabricating a semiconductor device of claim 18, wherein, The method further comprises: forming a storage structure on the side of the conductive structure far away from the semiconductor body along the first direction; forming a word line on at least one side of the semiconductor body; forming a bit line on the surface of the semiconductor body far away from the conductive structure among the two surfaces of the semiconductor body arranged oppositely along the first direction.

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